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Rasky_hw
Commit 0f12a941 authored by Franco (nextime) Lanza's avatar Franco (nextime) Lanza
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CPLD sheet complete

parent 367c73a8
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FPGA.sch
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Rasky_v1-cache.lib
View file @ 0f12a941
......@@ -154,6 +154,45 @@ X (ADC4/TCK)PF4 39 1200 -1050 300 L 50 50 1 1 I
ENDDRAW
ENDDEF
#
# AVR-JTAG-10
#
DEF AVR-JTAG-10 CON 0 40 Y Y 1 F N
F0 "CON" -170 330 50 H V C CNN
F1 "AVR-JTAG-10" -340 -330 50 H V L BNN
F2 "AVR-JTAG-10" -570 20 50 V I C CNN
F3 "" 0 0 60 H V C CNN
$FPLIST
AVR-JTAG-10
$ENDFPLIST
DRAW
T 0 230 200 45 0 0 0 GND Normal 1 C C
T 0 -360 -100 45 0 0 0 NC Normal 1 C C
T 0 240 -200 45 0 1 0 GND Normal 1 C C
T 0 290 0 45 0 1 0 nSRST Normal 1 C C
T 0 290 -100 45 0 1 0 nTRST Normal 1 C C
T 0 -380 200 45 0 1 0 TCK Normal 1 C C
T 0 -370 -200 45 0 1 0 TDI Normal 1 C C
T 0 -380 100 45 0 1 0 TDO Normal 1 C C
T 0 -380 0 45 0 1 0 TMS Normal 1 C C
T 0 260 100 45 0 1 0 VREF Normal 1 C C
S -280 -230 130 -250 0 1 0 F
S -280 -40 -260 -250 0 1 0 F
S -260 290 -280 40 0 1 0 F
S -260 290 130 270 0 1 0 F
S 110 290 130 -230 0 1 0 F
X ~ 1 -200 200 100 R 40 40 1 1 P
X ~ 2 50 200 100 L 40 40 1 1 P
X ~ 3 -200 100 100 R 40 40 1 1 P
X ~ 4 50 100 100 L 40 40 1 1 P
X ~ 5 -200 0 100 R 40 40 1 1 P
X ~ 6 50 0 100 L 40 40 1 1 P
X ~ 7 -200 -100 100 R 40 40 1 1 P
X ~ 8 50 -100 100 L 40 40 1 1 P
X ~ 9 -200 -200 100 R 40 40 1 1 P
X ~ 10 50 -200 100 L 40 40 1 1 P
ENDDRAW
ENDDEF
#
# CONN_01X01
#
DEF CONN_01X01 P 0 40 Y N 1 F N
......@@ -446,6 +485,27 @@ X A16 39 -700 -500 300 R 60 60 1 1 I
ENDDRAW
ENDDEF
#
# Led_Small
#
DEF Led_Small D 0 10 N N 1 F N
F0 "D" -50 125 50 H V L CNN
F1 "Led_Small" -175 -100 50 H V L CNN
F2 "" 0 0 60 V V C CNN
F3 "" 0 0 60 V V C CNN
$FPLIST
CP*
SM*
$ENDFPLIST
DRAW
P 2 0 1 0 -30 -40 -30 40 N
P 4 0 1 0 30 -40 -30 0 30 40 30 -40 F
P 5 0 1 0 0 30 -20 50 -10 50 -20 50 -20 40 N
P 5 0 1 0 20 50 0 70 10 70 0 70 0 60 N
X K 1 -100 0 70 R 40 40 1 1 P
X A 2 100 0 70 L 40 40 1 1 P
ENDDRAW
ENDDEF
#
# MC1413
#
DEF MC1413 U 0 40 Y Y 1 F N
......
Rasky_v1.sch
View file @ 0f12a941
......@@ -105,23 +105,33 @@ Comment3 ""
Comment4 ""
$EndDescr
$Sheet
S 1400 3200 950 700
S 1400 2850 950 1050
U 55CDFACC
F0 "VENCODER" 60
F1 "FPGA.sch" 60
F2 "SRAM_IO[0..7]" B R 2350 2950 60
F3 "SRAM_A[0..18]" I R 2350 3050 60
F4 "PIX[0..7]" I R 2350 3150 60
F5 "SRAM_OE" I R 2350 3250 60
F6 "TVP_HSOUT" I R 2350 3350 60
F7 "TVP_VSOUT" I R 2350 3450 60
F8 "TVP_DATACLK" I R 2350 3550 60
F9 "SRAM_WE" I R 2350 3650 60
F10 "SRAM_CE" I R 2350 3750 60
F11 "VBUF_SPI" B R 2350 3850 60
$EndSheet
$Sheet
S 1400 2100 950 800
S 1400 1800 950 800
U 55CF4C76
F0 "TVP7002" 60
F1 "TVP7002.sch" 60
F2 "TVP_PWDOWN" I R 2350 2200 60
F3 "TVP_RESET" I R 2350 2300 60
F4 "TVP_I2C" B R 2350 2400 60
F5 "TVP_DATACLK" I R 2350 2500 60
F6 "TVP_VSOUT" O R 2350 2600 60
F7 "TVP_HSOUT" O R 2350 2700 60
F8 "PIX[0..7]" O R 2350 2800 60
F2 "TVP_PWDOWN" I R 2350 1900 60
F3 "TVP_RESET" I R 2350 2000 60
F4 "TVP_I2C" B R 2350 2100 60
F5 "TVP_DATACLK" I R 2350 2200 60
F6 "TVP_VSOUT" O R 2350 2300 60
F7 "TVP_HSOUT" O R 2350 2400 60
F8 "PIX[0..7]" O R 2350 2500 60
$EndSheet
$Sheet
S 1400 5100 950 700
......@@ -798,25 +808,33 @@ Text Label 4500 2750 0 60 ~ 0
REL_1
Text Label 4500 2850 0 60 ~ 0
REL_2
Text Label 2400 2200 0 60 ~ 0
Text Label 2400 1900 0 60 ~ 0
TVP_PWDOWN
Text Label 2400 2300 0 60 ~ 0
Text Label 2400 2000 0 60 ~ 0
TVP_RESET
Text Label 2750 2400 2 60 ~ 0
Text Label 2750 2100 2 60 ~ 0
TVP_I2C
NoConn ~ 9900 1850
NoConn ~ 9900 1950
NoConn ~ 9900 2050
NoConn ~ 9900 5600
NoConn ~ 9900 5700
Text Label 2400 2500 0 60 ~ 0
Text Label 2400 2200 0 60 ~ 0
TVP_DATACLK
Text Label 2400 2600 0 60 ~ 0
Text Label 2400 2300 0 60 ~ 0
TVP_VSOUT
Text Label 2400 2700 0 60 ~ 0
Text Label 2400 2400 0 60 ~ 0
TVP_HSOUT
Text Label 2400 2800 0 60 ~ 0
Text Label 2400 2500 0 60 ~ 0
PIX[0..7]
Text Label 2450 5200 0 60 ~ 0
DIN_1
Text Label 2450 5350 0 60 ~ 0
DIN_2
Text Label 2450 5500 0 60 ~ 0
REL_1
Text Label 2450 5650 0 60 ~ 0
REL_2
Wire Wire Line
7150 1250 6850 1250
Wire Wire Line
......@@ -1135,19 +1153,19 @@ Wire Wire Line
Wire Wire Line
4950 2850 4450 2850
Wire Wire Line
2350 2200 2800 2200
2350 1900 2800 1900
Wire Wire Line
2350 2300 2800 2300
2350 2000 2800 2000
Wire Bus Line
2350 2400 2800 2400
2350 2100 2800 2100
Wire Wire Line
2350 2500 2800 2500
2350 2200 2800 2200
Wire Wire Line
2350 2600 2800 2600
2350 2300 2800 2300
Wire Wire Line
2350 2700 2800 2700
2350 2400 2800 2400
Wire Bus Line
2350 2800 2800 2800
2350 2500 2800 2500
Wire Wire Line
2350 5200 2800 5200
Wire Wire Line
......@@ -1156,12 +1174,44 @@ Wire Wire Line
2350 5500 2800 5500
Wire Wire Line
2350 5650 2800 5650
Text Label 2450 5200 0 60 ~ 0
DIN_1
Text Label 2450 5350 0 60 ~ 0
DIN_2
Text Label 2450 5500 0 60 ~ 0
REL_1
Text Label 2450 5650 0 60 ~ 0
REL_2
Wire Bus Line
2350 2950 2850 2950
Wire Bus Line
2350 3050 2850 3050
Wire Bus Line
2350 3150 2850 3150
Wire Wire Line
2350 3250 2850 3250
Wire Wire Line
2350 3650 2850 3650
Wire Wire Line
2350 3750 2850 3750
Text Label 2450 2950 0 60 ~ 0
SRAM_IO[0..7]
Text Label 2450 3050 0 60 ~ 0
SRAM_A[0..18]
Text Label 2450 3150 0 60 ~ 0
PIX[0..7]
Wire Bus Line
2350 3850 2850 3850
Wire Wire Line
2350 3350 2850 3350
Wire Wire Line
2350 3450 2850 3450
Wire Wire Line
2350 3550 2850 3550
Text Label 2450 3250 0 60 ~ 0
SRAM_OE
Text Label 2450 3350 0 60 ~ 0
TVP_HSOUT
Text Label 2450 3450 0 60 ~ 0
TVP_VSOUT
Text Label 2450 3550 0 60 ~ 0
TVP_DATACLK
Text Label 2450 3650 0 60 ~ 0
SRAM_WE
Text Label 2450 3750 0 60 ~ 0
SRAM_CE
Text Label 2450 3850 0 60 ~ 0
VBUF_SPI
$EndSCHEMATC
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