Commit fb592855 authored by Mike Lyons's avatar Mike Lyons

Now supporting reading data from vspi to cheetah usb/spi

parent ef91cf35
...@@ -41,10 +41,11 @@ module spiifc( ...@@ -41,10 +41,11 @@ module spiifc(
// Defines // Defines
`define CMD_READ_START 8'd1 `define CMD_READ_START 8'd1
`define CMD_READ_MORE 8'd2 `define CMD_READ_MORE 8'd2
`define CMD_WRITE_START 8'd3
`define STATE_GET_CMD 8'd0 `define STATE_GET_CMD 8'd0
`define STATE_READING 8'd1 `define STATE_READING 8'd1
`define STATE_WRITING 8'd2
// //
// Input/Output defs // Input/Output defs
...@@ -91,6 +92,9 @@ module spiifc( ...@@ -91,6 +92,9 @@ module spiifc(
reg [ 7: 0] cmd; reg [ 7: 0] cmd;
reg [ 7: 0] stateReg; reg [ 7: 0] stateReg;
reg [11: 0] txMemAddrReg;
reg [ 2: 0] txBitAddr;
// //
// Wires // Wires
// //
...@@ -105,18 +109,21 @@ module spiifc( ...@@ -105,18 +109,21 @@ module spiifc(
wire [ 7: 0] state; wire [ 7: 0] state;
wire txMemAddrReset;
// //
// Output assigns // Output assigns
// //
assign debug_out = debug_reg; assign debug_out = debug_reg;
assign SPI_MISO = 0;
assign txMemAddr = 0;
assign rcMemAddr = rcMemAddrReg; assign rcMemAddr = rcMemAddrReg;
assign rcMemData = rcMemDataReg; assign rcMemData = rcMemDataReg;
assign rcMemWE = rcMemWEReg; assign rcMemWE = rcMemWEReg;
assign txMemAddrReset = (rcByteValid && rcByte == `CMD_WRITE_START ? 1 : 0);
assign txMemAddr = (txMemAddrReset ? 0 : txMemAddrReg);
assign SPI_MISO = txMemData[txBitAddr];
assign ssFastToggle = assign ssFastToggle =
(ssPrev == 1 && SPI_SS == 0 ? ~ssFastToggleReg : ssFastToggleReg); (ssPrev == 1 && SPI_SS == 0 ? ~ssFastToggleReg : ssFastToggleReg);
...@@ -156,7 +163,6 @@ module spiifc( ...@@ -156,7 +163,6 @@ module spiifc(
always @(posedge SPI_CLK) begin always @(posedge SPI_CLK) begin
ssSlowToggle <= ssFastToggle; ssSlowToggle <= ssFastToggle;
if (Reset) begin if (Reset) begin
// Resetting // Resetting
...@@ -168,6 +174,7 @@ module spiifc( ...@@ -168,6 +174,7 @@ module spiifc(
end else begin end else begin
// Not resetting // Not resetting
ssTurnOnHandled <= ssTurnOn; ssTurnOnHandled <= ssTurnOn;
stateReg <= state; stateReg <= state;
rcMemAddrReg <= rcMemAddrNext; rcMemAddrReg <= rcMemAddrNext;
...@@ -176,6 +183,14 @@ module spiifc( ...@@ -176,6 +183,14 @@ module spiifc(
rcByteReg[rcBitIndex] <= SPI_MOSI; rcByteReg[rcBitIndex] <= SPI_MOSI;
rcBitIndexReg <= rcBitIndex - 3'd1; rcBitIndexReg <= rcBitIndex - 3'd1;
rcStarted <= 1; rcStarted <= 1;
// Update txBitAddr if writing out
if (`STATE_WRITING == state) begin
if (txBitAddr == 3'd1) begin
txMemAddrReg <= txMemAddr + 1;
end
txBitAddr <= txBitAddr - 1;
end
end end
// We've just received a byte (well, currently receiving the last bit) // We've just received a byte (well, currently receiving the last bit)
...@@ -192,12 +207,20 @@ module spiifc( ...@@ -192,12 +207,20 @@ module spiifc(
stateReg <= `STATE_READING; stateReg <= `STATE_READING;
end else if (`CMD_READ_MORE == rcByte) begin end else if (`CMD_READ_MORE == rcByte) begin
stateReg <= `STATE_READING; stateReg <= `STATE_READING;
end else if (`CMD_WRITE_START == rcByte) begin
txBitAddr <= 3'd7;
stateReg <= `STATE_WRITING;
txMemAddrReg <= txMemAddr; // Keep at 0
end end
end else if (`STATE_READING == state) begin end else if (`STATE_READING == state) begin
rcMemDataReg <= rcByte; rcMemDataReg <= rcByte;
rcMemAddrNext <= rcMemAddr + 1; rcMemAddrNext <= rcMemAddr + 1;
rcMemWEReg <= 1; rcMemWEReg <= 1;
// end else if (`STATE_WRITING == state) begin
// txBitAddr <= 3'd7;
// stateReg <= `STATE_WRITING;
end end
end else begin end else begin
......
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\ No newline at end of file
...@@ -4,10 +4,10 @@ ...@@ -4,10 +4,10 @@
// Company: // Company:
// Engineer: // Engineer:
// //
// Create Date: 19:46:21 10/18/2011 // Create Date: 11:08:12 02/15/2012
// Design Name: spiifc // Design Name: spiifc
// Module Name: C:/workspace/robobees/hbp/fpga/spiifc/spiifc_tb.v // Module Name: C:/workspace/robobees/hbp/fpga/spitest/pcores/spi_v1_00_a/hdl/verilog/spiifc_tb2.v
// Project Name: spiifc // Project Name: spi
// Target Device: // Target Device:
// Tool versions: // Tool versions:
// Description: // Description:
...@@ -26,73 +26,110 @@ module spiifc_tb; ...@@ -26,73 +26,110 @@ module spiifc_tb;
// Inputs // Inputs
reg Reset; reg Reset;
reg SysClk;
reg SPI_CLK; reg SPI_CLK;
reg SPI_MOSI; reg SPI_MOSI;
reg SPI_SS; reg SPI_SS;
reg [7:0] MemData; reg [7:0] txMemData;
// Outputs // Outputs
wire SPI_MISO; wire SPI_MISO;
wire [11:0] MemAddr; wire [11:0] txMemAddr;
wire [11:0] rcMemAddr;
wire [7:0] rcMemData;
wire rcMemWE;
wire [7:0] debug_out;
// Memory
reg [7:0] Mem [0:4095];
integer i;
// Instantiate the Unit Under Test (UUT) // Instantiate the Unit Under Test (UUT)
spiifc uut ( spiifc uut (
.Reset(Reset), .Reset(Reset),
.SysClk(SysClk),
.SPI_CLK(SPI_CLK), .SPI_CLK(SPI_CLK),
.SPI_MISO(SPI_MISO), .SPI_MISO(SPI_MISO),
.SPI_MOSI(SPI_MOSI), .SPI_MOSI(SPI_MOSI),
.SPI_SS(SPI_SS), .SPI_SS(SPI_SS),
.MemAddr(MemAddr), .txMemAddr(txMemAddr),
.MemData(MemData) .txMemData(txMemData),
.rcMemAddr(rcMemAddr),
.rcMemData(rcMemData),
.rcMemWE(rcMemWE),
.debug_out(debug_out)
); );
always @(posedge SPI_CLK) begin task recvByte;
MemData <= Mem[MemAddr]; input [7:0] rcByte;
end integer rcBitIndex;
begin
$display("%g - spiifc receiving byte '0x%h'", $time, rcByte);
for (rcBitIndex = 0; rcBitIndex < 8; rcBitIndex = rcBitIndex + 1) begin
SPI_MOSI = rcByte[7 - rcBitIndex];
#100;
end
end
endtask
always @(*) begin always begin
#50; #20 SysClk = ~SysClk;
SPI_CLK <= ~SPI_CLK;
end end
initial begin reg SPI_CLK_en;
// Initialize memory initial begin
for (i = 0; i < 4096; i = i + 2) begin #310
// Mem[i] <= i[7:0]; SPI_CLK_en = 1;
Mem[i] <= 8'hFF; end
Mem[i+1] <= 8'h00; always begin
#10
if (SPI_CLK_en) begin
#40 SPI_CLK = ~SPI_CLK;
end end
end
integer fdRcBytes;
integer fdTxBytes;
integer dummy;
integer currRcByte;
integer rcBytesNotEmpty;
reg [8*10:1] rcBytesStr;
initial begin
// Initialize Inputs // Initialize Inputs
Reset = 0; Reset = 0;
SysClk = 0;
SPI_CLK = 0; SPI_CLK = 0;
SPI_CLK_en = 0;
SPI_MOSI = 0; SPI_MOSI = 0;
SPI_SS = 1; SPI_SS = 1;
txMemData = 0;
// Wait 100 ns for global reset to finish // Wait 100 ns for global reset to finish
#100; #100;
Reset = 1;
// Add stimulus here
Reset <= 1'b1;
#100;
Reset <= 1'b0;
#100; #100;
Reset = 0;
SPI_SS <= 1'b0; #100;
#4000;
// Add stimulus here
SPI_SS = 0;
// For each byte, transmit its bits
fdRcBytes = $fopen("rc-bytes-tx-test.txt", "r");
rcBytesNotEmpty = 1;
while (rcBytesNotEmpty) begin
rcBytesNotEmpty = $fgets(rcBytesStr, fdRcBytes);
if (rcBytesNotEmpty) begin
dummy = $sscanf(rcBytesStr, "%x", currRcByte);
recvByte(currRcByte);
end
end
SPI_SS <= 1'b1; // Wrap it up.
#400; SPI_SS = 1;
#1000;
$finish; $finish;
end end
endmodule endmodule
...@@ -86,6 +86,7 @@ module spiifc_tb2; ...@@ -86,6 +86,7 @@ module spiifc_tb2;
end end
integer fdRcBytes; integer fdRcBytes;
integer fdTxBytes;
integer dummy; integer dummy;
integer currRcByte; integer currRcByte;
integer rcBytesNotEmpty; integer rcBytesNotEmpty;
......
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