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rasky
vSPI
Commits
fb592855
Commit
fb592855
authored
Feb 24, 2012
by
Mike Lyons
Browse files
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Plain Diff
Now supporting reading data from vspi to cheetah usb/spi
parent
ef91cf35
Changes
4
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4 changed files
with
111 additions
and
41 deletions
+111
-41
spiifc.v
src/spi_base/spiifc.v
+28
-5
rc-bytes-tx-test.txt
test/spi_base/rc-bytes-tx-test.txt
+9
-0
spiifc_tb.v
test/spi_base/spiifc_tb.v
+73
-36
spiifc_tb2.v
test/spi_base/spiifc_tb2.v
+1
-0
No files found.
src/spi_base/spiifc.v
View file @
fb592855
...
...
@@ -41,10 +41,11 @@ module spiifc(
// Defines
`define
CMD_READ_START 8
'
d1
`define
CMD_READ_MORE 8
'
d2
`define
CMD_WRITE_START 8
'
d3
`define
STATE_GET_CMD 8
'
d0
`define
STATE_READING 8
'
d1
`define
STATE_WRITING 8
'
d2
//
// Input/Output defs
...
...
@@ -91,6 +92,9 @@ module spiifc(
reg
[
7
:
0
]
cmd
;
reg
[
7
:
0
]
stateReg
;
reg
[
11
:
0
]
txMemAddrReg
;
reg
[
2
:
0
]
txBitAddr
;
//
// Wires
//
...
...
@@ -105,18 +109,21 @@ module spiifc(
wire
[
7
:
0
]
state
;
wire
txMemAddrReset
;
//
// Output assigns
//
assign
debug_out
=
debug_reg
;
assign
SPI_MISO
=
0
;
assign
txMemAddr
=
0
;
assign
rcMemAddr
=
rcMemAddrReg
;
assign
rcMemData
=
rcMemDataReg
;
assign
rcMemWE
=
rcMemWEReg
;
assign
txMemAddrReset
=
(
rcByteValid
&&
rcByte
==
`CMD_WRITE_START
?
1
:
0
)
;
assign
txMemAddr
=
(
txMemAddrReset
?
0
:
txMemAddrReg
)
;
assign
SPI_MISO
=
txMemData
[
txBitAddr
]
;
assign
ssFastToggle
=
(
ssPrev
==
1
&&
SPI_SS
==
0
?
~
ssFastToggleReg
:
ssFastToggleReg
)
;
...
...
@@ -156,7 +163,6 @@ module spiifc(
always
@
(
posedge
SPI_CLK
)
begin
ssSlowToggle
<=
ssFastToggle
;
if
(
Reset
)
begin
// Resetting
...
...
@@ -168,6 +174,7 @@ module spiifc(
end
else
begin
// Not resetting
ssTurnOnHandled
<=
ssTurnOn
;
stateReg
<=
state
;
rcMemAddrReg
<=
rcMemAddrNext
;
...
...
@@ -176,6 +183,14 @@ module spiifc(
rcByteReg
[
rcBitIndex
]
<=
SPI_MOSI
;
rcBitIndexReg
<=
rcBitIndex
-
3'd1
;
rcStarted
<=
1
;
// Update txBitAddr if writing out
if
(
`STATE_WRITING
==
state
)
begin
if
(
txBitAddr
==
3'd1
)
begin
txMemAddrReg
<=
txMemAddr
+
1
;
end
txBitAddr
<=
txBitAddr
-
1
;
end
end
// We've just received a byte (well, currently receiving the last bit)
...
...
@@ -192,12 +207,20 @@ module spiifc(
stateReg
<=
`STATE_READING
;
end
else
if
(
`CMD_READ_MORE
==
rcByte
)
begin
stateReg
<=
`STATE_READING
;
end
else
if
(
`CMD_WRITE_START
==
rcByte
)
begin
txBitAddr
<=
3'd7
;
stateReg
<=
`STATE_WRITING
;
txMemAddrReg
<=
txMemAddr
;
// Keep at 0
end
end
else
if
(
`STATE_READING
==
state
)
begin
rcMemDataReg
<=
rcByte
;
rcMemAddrNext
<=
rcMemAddr
+
1
;
rcMemWEReg
<=
1
;
// end else if (`STATE_WRITING == state) begin
// txBitAddr <= 3'd7;
// stateReg <= `STATE_WRITING;
end
end
else
begin
...
...
test/spi_base/rc-bytes-tx-test.txt
0 → 100644
View file @
fb592855
03
00
00
00
00
00
00
00
00
\ No newline at end of file
test/spi_base/spiifc_tb.v
View file @
fb592855
...
...
@@ -4,10 +4,10 @@
// Company:
// Engineer:
//
// Create Date: 1
9:46:21 10/18/2011
// Create Date: 1
1:08:12 02/15/2012
// Design Name: spiifc
// Module Name: C:/workspace/robobees/hbp/fpga/spi
ifc/spiifc_tb
.v
// Project Name: spi
ifc
// Module Name: C:/workspace/robobees/hbp/fpga/spi
test/pcores/spi_v1_00_a/hdl/verilog/spiifc_tb2
.v
// Project Name: spi
// Target Device:
// Tool versions:
// Description:
...
...
@@ -26,73 +26,110 @@ module spiifc_tb;
// Inputs
reg
Reset
;
reg
SysClk
;
reg
SPI_CLK
;
reg
SPI_MOSI
;
reg
SPI_SS
;
reg
[
7
:
0
]
MemData
;
reg
[
7
:
0
]
tx
MemData
;
// Outputs
wire
SPI_MISO
;
wire
[
11
:
0
]
MemAddr
;
wire
[
11
:
0
]
txMemAddr
;
wire
[
11
:
0
]
rcMemAddr
;
wire
[
7
:
0
]
rcMemData
;
wire
rcMemWE
;
wire
[
7
:
0
]
debug_out
;
// Memory
reg
[
7
:
0
]
Mem
[
0
:
4095
]
;
integer
i
;
// Instantiate the Unit Under Test (UUT)
spiifc
uut
(
.
Reset
(
Reset
)
,
.
SysClk
(
SysClk
)
,
.
SPI_CLK
(
SPI_CLK
)
,
.
SPI_MISO
(
SPI_MISO
)
,
.
SPI_MOSI
(
SPI_MOSI
)
,
.
SPI_SS
(
SPI_SS
)
,
.
MemAddr
(
MemAddr
)
,
.
MemData
(
MemData
)
.
SPI_SS
(
SPI_SS
)
,
.
txMemAddr
(
txMemAddr
)
,
.
txMemData
(
txMemData
)
,
.
rcMemAddr
(
rcMemAddr
)
,
.
rcMemData
(
rcMemData
)
,
.
rcMemWE
(
rcMemWE
)
,
.
debug_out
(
debug_out
)
)
;
always
@
(
posedge
SPI_CLK
)
begin
MemData
<=
Mem
[
MemAddr
]
;
end
task
recvByte
;
input
[
7
:
0
]
rcByte
;
integer
rcBitIndex
;
begin
$
display
(
"%g - spiifc receiving byte '0x%h'"
,
$
time
,
rcByte
)
;
for
(
rcBitIndex
=
0
;
rcBitIndex
<
8
;
rcBitIndex
=
rcBitIndex
+
1
)
begin
SPI_MOSI
=
rcByte
[
7
-
rcBitIndex
]
;
#
100
;
end
end
endtask
always
@
(
*
)
begin
#
50
;
SPI_CLK
<=
~
SPI_CLK
;
always
begin
#
20
SysClk
=
~
SysClk
;
end
initial
begin
// Initialize memory
for
(
i
=
0
;
i
<
4096
;
i
=
i
+
2
)
begin
// Mem[i] <= i[7:0];
Mem
[
i
]
<=
8'hFF
;
Mem
[
i
+
1
]
<=
8'h00
;
reg
SPI_CLK_en
;
initial
begin
#
310
SPI_CLK_en
=
1
;
end
always
begin
#
10
if
(
SPI_CLK_en
)
begin
#
40
SPI_CLK
=
~
SPI_CLK
;
end
end
integer
fdRcBytes
;
integer
fdTxBytes
;
integer
dummy
;
integer
currRcByte
;
integer
rcBytesNotEmpty
;
reg
[
8
*
10
:
1
]
rcBytesStr
;
initial
begin
// Initialize Inputs
Reset
=
0
;
SysClk
=
0
;
SPI_CLK
=
0
;
SPI_CLK_en
=
0
;
SPI_MOSI
=
0
;
SPI_SS
=
1
;
txMemData
=
0
;
// Wait 100 ns for global reset to finish
#
100
;
// Add stimulus here
Reset
<=
1'b1
;
#
100
;
Reset
=
1
;
Reset
<=
1'b0
;
#
100
;
Reset
=
0
;
SPI_SS
<=
1'b0
;
#
4000
;
#
100
;
// Add stimulus here
SPI_SS
=
0
;
// For each byte, transmit its bits
fdRcBytes
=
$
fopen
(
"rc-bytes-tx-test.txt"
,
"r"
)
;
rcBytesNotEmpty
=
1
;
while
(
rcBytesNotEmpty
)
begin
rcBytesNotEmpty
=
$
fgets
(
rcBytesStr
,
fdRcBytes
)
;
if
(
rcBytesNotEmpty
)
begin
dummy
=
$
sscanf
(
rcBytesStr
,
"%x"
,
currRcByte
)
;
recvByte
(
currRcByte
)
;
end
end
SPI_SS
<=
1'b1
;
#
400
;
// Wrap it up.
SPI_SS
=
1
;
#
1000
;
$
finish
;
end
endmodule
test/spi_base/spiifc_tb2.v
View file @
fb592855
...
...
@@ -86,6 +86,7 @@ module spiifc_tb2;
end
integer
fdRcBytes
;
integer
fdTxBytes
;
integer
dummy
;
integer
currRcByte
;
integer
rcBytesNotEmpty
;
...
...
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