Skip to content

V
vSPI
Commit c6e2ce64 authored by Mike Lyons's avatar Mike Lyons
Browse files
Options

Fastclock now working (appears to at least) at 3mbps

parent fba24c05
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 798 additions and 95 deletions
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/fuseRelaunch.cmd
View file @ c6e2ce64
-intstyle "ise" -incremental -lib "unisims_ver" -lib "unimacro_ver" -lib "xilinxcorelib_ver" -lib "secureip" -o "C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc_tb_isim_beh.exe" -prj "C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc_tb_beh.prj" "work.spiifc_tb" "work.glbl"
-intstyle "ise" -incremental -lib "unisims_ver" -lib "unimacro_ver" -lib "xilinxcorelib_ver" -lib "secureip" -o "C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc_tb2_isim_beh.exe" -prj "C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc_tb2_beh.prj" "work.spiifc_tb2" "work.glbl"
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/iseconfig/spiifc.projectmgr
View file @ c6e2ce64
......@@ -11,13 +11,13 @@
<ClosedNode>/spiifc - IMP C:|Users|mjlyons|workspace|vSPI|projnav|xps|pcores|spiifc_v1_00_a|hdl|vhdl|spiifc.vhd/PLBV46_SLAVE_BURST_I - plbv46_slave_burst - implementation/I_SLAVE_ATTACHMENT - plb_slave_attachment - implementation</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem>spiifc_tb2 (C:/Users/mjlyons/workspace/vSPI/test/spi_base/spiifc_tb2.v)</SelectedItem>
<SelectedItem>spiwrap (C:/Users/mjlyons/workspace/vSPI/src/spi_base/spiwrap.v)</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000225000000020000000000000000000000000200000064ffffffff000000810000000300000002000002250000000100000003000000000000000100000003</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
<CurrentItem>spiifc_tb2 (C:/Users/mjlyons/workspace/vSPI/test/spi_base/spiifc_tb2.v)</CurrentItem>
<CurrentItem>spiwrap (C:/Users/mjlyons/workspace/vSPI/src/spi_base/spiwrap.v)</CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
<ClosedNodes>
......@@ -88,13 +88,13 @@
<ClosedNode>User Constraints</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem></SelectedItem>
<SelectedItem>Manage Configuration Project (iMPACT)</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f8000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem>
<CurrentItem>Manage Configuration Project (iMPACT)</CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_XCO" guiview="Process" >
<ClosedNodes>
......@@ -115,18 +115,15 @@
<ClosedNodes>
<ClosedNodesVersion>2</ClosedNodesVersion>
<ClosedNode>/spiifc - IMP C:|Users|mjlyons|workspace|vSPI|projnav|xps|pcores|spiifc_v1_00_a|hdl|vhdl|spiifc.vhd</ClosedNode>
<ClosedNode>/spiifc_tb C:|Users|mjlyons|workspace|vSPI|test|spi_base|spiifc_tb.v</ClosedNode>
<ClosedNode>/spiifc_tb2 C:|Users|mjlyons|workspace|vSPI|test|spi_base|spiifc_tb2.v</ClosedNode>
<ClosedNode>/spiwrap C:|Users|mjlyons|workspace|vSPI|src|spi_base|spiwrap.v</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem>spiifc_tb (C:/Users/mjlyons/workspace/vSPI/test/spi_base/spiifc_tb.v)</SelectedItem>
<SelectedItem>spiifc_tb2 (C:/Users/mjlyons/workspace/vSPI/test/spi_base/spiifc_tb2.v)</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000000be000000020000000000000000000000000200000064ffffffff000000810000000300000002000000be0000000100000003000000000000000100000003</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>spiifc_tb (C:/Users/mjlyons/workspace/vSPI/test/spi_base/spiifc_tb.v)</CurrentItem>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000133000000020000000000000000000000000200000064ffffffff000000810000000300000002000001330000000100000003000000000000000100000003</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
<CurrentItem>spiifc_tb2 (C:/Users/mjlyons/workspace/vSPI/test/spi_base/spiifc_tb2.v)</CurrentItem>
</ItemView>
<ItemView engineview="BehavioralSim" sourcetype="" guiview="Process" >
<ClosedNodes>
......
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/iseconfig/spiifc.xreport
View file @ c6e2ce64
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2012-03-07T09:22:38</DateModified>
<ModuleName>spiifc</ModuleName>
<SummaryTimeStamp>2012-03-06T18:02:57</SummaryTimeStamp>
<DateModified>2012-03-07T12:09:17</DateModified>
<ModuleName>spiwrap</ModuleName>
<SummaryTimeStamp>2012-03-07T10:02:06</SummaryTimeStamp>
<SavedFilePath>C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/iseconfig/spiifc.xreport</SavedFilePath>
<ImplementationReportsDirectory>C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav\</ImplementationReportsDirectory>
<DateInitialized>2012-03-06T14:46:14</DateInitialized>
<DateInitialized>2012-03-07T09:46:20</DateInitialized>
<EnableMessageFiltering>false</EnableMessageFiltering>
</header>
<body>
......
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/iseconfig/spiwrap.xreport
View file @ c6e2ce64
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2012-03-06T15:48:54</DateModified>
<ModuleName>spiifc</ModuleName>
<SummaryTimeStamp>Unknown</SummaryTimeStamp>
<DateModified>2012-03-07T16:13:02</DateModified>
<ModuleName>spiwrap</ModuleName>
<SummaryTimeStamp>2012-03-07T14:29:36</SummaryTimeStamp>
<SavedFilePath>C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/iseconfig/spiwrap.xreport</SavedFilePath>
<ImplementationReportsDirectory>C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav\</ImplementationReportsDirectory>
<DateInitialized>2012-03-06T15:48:54</DateInitialized>
......
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/par_usage_statistics.html
View file @ c6e2ce64
<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<xtag-section name="ParStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>Par Statistics</B></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>152</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>555</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>555</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>412</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>5.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>6.1 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>32</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>141</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>141</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>128</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>5.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>6.7 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>7.0 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>8.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>9.0 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>9.0 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>9.0 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>9.0 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>9.0 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>9.0 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>4.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>9.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>3.7</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>1.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>3.2</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>3.9</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>8.6 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>8.7 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>8.7 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>8.7 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>8.7 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>8.7 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>8.7 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>11.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>11.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>3.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>19.6</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>1.7</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0147</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0036</xtag-par-property-value></TD></TR>
</xtag-section>
</TABLE>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc.gise
View file @ c6e2ce64
......@@ -27,7 +27,7 @@
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1331066936" xil_pn:in_ck="-8467753332869629521" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1331066936">
<transform xil_pn:end_ts="1331148521" xil_pn:in_ck="-8467753332869629521" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1331148521">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
......
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiwrap_summary.html → projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc_summary.html
View file @ c6e2ce64
......@@ -2,7 +2,7 @@
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>spiifc Project Status</B></TD></TR>
<TD ALIGN=CENTER COLSPAN='4'><B>spiwrap Project Status</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>spiifc.xise</TD>
......@@ -10,7 +10,7 @@
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
<TD>spiifc</TD>
<TD>spiwrap</TD>
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
<TD>New</TD>
</TR>
......@@ -74,5 +74,5 @@
</TABLE>
<br><center><b>Date Generated:</b> 03/07/2012 - 09:22:39</center>
<br><center><b>Date Generated:</b> 03/07/2012 - 16:13:02</center>
</BODY></HTML>
\ No newline at end of file
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/tb2_fastclock.wcfg 0 → 100644
View file @ c6e2ce64
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc_tb2_isim_beh.wdb" id="1" type="auto">
<top_modules>
<top_module name="glbl" />
<top_module name="spiifc_tb2" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="23" />
<wvobject fp_name="/spiifc_tb2/SPI_MISO" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SPI_MISO</obj_property>
<obj_property name="ObjectShortName">SPI_MISO</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/txMemAddr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">txMemAddr[11:0]</obj_property>
<obj_property name="ObjectShortName">txMemAddr[11:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/rcMemAddr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">rcMemAddr[11:0]</obj_property>
<obj_property name="ObjectShortName">rcMemAddr[11:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/rcMemData" type="array" db_ref_id="1">
<obj_property name="ElementShortName">rcMemData[7:0]</obj_property>
<obj_property name="ObjectShortName">rcMemData[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/rcMemWE" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rcMemWE</obj_property>
<obj_property name="ObjectShortName">rcMemWE</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/debug_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">debug_out[7:0]</obj_property>
<obj_property name="ObjectShortName">debug_out[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/Reset" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">Reset</obj_property>
<obj_property name="ObjectShortName">Reset</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/SysClk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SysClk</obj_property>
<obj_property name="ObjectShortName">SysClk</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/SPI_CLK" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SPI_CLK</obj_property>
<obj_property name="ObjectShortName">SPI_CLK</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/SPI_MOSI" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SPI_MOSI</obj_property>
<obj_property name="ObjectShortName">SPI_MOSI</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/SPI_SS" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SPI_SS</obj_property>
<obj_property name="ObjectShortName">SPI_SS</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/txMemData" type="array" db_ref_id="1">
<obj_property name="ElementShortName">txMemData[7:0]</obj_property>
<obj_property name="ObjectShortName">txMemData[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/SPI_CLK_en" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SPI_CLK_en</obj_property>
<obj_property name="ObjectShortName">SPI_CLK_en</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/fdRcBytes" type="array" db_ref_id="1">
<obj_property name="ElementShortName">fdRcBytes[31:0]</obj_property>
<obj_property name="ObjectShortName">fdRcBytes[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/fdTxBytes" type="array" db_ref_id="1">
<obj_property name="ElementShortName">fdTxBytes[31:0]</obj_property>
<obj_property name="ObjectShortName">fdTxBytes[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/dummy" type="array" db_ref_id="1">
<obj_property name="ElementShortName">dummy[31:0]</obj_property>
<obj_property name="ObjectShortName">dummy[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/currRcByte" type="array" db_ref_id="1">
<obj_property name="ElementShortName">currRcByte[31:0]</obj_property>
<obj_property name="ObjectShortName">currRcByte[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/rcBytesNotEmpty" type="array" db_ref_id="1">
<obj_property name="ElementShortName">rcBytesNotEmpty[31:0]</obj_property>
<obj_property name="ObjectShortName">rcBytesNotEmpty[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/rcBytesStr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">rcBytesStr[80:1]</obj_property>
<obj_property name="ObjectShortName">rcBytesStr[80:1]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/uut/rcByteValid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rcByteValid</obj_property>
<obj_property name="ObjectShortName">rcByteValid</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/uut/rcByte" type="array" db_ref_id="1">
<obj_property name="ElementShortName">rcByte[7:0]</obj_property>
<obj_property name="ObjectShortName">rcByte[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/uut/rcBitIndex" type="array" db_ref_id="1">
<obj_property name="ElementShortName">rcBitIndex[2:0]</obj_property>
<obj_property name="ObjectShortName">rcBitIndex[2:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/uut/state" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">state</obj_property>
<obj_property name="ObjectShortName">state</obj_property>
</wvobject>
</wave_config>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/webtalk_impact.xml
View file @ c6e2ce64
......@@ -3,9 +3,9 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="impact" timeStamp="Tue Mar 06 15:24:19 2012">
<application name="impact" timeStamp="Wed Mar 07 14:31:40 2012">
<section name="Project Information" visible="false">
<property name="ProjectID" value="5ea5de4132cd436698ae1e90d83ce606"/>
<property name="ProjectID" value="da00646f0b4c4ac8baf5d51b1868f1e8"/>
<property name="ProjectIteration" value="1"/>
</section>
<section name="iMPACT Project Info" visible="true">
......@@ -27,10 +27,6 @@ This means code written to parse this file will need to be revisited each subseq
<item name="Boundary Scan Operations Statistics">
<property name="BSCAN Operation" value="Program -p 0
"/>
<property name="BSCAN Operation" value="Program -p 0
"/>
<property name="BSCAN Operation" value="Program -p 0
"/>
</item>
<item name="Cable Summary">
<property name="Cable Type" value="Platform Cable USB"/>
......
src/spi_base/spiifc.v
View file @ c6e2ce64
......@@ -71,13 +71,19 @@ output [7:0] debug_out;
//
// Registers
//
reg SPI_CLK_reg; // Stabalized version of SPI_CLK
reg SPI_CLK_reg1;
reg SPI_SS_reg; // Stabalized version of SPI_SS
reg SPI_SS_reg1;
reg SPI_MOSI_reg; // Stabalized version of SPI_MOSI
reg SPI_MOSI_reg1;
reg prev_spiClk; // Value of SPI_CLK during last SysClk cycle
reg prev_spiSS; // Value of SPI_SS during last SysClk cycle
reg [7:0] state_reg; // Register backing the 'state' wire
reg [7:0] rcByte_reg; // Register backing 'rcByte'
reg [2:0] rcBitIndex_reg; // Register backing 'rcBitIndex'
reg [AddrBits-1:0] rcMemAddr_reg; // Byte addr to write MOSI data to
reg [7:0] debug_reg; // register backing debug_out signal
//
// Wires
//
......@@ -88,30 +94,40 @@ wire rcByteValid; // rcByte is valid and new
wire [7:0] rcByte; // Byte received from master
wire [2:0] rcBitIndex; // Bit of rcByte to write to next
// Save buffered SPI inputs
always @(posedge SysClk) begin
SPI_CLK_reg1 <= SPI_CLK;
SPI_CLK_reg <= SPI_CLK_reg1;
SPI_SS_reg1 <= SPI_SS;
SPI_SS_reg <= SPI_SS_reg1;
SPI_MOSI_reg1 <= SPI_MOSI;
SPI_MOSI_reg <= SPI_MOSI_reg1;
end
// Detect new valid bit
always @(posedge SysClk) begin
prev_spiClk <= SPI_CLK;
prev_spiClk <= SPI_CLK_reg;
end
assign risingSpiClk = SPI_CLK & (~prev_spiClk);
assign validSpiBit = risingSpiClk & (~SPI_SS);
assign risingSpiClk = SPI_CLK_reg & (~prev_spiClk);
assign validSpiBit = risingSpiClk & (~SPI_SS_reg);
// Detect new SPI packet (SS dropped low)
always @(posedge SysClk) begin
prev_spiSS <= SPI_SS;
prev_spiSS <= SPI_SS_reg;
end
assign packetStart = prev_spiSS & (~SPI_SS);
assign packetStart = prev_spiSS & (~SPI_SS_reg);
// Build incoming byte
always @(posedge SysClk) begin
if (validSpiBit) begin
rcByte_reg[rcBitIndex] <= SPI_MOSI;
rcByte_reg[rcBitIndex] <= SPI_MOSI_reg;
rcBitIndex_reg <= (rcBitIndex > 0 ? rcBitIndex - 1 : 7);
end else begin
rcBitIndex_reg <= rcBitIndex;
end
end
assign rcBitIndex = (Reset || packetStart ? 7 : rcBitIndex_reg);
assign rcByte = {rcByte_reg[7:1], SPI_MOSI};
assign rcByte = {rcByte_reg[7:1], SPI_MOSI_reg};
assign rcByteValid = (validSpiBit && rcBitIndex == 0 ? 1 : 0);
// Incoming MOSI data buffer management
......@@ -128,6 +144,10 @@ always @(posedge SysClk) begin
end
end
// Outgoing MISO data buffer management
// TODO: implement
assign SPI_MISO = 1'b0;
// State machine
always @(*) begin
if (Reset || packetStart) begin
......@@ -157,4 +177,12 @@ always @(posedge SysClk) begin
end
end
// Debugging
always @(posedge SysClk) begin
if (rcByteValid) begin
debug_reg <= rcByte;
end
end
assign debug_out = debug_reg;
endmodule
src/spi_base/spiwrap.v
View file @ c6e2ce64
......@@ -108,6 +108,6 @@ spiifc mySpiIfc (
.debug_out(debug_out)
);
assign leds = /*rcMem_douta[31:24]*/ debug_out;
assign leds = /* rcMem_douta[7:0] */ debug_out ;
endmodule
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment