Fastclock now working (appears to at least) at 3mbps

projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/fuseRelaunch.cmd

--intstyle "ise" -incremental -lib "unisims_ver" -lib "unimacro_ver" -lib "xilinxcorelib_ver" -lib "secureip" -o "C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc_tb_isim_beh.exe" -prj "C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc_tb_beh.prj" "work.spiifc_tb" "work.glbl" 
+-intstyle "ise" -incremental -lib "unisims_ver" -lib "unimacro_ver" -lib "xilinxcorelib_ver" -lib "secureip" -o "C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc_tb2_isim_beh.exe" -prj "C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc_tb2_beh.prj" "work.spiifc_tb2" "work.glbl" 

projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/iseconfig/spiifc.projectmgr

@@ -11,13 +11,13 @@
          <ClosedNode>/spiifc - IMP C:|Users|mjlyons|workspace|vSPI|projnav|xps|pcores|spiifc_v1_00_a|hdl|vhdl|spiifc.vhd/PLBV46_SLAVE_BURST_I - plbv46_slave_burst - implementation/I_SLAVE_ATTACHMENT - plb_slave_attachment - implementation</ClosedNode>
       </ClosedNodes>
       <SelectedItems>
-         <SelectedItem>spiifc_tb2 (C:/Users/mjlyons/workspace/vSPI/test/spi_base/spiifc_tb2.v)</SelectedItem>
+         <SelectedItem>spiwrap (C:/Users/mjlyons/workspace/vSPI/src/spi_base/spiwrap.v)</SelectedItem>
       </SelectedItems>
       <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
       <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
       <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000225000000020000000000000000000000000200000064ffffffff000000810000000300000002000002250000000100000003000000000000000100000003</ViewHeaderState>
       <UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
-      <CurrentItem>spiifc_tb2 (C:/Users/mjlyons/workspace/vSPI/test/spi_base/spiifc_tb2.v)</CurrentItem>
+      <CurrentItem>spiwrap (C:/Users/mjlyons/workspace/vSPI/src/spi_base/spiwrap.v)</CurrentItem>
    </ItemView>
    <ItemView engineview="SynthesisOnly" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
       <ClosedNodes>
@@ -88,13 +88,13 @@
          <ClosedNode>User Constraints</ClosedNode>
       </ClosedNodes>
       <SelectedItems>
-         <SelectedItem></SelectedItem>
+         <SelectedItem>Manage Configuration Project (iMPACT)</SelectedItem>
       </SelectedItems>
       <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
       <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
       <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f8000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000</ViewHeaderState>
       <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
-      <CurrentItem></CurrentItem>
+      <CurrentItem>Manage Configuration Project (iMPACT)</CurrentItem>
    </ItemView>
    <ItemView engineview="SynthesisOnly" sourcetype="DESUT_XCO" guiview="Process" >
       <ClosedNodes>
@@ -115,18 +115,15 @@
       <ClosedNodes>
          <ClosedNodesVersion>2</ClosedNodesVersion>
          <ClosedNode>/spiifc - IMP C:|Users|mjlyons|workspace|vSPI|projnav|xps|pcores|spiifc_v1_00_a|hdl|vhdl|spiifc.vhd</ClosedNode>
-         <ClosedNode>/spiifc_tb C:|Users|mjlyons|workspace|vSPI|test|spi_base|spiifc_tb.v</ClosedNode>
-         <ClosedNode>/spiifc_tb2 C:|Users|mjlyons|workspace|vSPI|test|spi_base|spiifc_tb2.v</ClosedNode>
-         <ClosedNode>/spiwrap C:|Users|mjlyons|workspace|vSPI|src|spi_base|spiwrap.v</ClosedNode>
       </ClosedNodes>
       <SelectedItems>
-         <SelectedItem>spiifc_tb (C:/Users/mjlyons/workspace/vSPI/test/spi_base/spiifc_tb.v)</SelectedItem>
+         <SelectedItem>spiifc_tb2 (C:/Users/mjlyons/workspace/vSPI/test/spi_base/spiifc_tb2.v)</SelectedItem>
       </SelectedItems>
       <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
       <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
-      <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000000be000000020000000000000000000000000200000064ffffffff000000810000000300000002000000be0000000100000003000000000000000100000003</ViewHeaderState>
-      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
-      <CurrentItem>spiifc_tb (C:/Users/mjlyons/workspace/vSPI/test/spi_base/spiifc_tb.v)</CurrentItem>
+      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000133000000020000000000000000000000000200000064ffffffff000000810000000300000002000001330000000100000003000000000000000100000003</ViewHeaderState>
+      <UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
+      <CurrentItem>spiifc_tb2 (C:/Users/mjlyons/workspace/vSPI/test/spi_base/spiifc_tb2.v)</CurrentItem>
    </ItemView>
    <ItemView engineview="BehavioralSim" sourcetype="" guiview="Process" >
       <ClosedNodes>

projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/iseconfig/spiifc.xreport

 <?xml version='1.0' encoding='UTF-8'?>
 <report-views version="2.0" >
  <header>
-  <DateModified>2012-03-07T09:22:38</DateModified>
-  <ModuleName>spiifc</ModuleName>
-  <SummaryTimeStamp>2012-03-06T18:02:57</SummaryTimeStamp>
+  <DateModified>2012-03-07T12:09:17</DateModified>
+  <ModuleName>spiwrap</ModuleName>
+  <SummaryTimeStamp>2012-03-07T10:02:06</SummaryTimeStamp>
   <SavedFilePath>C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/iseconfig/spiifc.xreport</SavedFilePath>
   <ImplementationReportsDirectory>C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav\</ImplementationReportsDirectory>
-  <DateInitialized>2012-03-06T14:46:14</DateInitialized>
+  <DateInitialized>2012-03-07T09:46:20</DateInitialized>
   <EnableMessageFiltering>false</EnableMessageFiltering>
  </header>
  <body>

projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/iseconfig/spiwrap.xreport

 <?xml version='1.0' encoding='UTF-8'?>
 <report-views version="2.0" >
  <header>
-  <DateModified>2012-03-06T15:48:54</DateModified>
-  <ModuleName>spiifc</ModuleName>
-  <SummaryTimeStamp>Unknown</SummaryTimeStamp>
+  <DateModified>2012-03-07T16:13:02</DateModified>
+  <ModuleName>spiwrap</ModuleName>
+  <SummaryTimeStamp>2012-03-07T14:29:36</SummaryTimeStamp>
   <SavedFilePath>C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/iseconfig/spiwrap.xreport</SavedFilePath>
   <ImplementationReportsDirectory>C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav\</ImplementationReportsDirectory>
   <DateInitialized>2012-03-06T15:48:54</DateInitialized>

projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/par_usage_statistics.html

 <TABLE BORDER CELLSPACING=0 WIDTH='100%'>
 <xtag-section name="ParStatistics">
 <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>Par Statistics</B></TD></TR>
-<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>152</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>555</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>555</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>412</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>5.4 sec</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>6.1 sec</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>32</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>141</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>141</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>128</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>5.8 sec</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>6.7 sec</xtag-par-property-value></TD></TR>
 <TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>7.0 sec</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>8.8 sec</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>9.0 sec</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>9.0 sec</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>9.0 sec</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>9.0 sec</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>9.0 sec</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>9.0 sec</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>4.0</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>9.0</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>3.7</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>1.0</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>3.2</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>3.9</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>8.6 sec</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>8.7 sec</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>8.7 sec</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>8.7 sec</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>8.7 sec</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>8.7 sec</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>8.7 sec</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>11.0</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>11.0</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>3.0</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>19.6</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>1.7</xtag-par-property-value></TD></TR>
 <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
 <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
 <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
 <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
 <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
 <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0147</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0036</xtag-par-property-value></TD></TR>
 </xtag-section>
 </TABLE>

projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc.gise

@@ -27,7 +27,7 @@
   </files>
 
   <transforms xmlns="http://www.xilinx.com/XMLSchema">
-    <transform xil_pn:end_ts="1331066936" xil_pn:in_ck="-8467753332869629521" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1331066936">
+    <transform xil_pn:end_ts="1331148521" xil_pn:in_ck="-8467753332869629521" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1331148521">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>

projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc.xise

@@ -17,117 +17,117 @@
   <files>
     <file xil_pn:name="../../hdl/vhdl/spiifc.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="../../hdl/verilog/user_logic.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/proc_common_pkg.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
       <library xil_pn:name="proc_common_v3_00_a"/>
     </file>
     <file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ipif_pkg.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
       <library xil_pn:name="proc_common_v3_00_a"/>
     </file>
     <file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_muxcy.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
       <library xil_pn:name="proc_common_v3_00_a"/>
     </file>
     <file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_gate128.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
       <library xil_pn:name="proc_common_v3_00_a"/>
     </file>
     <file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/family_support.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
       <library xil_pn:name="proc_common_v3_00_a"/>
     </file>
     <file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
       <library xil_pn:name="proc_common_v3_00_a"/>
     </file>
     <file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter_f.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
       <library xil_pn:name="proc_common_v3_00_a"/>
     </file>
     <file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/flex_addr_cntr.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
       <library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
     </file>
     <file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/addr_reg_cntr_brst_flex.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
       <library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
     </file>
     <file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plb_address_decoder.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
       <library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
     </file>
     <file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/burst_support.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
       <library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
     </file>
     <file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/wr_buffer.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
       <library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
     </file>
     <file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/be_reset_gen.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
       <library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
     </file>
     <file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plb_slave_attachment.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
       <library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
     </file>
     <file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/data_mirror_128.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
       <library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
     </file>
     <file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plbv46_slave_burst.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
       <library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
     </file>
     <file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v2_01_a/hdl/vhdl/interrupt_control.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
       <library xil_pn:name="interrupt_control_v2_01_a"/>
     </file>
     <file xil_pn:name="ipcore_dir/buffermem.xco" xil_pn:type="FILE_COREGEN">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
     </file>
     <file xil_pn:name="../../../../../../src/spi_base/spiifc.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
     </file>
     <file xil_pn:name="../../../../../../src/spi_base/spiwrap.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
     </file>
     <file xil_pn:name="../../../../../../test/spi_base/spiifc_tb.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
       <association xil_pn:name="PostMapSimulation" xil_pn:seqID="92"/>
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="92"/>
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="92"/>
     </file>
     <file xil_pn:name="../../../../../../test/spi_base/spiifc_tb2.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="../../../../../ucf/atlys/spiwrap.ucf" xil_pn:type="FILE_UCF">
@@ -247,9 +247,9 @@
     <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
     <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|spiifc|IMP" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="../../hdl/vhdl/spiifc.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/spiifc" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Module|spiwrap" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="../../../../../../src/spi_base/spiwrap.v" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/spiwrap" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -313,7 +313,7 @@
     <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output File Name" xil_pn:value="spiifc" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output File Name" xil_pn:value="spiwrap" xil_pn:valueState="default"/>
     <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
@@ -327,10 +327,10 @@
     <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
     <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
     <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="spiifc_map.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="spiifc_timesim.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="spiifc_synthesis.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="spiifc_translate.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="spiwrap_map.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="spiwrap_timesim.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="spiwrap_synthesis.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="spiwrap_translate.v" xil_pn:valueState="default"/>
     <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
     <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -373,8 +373,8 @@
     <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
     <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/spiifc_tb" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.spiifc_tb" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/spiifc_tb2" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.spiifc_tb2" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
@@ -392,7 +392,7 @@
     <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
     <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.spiifc_tb" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.spiifc_tb2" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
@@ -443,7 +443,7 @@
     <!--                                                                                  -->
     <!-- The following properties are for internal use only. These should not be modified.-->
     <!--                                                                                  -->
-    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|spiifc_tb" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|spiifc_tb2" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DesignName" xil_pn:value="spiifc" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>

projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc_envsettings.html

+<HTML><HEAD><TITLE>Xilinx System Settings Report</TITLE></HEAD>
+<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
+<center><big><big><b>System Settings</b></big></big></center><br>
+<A NAME="Environment Settings"></A>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
+<TD ALIGN=CENTER COLSPAN='5'><B> Environment Settings </B></TD>
+</tr>
+<tr bgcolor='#ffff99'>
+<td><b>Environment Variable</b></td>
+<td><b>xst</b></td>
+<td><b>ngdbuild</b></td>
+<td><b>map</b></td>
+<td><b>par</b></td>
+</tr>
+<tr>
+<td>PATHEXT</td>
+<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
+<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
+<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
+<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
+</tr>
+<tr>
+<td>Path</td>
+<td>C:\Xilinx\13.2\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\13.2\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\13.2\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\13.2\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\13.2\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\13.2\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\13.2\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\13.2\ISE_DS\EDK\gnu\microblaze\nt64\bin;<br>C:\Xilinx\13.2\ISE_DS\EDK\gnu\powerpc-eabi\nt64\bin;<br>C:\Xilinx\13.2\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\13.2\ISE_DS\common\bin\nt64;<br>C:\Xilinx\13.2\ISE_DS\common\lib\nt64;<br>C:\Program Files (x86)\Atmel\AVR Tools\AVR Toolchain\bin;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files (x86)\Java\jdk1.6.0_26\bin;<br>c:\python27;<br>C:\Python27\Scripts;<br>C:\Program Files\SlikSvn\bin\;<br>C:\Program Files (x86)\GnuWin32\bin;<br>C:\Program Files\Vim\vim73;<br>c:\Program Files (x86)\Microsoft SQL Server\100\Tools\Binn\;<br>c:\Program Files\Microsoft SQL Server\100\Tools\Binn\;<br>c:\Program Files\Microsoft SQL Server\100\DTS\Binn\;<br>c:\Program Files\TortoiseSVN\bin</td>
+<td>C:\Xilinx\13.2\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\13.2\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\13.2\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\13.2\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\13.2\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\13.2\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\13.2\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\13.2\ISE_DS\EDK\gnu\microblaze\nt64\bin;<br>C:\Xilinx\13.2\ISE_DS\EDK\gnu\powerpc-eabi\nt64\bin;<br>C:\Xilinx\13.2\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\13.2\ISE_DS\common\bin\nt64;<br>C:\Xilinx\13.2\ISE_DS\common\lib\nt64;<br>C:\Program Files (x86)\Atmel\AVR Tools\AVR Toolchain\bin;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files (x86)\Java\jdk1.6.0_26\bin;<br>c:\python27;<br>C:\Python27\Scripts;<br>C:\Program Files\SlikSvn\bin\;<br>C:\Program Files (x86)\GnuWin32\bin;<br>C:\Program Files\Vim\vim73;<br>c:\Program Files (x86)\Microsoft SQL Server\100\Tools\Binn\;<br>c:\Program Files\Microsoft SQL Server\100\Tools\Binn\;<br>c:\Program Files\Microsoft SQL Server\100\DTS\Binn\;<br>c:\Program Files\TortoiseSVN\bin</td>
+<td>C:\Xilinx\13.2\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\13.2\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\13.2\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\13.2\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\13.2\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\13.2\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\13.2\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\13.2\ISE_DS\EDK\gnu\microblaze\nt64\bin;<br>C:\Xilinx\13.2\ISE_DS\EDK\gnu\powerpc-eabi\nt64\bin;<br>C:\Xilinx\13.2\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\13.2\ISE_DS\common\bin\nt64;<br>C:\Xilinx\13.2\ISE_DS\common\lib\nt64;<br>C:\Program Files (x86)\Atmel\AVR Tools\AVR Toolchain\bin;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files (x86)\Java\jdk1.6.0_26\bin;<br>c:\python27;<br>C:\Python27\Scripts;<br>C:\Program Files\SlikSvn\bin\;<br>C:\Program Files (x86)\GnuWin32\bin;<br>C:\Program Files\Vim\vim73;<br>c:\Program Files (x86)\Microsoft SQL Server\100\Tools\Binn\;<br>c:\Program Files\Microsoft SQL Server\100\Tools\Binn\;<br>c:\Program Files\Microsoft SQL Server\100\DTS\Binn\;<br>c:\Program Files\TortoiseSVN\bin</td>
+<td>C:\Xilinx\13.2\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\13.2\ISE_DS\ISE\\bin\nt64;<br>C:\Xilinx\13.2\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\13.2\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\13.2\ISE_DS\ISE\lib\nt64;<br>C:\Xilinx\13.2\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\13.2\ISE_DS\EDK\lib\nt64;<br>C:\Xilinx\13.2\ISE_DS\EDK\gnu\microblaze\nt64\bin;<br>C:\Xilinx\13.2\ISE_DS\EDK\gnu\powerpc-eabi\nt64\bin;<br>C:\Xilinx\13.2\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\13.2\ISE_DS\common\bin\nt64;<br>C:\Xilinx\13.2\ISE_DS\common\lib\nt64;<br>C:\Program Files (x86)\Atmel\AVR Tools\AVR Toolchain\bin;<br>C:\Windows\system32;<br>C:\Windows;<br>C:\Windows\System32\Wbem;<br>C:\Windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files (x86)\Java\jdk1.6.0_26\bin;<br>c:\python27;<br>C:\Python27\Scripts;<br>C:\Program Files\SlikSvn\bin\;<br>C:\Program Files (x86)\GnuWin32\bin;<br>C:\Program Files\Vim\vim73;<br>c:\Program Files (x86)\Microsoft SQL Server\100\Tools\Binn\;<br>c:\Program Files\Microsoft SQL Server\100\Tools\Binn\;<br>c:\Program Files\Microsoft SQL Server\100\DTS\Binn\;<br>c:\Program Files\TortoiseSVN\bin</td>
+</tr>
+<tr>
+<td>XILINX</td>
+<td>C:\Xilinx\13.2\ISE_DS\ISE\</td>
+<td>C:\Xilinx\13.2\ISE_DS\ISE\</td>
+<td>C:\Xilinx\13.2\ISE_DS\ISE\</td>
+<td>C:\Xilinx\13.2\ISE_DS\ISE\</td>
+</tr>
+<tr>
+<td>XILINX_DSP</td>
+<td>C:\Xilinx\13.2\ISE_DS\ISE</td>
+<td>C:\Xilinx\13.2\ISE_DS\ISE</td>
+<td>C:\Xilinx\13.2\ISE_DS\ISE</td>
+<td>C:\Xilinx\13.2\ISE_DS\ISE</td>
+</tr>
+<tr>
+<td>XILINX_EDK</td>
+<td>C:\Xilinx\13.2\ISE_DS\EDK</td>
+<td>C:\Xilinx\13.2\ISE_DS\EDK</td>
+<td>C:\Xilinx\13.2\ISE_DS\EDK</td>
+<td>C:\Xilinx\13.2\ISE_DS\EDK</td>
+</tr>
+<tr>
+<td>XILINX_FOR_ALTIUM_OVERRIDE</td>
+<td> </td>
+<td> </td>
+<td> </td>
+<td> </td>
+</tr>
+<tr>
+<td>XILINX_PLANAHEAD</td>
+<td>C:\Xilinx\13.2\ISE_DS\PlanAhead</td>
+<td>C:\Xilinx\13.2\ISE_DS\PlanAhead</td>
+<td>C:\Xilinx\13.2\ISE_DS\PlanAhead</td>
+<td>C:\Xilinx\13.2\ISE_DS\PlanAhead</td>
+</tr>
+</TABLE>
+<A NAME="Synthesis Property Settings"></A>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
+<TD ALIGN=CENTER COLSPAN='4'><B>Synthesis Property Settings </B></TD>
+</tr>
+<tr bgcolor='#ffff99'>
+<td><b>Switch Name</b></td>
+<td><b>Property Name</b></td>
+<td><b>Value</b></td>
+<td><b>Default Value</b></td>
+</tr>
+<tr>
+<td>-ifn</td>
+<td>&nbsp;</td>
+<td>spiwrap.prj</td>
+<td>&nbsp;</td>
+</tr>
+<tr>
+<td>-ifmt</td>
+<td>&nbsp;</td>
+<td>mixed</td>
+<td>Mixed</td>
+</tr>
+<tr>
+<td>-ofn</td>
+<td>&nbsp;</td>
+<td>spiwrap</td>
+<td>&nbsp;</td>
+</tr>
+<tr>
+<td>-ofmt</td>
+<td>&nbsp;</td>
+<td>NGC</td>
+<td>NGC</td>
+</tr>
+<tr>
+<td>-p</td>
+<td>&nbsp;</td>
+<td>xc6slx45-2-csg324</td>
+<td>&nbsp;</td>
+</tr>
+<tr>
+<td>-top</td>
+<td>&nbsp;</td>
+<td>spiwrap</td>
+<td>&nbsp;</td>
+</tr>
+<tr>
+<td>-opt_mode</td>
+<td>Optimization Goal</td>
+<td>Speed</td>
+<td>Speed</td>
+</tr>
+<tr>
+<td>-opt_level</td>
+<td>Optimization Effort</td>
+<td>1</td>
+<td>1</td>
+</tr>
+<tr>
+<td>-power</td>
+<td>Power Reduction</td>
+<td>NO</td>
+<td>No</td>
+</tr>
+<tr>
+<td>-iuc</td>
+<td>Use synthesis Constraints File</td>
+<td>NO</td>
+<td>No</td>
+</tr>
+<tr>
+<td>-keep_hierarchy</td>
+<td>Keep Hierarchy</td>
+<td>No</td>
+<td>No</td>
+</tr>
+<tr>
+<td>-netlist_hierarchy</td>
+<td>Netlist Hierarchy</td>
+<td>As_Optimized</td>
+<td>As_Optimized</td>
+</tr>
+<tr>
+<td>-rtlview</td>
+<td>Generate RTL Schematic</td>
+<td>Yes</td>
+<td>No</td>
+</tr>
+<tr>
+<td>-glob_opt</td>
+<td>Global Optimization Goal</td>
+<td>AllClockNets</td>
+<td>AllClockNets</td>
+</tr>
+<tr>
+<td>-read_cores</td>
+<td>Read Cores</td>
+<td>YES</td>
+<td>Yes</td>
+</tr>
+<tr>
+<td>-sd</td>
+<td>Cores Search Directories</td>
+<td>{&quot;ipcore_dir&quot;  }</td>
+<td>&nbsp;</td>
+</tr>
+<tr>
+<td>-write_timing_constraints</td>
+<td>Write Timing Constraints</td>
+<td>NO</td>
+<td>No</td>
+</tr>
+<tr>
+<td>-cross_clock_analysis</td>
+<td>Cross Clock Analysis</td>
+<td>NO</td>
+<td>No</td>
+</tr>
+<tr>
+<td>-bus_delimiter</td>
+<td>Bus Delimiter</td>
+<td>&lt;&gt;</td>
+<td>&lt;&gt;</td>
+</tr>
+<tr>
+<td>-slice_utilization_ratio</td>
+<td>Slice Utilization Ratio</td>
+<td>100</td>
+<td>100</td>
+</tr>
+<tr>
+<td>-bram_utilization_ratio</td>
+<td>BRAM Utilization Ratio</td>
+<td>100</td>
+<td>100</td>
+</tr>
+<tr>
+<td>-dsp_utilization_ratio</td>
+<td>DSP Utilization Ratio</td>
+<td>100</td>
+<td>100</td>
+</tr>
+<tr>
+<td>-reduce_control_sets</td>
+<td>&nbsp;</td>
+<td>Auto</td>
+<td>Auto</td>
+</tr>
+<tr>
+<td>-fsm_extract</td>
+<td>&nbsp;</td>
+<td>YES</td>
+<td>Yes</td>
+</tr>
+<tr>
+<td>-fsm_encoding</td>
+<td>&nbsp;</td>
+<td>Auto</td>
+<td>Auto</td>
+</tr>
+<tr>
+<td>-safe_implementation</td>
+<td>&nbsp;</td>
+<td>No</td>
+<td>No</td>
+</tr>
+<tr>
+<td>-fsm_style</td>
+<td>&nbsp;</td>
+<td>LUT</td>
+<td>LUT</td>
+</tr>
+<tr>
+<td>-ram_extract</td>
+<td>&nbsp;</td>
+<td>Yes</td>
+<td>Yes</td>
+</tr>
+<tr>
+<td>-ram_style</td>
+<td>&nbsp;</td>
+<td>Auto</td>
+<td>Auto</td>
+</tr>
+<tr>
+<td>-rom_extract</td>
+<td>&nbsp;</td>
+<td>Yes</td>
+<td>Yes</td>
+</tr>
+<tr>
+<td>-shreg_extract</td>
+<td>&nbsp;</td>
+<td>YES</td>
+<td>Yes</td>
+</tr>
+<tr>
+<td>-rom_style</td>
+<td>&nbsp;</td>
+<td>Auto</td>
+<td>Auto</td>
+</tr>
+<tr>
+<td>-auto_bram_packing</td>
+<td>&nbsp;</td>
+<td>NO</td>
+<td>No</td>
+</tr>
+<tr>
+<td>-resource_sharing</td>
+<td>&nbsp;</td>
+<td>YES</td>
+<td>Yes</td>
+</tr>
+<tr>
+<td>-async_to_sync</td>
+<td>&nbsp;</td>
+<td>NO</td>
+<td>No</td>
+</tr>
+<tr>
+<td>-use_dsp48</td>
+<td>&nbsp;</td>
+<td>Auto</td>
+<td>Auto</td>
+</tr>
+<tr>
+<td>-iobuf</td>
+<td>&nbsp;</td>
+<td>YES</td>
+<td>Yes</td>
+</tr>
+<tr>
+<td>-max_fanout</td>
+<td>&nbsp;</td>
+<td>100000</td>
+<td>100000</td>
+</tr>
+<tr>
+<td>-bufg</td>
+<td>&nbsp;</td>
+<td>16</td>
+<td>16</td>
+</tr>
+<tr>
+<td>-register_duplication</td>
+<td>&nbsp;</td>
+<td>YES</td>
+<td>Yes</td>
+</tr>
+<tr>
+<td>-register_balancing</td>
+<td>&nbsp;</td>
+<td>No</td>
+<td>No</td>
+</tr>
+<tr>
+<td>-optimize_primitives</td>
+<td>&nbsp;</td>
+<td>NO</td>
+<td>No</td>
+</tr>
+<tr>
+<td>-use_clock_enable</td>
+<td>&nbsp;</td>
+<td>Auto</td>
+<td>Auto</td>
+</tr>
+<tr>
+<td>-use_sync_set</td>
+<td>&nbsp;</td>
+<td>Auto</td>
+<td>Auto</td>
+</tr>
+<tr>
+<td>-use_sync_reset</td>
+<td>&nbsp;</td>
+<td>Auto</td>
+<td>Auto</td>
+</tr>
+<tr>
+<td>-iob</td>
+<td>&nbsp;</td>
+<td>Auto</td>
+<td>Auto</td>
+</tr>
+<tr>
+<td>-equivalent_register_removal</td>
+<td>&nbsp;</td>
+<td>YES</td>
+<td>Yes</td>
+</tr>
+<tr>
+<td>-slice_utilization_ratio_maxmargin</td>
+<td>&nbsp;</td>
+<td>5</td>
+<td>0</td>
+</tr>
+</TABLE>
+<A NAME="Translation Property Settings"></A>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
+<TD ALIGN=CENTER COLSPAN='4'><B>Translation Property Settings </B></TD>
+</tr>
+<tr bgcolor='#ffff99'>
+<td><b>Switch Name</b></td>
+<td><b>Property Name</b></td>
+<td><b>Value</b></td>
+<td><b>Default Value</b></td>
+</tr>
+<tr>
+<td>-intstyle</td>
+<td>&nbsp;</td>
+<td>ise</td>
+<td>None</td>
+</tr>
+<tr>
+<td>-dd</td>
+<td>&nbsp;</td>
+<td>_ngo</td>
+<td>None</td>
+</tr>
+<tr>
+<td>-p</td>
+<td>&nbsp;</td>
+<td>xc6slx45-csg324-2</td>
+<td>None</td>
+</tr>
+<tr>
+<td>-sd</td>
+<td>Macro Search Path</td>
+<td>ipcore_dir</td>
+<td>None</td>
+</tr>
+<tr>
+<td>-uc</td>
+<td>&nbsp;</td>
+<td>C:/Users/mjlyons/workspace/vSPI/projnav/ucf/atlys/spiwrap.ucf</td>
+<td>None</td>
+</tr>
+</TABLE>
+<A NAME="Map Property Settings"></A>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
+<TD ALIGN=CENTER COLSPAN='4'><B>Map Property Settings </B></TD>
+</tr>
+<tr bgcolor='#ffff99'>
+<td><b>Switch Name</b></td>
+<td><b>Property Name</b></td>
+<td><b>Value</b></td>
+<td><b>Default Value</b></td>
+</tr>
+<tr>
+<td>-ol</td>
+<td>Place & Route Effort Level (Overall)</td>
+<td>high</td>
+<td>high</td>
+</tr>
+<tr>
+<td>-xt</td>
+<td>Extra Cost Tables</td>
+<td>0</td>
+<td>0</td>
+</tr>
+<tr>
+<td>-ir</td>
+<td>Use RLOC Constraints</td>
+<td>OFF</td>
+<td>OFF</td>
+</tr>
+<tr>
+<td>-t</td>
+<td>Starting Placer Cost Table (1-100) Map</td>
+<td>1</td>
+<td>0</td>
+</tr>
+<tr>
+<td>-r</td>
+<td>Register Ordering</td>
+<td>4</td>
+<td>4</td>
+</tr>
+<tr>
+<td>-intstyle</td>
+<td>&nbsp;</td>
+<td>ise</td>
+<td>None</td>
+</tr>
+<tr>
+<td>-lc</td>
+<td>LUT Combining</td>
+<td>off</td>
+<td>off</td>
+</tr>
+<tr>
+<td>-o</td>
+<td>&nbsp;</td>
+<td>spiwrap_map.ncd</td>
+<td>None</td>
+</tr>
+<tr>
+<td>-w</td>
+<td>&nbsp;</td>
+<td>true</td>
+<td>false</td>
+</tr>
+<tr>
+<td>-pr</td>
+<td>Pack I/O Registers/Latches into IOBs</td>
+<td>off</td>
+<td>off</td>
+</tr>
+<tr>
+<td>-p</td>
+<td>&nbsp;</td>
+<td>xc6slx45-csg324-2</td>
+<td>None</td>
+</tr>
+</TABLE>
+<A NAME="Place and Route Property Settings"></A>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
+<TD ALIGN=CENTER COLSPAN='4'><B>Place and Route Property Settings </B></TD>
+</tr>
+<tr bgcolor='#ffff99'>
+<td><b>Switch Name</b></td>
+<td><b>Property Name</b></td>
+<td><b>Value</b></td>
+<td><b>Default Value</b></td>
+</tr>
+<tr>
+<td>-intstyle</td>
+<td>&nbsp;</td>
+<td>ise</td>
+<td>&nbsp;</td>
+</tr>
+<tr>
+<td>-mt</td>
+<td>Enable Multi-Threading</td>
+<td>off</td>
+<td>off</td>
+</tr>
+<tr>
+<td>-ol</td>
+<td>Place & Route Effort Level (Overall)</td>
+<td>high</td>
+<td>std</td>
+</tr>
+<tr>
+<td>-w</td>
+<td>&nbsp;</td>
+<td>true</td>
+<td>false</td>
+</tr>
+</TABLE>
+<A NAME="Operating System Information"></A>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
+<TD ALIGN=CENTER COLSPAN='5'><B> Operating System Information </B></TD>
+</tr>
+<tr bgcolor='#ffff99'>
+<td><b>Operating System Information</b></td>
+<td><b>xst</b></td>
+<td><b>ngdbuild</b></td>
+<td><b>map</b></td>
+<td><b>par</b></td>
+</tr>
+<tr>
+<td>CPU Architecture/Speed</td>
+<td>Intel(R) Core(TM) i5-2400S CPU @ 2.50GHz/2499 MHz</td>
+<td>Intel(R) Core(TM) i5-2400S CPU @ 2.50GHz/2499 MHz</td>
+<td>Intel(R) Core(TM) i5-2400S CPU @ 2.50GHz/2499 MHz</td>
+<td>Intel(R) Core(TM) i5-2400S CPU @ 2.50GHz/2499 MHz</td>
+</tr>
+<tr>
+<td>Host</td>
+<td>WIN-MEQROG0RPAS</td>
+<td>WIN-MEQROG0RPAS</td>
+<td>WIN-MEQROG0RPAS</td>
+<td>WIN-MEQROG0RPAS</td>
+</tr>
+<tr>
+<td>OS Name</td>
+<td>Microsoft Windows 7 , 64-bit</td>
+<td>Microsoft Windows 7 , 64-bit</td>
+<td>Microsoft Windows 7 , 64-bit</td>
+<td>Microsoft Windows 7 , 64-bit</td>
+</tr>
+<tr>
+<td>OS Release</td>
+<td>Service Pack 1  (build 7601)</td>
+<td>Service Pack 1  (build 7601)</td>
+<td>Service Pack 1  (build 7601)</td>
+<td>Service Pack 1  (build 7601)</td>
+</tr>
+</TABLE>
+</BODY> </HTML>
\ No newline at end of file

projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiwrap_summary.html → projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc_summary.html

@@ -2,7 +2,7 @@
 <BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
 <TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
 <TR ALIGN=CENTER BGCOLOR='#99CCFF'>
-<TD ALIGN=CENTER COLSPAN='4'><B>spiifc Project Status</B></TD></TR>
+<TD ALIGN=CENTER COLSPAN='4'><B>spiwrap Project Status</B></TD></TR>
 <TR ALIGN=LEFT>
 <TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
 <TD>spiifc.xise</TD>
@@ -10,7 +10,7 @@
 </TR>
 <TR ALIGN=LEFT>
 <TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
-<TD>spiifc</TD>
+<TD>spiwrap</TD>
 <TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
 <TD>New</TD>
 </TR>
@@ -74,5 +74,5 @@
 </TABLE>
 
 
-<br><center><b>Date Generated:</b> 03/07/2012 - 09:22:39</center>
+<br><center><b>Date Generated:</b> 03/07/2012 - 16:13:02</center>
 </BODY></HTML>
\ No newline at end of file

projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiwrap_guide.ncd

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 XILINX-XDM V1.6
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   1914     624eNqtWMGSpDYM/Zl8gG1JYNOXreSyx2zt5gNoGo5TNYfkQvW/RzZgGYMbmN6Z6h6Qn55kW0+YwQFrdAj86WlAAwhOKb7vkMhiRwNZMGDI8Xc2wlf73n4MgJQiwyNsDywANbNAasUBdH7PWBX46jji1v44kPZYic/jnAMhZ8ZXqd860ot5hZxJF2c4EBEyVhWzQjjI6kreK+ZlLqv15tXWfo1PxJW16AkzbsIONFJYne1+ThFSvyr6ERj/iRwmcMxYXnODGh+zFyZeGL08gwnXaQRVwOIGa1bZHGHNXH1AcApbr7Hz9T5Whzo+j6ZLaHcBbfI5HqCXWZpTaLeqklQTE0fwez4/wN0b1eD40T4auP3bdo25/dPeG443+glBe5rcb2/FpRQKsphUitiWMYF9o6lN3n4MgxzSpmaCkFRq5VYD+X3a1FCaU5gjR865XjSKkj9HUYcNDk80ODiV4Yum87X8V+ylhgehxbyOvW12kZeLtA6FDrtVAmkDC37Wyy8RCEQOMzfmNTaVHiSi2MPWO1gsYNft5RhNl9DuAtrszrGMrpPm/AqN0owEHdszXGhGEDnCdWhGHTcjCM3IPJJupPvWdyPD3SjVNK/IRtOOvwmrXSWvxl/Ud86bK3jhCPoK90mF8zeiZqye69UzoH/0stXND/rjyF/j3XhlB4wvxM0YfP824fgz7+TbEa8yrvrGvCN5ddWnIp9l2na57ZhUvfDv4fu54lWmFO2VEscpjPfYF7FVHJ+wy9FuT4FVcnwMaiUTsDkvLNgwTtkc5NUBk2fTI/NN7EVfP8a7M2v+ETUPKtV8FzSvM81PR8nfr/mc9zdq/lTU65xFnXwtXuJ9WpGnIl1hO6NIdSrqWaaStlXhhFIVtB30yieOPb3iou0w/lrbuKPtfj7JlPQ6jYf+WNBstXqpvqbZydePYdRsL5rtE81aPbLE28Lhlg/nZPmXiQ4Ot273GGF3lt0dvnTYw5cOHRpzMeeDl47gPc8LfHsLCzQ0urGjXxk9dbOH890Ms/epZQfu/gRFKvxThelZLVR4P9KFGjjLAPNTa8NAFaPgwBs3r5tX42P2j4pr8amogfMriG/Fd1/W0eQbdJSjL7FgZNFvsKiZBd7IZdrLiUW/wWKWM8EbuUx1PbG8sy5LrwNfASxlQm51emp1Zm51zw+rohVVtLYmWuPry/PjLlgQ7L0XbButWlfRrLvELGidoE2CtmK2dTSn1iFaK7E6waJYWx2tkrIeZCbaJOZOzAnHIPG0BDQEEhATsxUziLmSJUUJaR4JtyRoeplMn1gFLEtqBhetsqKAybZIPCCSeH1ibgUtc4EkaROze/73y4bt4l81/qS6cVXj+MnAz2wzQGMG3rfbd/582vZ21/7RwXCmGr9bd/vDYgPebiHYVbTbxthl+HnXYLfjbRz3P9++/TUC7yUNunNdq9jw50hjW8/ZQTfcPlt3e44tRJOeTXYyGX7wP5qB8yUx1mzsm44TMD3XKc+p6jm5iud2XyO9+8CL4yYzZ/D3+IMXU91+3BvFsbTyN59ahzvoO67kT5/04P9o/sM+/wPjh/0D
\ No newline at end of file

projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/tb2_fastclock.wcfg

+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc_tb2_isim_beh.wdb" id="1" type="auto">
+         <top_modules>
+            <top_module name="glbl" />
+            <top_module name="spiifc_tb2" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <WVObjectSize size="23" />
+   <wvobject fp_name="/spiifc_tb2/SPI_MISO" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">SPI_MISO</obj_property>
+      <obj_property name="ObjectShortName">SPI_MISO</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spiifc_tb2/txMemAddr" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">txMemAddr[11:0]</obj_property>
+      <obj_property name="ObjectShortName">txMemAddr[11:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spiifc_tb2/rcMemAddr" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">rcMemAddr[11:0]</obj_property>
+      <obj_property name="ObjectShortName">rcMemAddr[11:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spiifc_tb2/rcMemData" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">rcMemData[7:0]</obj_property>
+      <obj_property name="ObjectShortName">rcMemData[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spiifc_tb2/rcMemWE" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">rcMemWE</obj_property>
+      <obj_property name="ObjectShortName">rcMemWE</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spiifc_tb2/debug_out" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">debug_out[7:0]</obj_property>
+      <obj_property name="ObjectShortName">debug_out[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spiifc_tb2/Reset" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">Reset</obj_property>
+      <obj_property name="ObjectShortName">Reset</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spiifc_tb2/SysClk" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">SysClk</obj_property>
+      <obj_property name="ObjectShortName">SysClk</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spiifc_tb2/SPI_CLK" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">SPI_CLK</obj_property>
+      <obj_property name="ObjectShortName">SPI_CLK</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spiifc_tb2/SPI_MOSI" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">SPI_MOSI</obj_property>
+      <obj_property name="ObjectShortName">SPI_MOSI</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spiifc_tb2/SPI_SS" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">SPI_SS</obj_property>
+      <obj_property name="ObjectShortName">SPI_SS</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spiifc_tb2/txMemData" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">txMemData[7:0]</obj_property>
+      <obj_property name="ObjectShortName">txMemData[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spiifc_tb2/SPI_CLK_en" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">SPI_CLK_en</obj_property>
+      <obj_property name="ObjectShortName">SPI_CLK_en</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spiifc_tb2/fdRcBytes" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">fdRcBytes[31:0]</obj_property>
+      <obj_property name="ObjectShortName">fdRcBytes[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spiifc_tb2/fdTxBytes" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">fdTxBytes[31:0]</obj_property>
+      <obj_property name="ObjectShortName">fdTxBytes[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spiifc_tb2/dummy" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">dummy[31:0]</obj_property>
+      <obj_property name="ObjectShortName">dummy[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spiifc_tb2/currRcByte" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">currRcByte[31:0]</obj_property>
+      <obj_property name="ObjectShortName">currRcByte[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spiifc_tb2/rcBytesNotEmpty" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">rcBytesNotEmpty[31:0]</obj_property>
+      <obj_property name="ObjectShortName">rcBytesNotEmpty[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spiifc_tb2/rcBytesStr" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">rcBytesStr[80:1]</obj_property>
+      <obj_property name="ObjectShortName">rcBytesStr[80:1]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spiifc_tb2/uut/rcByteValid" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">rcByteValid</obj_property>
+      <obj_property name="ObjectShortName">rcByteValid</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spiifc_tb2/uut/rcByte" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">rcByte[7:0]</obj_property>
+      <obj_property name="ObjectShortName">rcByte[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spiifc_tb2/uut/rcBitIndex" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">rcBitIndex[2:0]</obj_property>
+      <obj_property name="ObjectShortName">rcBitIndex[2:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spiifc_tb2/uut/state" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">state</obj_property>
+      <obj_property name="ObjectShortName">state</obj_property>
+   </wvobject>
+</wave_config>

projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/webtalk_impact.xml

@@ -3,9 +3,9 @@
 <!--The data in this file is primarily intended for consumption by Xilinx tools.
 The structure and the elements are likely to change over the next few releases.
 This means code written to parse this file will need to be revisited each subsequent release.-->
-<application name="impact" timeStamp="Tue Mar 06 15:24:19 2012">
+<application name="impact" timeStamp="Wed Mar 07 14:31:40 2012">
 <section name="Project Information" visible="false">
-<property name="ProjectID" value="5ea5de4132cd436698ae1e90d83ce606"/>
+<property name="ProjectID" value="da00646f0b4c4ac8baf5d51b1868f1e8"/>
 <property name="ProjectIteration" value="1"/>
 </section>
 <section name="iMPACT Project Info" visible="true">
@@ -27,10 +27,6 @@ This means code written to parse this file will need to be revisited each subseq
 <item name="Boundary Scan Operations Statistics">
 <property name="BSCAN Operation" value="Program -p 0
 "/>
-<property name="BSCAN Operation" value="Program -p 0
-"/>
-<property name="BSCAN Operation" value="Program -p 0
-"/>
 </item>
 <item name="Cable Summary">
 <property name="Cable Type" value="Platform Cable USB"/>

src/spi_base/spiifc.v

@@ -71,13 +71,19 @@ output          [7:0] debug_out;
 //
 // Registers
 //
+reg                   SPI_CLK_reg;    // Stabalized version of SPI_CLK
+reg                   SPI_CLK_reg1;
+reg                   SPI_SS_reg;     // Stabalized version of SPI_SS
+reg                   SPI_SS_reg1;
+reg                   SPI_MOSI_reg;   // Stabalized version of SPI_MOSI
+reg                   SPI_MOSI_reg1;
 reg                   prev_spiClk;    // Value of SPI_CLK during last SysClk cycle
 reg                   prev_spiSS;     // Value of SPI_SS during last SysClk cycle
 reg             [7:0] state_reg;      // Register backing the 'state' wire
 reg             [7:0] rcByte_reg;     // Register backing 'rcByte'
 reg             [2:0] rcBitIndex_reg; // Register backing 'rcBitIndex'
 reg    [AddrBits-1:0] rcMemAddr_reg;  // Byte addr to write MOSI data to
-
+reg             [7:0] debug_reg;      // register backing debug_out signal
 //
 // Wires
 //
@@ -88,30 +94,40 @@ wire                  rcByteValid;    // rcByte is valid and new
 wire            [7:0] rcByte;         // Byte received from master
 wire            [2:0] rcBitIndex;     // Bit of rcByte to write to next
 
+// Save buffered SPI inputs
+always @(posedge SysClk) begin
+  SPI_CLK_reg1 <= SPI_CLK;
+  SPI_CLK_reg <= SPI_CLK_reg1;
+  SPI_SS_reg1 <= SPI_SS;
+  SPI_SS_reg <= SPI_SS_reg1;
+  SPI_MOSI_reg1 <= SPI_MOSI;
+  SPI_MOSI_reg <= SPI_MOSI_reg1;
+end
+
 // Detect new valid bit
 always @(posedge SysClk) begin
-  prev_spiClk <= SPI_CLK;
+  prev_spiClk <= SPI_CLK_reg;
 end
-assign risingSpiClk = SPI_CLK & (~prev_spiClk);
-assign validSpiBit = risingSpiClk & (~SPI_SS);
+assign risingSpiClk = SPI_CLK_reg & (~prev_spiClk);
+assign validSpiBit = risingSpiClk & (~SPI_SS_reg);
 
 // Detect new SPI packet (SS dropped low)
 always @(posedge SysClk) begin
-  prev_spiSS <= SPI_SS;
+  prev_spiSS <= SPI_SS_reg;
 end
-assign packetStart = prev_spiSS & (~SPI_SS);
+assign packetStart = prev_spiSS & (~SPI_SS_reg);
 
 // Build incoming byte
 always @(posedge SysClk) begin
   if (validSpiBit) begin
-    rcByte_reg[rcBitIndex] <= SPI_MOSI;
+    rcByte_reg[rcBitIndex] <= SPI_MOSI_reg;
     rcBitIndex_reg <= (rcBitIndex > 0 ? rcBitIndex - 1 : 7);
   end else begin
     rcBitIndex_reg <= rcBitIndex;
   end
 end
 assign rcBitIndex = (Reset || packetStart ? 7 : rcBitIndex_reg); 
-assign rcByte = {rcByte_reg[7:1], SPI_MOSI};
+assign rcByte = {rcByte_reg[7:1], SPI_MOSI_reg};
 assign rcByteValid = (validSpiBit && rcBitIndex == 0 ? 1 : 0);
 
 // Incoming MOSI data buffer management
@@ -128,6 +144,10 @@ always @(posedge SysClk) begin
   end
 end
 
+// Outgoing MISO data buffer management
+// TODO: implement
+assign SPI_MISO = 1'b0;
+
 // State machine
 always @(*) begin
   if (Reset || packetStart) begin
@@ -157,4 +177,12 @@ always @(posedge SysClk) begin
   end
 end
 
+// Debugging
+always @(posedge SysClk) begin
+  if (rcByteValid) begin
+    debug_reg <= rcByte;
+  end
+end
+assign debug_out = debug_reg;
+
 endmodule

src/spi_base/spiwrap.v

@@ -108,6 +108,6 @@ spiifc mySpiIfc (
   .debug_out(debug_out)
 );
 
-assign leds = /*rcMem_douta[31:24]*/ debug_out;
+assign leds = /* rcMem_douta[7:0] */ debug_out ;
 
 endmodule