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vSPI
Commit 94c99edd authored by Mike Lyons's avatar Mike Lyons
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SPI adapter working, but occasionally buggy, in xps/xsdk

parent 928419df
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Showing with 3262 additions and 376 deletions
projnav/ucf/atlys/spiwrap.ucf 0 → 100644
View file @ 94c99edd
Net Reset LOC=N4 | IOSTANDARD=LVCMOS18;
Net SysClk LOC=L15 | IOSTANDARD=LVCMOS33;
# SPI Port
Net spi_miso LOC=U16 | IOSTANDARD=LVCMOS33;
Net spi_mosi LOC=U15 | IOSTANDARD=LVCMOS33;
Net spi_clk LOC=R10 | IOSTANDARD=LVCMOS33;
Net spi_ss LOC=M11 | IOSTANDARD=LVCMOS33;
# LEDs
Net leds<0> LOC=U18 | IOSTANDARD=LVCMOS33;
Net leds<1> LOC=M14 | IOSTANDARD=LVCMOS33;
Net leds<2> LOC=N14 | IOSTANDARD=LVCMOS33;
Net leds<3> LOC=L14 | IOSTANDARD=LVCMOS33;
Net leds<4> LOC=M13 | IOSTANDARD=LVCMOS33;
Net leds<5> LOC=D4 | IOSTANDARD=LVCMOS33;
Net leds<6> LOC=P16 | IOSTANDARD=LVCMOS33;
Net leds<7> LOC=N12 | IOSTANDARD=LVCMOS33;
projnav/xps/SDK/SDK_Export/hw/system.xml
View file @ 94c99edd
<EDKSYSTEM EDKVERSION="13.2" EDWVERSION="1.2" TIMESTAMP="Wed Feb 29 10:59:16 2012">
<EDKSYSTEM EDKVERSION="13.2" EDWVERSION="1.2" TIMESTAMP="Tue Mar 06 16:45:32 2012">
<SYSTEMINFO ARCH="spartan6" DEVICE="xc6slx45" PACKAGE="csg324" PART="xc6slx45csg324-2" SOURCE="C:/Users/mjlyons/workspace/vSPI/projnav/xps/system.xmp" SPEEDGRADE="-2"/>
......@@ -9,6 +9,10 @@
<PORT DIR="I" ENDIAN="BIG" LEFT="0" LSB="4" MHS_INDEX="2" MSB="0" NAME="fpga_0_Push_Buttons_5Bits_GPIO_IO_I_pin" RIGHT="4" SIGNAME="fpga_0_Push_Buttons_5Bits_GPIO_IO_I_pin"/>
<PORT CLKFREQUENCY="100000000" DIR="I" MHS_INDEX="3" NAME="fpga_0_clk_1_sys_clk_pin" SIGIS="CLK" SIGNAME="CLK_S"/>
<PORT DIR="I" MHS_INDEX="4" NAME="fpga_0_rst_1_sys_rst_pin" RSTPOLARITY="0" SIGIS="RST" SIGNAME="sys_rst_s"/>
<PORT CLKFREQUENCY="50000000" DIR="I" MHS_INDEX="5" NAME="spiifc_0_SPI_CLK_pin" SIGIS="CLK" SIGNAME="spiifc_0_SPI_CLK"/>
<PORT DIR="O" MHS_INDEX="6" NAME="spiifc_0_SPI_MISO_pin" SIGNAME="spiifc_0_SPI_MISO"/>
<PORT DIR="I" MHS_INDEX="7" NAME="spiifc_0_SPI_MOSI_pin" SIGNAME="spiifc_0_SPI_MOSI"/>
<PORT DIR="I" MHS_INDEX="8" NAME="spiifc_0_SPI_SS_pin" SIGNAME="spiifc_0_SPI_SS"/>
</EXTERNALPORTS>
<MODULES>
......@@ -4592,49 +4596,53 @@
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="16" NAME="C_MEM1_HIGHADDR" TYPE="std_logic_vector" VALUE="0x85011FFF"/>
</PARAMETERS>
<PORTS>
<PORT BUS="SPLB" CLKFREQUENCY="66666666" DEF_SIGNAME="clk_66_6667MHz" DIR="I" MPD_INDEX="0" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="clk_66_6667MHz"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_SPLB_Rst" DIR="I" MPD_INDEX="1" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="mb_plb_SPLB_Rst"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="mb_plb_PLB_ABus" VECFORMULA="[0:31]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_UABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="mb_plb_PLB_UABus" VECFORMULA="[0:31]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_PAValid" DIR="I" MPD_INDEX="4" NAME="PLB_PAValid" SIGNAME="mb_plb_PLB_PAValid"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_SAValid" DIR="I" MPD_INDEX="5" NAME="PLB_SAValid" SIGNAME="mb_plb_PLB_SAValid"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPrim" DIR="I" MPD_INDEX="6" NAME="PLB_rdPrim" SIGNAME="mb_plb_PLB_rdPrim"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPrim" DIR="I" MPD_INDEX="7" NAME="PLB_wrPrim" SIGNAME="mb_plb_PLB_wrPrim"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_masterID" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="8" MSB="0" NAME="PLB_masterID" RIGHT="1" SIGNAME="mb_plb_PLB_masterID" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_abort" DIR="I" MPD_INDEX="9" NAME="PLB_abort" SIGNAME="mb_plb_PLB_abort"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_busLock" DIR="I" MPD_INDEX="10" NAME="PLB_busLock" SIGNAME="mb_plb_PLB_busLock"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_RNW" DIR="I" MPD_INDEX="11" NAME="PLB_RNW" SIGNAME="mb_plb_PLB_RNW"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="12" MSB="0" NAME="PLB_BE" RIGHT="3" SIGNAME="mb_plb_PLB_BE" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_MSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="13" MSB="0" NAME="PLB_MSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSize" VECFORMULA="[0:1]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_size" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="14" MSB="0" NAME="PLB_size" RIGHT="3" SIGNAME="mb_plb_PLB_size" VECFORMULA="[0:3]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_type" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="15" MSB="0" NAME="PLB_type" RIGHT="2" SIGNAME="mb_plb_PLB_type" VECFORMULA="[0:2]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_lockErr" DIR="I" MPD_INDEX="16" NAME="PLB_lockErr" SIGNAME="mb_plb_PLB_lockErr"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="17" MSB="0" NAME="PLB_wrDBus" RIGHT="31" SIGNAME="mb_plb_PLB_wrDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrBurst" DIR="I" MPD_INDEX="18" NAME="PLB_wrBurst" SIGNAME="mb_plb_PLB_wrBurst"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdBurst" DIR="I" MPD_INDEX="19" NAME="PLB_rdBurst" SIGNAME="mb_plb_PLB_rdBurst"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendReq" DIR="I" MPD_INDEX="20" NAME="PLB_wrPendReq" SIGNAME="mb_plb_PLB_wrPendReq"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendReq" DIR="I" MPD_INDEX="21" NAME="PLB_rdPendReq" SIGNAME="mb_plb_PLB_rdPendReq"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="22" MSB="0" NAME="PLB_wrPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_wrPendPri" VECFORMULA="[0:1]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="23" MSB="0" NAME="PLB_rdPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_rdPendPri" VECFORMULA="[0:1]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_reqPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="24" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="mb_plb_PLB_reqPri" VECFORMULA="[0:1]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_TAttribute" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="25" MSB="0" NAME="PLB_TAttribute" RIGHT="15" SIGNAME="mb_plb_PLB_TAttribute" VECFORMULA="[0:15]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_addrAck" DIR="O" MPD_INDEX="26" NAME="Sl_addrAck" SIGNAME="mb_plb_Sl_addrAck"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_SSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="27" MSB="0" NAME="Sl_SSize" RIGHT="1" SIGNAME="mb_plb_Sl_SSize" VECFORMULA="[0:1]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wait" DIR="O" MPD_INDEX="28" NAME="Sl_wait" SIGNAME="mb_plb_Sl_wait"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rearbitrate" DIR="O" MPD_INDEX="29" NAME="Sl_rearbitrate" SIGNAME="mb_plb_Sl_rearbitrate"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrDAck" DIR="O" MPD_INDEX="30" NAME="Sl_wrDAck" SIGNAME="mb_plb_Sl_wrDAck"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrComp" DIR="O" MPD_INDEX="31" NAME="Sl_wrComp" SIGNAME="mb_plb_Sl_wrComp"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrBTerm" DIR="O" MPD_INDEX="32" NAME="Sl_wrBTerm" SIGNAME="mb_plb_Sl_wrBTerm"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="33" MSB="0" NAME="Sl_rdDBus" RIGHT="31" SIGNAME="mb_plb_Sl_rdDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdWdAddr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="34" MSB="0" NAME="Sl_rdWdAddr" RIGHT="3" SIGNAME="mb_plb_Sl_rdWdAddr" VECFORMULA="[0:3]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDAck" DIR="O" MPD_INDEX="35" NAME="Sl_rdDAck" SIGNAME="mb_plb_Sl_rdDAck"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdComp" DIR="O" MPD_INDEX="36" NAME="Sl_rdComp" SIGNAME="mb_plb_Sl_rdComp"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdBTerm" DIR="O" MPD_INDEX="37" NAME="Sl_rdBTerm" SIGNAME="mb_plb_Sl_rdBTerm"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MBusy" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="38" MSB="0" NAME="Sl_MBusy" RIGHT="2" SIGNAME="mb_plb_Sl_MBusy" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MWrErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="39" MSB="0" NAME="Sl_MWrErr" RIGHT="2" SIGNAME="mb_plb_Sl_MWrErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MRdErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="40" MSB="0" NAME="Sl_MRdErr" RIGHT="2" SIGNAME="mb_plb_Sl_MRdErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MIRQ" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="41" MSB="0" NAME="Sl_MIRQ" RIGHT="2" SIGNAME="mb_plb_Sl_MIRQ" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
<PORT DIR="O" MPD_INDEX="42" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
<PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SPI_CLK" SIGNAME="spiifc_0_SPI_CLK"/>
<PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="SPI_MOSI" SIGNAME="spiifc_0_SPI_MOSI"/>
<PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="2" NAME="SPI_MISO" SIGNAME="spiifc_0_SPI_MISO"/>
<PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="3" NAME="SPI_SS" SIGNAME="spiifc_0_SPI_SS"/>
<PORT BUS="SPLB" CLKFREQUENCY="66666666" DEF_SIGNAME="clk_66_6667MHz" DIR="I" MPD_INDEX="4" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="clk_66_6667MHz"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_SPLB_Rst" DIR="I" MPD_INDEX="5" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="mb_plb_SPLB_Rst"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="6" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="mb_plb_PLB_ABus" VECFORMULA="[0:31]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_UABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="7" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="mb_plb_PLB_UABus" VECFORMULA="[0:31]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_PAValid" DIR="I" MPD_INDEX="8" NAME="PLB_PAValid" SIGNAME="mb_plb_PLB_PAValid"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_SAValid" DIR="I" MPD_INDEX="9" NAME="PLB_SAValid" SIGNAME="mb_plb_PLB_SAValid"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPrim" DIR="I" MPD_INDEX="10" NAME="PLB_rdPrim" SIGNAME="mb_plb_PLB_rdPrim"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPrim" DIR="I" MPD_INDEX="11" NAME="PLB_wrPrim" SIGNAME="mb_plb_PLB_wrPrim"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_masterID" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="12" MSB="0" NAME="PLB_masterID" RIGHT="1" SIGNAME="mb_plb_PLB_masterID" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_abort" DIR="I" MPD_INDEX="13" NAME="PLB_abort" SIGNAME="mb_plb_PLB_abort"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_busLock" DIR="I" MPD_INDEX="14" NAME="PLB_busLock" SIGNAME="mb_plb_PLB_busLock"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_RNW" DIR="I" MPD_INDEX="15" NAME="PLB_RNW" SIGNAME="mb_plb_PLB_RNW"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="16" MSB="0" NAME="PLB_BE" RIGHT="3" SIGNAME="mb_plb_PLB_BE" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_MSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="17" MSB="0" NAME="PLB_MSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSize" VECFORMULA="[0:1]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_size" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="18" MSB="0" NAME="PLB_size" RIGHT="3" SIGNAME="mb_plb_PLB_size" VECFORMULA="[0:3]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_type" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="19" MSB="0" NAME="PLB_type" RIGHT="2" SIGNAME="mb_plb_PLB_type" VECFORMULA="[0:2]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_lockErr" DIR="I" MPD_INDEX="20" NAME="PLB_lockErr" SIGNAME="mb_plb_PLB_lockErr"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="21" MSB="0" NAME="PLB_wrDBus" RIGHT="31" SIGNAME="mb_plb_PLB_wrDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrBurst" DIR="I" MPD_INDEX="22" NAME="PLB_wrBurst" SIGNAME="mb_plb_PLB_wrBurst"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdBurst" DIR="I" MPD_INDEX="23" NAME="PLB_rdBurst" SIGNAME="mb_plb_PLB_rdBurst"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendReq" DIR="I" MPD_INDEX="24" NAME="PLB_wrPendReq" SIGNAME="mb_plb_PLB_wrPendReq"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendReq" DIR="I" MPD_INDEX="25" NAME="PLB_rdPendReq" SIGNAME="mb_plb_PLB_rdPendReq"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="26" MSB="0" NAME="PLB_wrPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_wrPendPri" VECFORMULA="[0:1]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="27" MSB="0" NAME="PLB_rdPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_rdPendPri" VECFORMULA="[0:1]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_reqPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="28" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="mb_plb_PLB_reqPri" VECFORMULA="[0:1]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_TAttribute" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="29" MSB="0" NAME="PLB_TAttribute" RIGHT="15" SIGNAME="mb_plb_PLB_TAttribute" VECFORMULA="[0:15]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_addrAck" DIR="O" MPD_INDEX="30" NAME="Sl_addrAck" SIGNAME="mb_plb_Sl_addrAck"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_SSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="31" MSB="0" NAME="Sl_SSize" RIGHT="1" SIGNAME="mb_plb_Sl_SSize" VECFORMULA="[0:1]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wait" DIR="O" MPD_INDEX="32" NAME="Sl_wait" SIGNAME="mb_plb_Sl_wait"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rearbitrate" DIR="O" MPD_INDEX="33" NAME="Sl_rearbitrate" SIGNAME="mb_plb_Sl_rearbitrate"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrDAck" DIR="O" MPD_INDEX="34" NAME="Sl_wrDAck" SIGNAME="mb_plb_Sl_wrDAck"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrComp" DIR="O" MPD_INDEX="35" NAME="Sl_wrComp" SIGNAME="mb_plb_Sl_wrComp"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrBTerm" DIR="O" MPD_INDEX="36" NAME="Sl_wrBTerm" SIGNAME="mb_plb_Sl_wrBTerm"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="37" MSB="0" NAME="Sl_rdDBus" RIGHT="31" SIGNAME="mb_plb_Sl_rdDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdWdAddr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="38" MSB="0" NAME="Sl_rdWdAddr" RIGHT="3" SIGNAME="mb_plb_Sl_rdWdAddr" VECFORMULA="[0:3]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDAck" DIR="O" MPD_INDEX="39" NAME="Sl_rdDAck" SIGNAME="mb_plb_Sl_rdDAck"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdComp" DIR="O" MPD_INDEX="40" NAME="Sl_rdComp" SIGNAME="mb_plb_Sl_rdComp"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdBTerm" DIR="O" MPD_INDEX="41" NAME="Sl_rdBTerm" SIGNAME="mb_plb_Sl_rdBTerm"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MBusy" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="42" MSB="0" NAME="Sl_MBusy" RIGHT="2" SIGNAME="mb_plb_Sl_MBusy" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MWrErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="43" MSB="0" NAME="Sl_MWrErr" RIGHT="2" SIGNAME="mb_plb_Sl_MWrErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MRdErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="44" MSB="0" NAME="Sl_MRdErr" RIGHT="2" SIGNAME="mb_plb_Sl_MRdErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MIRQ" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="45" MSB="0" NAME="Sl_MIRQ" RIGHT="2" SIGNAME="mb_plb_Sl_MIRQ" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
<PORT DIR="O" MPD_INDEX="46" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="mb_plb" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SPLB" TYPE="SLAVE">
......
projnav/xps/SDK/SDK_Export/hw/system_bd.bmm
View file @ 94c99edd
......@@ -21,38 +21,38 @@ ADDRESS_MAP microblaze_0 MICROBLAZE 100
ADDRESS_SPACE lmb_bram_combined RAMB16 [0x00000000:0x0000FFFF]
BUS_BLOCK
lmb_bram/lmb_bram/ramb16bwer_0 [31:31] INPUT = lmb_bram_combined_0.mem PLACED = X2Y46;
lmb_bram/lmb_bram/ramb16bwer_1 [30:30] INPUT = lmb_bram_combined_1.mem PLACED = X2Y44;
lmb_bram/lmb_bram/ramb16bwer_2 [29:29] INPUT = lmb_bram_combined_2.mem PLACED = X2Y42;
lmb_bram/lmb_bram/ramb16bwer_3 [28:28] INPUT = lmb_bram_combined_3.mem PLACED = X3Y42;
lmb_bram/lmb_bram/ramb16bwer_4 [27:27] INPUT = lmb_bram_combined_4.mem PLACED = X2Y40;
lmb_bram/lmb_bram/ramb16bwer_5 [26:26] INPUT = lmb_bram_combined_5.mem PLACED = X2Y38;
lmb_bram/lmb_bram/ramb16bwer_6 [25:25] INPUT = lmb_bram_combined_6.mem PLACED = X2Y32;
lmb_bram/lmb_bram/ramb16bwer_7 [24:24] INPUT = lmb_bram_combined_7.mem PLACED = X3Y40;
lmb_bram/lmb_bram/ramb16bwer_8 [23:23] INPUT = lmb_bram_combined_8.mem PLACED = X3Y38;
lmb_bram/lmb_bram/ramb16bwer_9 [22:22] INPUT = lmb_bram_combined_9.mem PLACED = X3Y36;
lmb_bram/lmb_bram/ramb16bwer_10 [21:21] INPUT = lmb_bram_combined_10.mem PLACED = X2Y36;
lmb_bram/lmb_bram/ramb16bwer_11 [20:20] INPUT = lmb_bram_combined_11.mem PLACED = X2Y34;
lmb_bram/lmb_bram/ramb16bwer_12 [19:19] INPUT = lmb_bram_combined_12.mem PLACED = X1Y30;
lmb_bram/lmb_bram/ramb16bwer_13 [18:18] INPUT = lmb_bram_combined_13.mem PLACED = X3Y24;
lmb_bram/lmb_bram/ramb16bwer_14 [17:17] INPUT = lmb_bram_combined_14.mem PLACED = X2Y26;
lmb_bram/lmb_bram/ramb16bwer_15 [16:16] INPUT = lmb_bram_combined_15.mem PLACED = X1Y26;
lmb_bram/lmb_bram/ramb16bwer_16 [15:15] INPUT = lmb_bram_combined_16.mem PLACED = X3Y32;
lmb_bram/lmb_bram/ramb16bwer_17 [14:14] INPUT = lmb_bram_combined_17.mem PLACED = X1Y32;
lmb_bram/lmb_bram/ramb16bwer_18 [13:13] INPUT = lmb_bram_combined_18.mem PLACED = X1Y28;
lmb_bram/lmb_bram/ramb16bwer_19 [12:12] INPUT = lmb_bram_combined_19.mem PLACED = X3Y34;
lmb_bram/lmb_bram/ramb16bwer_20 [11:11] INPUT = lmb_bram_combined_20.mem PLACED = X2Y24;
lmb_bram/lmb_bram/ramb16bwer_21 [10:10] INPUT = lmb_bram_combined_21.mem PLACED = X2Y18;
lmb_bram/lmb_bram/ramb16bwer_22 [9:9] INPUT = lmb_bram_combined_22.mem PLACED = X2Y20;
lmb_bram/lmb_bram/ramb16bwer_23 [8:8] INPUT = lmb_bram_combined_23.mem PLACED = X2Y22;
lmb_bram/lmb_bram/ramb16bwer_24 [7:7] INPUT = lmb_bram_combined_24.mem PLACED = X3Y26;
lmb_bram/lmb_bram/ramb16bwer_25 [6:6] INPUT = lmb_bram_combined_25.mem PLACED = X3Y30;
lmb_bram/lmb_bram/ramb16bwer_26 [5:5] INPUT = lmb_bram_combined_26.mem PLACED = X2Y28;
lmb_bram/lmb_bram/ramb16bwer_27 [4:4] INPUT = lmb_bram_combined_27.mem PLACED = X3Y28;
lmb_bram/lmb_bram/ramb16bwer_28 [3:3] INPUT = lmb_bram_combined_28.mem PLACED = X3Y22;
lmb_bram/lmb_bram/ramb16bwer_29 [2:2] INPUT = lmb_bram_combined_29.mem PLACED = X2Y30;
lmb_bram/lmb_bram/ramb16bwer_30 [1:1] INPUT = lmb_bram_combined_30.mem PLACED = X2Y14;
lmb_bram/lmb_bram/ramb16bwer_31 [0:0] INPUT = lmb_bram_combined_31.mem PLACED = X2Y16;
lmb_bram/lmb_bram/ramb16bwer_0 [31:31] INPUT = lmb_bram_combined_0.mem PLACED = X2Y44;
lmb_bram/lmb_bram/ramb16bwer_1 [30:30] INPUT = lmb_bram_combined_1.mem PLACED = X3Y42;
lmb_bram/lmb_bram/ramb16bwer_2 [29:29] INPUT = lmb_bram_combined_2.mem PLACED = X2Y48;
lmb_bram/lmb_bram/ramb16bwer_3 [28:28] INPUT = lmb_bram_combined_3.mem PLACED = X2Y40;
lmb_bram/lmb_bram/ramb16bwer_4 [27:27] INPUT = lmb_bram_combined_4.mem PLACED = X3Y40;
lmb_bram/lmb_bram/ramb16bwer_5 [26:26] INPUT = lmb_bram_combined_5.mem PLACED = X2Y46;
lmb_bram/lmb_bram/ramb16bwer_6 [25:25] INPUT = lmb_bram_combined_6.mem PLACED = X2Y42;
lmb_bram/lmb_bram/ramb16bwer_7 [24:24] INPUT = lmb_bram_combined_7.mem PLACED = X3Y38;
lmb_bram/lmb_bram/ramb16bwer_8 [23:23] INPUT = lmb_bram_combined_8.mem PLACED = X1Y38;
lmb_bram/lmb_bram/ramb16bwer_9 [22:22] INPUT = lmb_bram_combined_9.mem PLACED = X2Y38;
lmb_bram/lmb_bram/ramb16bwer_10 [21:21] INPUT = lmb_bram_combined_10.mem PLACED = X3Y36;
lmb_bram/lmb_bram/ramb16bwer_11 [20:20] INPUT = lmb_bram_combined_11.mem PLACED = X3Y34;
lmb_bram/lmb_bram/ramb16bwer_12 [19:19] INPUT = lmb_bram_combined_12.mem PLACED = X2Y26;
lmb_bram/lmb_bram/ramb16bwer_13 [18:18] INPUT = lmb_bram_combined_13.mem PLACED = X3Y28;
lmb_bram/lmb_bram/ramb16bwer_14 [17:17] INPUT = lmb_bram_combined_14.mem PLACED = X2Y30;
lmb_bram/lmb_bram/ramb16bwer_15 [16:16] INPUT = lmb_bram_combined_15.mem PLACED = X2Y28;
lmb_bram/lmb_bram/ramb16bwer_16 [15:15] INPUT = lmb_bram_combined_16.mem PLACED = X2Y32;
lmb_bram/lmb_bram/ramb16bwer_17 [14:14] INPUT = lmb_bram_combined_17.mem PLACED = X0Y32;
lmb_bram/lmb_bram/ramb16bwer_18 [13:13] INPUT = lmb_bram_combined_18.mem PLACED = X1Y32;
lmb_bram/lmb_bram/ramb16bwer_19 [12:12] INPUT = lmb_bram_combined_19.mem PLACED = X1Y34;
lmb_bram/lmb_bram/ramb16bwer_20 [11:11] INPUT = lmb_bram_combined_20.mem PLACED = X2Y22;
lmb_bram/lmb_bram/ramb16bwer_21 [10:10] INPUT = lmb_bram_combined_21.mem PLACED = X2Y24;
lmb_bram/lmb_bram/ramb16bwer_22 [9:9] INPUT = lmb_bram_combined_22.mem PLACED = X1Y28;
lmb_bram/lmb_bram/ramb16bwer_23 [8:8] INPUT = lmb_bram_combined_23.mem PLACED = X3Y24;
lmb_bram/lmb_bram/ramb16bwer_24 [7:7] INPUT = lmb_bram_combined_24.mem PLACED = X3Y32;
lmb_bram/lmb_bram/ramb16bwer_25 [6:6] INPUT = lmb_bram_combined_25.mem PLACED = X1Y36;
lmb_bram/lmb_bram/ramb16bwer_26 [5:5] INPUT = lmb_bram_combined_26.mem PLACED = X2Y36;
lmb_bram/lmb_bram/ramb16bwer_27 [4:4] INPUT = lmb_bram_combined_27.mem PLACED = X2Y34;
lmb_bram/lmb_bram/ramb16bwer_28 [3:3] INPUT = lmb_bram_combined_28.mem PLACED = X3Y30;
lmb_bram/lmb_bram/ramb16bwer_29 [2:2] INPUT = lmb_bram_combined_29.mem PLACED = X3Y26;
lmb_bram/lmb_bram/ramb16bwer_30 [1:1] INPUT = lmb_bram_combined_30.mem PLACED = X1Y26;
lmb_bram/lmb_bram/ramb16bwer_31 [0:0] INPUT = lmb_bram_combined_31.mem PLACED = X1Y30;
END_BUS_BLOCK;
END_ADDRESS_SPACE;
......
projnav/xps/SDK/SDK_Workspace/demo/.cproject
View file @ 94c99edd
......@@ -32,7 +32,7 @@
<option id="xilinx.gnu.mb.compiler.inferred.usepcmp.2025998320" superClass="xilinx.gnu.mb.compiler.inferred.usepcmp" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.compiler.inferred.mul.759631855" superClass="xilinx.gnu.mb.compiler.inferred.mul" value="xilinx.gnu.mb.compiler.inferred.mul.32bit" valueType="enumerated"/>
<option id="xilinx.gnu.compiler.inferred.swplatform.includes.8831996" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">
<listOptionValue builtIn="false" value="../../demobsp/microblaze_0/include"/>
<listOptionValue builtIn="false" value="../../standalone_bsp_0/microblaze_0/include"/>
</option>
<inputType id="xilinx.gnu.compiler.input.347712346" name="C source files" superClass="xilinx.gnu.compiler.input"/>
</tool>
......@@ -44,7 +44,7 @@
<option id="xilinx.gnu.mb.compiler.inferred.usepcmp.1786658605" superClass="xilinx.gnu.mb.compiler.inferred.usepcmp" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.compiler.inferred.mul.1923590513" superClass="xilinx.gnu.mb.compiler.inferred.mul" value="xilinx.gnu.mb.compiler.inferred.mul.32bit" valueType="enumerated"/>
<option id="xilinx.gnu.compiler.inferred.swplatform.includes.807993403" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">
<listOptionValue builtIn="false" value="../../demobsp/microblaze_0/include"/>
<listOptionValue builtIn="false" value="../../standalone_bsp_0/microblaze_0/include"/>
</option>
<inputType id="xilinx.gnu.mb.cxx.compiler.input.648873885" name="C++ source files" superClass="xilinx.gnu.mb.cxx.compiler.input"/>
</tool>
......@@ -55,7 +55,7 @@
<option id="xilinx.gnu.mb.linker.inferred.usepcmp.1889097504" superClass="xilinx.gnu.mb.linker.inferred.usepcmp" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.linker.inferred.mul.1038478631" superClass="xilinx.gnu.mb.linker.inferred.mul" value="xilinx.gnu.mb.linker.inferred.mul.32bit" valueType="enumerated"/>
<option id="xilinx.gnu.linker.inferred.swplatform.lpath.1046693538" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">
<listOptionValue builtIn="false" value="../../demobsp/microblaze_0/lib"/>
<listOptionValue builtIn="false" value="../../standalone_bsp_0/microblaze_0/lib"/>
</option>
<inputType id="xilinx.gnu.linker.input.59786092" superClass="xilinx.gnu.linker.input">
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
......@@ -69,7 +69,7 @@
<option id="xilinx.gnu.mb.linker.inferred.usepcmp.683225781" superClass="xilinx.gnu.mb.linker.inferred.usepcmp" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.linker.inferred.mul.1665375810" superClass="xilinx.gnu.mb.linker.inferred.mul" value="xilinx.gnu.mb.linker.inferred.mul.32bit" valueType="enumerated"/>
<option id="xilinx.gnu.linker.inferred.swplatform.lpath.648441665" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">
<listOptionValue builtIn="false" value="../../demobsp/microblaze_0/lib"/>
<listOptionValue builtIn="false" value="../../standalone_bsp_0/microblaze_0/lib"/>
</option>
<inputType id="xilinx.gnu.linker.input.308356398" superClass="xilinx.gnu.linker.input">
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
......@@ -702,6 +702,9 @@
</scannerConfigBuildInfo>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
<storageModule moduleId="org.eclipse.cdt.core.language.mapping"/>
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
</cconfiguration>
<cconfiguration id="xilinx.gnu.mb.exe.release.1874379234">
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="xilinx.gnu.mb.exe.release.1874379234" moduleId="org.eclipse.cdt.core.settings" name="Release">
......@@ -732,7 +735,7 @@
<option id="xilinx.gnu.mb.compiler.inferred.usepcmp.2117022726" superClass="xilinx.gnu.mb.compiler.inferred.usepcmp" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.compiler.inferred.mul.1935521183" superClass="xilinx.gnu.mb.compiler.inferred.mul" value="xilinx.gnu.mb.compiler.inferred.mul.32bit" valueType="enumerated"/>
<option id="xilinx.gnu.compiler.inferred.swplatform.includes.866562977" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">
<listOptionValue builtIn="false" value="../../demobsp/microblaze_0/include"/>
<listOptionValue builtIn="false" value="../../standalone_bsp_0/microblaze_0/include"/>
</option>
<inputType id="xilinx.gnu.compiler.input.794413244" name="C source files" superClass="xilinx.gnu.compiler.input"/>
</tool>
......@@ -744,7 +747,7 @@
<option id="xilinx.gnu.mb.compiler.inferred.usepcmp.1558683552" superClass="xilinx.gnu.mb.compiler.inferred.usepcmp" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.compiler.inferred.mul.13660006" superClass="xilinx.gnu.mb.compiler.inferred.mul" value="xilinx.gnu.mb.compiler.inferred.mul.32bit" valueType="enumerated"/>
<option id="xilinx.gnu.compiler.inferred.swplatform.includes.1802910256" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">
<listOptionValue builtIn="false" value="../../demobsp/microblaze_0/include"/>
<listOptionValue builtIn="false" value="../../standalone_bsp_0/microblaze_0/include"/>
</option>
<inputType id="xilinx.gnu.mb.cxx.compiler.input.2035748458" name="C++ source files" superClass="xilinx.gnu.mb.cxx.compiler.input"/>
</tool>
......@@ -755,7 +758,7 @@
<option id="xilinx.gnu.mb.linker.inferred.usepcmp.2060796612" superClass="xilinx.gnu.mb.linker.inferred.usepcmp" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.linker.inferred.mul.1077867032" superClass="xilinx.gnu.mb.linker.inferred.mul" value="xilinx.gnu.mb.linker.inferred.mul.32bit" valueType="enumerated"/>
<option id="xilinx.gnu.linker.inferred.swplatform.lpath.1203525340" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">
<listOptionValue builtIn="false" value="../../demobsp/microblaze_0/lib"/>
<listOptionValue builtIn="false" value="../../standalone_bsp_0/microblaze_0/lib"/>
</option>
<inputType id="xilinx.gnu.linker.input.1104704384" superClass="xilinx.gnu.linker.input">
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
......@@ -769,7 +772,7 @@
<option id="xilinx.gnu.mb.linker.inferred.usepcmp.1468747866" superClass="xilinx.gnu.mb.linker.inferred.usepcmp" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.linker.inferred.mul.1150761071" superClass="xilinx.gnu.mb.linker.inferred.mul" value="xilinx.gnu.mb.linker.inferred.mul.32bit" valueType="enumerated"/>
<option id="xilinx.gnu.linker.inferred.swplatform.lpath.1133642997" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">
<listOptionValue builtIn="false" value="../../demobsp/microblaze_0/lib"/>
<listOptionValue builtIn="false" value="../../standalone_bsp_0/microblaze_0/lib"/>
</option>
<inputType id="xilinx.gnu.linker.input.300985381" superClass="xilinx.gnu.linker.input">
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
......@@ -1402,6 +1405,9 @@
</scannerConfigBuildInfo>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
<storageModule moduleId="org.eclipse.cdt.core.language.mapping"/>
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
</cconfiguration>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
......
projnav/xps/SDK/SDK_Workspace/demo/.project
View file @ 94c99edd
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>demo</name>
<comment>demobsp - microblaze_0</comment>
<comment></comment>
<projects>
<project>standalone_bsp_0</project>
<project>demobsp</project>
</projects>
<buildSpec>
......
projnav/xps/SDK/SDK_Workspace/demo/Debug/makefile
View file @ 94c99edd
......@@ -50,7 +50,7 @@ all: demo.elf secondary-outputs
demo.elf: $(OBJS) $(USER_OBJS)
@echo Building target: $@
@echo Invoking: MicroBlaze g++ linker
mb-g++ -L../../demobsp/microblaze_0/lib -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.20.a -mno-xl-soft-mul -o"demo.elf" $(OBJS) $(USER_OBJS) $(LIBS)
mb-g++ -L../../standalone_bsp_0/microblaze_0/lib -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.20.a -mno-xl-soft-mul -o"demo.elf" $(OBJS) $(USER_OBJS) $(LIBS)
@echo Finished building target: $@
@echo ' '
......
projnav/xps/SDK/SDK_Workspace/demo/Debug/src/subdir.mk
View file @ 94c99edd
......@@ -17,7 +17,7 @@ CC_DEPS += \
src/%.o: ../src/%.cc
@echo Building file: $<
@echo Invoking: MicroBlaze g++ compiler
mb-g++ -Wall -O0 -g3 -c -fmessage-length=0 -I../../demobsp/microblaze_0/include -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.20.a -mno-xl-soft-mul -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -o"$@" "$<"
mb-g++ -Wall -O0 -g3 -c -fmessage-length=0 -I../../standalone_bsp_0/microblaze_0/include -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.20.a -mno-xl-soft-mul -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -o"$@" "$<"
@echo Finished building: $<
@echo ' '
......
projnav/xps/SDK/SDK_Workspace/demo/src/main.cc
View file @ 94c99edd
......@@ -85,7 +85,7 @@ int DmaCopy(void * pSrc, void * pDest, size_t byteCount)
int main()
{
int status;
int status, i;
// Initialize system
if (XST_SUCCESS != (status = InitDma())) {
......@@ -99,6 +99,42 @@ int main()
// Test DMA
SpiifcDmaTest();
// Spiifc loopback: anything sent to spiifc is sent back
while (1) {
/*
for (i = 0; i < 1024; i++) {
pMisoBase[i] = pMosiBase[i];
}
*/
xil_printf(
"pMosiBase = [ 0x%08x 0x%08x 0x%08x ... ]\n"
"pMisoBase = [ 0x%08x 0x%08x 0x%08x ... ]\n"
"\n",
pMosiBase[0], pMosiBase[1], pMosiBase[2],
pMisoBase[0], pMisoBase[1], pMisoBase[2]);
DmaCopy(pMosiBase, pMisoBase, DMA_BUFFER_BYTE_SIZE);
//xil_printf("debug_out: 0x%08X\n", pSpiifcBase[0]);
/*
xil_printf("pMosiBase = [ 0x%02X 0x%02X 0x%02X 0x%02X ]\n",
pMosiBase[0] & 0xFF, (pMosiBase[0] >> 8) & 0xFF,
(pMosiBase[0] >> 16) & 0xFF, (pMosiBase[0] >> 24) & 0xFF);
xil_printf("pMisoBase = [ 0x%02X 0x%02X 0x%02X 0x%02X ]\n",
pMisoBase[0] & 0xFF, (pMisoBase[0] >> 8) & 0xFF,
(pMisoBase[0] >> 16) & 0xFF, (pMisoBase[0] >> 24) & 0xFF);
*/
}
/*
int i = 0;
for (i = 0; i < 40000000; i++) { ; }
for (i = 0; i < 1024; i++) {
xil_printf("pMOSI[i] = 0x%08X\n", pMosiBase[i]);
}
*/
}
void SpiifcPioTest()
......@@ -142,10 +178,14 @@ void SpiifcDmaTest()
// Pattern DMA memory buffer
for(i = 0; i < DMA_BUFFER_BYTE_SIZE/4; i++) {
pMosiBase[i] = ((i*4) & 0xFF) << 24 |
((i*4+1) & 0xFF) << 16 |
((i*4+2) & 0xFF) << 8 |
((i*4+3) & 0xFF);
pMosiBase[i] = ((i*4+3) & 0xFF) << 24 |
((i*4+2) & 0xFF) << 16 |
((i*4+1) & 0xFF) << 8 |
((i*4+0) & 0xFF);
//pMosiBase[i] = 0xAABBCCDD;
//xil_printf("0x%08X\n", pMosiBase[i]);
}
// DMA buffer to Spiifc.MISO buffer
......@@ -158,14 +198,15 @@ void SpiifcDmaTest()
u32 expectedDmaWord = 0;
int failWords = 0;
for (i = 0; i < (DMA_BUFFER_BYTE_SIZE/4); i++) {
expectedDmaWord = ((i*4+0) & 0xFF) << 24 |
((i*4+1) & 0xFF) << 16 |
((i*4+2) & 0xFF) << 8 |
((i*4+3) & 0xFF) << 0;
expectedDmaWord = ((i*4+3) & 0xFF) << 24 |
((i*4+2) & 0xFF) << 16 |
((i*4+1) & 0xFF) << 8 |
((i*4+0) & 0xFF) << 0;
if (pMisoBase[i] != expectedDmaWord) {
xil_printf(
"[FAIL] DMA mem word [i]: expected=0x%08X, actual=0x%08X\n",
expectedDmaWord, pMisoBase);
expectedDmaWord, pMisoBase[i]);
}
}
if (0 == failWords) {
......
projnav/xps/SDK/SDK_Workspace/demobsp/.cproject → projnav/xps/SDK/SDK_Workspace/standalone_bsp_0/.cproject
View file @ 94c99edd
......@@ -3,8 +3,8 @@
<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
<storageModule moduleId="org.eclipse.cdt.core.settings">
<cconfiguration id="org.eclipse.cdt.core.default.config.948582058">
<storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.948582058" moduleId="org.eclipse.cdt.core.settings" name="Configuration">
<cconfiguration id="org.eclipse.cdt.core.default.config.1065451617">
<storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.1065451617" moduleId="org.eclipse.cdt.core.settings" name="Configuration">
<externalSettings/>
<extensions/>
</storageModule>
......
projnav/xps/SDK/SDK_Workspace/demobsp/.project → projnav/xps/SDK/SDK_Workspace/standalone_bsp_0/.project
View file @ 94c99edd
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>demobsp</name>
<name>standalone_bsp_0</name>
<comment></comment>
<projects>
<project>xps_hw_platform</project>
......
projnav/xps/SDK/SDK_Workspace/standalone_bsp_0/libgen.log 0 → 100644
View file @ 94c99edd
Release 13.2 - libgen Xilinx EDK 13.2 Build EDK_O.61xd
(nt64)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
Command Line: libgen -hw ../xps_hw_platform/system.xml -pe microblaze_0 -log
libgen.log system.mss
Staging source files.
Running DRCs.
Running generate.
Running post_generate.
Running include - 'make -s include "COMPILER=mb-gcc" "ARCHIVER=mb-ar"
"COMPILER_FLAGS=-mno-xl-soft-mul -mxl-barrel-shift -mxl-pattern-compare
-mcpu=v8.20.a -O2 -c" "EXTRA_COMPILER_FLAGS=-g"'.
Running libs - 'make -s libs "COMPILER=mb-gcc" "ARCHIVER=mb-ar"
"COMPILER_FLAGS=-mno-xl-soft-mul -mxl-barrel-shift -mxl-pattern-compare
-mcpu=v8.20.a -O2 -c" "EXTRA_COMPILER_FLAGS=-g"'.
Running execs_generate.
projnav/xps/SDK/SDK_Workspace/xps_hw_platform/system.xml
View file @ 94c99edd
<EDKSYSTEM EDKVERSION="13.2" EDWVERSION="1.2" TIMESTAMP="Wed Feb 29 10:59:16 2012">
<EDKSYSTEM EDKVERSION="13.2" EDWVERSION="1.2" TIMESTAMP="Tue Mar 06 16:45:32 2012">
<SYSTEMINFO ARCH="spartan6" DEVICE="xc6slx45" PACKAGE="csg324" PART="xc6slx45csg324-2" SOURCE="C:/Users/mjlyons/workspace/vSPI/projnav/xps/system.xmp" SPEEDGRADE="-2"/>
......@@ -9,6 +9,10 @@
<PORT DIR="I" ENDIAN="BIG" LEFT="0" LSB="4" MHS_INDEX="2" MSB="0" NAME="fpga_0_Push_Buttons_5Bits_GPIO_IO_I_pin" RIGHT="4" SIGNAME="fpga_0_Push_Buttons_5Bits_GPIO_IO_I_pin"/>
<PORT CLKFREQUENCY="100000000" DIR="I" MHS_INDEX="3" NAME="fpga_0_clk_1_sys_clk_pin" SIGIS="CLK" SIGNAME="CLK_S"/>
<PORT DIR="I" MHS_INDEX="4" NAME="fpga_0_rst_1_sys_rst_pin" RSTPOLARITY="0" SIGIS="RST" SIGNAME="sys_rst_s"/>
<PORT CLKFREQUENCY="50000000" DIR="I" MHS_INDEX="5" NAME="spiifc_0_SPI_CLK_pin" SIGIS="CLK" SIGNAME="spiifc_0_SPI_CLK"/>
<PORT DIR="O" MHS_INDEX="6" NAME="spiifc_0_SPI_MISO_pin" SIGNAME="spiifc_0_SPI_MISO"/>
<PORT DIR="I" MHS_INDEX="7" NAME="spiifc_0_SPI_MOSI_pin" SIGNAME="spiifc_0_SPI_MOSI"/>
<PORT DIR="I" MHS_INDEX="8" NAME="spiifc_0_SPI_SS_pin" SIGNAME="spiifc_0_SPI_SS"/>
</EXTERNALPORTS>
<MODULES>
......@@ -4592,49 +4596,53 @@
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="16" NAME="C_MEM1_HIGHADDR" TYPE="std_logic_vector" VALUE="0x85011FFF"/>
</PARAMETERS>
<PORTS>
<PORT BUS="SPLB" CLKFREQUENCY="66666666" DEF_SIGNAME="clk_66_6667MHz" DIR="I" MPD_INDEX="0" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="clk_66_6667MHz"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_SPLB_Rst" DIR="I" MPD_INDEX="1" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="mb_plb_SPLB_Rst"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="mb_plb_PLB_ABus" VECFORMULA="[0:31]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_UABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="mb_plb_PLB_UABus" VECFORMULA="[0:31]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_PAValid" DIR="I" MPD_INDEX="4" NAME="PLB_PAValid" SIGNAME="mb_plb_PLB_PAValid"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_SAValid" DIR="I" MPD_INDEX="5" NAME="PLB_SAValid" SIGNAME="mb_plb_PLB_SAValid"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPrim" DIR="I" MPD_INDEX="6" NAME="PLB_rdPrim" SIGNAME="mb_plb_PLB_rdPrim"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPrim" DIR="I" MPD_INDEX="7" NAME="PLB_wrPrim" SIGNAME="mb_plb_PLB_wrPrim"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_masterID" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="8" MSB="0" NAME="PLB_masterID" RIGHT="1" SIGNAME="mb_plb_PLB_masterID" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_abort" DIR="I" MPD_INDEX="9" NAME="PLB_abort" SIGNAME="mb_plb_PLB_abort"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_busLock" DIR="I" MPD_INDEX="10" NAME="PLB_busLock" SIGNAME="mb_plb_PLB_busLock"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_RNW" DIR="I" MPD_INDEX="11" NAME="PLB_RNW" SIGNAME="mb_plb_PLB_RNW"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="12" MSB="0" NAME="PLB_BE" RIGHT="3" SIGNAME="mb_plb_PLB_BE" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_MSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="13" MSB="0" NAME="PLB_MSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSize" VECFORMULA="[0:1]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_size" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="14" MSB="0" NAME="PLB_size" RIGHT="3" SIGNAME="mb_plb_PLB_size" VECFORMULA="[0:3]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_type" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="15" MSB="0" NAME="PLB_type" RIGHT="2" SIGNAME="mb_plb_PLB_type" VECFORMULA="[0:2]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_lockErr" DIR="I" MPD_INDEX="16" NAME="PLB_lockErr" SIGNAME="mb_plb_PLB_lockErr"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="17" MSB="0" NAME="PLB_wrDBus" RIGHT="31" SIGNAME="mb_plb_PLB_wrDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrBurst" DIR="I" MPD_INDEX="18" NAME="PLB_wrBurst" SIGNAME="mb_plb_PLB_wrBurst"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdBurst" DIR="I" MPD_INDEX="19" NAME="PLB_rdBurst" SIGNAME="mb_plb_PLB_rdBurst"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendReq" DIR="I" MPD_INDEX="20" NAME="PLB_wrPendReq" SIGNAME="mb_plb_PLB_wrPendReq"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendReq" DIR="I" MPD_INDEX="21" NAME="PLB_rdPendReq" SIGNAME="mb_plb_PLB_rdPendReq"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="22" MSB="0" NAME="PLB_wrPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_wrPendPri" VECFORMULA="[0:1]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="23" MSB="0" NAME="PLB_rdPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_rdPendPri" VECFORMULA="[0:1]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_reqPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="24" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="mb_plb_PLB_reqPri" VECFORMULA="[0:1]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_TAttribute" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="25" MSB="0" NAME="PLB_TAttribute" RIGHT="15" SIGNAME="mb_plb_PLB_TAttribute" VECFORMULA="[0:15]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_addrAck" DIR="O" MPD_INDEX="26" NAME="Sl_addrAck" SIGNAME="mb_plb_Sl_addrAck"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_SSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="27" MSB="0" NAME="Sl_SSize" RIGHT="1" SIGNAME="mb_plb_Sl_SSize" VECFORMULA="[0:1]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wait" DIR="O" MPD_INDEX="28" NAME="Sl_wait" SIGNAME="mb_plb_Sl_wait"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rearbitrate" DIR="O" MPD_INDEX="29" NAME="Sl_rearbitrate" SIGNAME="mb_plb_Sl_rearbitrate"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrDAck" DIR="O" MPD_INDEX="30" NAME="Sl_wrDAck" SIGNAME="mb_plb_Sl_wrDAck"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrComp" DIR="O" MPD_INDEX="31" NAME="Sl_wrComp" SIGNAME="mb_plb_Sl_wrComp"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrBTerm" DIR="O" MPD_INDEX="32" NAME="Sl_wrBTerm" SIGNAME="mb_plb_Sl_wrBTerm"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="33" MSB="0" NAME="Sl_rdDBus" RIGHT="31" SIGNAME="mb_plb_Sl_rdDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdWdAddr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="34" MSB="0" NAME="Sl_rdWdAddr" RIGHT="3" SIGNAME="mb_plb_Sl_rdWdAddr" VECFORMULA="[0:3]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDAck" DIR="O" MPD_INDEX="35" NAME="Sl_rdDAck" SIGNAME="mb_plb_Sl_rdDAck"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdComp" DIR="O" MPD_INDEX="36" NAME="Sl_rdComp" SIGNAME="mb_plb_Sl_rdComp"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdBTerm" DIR="O" MPD_INDEX="37" NAME="Sl_rdBTerm" SIGNAME="mb_plb_Sl_rdBTerm"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MBusy" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="38" MSB="0" NAME="Sl_MBusy" RIGHT="2" SIGNAME="mb_plb_Sl_MBusy" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MWrErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="39" MSB="0" NAME="Sl_MWrErr" RIGHT="2" SIGNAME="mb_plb_Sl_MWrErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MRdErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="40" MSB="0" NAME="Sl_MRdErr" RIGHT="2" SIGNAME="mb_plb_Sl_MRdErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MIRQ" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="41" MSB="0" NAME="Sl_MIRQ" RIGHT="2" SIGNAME="mb_plb_Sl_MIRQ" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
<PORT DIR="O" MPD_INDEX="42" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
<PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SPI_CLK" SIGNAME="spiifc_0_SPI_CLK"/>
<PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="SPI_MOSI" SIGNAME="spiifc_0_SPI_MOSI"/>
<PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="2" NAME="SPI_MISO" SIGNAME="spiifc_0_SPI_MISO"/>
<PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="3" NAME="SPI_SS" SIGNAME="spiifc_0_SPI_SS"/>
<PORT BUS="SPLB" CLKFREQUENCY="66666666" DEF_SIGNAME="clk_66_6667MHz" DIR="I" MPD_INDEX="4" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="clk_66_6667MHz"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_SPLB_Rst" DIR="I" MPD_INDEX="5" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="mb_plb_SPLB_Rst"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="6" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="mb_plb_PLB_ABus" VECFORMULA="[0:31]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_UABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="7" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="mb_plb_PLB_UABus" VECFORMULA="[0:31]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_PAValid" DIR="I" MPD_INDEX="8" NAME="PLB_PAValid" SIGNAME="mb_plb_PLB_PAValid"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_SAValid" DIR="I" MPD_INDEX="9" NAME="PLB_SAValid" SIGNAME="mb_plb_PLB_SAValid"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPrim" DIR="I" MPD_INDEX="10" NAME="PLB_rdPrim" SIGNAME="mb_plb_PLB_rdPrim"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPrim" DIR="I" MPD_INDEX="11" NAME="PLB_wrPrim" SIGNAME="mb_plb_PLB_wrPrim"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_masterID" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="12" MSB="0" NAME="PLB_masterID" RIGHT="1" SIGNAME="mb_plb_PLB_masterID" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_abort" DIR="I" MPD_INDEX="13" NAME="PLB_abort" SIGNAME="mb_plb_PLB_abort"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_busLock" DIR="I" MPD_INDEX="14" NAME="PLB_busLock" SIGNAME="mb_plb_PLB_busLock"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_RNW" DIR="I" MPD_INDEX="15" NAME="PLB_RNW" SIGNAME="mb_plb_PLB_RNW"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="16" MSB="0" NAME="PLB_BE" RIGHT="3" SIGNAME="mb_plb_PLB_BE" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_MSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="17" MSB="0" NAME="PLB_MSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSize" VECFORMULA="[0:1]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_size" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="18" MSB="0" NAME="PLB_size" RIGHT="3" SIGNAME="mb_plb_PLB_size" VECFORMULA="[0:3]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_type" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="19" MSB="0" NAME="PLB_type" RIGHT="2" SIGNAME="mb_plb_PLB_type" VECFORMULA="[0:2]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_lockErr" DIR="I" MPD_INDEX="20" NAME="PLB_lockErr" SIGNAME="mb_plb_PLB_lockErr"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="21" MSB="0" NAME="PLB_wrDBus" RIGHT="31" SIGNAME="mb_plb_PLB_wrDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrBurst" DIR="I" MPD_INDEX="22" NAME="PLB_wrBurst" SIGNAME="mb_plb_PLB_wrBurst"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdBurst" DIR="I" MPD_INDEX="23" NAME="PLB_rdBurst" SIGNAME="mb_plb_PLB_rdBurst"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendReq" DIR="I" MPD_INDEX="24" NAME="PLB_wrPendReq" SIGNAME="mb_plb_PLB_wrPendReq"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendReq" DIR="I" MPD_INDEX="25" NAME="PLB_rdPendReq" SIGNAME="mb_plb_PLB_rdPendReq"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="26" MSB="0" NAME="PLB_wrPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_wrPendPri" VECFORMULA="[0:1]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="27" MSB="0" NAME="PLB_rdPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_rdPendPri" VECFORMULA="[0:1]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_reqPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="28" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="mb_plb_PLB_reqPri" VECFORMULA="[0:1]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_TAttribute" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="29" MSB="0" NAME="PLB_TAttribute" RIGHT="15" SIGNAME="mb_plb_PLB_TAttribute" VECFORMULA="[0:15]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_addrAck" DIR="O" MPD_INDEX="30" NAME="Sl_addrAck" SIGNAME="mb_plb_Sl_addrAck"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_SSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="31" MSB="0" NAME="Sl_SSize" RIGHT="1" SIGNAME="mb_plb_Sl_SSize" VECFORMULA="[0:1]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wait" DIR="O" MPD_INDEX="32" NAME="Sl_wait" SIGNAME="mb_plb_Sl_wait"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rearbitrate" DIR="O" MPD_INDEX="33" NAME="Sl_rearbitrate" SIGNAME="mb_plb_Sl_rearbitrate"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrDAck" DIR="O" MPD_INDEX="34" NAME="Sl_wrDAck" SIGNAME="mb_plb_Sl_wrDAck"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrComp" DIR="O" MPD_INDEX="35" NAME="Sl_wrComp" SIGNAME="mb_plb_Sl_wrComp"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrBTerm" DIR="O" MPD_INDEX="36" NAME="Sl_wrBTerm" SIGNAME="mb_plb_Sl_wrBTerm"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="37" MSB="0" NAME="Sl_rdDBus" RIGHT="31" SIGNAME="mb_plb_Sl_rdDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdWdAddr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="38" MSB="0" NAME="Sl_rdWdAddr" RIGHT="3" SIGNAME="mb_plb_Sl_rdWdAddr" VECFORMULA="[0:3]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDAck" DIR="O" MPD_INDEX="39" NAME="Sl_rdDAck" SIGNAME="mb_plb_Sl_rdDAck"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdComp" DIR="O" MPD_INDEX="40" NAME="Sl_rdComp" SIGNAME="mb_plb_Sl_rdComp"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdBTerm" DIR="O" MPD_INDEX="41" NAME="Sl_rdBTerm" SIGNAME="mb_plb_Sl_rdBTerm"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MBusy" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="42" MSB="0" NAME="Sl_MBusy" RIGHT="2" SIGNAME="mb_plb_Sl_MBusy" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MWrErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="43" MSB="0" NAME="Sl_MWrErr" RIGHT="2" SIGNAME="mb_plb_Sl_MWrErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MRdErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="44" MSB="0" NAME="Sl_MRdErr" RIGHT="2" SIGNAME="mb_plb_Sl_MRdErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MIRQ" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="45" MSB="0" NAME="Sl_MIRQ" RIGHT="2" SIGNAME="mb_plb_Sl_MIRQ" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
<PORT DIR="O" MPD_INDEX="46" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="mb_plb" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SPLB" TYPE="SLAVE">
......
projnav/xps/SDK/SDK_Workspace/xps_hw_platform/system_bd.bmm
View file @ 94c99edd
......@@ -21,38 +21,38 @@ ADDRESS_MAP microblaze_0 MICROBLAZE 100
ADDRESS_SPACE lmb_bram_combined RAMB16 [0x00000000:0x0000FFFF]
BUS_BLOCK
lmb_bram/lmb_bram/ramb16bwer_0 [31:31] INPUT = lmb_bram_combined_0.mem PLACED = X2Y46;
lmb_bram/lmb_bram/ramb16bwer_1 [30:30] INPUT = lmb_bram_combined_1.mem PLACED = X2Y44;
lmb_bram/lmb_bram/ramb16bwer_2 [29:29] INPUT = lmb_bram_combined_2.mem PLACED = X2Y42;
lmb_bram/lmb_bram/ramb16bwer_3 [28:28] INPUT = lmb_bram_combined_3.mem PLACED = X3Y42;
lmb_bram/lmb_bram/ramb16bwer_4 [27:27] INPUT = lmb_bram_combined_4.mem PLACED = X2Y40;
lmb_bram/lmb_bram/ramb16bwer_5 [26:26] INPUT = lmb_bram_combined_5.mem PLACED = X2Y38;
lmb_bram/lmb_bram/ramb16bwer_6 [25:25] INPUT = lmb_bram_combined_6.mem PLACED = X2Y32;
lmb_bram/lmb_bram/ramb16bwer_7 [24:24] INPUT = lmb_bram_combined_7.mem PLACED = X3Y40;
lmb_bram/lmb_bram/ramb16bwer_8 [23:23] INPUT = lmb_bram_combined_8.mem PLACED = X3Y38;
lmb_bram/lmb_bram/ramb16bwer_9 [22:22] INPUT = lmb_bram_combined_9.mem PLACED = X3Y36;
lmb_bram/lmb_bram/ramb16bwer_10 [21:21] INPUT = lmb_bram_combined_10.mem PLACED = X2Y36;
lmb_bram/lmb_bram/ramb16bwer_11 [20:20] INPUT = lmb_bram_combined_11.mem PLACED = X2Y34;
lmb_bram/lmb_bram/ramb16bwer_12 [19:19] INPUT = lmb_bram_combined_12.mem PLACED = X1Y30;
lmb_bram/lmb_bram/ramb16bwer_13 [18:18] INPUT = lmb_bram_combined_13.mem PLACED = X3Y24;
lmb_bram/lmb_bram/ramb16bwer_14 [17:17] INPUT = lmb_bram_combined_14.mem PLACED = X2Y26;
lmb_bram/lmb_bram/ramb16bwer_15 [16:16] INPUT = lmb_bram_combined_15.mem PLACED = X1Y26;
lmb_bram/lmb_bram/ramb16bwer_16 [15:15] INPUT = lmb_bram_combined_16.mem PLACED = X3Y32;
lmb_bram/lmb_bram/ramb16bwer_17 [14:14] INPUT = lmb_bram_combined_17.mem PLACED = X1Y32;
lmb_bram/lmb_bram/ramb16bwer_18 [13:13] INPUT = lmb_bram_combined_18.mem PLACED = X1Y28;
lmb_bram/lmb_bram/ramb16bwer_19 [12:12] INPUT = lmb_bram_combined_19.mem PLACED = X3Y34;
lmb_bram/lmb_bram/ramb16bwer_20 [11:11] INPUT = lmb_bram_combined_20.mem PLACED = X2Y24;
lmb_bram/lmb_bram/ramb16bwer_21 [10:10] INPUT = lmb_bram_combined_21.mem PLACED = X2Y18;
lmb_bram/lmb_bram/ramb16bwer_22 [9:9] INPUT = lmb_bram_combined_22.mem PLACED = X2Y20;
lmb_bram/lmb_bram/ramb16bwer_23 [8:8] INPUT = lmb_bram_combined_23.mem PLACED = X2Y22;
lmb_bram/lmb_bram/ramb16bwer_24 [7:7] INPUT = lmb_bram_combined_24.mem PLACED = X3Y26;
lmb_bram/lmb_bram/ramb16bwer_25 [6:6] INPUT = lmb_bram_combined_25.mem PLACED = X3Y30;
lmb_bram/lmb_bram/ramb16bwer_26 [5:5] INPUT = lmb_bram_combined_26.mem PLACED = X2Y28;
lmb_bram/lmb_bram/ramb16bwer_27 [4:4] INPUT = lmb_bram_combined_27.mem PLACED = X3Y28;
lmb_bram/lmb_bram/ramb16bwer_28 [3:3] INPUT = lmb_bram_combined_28.mem PLACED = X3Y22;
lmb_bram/lmb_bram/ramb16bwer_29 [2:2] INPUT = lmb_bram_combined_29.mem PLACED = X2Y30;
lmb_bram/lmb_bram/ramb16bwer_30 [1:1] INPUT = lmb_bram_combined_30.mem PLACED = X2Y14;
lmb_bram/lmb_bram/ramb16bwer_31 [0:0] INPUT = lmb_bram_combined_31.mem PLACED = X2Y16;
lmb_bram/lmb_bram/ramb16bwer_0 [31:31] INPUT = lmb_bram_combined_0.mem PLACED = X2Y44;
lmb_bram/lmb_bram/ramb16bwer_1 [30:30] INPUT = lmb_bram_combined_1.mem PLACED = X3Y42;
lmb_bram/lmb_bram/ramb16bwer_2 [29:29] INPUT = lmb_bram_combined_2.mem PLACED = X2Y48;
lmb_bram/lmb_bram/ramb16bwer_3 [28:28] INPUT = lmb_bram_combined_3.mem PLACED = X2Y40;
lmb_bram/lmb_bram/ramb16bwer_4 [27:27] INPUT = lmb_bram_combined_4.mem PLACED = X3Y40;
lmb_bram/lmb_bram/ramb16bwer_5 [26:26] INPUT = lmb_bram_combined_5.mem PLACED = X2Y46;
lmb_bram/lmb_bram/ramb16bwer_6 [25:25] INPUT = lmb_bram_combined_6.mem PLACED = X2Y42;
lmb_bram/lmb_bram/ramb16bwer_7 [24:24] INPUT = lmb_bram_combined_7.mem PLACED = X3Y38;
lmb_bram/lmb_bram/ramb16bwer_8 [23:23] INPUT = lmb_bram_combined_8.mem PLACED = X1Y38;
lmb_bram/lmb_bram/ramb16bwer_9 [22:22] INPUT = lmb_bram_combined_9.mem PLACED = X2Y38;
lmb_bram/lmb_bram/ramb16bwer_10 [21:21] INPUT = lmb_bram_combined_10.mem PLACED = X3Y36;
lmb_bram/lmb_bram/ramb16bwer_11 [20:20] INPUT = lmb_bram_combined_11.mem PLACED = X3Y34;
lmb_bram/lmb_bram/ramb16bwer_12 [19:19] INPUT = lmb_bram_combined_12.mem PLACED = X2Y26;
lmb_bram/lmb_bram/ramb16bwer_13 [18:18] INPUT = lmb_bram_combined_13.mem PLACED = X3Y28;
lmb_bram/lmb_bram/ramb16bwer_14 [17:17] INPUT = lmb_bram_combined_14.mem PLACED = X2Y30;
lmb_bram/lmb_bram/ramb16bwer_15 [16:16] INPUT = lmb_bram_combined_15.mem PLACED = X2Y28;
lmb_bram/lmb_bram/ramb16bwer_16 [15:15] INPUT = lmb_bram_combined_16.mem PLACED = X2Y32;
lmb_bram/lmb_bram/ramb16bwer_17 [14:14] INPUT = lmb_bram_combined_17.mem PLACED = X0Y32;
lmb_bram/lmb_bram/ramb16bwer_18 [13:13] INPUT = lmb_bram_combined_18.mem PLACED = X1Y32;
lmb_bram/lmb_bram/ramb16bwer_19 [12:12] INPUT = lmb_bram_combined_19.mem PLACED = X1Y34;
lmb_bram/lmb_bram/ramb16bwer_20 [11:11] INPUT = lmb_bram_combined_20.mem PLACED = X2Y22;
lmb_bram/lmb_bram/ramb16bwer_21 [10:10] INPUT = lmb_bram_combined_21.mem PLACED = X2Y24;
lmb_bram/lmb_bram/ramb16bwer_22 [9:9] INPUT = lmb_bram_combined_22.mem PLACED = X1Y28;
lmb_bram/lmb_bram/ramb16bwer_23 [8:8] INPUT = lmb_bram_combined_23.mem PLACED = X3Y24;
lmb_bram/lmb_bram/ramb16bwer_24 [7:7] INPUT = lmb_bram_combined_24.mem PLACED = X3Y32;
lmb_bram/lmb_bram/ramb16bwer_25 [6:6] INPUT = lmb_bram_combined_25.mem PLACED = X1Y36;
lmb_bram/lmb_bram/ramb16bwer_26 [5:5] INPUT = lmb_bram_combined_26.mem PLACED = X2Y36;
lmb_bram/lmb_bram/ramb16bwer_27 [4:4] INPUT = lmb_bram_combined_27.mem PLACED = X2Y34;
lmb_bram/lmb_bram/ramb16bwer_28 [3:3] INPUT = lmb_bram_combined_28.mem PLACED = X3Y30;
lmb_bram/lmb_bram/ramb16bwer_29 [2:2] INPUT = lmb_bram_combined_29.mem PLACED = X3Y26;
lmb_bram/lmb_bram/ramb16bwer_30 [1:1] INPUT = lmb_bram_combined_30.mem PLACED = X1Y26;
lmb_bram/lmb_bram/ramb16bwer_31 [0:0] INPUT = lmb_bram_combined_31.mem PLACED = X1Y30;
END_BUS_BLOCK;
END_ADDRESS_SPACE;
......
projnav/xps/__xps/ise/system.xreport
View file @ 94c99edd
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2012-03-01T09:28:38</DateModified>
<DateModified>2012-03-06T18:05:57</DateModified>
<ModuleName>system</ModuleName>
<SummaryTimeStamp>2012-03-01T09:28:36</SummaryTimeStamp>
<SummaryTimeStamp>2012-03-06T18:05:56</SummaryTimeStamp>
<SavedFilePath>C:/Users/mjlyons/workspace/vSPI/projnav/xps/__xps/ise/system.xreport</SavedFilePath>
<FilterFile>filter.filter</FilterFile>
<SavedFilterFilePath>C:/Users/mjlyons/workspace/vSPI/projnav/xps/__xps/ise</SavedFilterFilePath>
......
projnav/xps/__xps/system.xml
View file @ 94c99edd
<EDKSYSTEM EDKVERSION="13.2" EDWVERSION="1.2" TIMESTAMP="Thu Mar 01 09:28:39 2012">
<EDKSYSTEM EDKVERSION="13.2" EDWVERSION="1.2" TIMESTAMP="Tue Mar 06 18:05:58 2012">
<SYSTEMINFO ARCH="spartan6" DEVICE="xc6slx45" PACKAGE="csg324" PART="xc6slx45csg324-2" SOURCE="C:/Users/mjlyons/workspace/vSPI/projnav/xps/system.xmp" SPEEDGRADE="-2"/>
......@@ -9,6 +9,10 @@
<PORT DIR="I" ENDIAN="BIG" LEFT="0" LSB="4" MHS_INDEX="2" MSB="0" NAME="fpga_0_Push_Buttons_5Bits_GPIO_IO_I_pin" RIGHT="4" SIGNAME="fpga_0_Push_Buttons_5Bits_GPIO_IO_I_pin"/>
<PORT CLKFREQUENCY="100000000" DIR="I" MHS_INDEX="3" NAME="fpga_0_clk_1_sys_clk_pin" SIGIS="CLK" SIGNAME="CLK_S"/>
<PORT DIR="I" MHS_INDEX="4" NAME="fpga_0_rst_1_sys_rst_pin" RSTPOLARITY="0" SIGIS="RST" SIGNAME="sys_rst_s"/>
<PORT CLKFREQUENCY="50000000" DIR="I" MHS_INDEX="5" NAME="spiifc_0_SPI_CLK_pin" SIGIS="CLK" SIGNAME="spiifc_0_SPI_CLK"/>
<PORT DIR="O" MHS_INDEX="6" NAME="spiifc_0_SPI_MISO_pin" SIGNAME="spiifc_0_SPI_MISO"/>
<PORT DIR="I" MHS_INDEX="7" NAME="spiifc_0_SPI_MOSI_pin" SIGNAME="spiifc_0_SPI_MOSI"/>
<PORT DIR="I" MHS_INDEX="8" NAME="spiifc_0_SPI_SS_pin" SIGNAME="spiifc_0_SPI_SS"/>
</EXTERNALPORTS>
<MODULES>
......@@ -3919,49 +3923,53 @@
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="16" NAME="C_MEM1_HIGHADDR" TYPE="std_logic_vector" VALUE="0x85011FFF"/>
</PARAMETERS>
<PORTS>
<PORT BUS="SPLB" CLKFREQUENCY="66666666" DEF_SIGNAME="clk_66_6667MHz" DIR="I" MPD_INDEX="0" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="clk_66_6667MHz"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_SPLB_Rst" DIR="I" MPD_INDEX="1" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="mb_plb_SPLB_Rst"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="mb_plb_PLB_ABus" VECFORMULA="[0:31]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_UABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="mb_plb_PLB_UABus" VECFORMULA="[0:31]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_PAValid" DIR="I" MPD_INDEX="4" NAME="PLB_PAValid" SIGNAME="mb_plb_PLB_PAValid"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_SAValid" DIR="I" MPD_INDEX="5" NAME="PLB_SAValid" SIGNAME="mb_plb_PLB_SAValid"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPrim" DIR="I" MPD_INDEX="6" NAME="PLB_rdPrim" SIGNAME="mb_plb_PLB_rdPrim"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPrim" DIR="I" MPD_INDEX="7" NAME="PLB_wrPrim" SIGNAME="mb_plb_PLB_wrPrim"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_masterID" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="8" MSB="0" NAME="PLB_masterID" RIGHT="1" SIGNAME="mb_plb_PLB_masterID" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_abort" DIR="I" MPD_INDEX="9" NAME="PLB_abort" SIGNAME="mb_plb_PLB_abort"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_busLock" DIR="I" MPD_INDEX="10" NAME="PLB_busLock" SIGNAME="mb_plb_PLB_busLock"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_RNW" DIR="I" MPD_INDEX="11" NAME="PLB_RNW" SIGNAME="mb_plb_PLB_RNW"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="12" MSB="0" NAME="PLB_BE" RIGHT="3" SIGNAME="mb_plb_PLB_BE" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_MSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="13" MSB="0" NAME="PLB_MSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSize" VECFORMULA="[0:1]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_size" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="14" MSB="0" NAME="PLB_size" RIGHT="3" SIGNAME="mb_plb_PLB_size" VECFORMULA="[0:3]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_type" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="15" MSB="0" NAME="PLB_type" RIGHT="2" SIGNAME="mb_plb_PLB_type" VECFORMULA="[0:2]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_lockErr" DIR="I" MPD_INDEX="16" NAME="PLB_lockErr" SIGNAME="mb_plb_PLB_lockErr"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="17" MSB="0" NAME="PLB_wrDBus" RIGHT="31" SIGNAME="mb_plb_PLB_wrDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrBurst" DIR="I" MPD_INDEX="18" NAME="PLB_wrBurst" SIGNAME="mb_plb_PLB_wrBurst"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdBurst" DIR="I" MPD_INDEX="19" NAME="PLB_rdBurst" SIGNAME="mb_plb_PLB_rdBurst"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendReq" DIR="I" MPD_INDEX="20" NAME="PLB_wrPendReq" SIGNAME="mb_plb_PLB_wrPendReq"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendReq" DIR="I" MPD_INDEX="21" NAME="PLB_rdPendReq" SIGNAME="mb_plb_PLB_rdPendReq"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="22" MSB="0" NAME="PLB_wrPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_wrPendPri" VECFORMULA="[0:1]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="23" MSB="0" NAME="PLB_rdPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_rdPendPri" VECFORMULA="[0:1]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_reqPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="24" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="mb_plb_PLB_reqPri" VECFORMULA="[0:1]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_TAttribute" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="25" MSB="0" NAME="PLB_TAttribute" RIGHT="15" SIGNAME="mb_plb_PLB_TAttribute" VECFORMULA="[0:15]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_addrAck" DIR="O" MPD_INDEX="26" NAME="Sl_addrAck" SIGNAME="mb_plb_Sl_addrAck"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_SSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="27" MSB="0" NAME="Sl_SSize" RIGHT="1" SIGNAME="mb_plb_Sl_SSize" VECFORMULA="[0:1]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wait" DIR="O" MPD_INDEX="28" NAME="Sl_wait" SIGNAME="mb_plb_Sl_wait"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rearbitrate" DIR="O" MPD_INDEX="29" NAME="Sl_rearbitrate" SIGNAME="mb_plb_Sl_rearbitrate"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrDAck" DIR="O" MPD_INDEX="30" NAME="Sl_wrDAck" SIGNAME="mb_plb_Sl_wrDAck"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrComp" DIR="O" MPD_INDEX="31" NAME="Sl_wrComp" SIGNAME="mb_plb_Sl_wrComp"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrBTerm" DIR="O" MPD_INDEX="32" NAME="Sl_wrBTerm" SIGNAME="mb_plb_Sl_wrBTerm"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="33" MSB="0" NAME="Sl_rdDBus" RIGHT="31" SIGNAME="mb_plb_Sl_rdDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdWdAddr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="34" MSB="0" NAME="Sl_rdWdAddr" RIGHT="3" SIGNAME="mb_plb_Sl_rdWdAddr" VECFORMULA="[0:3]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDAck" DIR="O" MPD_INDEX="35" NAME="Sl_rdDAck" SIGNAME="mb_plb_Sl_rdDAck"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdComp" DIR="O" MPD_INDEX="36" NAME="Sl_rdComp" SIGNAME="mb_plb_Sl_rdComp"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdBTerm" DIR="O" MPD_INDEX="37" NAME="Sl_rdBTerm" SIGNAME="mb_plb_Sl_rdBTerm"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MBusy" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="38" MSB="0" NAME="Sl_MBusy" RIGHT="2" SIGNAME="mb_plb_Sl_MBusy" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MWrErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="39" MSB="0" NAME="Sl_MWrErr" RIGHT="2" SIGNAME="mb_plb_Sl_MWrErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MRdErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="40" MSB="0" NAME="Sl_MRdErr" RIGHT="2" SIGNAME="mb_plb_Sl_MRdErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MIRQ" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="41" MSB="0" NAME="Sl_MIRQ" RIGHT="2" SIGNAME="mb_plb_Sl_MIRQ" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
<PORT DIR="O" MPD_INDEX="42" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
<PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SPI_CLK" SIGNAME="spiifc_0_SPI_CLK"/>
<PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="SPI_MOSI" SIGNAME="spiifc_0_SPI_MOSI"/>
<PORT DIR="O" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="2" NAME="SPI_MISO" SIGNAME="spiifc_0_SPI_MISO"/>
<PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="3" NAME="SPI_SS" SIGNAME="spiifc_0_SPI_SS"/>
<PORT BUS="SPLB" CLKFREQUENCY="66666666" DEF_SIGNAME="clk_66_6667MHz" DIR="I" MPD_INDEX="4" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="clk_66_6667MHz"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_SPLB_Rst" DIR="I" MPD_INDEX="5" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="mb_plb_SPLB_Rst"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="6" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="mb_plb_PLB_ABus" VECFORMULA="[0:31]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_UABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="7" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="mb_plb_PLB_UABus" VECFORMULA="[0:31]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_PAValid" DIR="I" MPD_INDEX="8" NAME="PLB_PAValid" SIGNAME="mb_plb_PLB_PAValid"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_SAValid" DIR="I" MPD_INDEX="9" NAME="PLB_SAValid" SIGNAME="mb_plb_PLB_SAValid"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPrim" DIR="I" MPD_INDEX="10" NAME="PLB_rdPrim" SIGNAME="mb_plb_PLB_rdPrim"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPrim" DIR="I" MPD_INDEX="11" NAME="PLB_wrPrim" SIGNAME="mb_plb_PLB_wrPrim"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_masterID" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="12" MSB="0" NAME="PLB_masterID" RIGHT="1" SIGNAME="mb_plb_PLB_masterID" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_abort" DIR="I" MPD_INDEX="13" NAME="PLB_abort" SIGNAME="mb_plb_PLB_abort"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_busLock" DIR="I" MPD_INDEX="14" NAME="PLB_busLock" SIGNAME="mb_plb_PLB_busLock"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_RNW" DIR="I" MPD_INDEX="15" NAME="PLB_RNW" SIGNAME="mb_plb_PLB_RNW"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="16" MSB="0" NAME="PLB_BE" RIGHT="3" SIGNAME="mb_plb_PLB_BE" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_MSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="17" MSB="0" NAME="PLB_MSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSize" VECFORMULA="[0:1]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_size" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="18" MSB="0" NAME="PLB_size" RIGHT="3" SIGNAME="mb_plb_PLB_size" VECFORMULA="[0:3]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_type" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="19" MSB="0" NAME="PLB_type" RIGHT="2" SIGNAME="mb_plb_PLB_type" VECFORMULA="[0:2]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_lockErr" DIR="I" MPD_INDEX="20" NAME="PLB_lockErr" SIGNAME="mb_plb_PLB_lockErr"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="21" MSB="0" NAME="PLB_wrDBus" RIGHT="31" SIGNAME="mb_plb_PLB_wrDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrBurst" DIR="I" MPD_INDEX="22" NAME="PLB_wrBurst" SIGNAME="mb_plb_PLB_wrBurst"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdBurst" DIR="I" MPD_INDEX="23" NAME="PLB_rdBurst" SIGNAME="mb_plb_PLB_rdBurst"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendReq" DIR="I" MPD_INDEX="24" NAME="PLB_wrPendReq" SIGNAME="mb_plb_PLB_wrPendReq"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendReq" DIR="I" MPD_INDEX="25" NAME="PLB_rdPendReq" SIGNAME="mb_plb_PLB_rdPendReq"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="26" MSB="0" NAME="PLB_wrPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_wrPendPri" VECFORMULA="[0:1]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="27" MSB="0" NAME="PLB_rdPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_rdPendPri" VECFORMULA="[0:1]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_reqPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="28" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="mb_plb_PLB_reqPri" VECFORMULA="[0:1]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_TAttribute" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="29" MSB="0" NAME="PLB_TAttribute" RIGHT="15" SIGNAME="mb_plb_PLB_TAttribute" VECFORMULA="[0:15]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_addrAck" DIR="O" MPD_INDEX="30" NAME="Sl_addrAck" SIGNAME="mb_plb_Sl_addrAck"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_SSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="31" MSB="0" NAME="Sl_SSize" RIGHT="1" SIGNAME="mb_plb_Sl_SSize" VECFORMULA="[0:1]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wait" DIR="O" MPD_INDEX="32" NAME="Sl_wait" SIGNAME="mb_plb_Sl_wait"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rearbitrate" DIR="O" MPD_INDEX="33" NAME="Sl_rearbitrate" SIGNAME="mb_plb_Sl_rearbitrate"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrDAck" DIR="O" MPD_INDEX="34" NAME="Sl_wrDAck" SIGNAME="mb_plb_Sl_wrDAck"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrComp" DIR="O" MPD_INDEX="35" NAME="Sl_wrComp" SIGNAME="mb_plb_Sl_wrComp"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrBTerm" DIR="O" MPD_INDEX="36" NAME="Sl_wrBTerm" SIGNAME="mb_plb_Sl_wrBTerm"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="37" MSB="0" NAME="Sl_rdDBus" RIGHT="31" SIGNAME="mb_plb_Sl_rdDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdWdAddr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="38" MSB="0" NAME="Sl_rdWdAddr" RIGHT="3" SIGNAME="mb_plb_Sl_rdWdAddr" VECFORMULA="[0:3]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDAck" DIR="O" MPD_INDEX="39" NAME="Sl_rdDAck" SIGNAME="mb_plb_Sl_rdDAck"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdComp" DIR="O" MPD_INDEX="40" NAME="Sl_rdComp" SIGNAME="mb_plb_Sl_rdComp"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdBTerm" DIR="O" MPD_INDEX="41" NAME="Sl_rdBTerm" SIGNAME="mb_plb_Sl_rdBTerm"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MBusy" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="42" MSB="0" NAME="Sl_MBusy" RIGHT="2" SIGNAME="mb_plb_Sl_MBusy" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MWrErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="43" MSB="0" NAME="Sl_MWrErr" RIGHT="2" SIGNAME="mb_plb_Sl_MWrErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MRdErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="44" MSB="0" NAME="Sl_MRdErr" RIGHT="2" SIGNAME="mb_plb_Sl_MRdErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MIRQ" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="45" MSB="0" NAME="Sl_MIRQ" RIGHT="2" SIGNAME="mb_plb_Sl_MIRQ" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
<PORT DIR="O" MPD_INDEX="46" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="mb_plb" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SPLB" TYPE="SLAVE">
......
projnav/xps/data/system.ucf
View file @ 94c99edd
......@@ -25,3 +25,9 @@ TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100000 kHz;
Net fpga_0_clk_1_sys_clk_pin LOC=L15 | IOSTANDARD=LVCMOS33;
Net fpga_0_rst_1_sys_rst_pin TIG;
Net fpga_0_rst_1_sys_rst_pin LOC=T15 | IOSTANDARD=LVCMOS33;
# SPI
NET "spiifc_0_SPI_CLK_pin" LOC = R10 | IOSTANDARD = LVCMOS33;
NET "spiifc_0_SPI_MISO_pin" LOC = U16 | IOSTANDARD = LVCMOS33;
NET "spiifc_0_SPI_MOSI_pin" LOC = U15 | IOSTANDARD = LVCMOS33;
NET "spiifc_0_SPI_SS_pin" LOC = M11 | IOSTANDARD = LVCMOS33;
projnav/xps/etc/system.gui
View file @ 94c99edd
......@@ -9,7 +9,7 @@
<VARIABLE COL_INDEX="1" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Bus Name" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="2" IS_VISIBLE="FALSE" VIEWDISP="Bus Standard" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="3" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="4" COL_WIDTH="813" IS_VISIBLE="TRUE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="4" COL_WIDTH="726" IS_VISIBLE="TRUE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="5" IS_VISIBLE="FALSE" VIEWDISP="IP Classification" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="6" IS_VISIBLE="FALSE" VIEWDISP="Type" VIEWTYPE="HEADER"/>
</HEADERS>
......@@ -81,26 +81,26 @@
<SET CLASS="PROJECT" DISPLAYMODE="TREE" VIEW_ID="PORT">
<HEADERS HSCROLL="0" VSCROLL="0">
<VARIABLE COL_INDEX="0" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Name" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="1" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Net" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="0" COL_WIDTH="201" IS_VISIBLE="TRUE" VIEWDISP="Name" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="1" COL_WIDTH="180" IS_VISIBLE="TRUE" VIEWDISP="Net" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="2" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Direction" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="3" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Range" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="4" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Class" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="5" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Frequency(Hz)" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="6" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Reset Polarity" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="7" COL_WIDTH="413" IS_VISIBLE="TRUE" VIEWDISP="Sensitivity" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="8" COL_WIDTH="213" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="8" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="9" IS_VISIBLE="FALSE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="10" IS_VISIBLE="TRUE" VIEWDISP="IP Classification" VIEWTYPE="HEADER"/>
</HEADERS>
<SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="0,630,180" VERSION="0"/>
<SET ID="ExternalPorts" IS_EXPANDED="TRUE"/>
<SET ID="spiifc_0" IS_EXPANDED="TRUE"/>
<SET ID="xps_central_dma_0" IS_EXPANDED="TRUE"/>
<STATUS>
<SELECTIONS/>
</STATUS>
<SEQUENCES IS_DEF_SEQUENCES="TRUE">
<VARIABLE ID="ExternalPorts" ROW_INDEX="0"/>
<VARIABLE ID="ExternalPorts" IS_EXPANDED="TRUE" ROW_INDEX="0"/>
<VARIABLE ID="microblaze_0" ROW_INDEX="4"/>
<VARIABLE ID="mb_plb" ROW_INDEX="3"/>
<VARIABLE ID="ilmb" ROW_INDEX="2"/>
......@@ -115,7 +115,7 @@
<VARIABLE ID="mdm_0" ROW_INDEX="9"/>
<VARIABLE ID="proc_sys_reset_0" ROW_INDEX="15"/>
<VARIABLE ID="spiifc_0" IS_EXPANDED="TRUE" ROW_INDEX="8"/>
<VARIABLE ID="xps_central_dma_0" IS_EXPANDED="TRUE" ROW_INDEX="10"/>
<VARIABLE ID="xps_central_dma_0" ROW_INDEX="10"/>
</SEQUENCES>
</SET>
......
projnav/xps/implementation/system_summary.html
View file @ 94c99edd
......@@ -31,7 +31,7 @@
<TR ALIGN=LEFT><TD>Platgen Log File</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Simgen Log File</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>BitInit Log File</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/mjlyons/workspace/vSPI/projnav/xps\system.log'>System Log File</A></TD><TD>Thu Mar 1 09:29:13 2012</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/mjlyons/workspace/vSPI/projnav/xps\system.log'>System Log File</A></TD><TD>Wed Mar 7 09:21:12 2012</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
</TABLE>
......@@ -57,5 +57,5 @@
</TABLE>
<br><center><b>Date Generated:</b> 03/01/2012 - 09:29:13</center>
<br><center><b>Date Generated:</b> 03/07/2012 - 09:21:12</center>
</BODY></HTML>
\ No newline at end of file
projnav/xps/pcores/spiifc.prj
View file @ 94c99edd
......@@ -13,6 +13,7 @@ vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPL
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_slave_burst_v1_01_a\hdl\vhdl\addr_reg_cntr_brst_flex.vhd"
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_slave_burst_v1_01_a\hdl\vhdl\plb_slave_attachment.vhd"
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_slave_burst_v1_01_a\hdl\vhdl\data_mirror_128.vhd"
verilog spiifc_v1_00_a "C:\Users\mjlyons\workspace\vSPI\src\spi_base\spiifc.v"
verilog spiifc_v1_00_a "C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav\ipcore_dir\buffermem.v"
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_slave_burst_v1_01_a\hdl\vhdl\plbv46_slave_burst.vhd"
vhdl interrupt_control_v2_01_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\interrupt_control_v2_01_a\hdl\vhdl\interrupt_control.vhd"
......
projnav/xps/pcores/spiifc_v1_00_a/data/spiifc_v2_1_0.bbd
View file @ 94c99edd
##############################################################################
## Filename: C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores/spiifc_v1_00_a/data/spiifc_v2_1_0.bbd
## Description: Black Box Definition
## Date: Tue Feb 28 16:31:09 2012 (by Create and Import Peripheral Wizard)
## Date: Tue Mar 06 14:12:58 2012 (by Create and Import Peripheral Wizard)
##############################################################################
Files
......
projnav/xps/pcores/spiifc_v1_00_a/data/spiifc_v2_1_0.mpd
View file @ 94c99edd
......@@ -40,6 +40,10 @@ PARAMETER C_MEM1_BASEADDR = 0xffffffff, DT = std_logic_vector, PAIR = C_MEM1_HIG
PARAMETER C_MEM1_HIGHADDR = 0x00000000, DT = std_logic_vector, PAIR = C_MEM1_BASEADDR, ADDRESS = HIGH, BUS = SPLB, ADDR_TYPE = MEMORY
## Ports
PORT SPI_CLK = "", DIR = I
PORT SPI_MOSI = "", DIR = I
PORT SPI_MISO = "", DIR = O
PORT SPI_SS = "", DIR = I
PORT SPLB_Clk = "", DIR = I, SIGIS = CLK, BUS = SPLB
PORT SPLB_Rst = SPLB_Rst, DIR = I, SIGIS = RST, BUS = SPLB
PORT PLB_ABus = PLB_ABus, DIR = I, VEC = [0:31], BUS = SPLB
......
projnav/xps/pcores/spiifc_v1_00_a/data/spiifc_v2_1_0.pao
View file @ 94c99edd
##############################################################################
## Filename: C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores/spiifc_v1_00_a/data/spiifc_v2_1_0.pao
## Description: Peripheral Analysis Order
## Date: Tue Feb 28 16:31:09 2012 (by Create and Import Peripheral Wizard)
## Date: Tue Mar 06 14:12:58 2012 (by Create and Import Peripheral Wizard)
##############################################################################
lib proc_common_v3_00_a proc_common_pkg vhdl
......@@ -19,6 +19,7 @@ lib plbv46_slave_burst_v1_01_a be_reset_gen vhdl
lib plbv46_slave_burst_v1_01_a addr_reg_cntr_brst_flex vhdl
lib plbv46_slave_burst_v1_01_a plb_slave_attachment vhdl
lib plbv46_slave_burst_v1_01_a data_mirror_128 vhdl
lib spiifc_v1_00_a spiifc verilog
lib spiifc_v1_00_a buffermem verilog
lib plbv46_slave_burst_v1_01_a plbv46_slave_burst vhdl
lib interrupt_control_v2_01_a interrupt_control vhdl
......
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/fuse.xmsgs 0 → 100644
View file @ 94c99edd
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
</messages>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/fuseRelaunch.cmd 0 → 100644
View file @ 94c99edd
-intstyle "ise" -incremental -lib "unisims_ver" -lib "unimacro_ver" -lib "xilinxcorelib_ver" -lib "secureip" -o "C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc_tb_isim_beh.exe" -prj "C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc_tb_beh.prj" "work.spiifc_tb" "work.glbl"
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/impact.xsl 0 → 100644
View file @ 94c99edd
<xsl:stylesheet
xmlns:xsl="http://www.w3.org/1999/XSL/Transform"
version="1.0">
<xsl:output method="html"/>
<xsl:template match="/">
<b>
<xsl:text>Current iMPACT Usage Statistics.</xsl:text>
<br></br>
<xsl:text>Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.</xsl:text>
</b>
<br></br>
<br></br>
<xsl:text>This page displays the current iMPACT device usage statistics that will be sent to Xilinx using WebTalk.</xsl:text>
<table width = "100%" border="1" CELLSPACING="0" cols="50% 50%">
<xsl:for-each select="document/application/section">
<tr>
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projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/impact_impact.xwbt 0 → 100644
View file @ 94c99edd
INTSTYLE=impact
INFILE=C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav\impact.xsl
OUTFILE=C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav\impact.xsl
FAMILY=Single
PART=Single
WORKINGDIR=C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav
LICENSE=iMPACT
USER_INFO=iMPACT
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/iseconfig/spiifc.projectmgr
View file @ 94c99edd
......@@ -11,13 +11,13 @@
<ClosedNode>/spiifc - IMP C:|Users|mjlyons|workspace|vSPI|projnav|xps|pcores|spiifc_v1_00_a|hdl|vhdl|spiifc.vhd/PLBV46_SLAVE_BURST_I - plbv46_slave_burst - implementation/I_SLAVE_ATTACHMENT - plb_slave_attachment - implementation</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem>USER_LOGIC_I - user_logic (C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/hdl/verilog/user_logic.v)</SelectedItem>
<SelectedItem>spiifc_tb2 (C:/Users/mjlyons/workspace/vSPI/test/spi_base/spiifc_tb2.v)</SelectedItem>
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<CurrentItem>USER_LOGIC_I - user_logic (C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/hdl/verilog/user_logic.v)</CurrentItem>
<CurrentItem>spiifc_tb2 (C:/Users/mjlyons/workspace/vSPI/test/spi_base/spiifc_tb2.v)</CurrentItem>
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<ClosedNodes>
......@@ -29,13 +29,13 @@
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......@@ -81,6 +81,11 @@
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......@@ -106,4 +111,62 @@
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<ClosedNode>/spiifc_tb C:|Users|mjlyons|workspace|vSPI|test|spi_base|spiifc_tb.v</ClosedNode>
<ClosedNode>/spiifc_tb2 C:|Users|mjlyons|workspace|vSPI|test|spi_base|spiifc_tb2.v</ClosedNode>
<ClosedNode>/spiwrap C:|Users|mjlyons|workspace|vSPI|src|spi_base|spiwrap.v</ClosedNode>
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<SelectedItem>spiifc_tb (C:/Users/mjlyons/workspace/vSPI/test/spi_base/spiifc_tb.v)</SelectedItem>
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<CurrentItem>spiifc_tb (C:/Users/mjlyons/workspace/vSPI/test/spi_base/spiifc_tb.v)</CurrentItem>
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projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/iseconfig/spiifc.xreport
View file @ 94c99edd
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2012-03-01T09:27:04</DateModified>
<DateModified>2012-03-07T09:22:38</DateModified>
<ModuleName>spiifc</ModuleName>
<SummaryTimeStamp>2012-02-29T17:29:17</SummaryTimeStamp>
<SummaryTimeStamp>2012-03-06T18:02:57</SummaryTimeStamp>
<SavedFilePath>C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/iseconfig/spiifc.xreport</SavedFilePath>
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<DateInitialized>2012-02-29T17:30:10</DateInitialized>
<DateInitialized>2012-03-06T14:46:14</DateInitialized>
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<view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="spiifc.twx" label="Static Timing" />
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="spiifc_html/fit/report.htm" label="CPLD Fitter Report" />
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="spiifc_html/tim/report.htm" label="CPLD Timing Report" />
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<viewgroup label="XPS Errors and Warnings" >
<view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" />
......@@ -38,7 +38,7 @@
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<view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
......@@ -54,7 +54,7 @@
<view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" />
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<view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="spiifc.syr" label="Synthesis Report" >
<view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="spiwrap.syr" label="Synthesis Report" >
<toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
<toc-item title="Synthesis Options Summary" target=" Synthesis Options Summary " />
<toc-item title="HDL Compilation" target=" HDL Compilation " />
......@@ -80,15 +80,15 @@
<toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
<toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
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<view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="spiifc.srr" label="Synplify Report" />
<view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="spiifc.prec_log" label="Precision Report" />
<view inputState="Synthesized" program="ngdbuild" type="Report" file="spiifc.bld" label="Translation Report" >
<view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="spiwrap.srr" label="Synplify Report" />
<view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="spiwrap.prec_log" label="Precision Report" />
<view inputState="Synthesized" program="ngdbuild" type="Report" file="spiwrap.bld" label="Translation Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Command Line" target="Command Line:" />
<toc-item title="Partition Status" target="Partition Implementation Status" />
<toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
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<view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="spiifc_map.mrp" label="Map Report" >
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="spiwrap_map.mrp" label="Map Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
<toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
<toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
......@@ -104,7 +104,7 @@
<toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
<toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
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<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="spiwrap.par" label="Place and Route Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Device Utilization" target="Device Utilization Summary:" />
<toc-item title="Router Information" target="Starting Router" />
......@@ -113,7 +113,7 @@
<toc-item title="Timing Results" target="Timing Score:" />
<toc-item title="Final Summary" target="Peak Memory Usage:" />
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<view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="spiifc.twr" label="Post-PAR Static Timing Report" >
<view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="spiwrap.twr" label="Post-PAR Static Timing Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Timing Report Description" target="Device,package,speed:" />
<toc-item title="Informational Messages" target="INFO:" />
......@@ -124,22 +124,22 @@
<toc-item title="Timing Summary" target="Timing summary:" />
<toc-item title="Trace Settings" target="Trace Settings:" />
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<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="spiifc.rpt" label="CPLD Fitter Report (Text)" >
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="spiwrap.rpt" label="CPLD Fitter Report (Text)" >
<toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
<toc-item title="Resources Summary" target="** Mapped Resource Summary **" />
<toc-item title="Pin Resources" target="** Pin Resources **" />
<toc-item title="Global Resources" target="** Global Control Resources **" />
</view>
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="spiifc.tim" label="CPLD Timing Report (Text)" >
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="spiwrap.tim" label="CPLD Timing Report (Text)" >
<toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
<toc-item title="Performance Summary" target="Performance Summary:" />
</view>
<view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="spiifc.pwr" label="Power Report" >
<view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="spiwrap.pwr" label="Power Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Power summary" target="Power summary" />
<toc-item title="Thermal summary" target="Thermal summary" />
</view>
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="spiifc.bgn" label="Bitgen Report" >
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="spiwrap.bgn" label="Bitgen Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
<toc-item title="Final Summary" target="DRC detected" />
......@@ -147,20 +147,20 @@
</viewgroup>
<viewgroup label="Secondary Reports" >
<view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
<view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/spiifc_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
<view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/spiwrap_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/spiifc_translate.nlf" label="Post-Translate Simulation Model Report" >
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/spiwrap_translate.nlf" label="Post-Translate Simulation Model Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="spiifc_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="spiifc_map.map" label="Map Log File" >
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="spiwrap_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="spiwrap_map.map" label="Map Log File" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
<toc-item title="Design Information" target="Design Information" />
<toc-item title="Design Summary" target="Design Summary" />
</view>
<view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
<view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spiifc_preroute.twr" label="Post-Map Static Timing Report" >
<view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spiwrap_preroute.twr" label="Post-Map Static Timing Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Timing Report Description" target="Device,package,speed:" />
<toc-item title="Informational Messages" target="INFO:" />
......@@ -171,43 +171,43 @@
<toc-item title="Timing Summary" target="Timing summary:" />
<toc-item title="Trace Settings" target="Trace Settings:" />
</view>
<view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/spiifc_map.nlf" label="Post-Map Simulation Model Report" />
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spiifc_map.psr" label="Physical Synthesis Report" >
<view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/spiwrap_map.nlf" label="Post-Map Simulation Model Report" />
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spiwrap_map.psr" label="Physical Synthesis Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="spiifc_pad.txt" label="Pad Report" >
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="spiwrap_pad.txt" label="Pad Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="spiifc.unroutes" label="Unroutes Report" >
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="spiwrap.unroutes" label="Unroutes Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
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......
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/iseconfig/spiwrap.xreport 0 → 100644
View file @ 94c99edd
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<header>
<DateModified>2012-03-06T15:48:54</DateModified>
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<toc-item title="Synthesis Options Summary" target=" Synthesis Options Summary " />
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<toc-item title="Final Report" target=" Final Report " />
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<toc-item title="Command Line" target="Command Line:" />
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<toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
<toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
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<toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" />
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<toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" />
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<toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
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<toc-item title="Device Utilization" target="Device Utilization Summary:" />
<toc-item title="Router Information" target="Starting Router" />
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<toc-item title="Timing Report Description" target="Device,package,speed:" />
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<toc-item title="Resources Summary" target="** Mapped Resource Summary **" />
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</report-views>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/par_usage_statistics.html 0 → 100644
View file @ 94c99edd
<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<xtag-section name="ParStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>Par Statistics</B></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>152</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>555</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>555</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>412</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>5.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>6.1 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>7.0 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>8.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>9.0 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>9.0 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>9.0 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>9.0 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>9.0 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>9.0 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>4.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>9.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>3.7</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>1.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>3.2</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>3.9</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0147</xtag-par-property-value></TD></TR>
</xtag-section>
</TABLE>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/rc-bytes-tx-test.txt 0 → 100644
View file @ 94c99edd
03
00
00
00
00
00
00
00
00
\ No newline at end of file
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/rc-bytes.txt 0 → 100644
View file @ 94c99edd
01
FF
F0
33
55
12
34
56
78
9A
\ No newline at end of file
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc.gise
View file @ 94c99edd
......@@ -21,10 +21,13 @@
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="spiifc.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_NCD" xil_pn:name="spiifc_guide.ncd" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_NCD" xil_pn:name="spiwrap_guide.ncd" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:name="TRAN_SubProjectAbstractToPreProxy">
<transform xil_pn:end_ts="1331066936" xil_pn:in_ck="-8467753332869629521" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1331066936">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
......
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc.xise
View file @ 94c99edd
......@@ -16,101 +16,122 @@
<files>
<file xil_pn:name="../../hdl/vhdl/spiifc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="../../hdl/verilog/user_logic.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/proc_common_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
<library xil_pn:name="proc_common_v3_00_a"/>
</file>
<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ipif_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
<library xil_pn:name="proc_common_v3_00_a"/>
</file>
<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_muxcy.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
<library xil_pn:name="proc_common_v3_00_a"/>
</file>
<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_gate128.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
<library xil_pn:name="proc_common_v3_00_a"/>
</file>
<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/family_support.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
<library xil_pn:name="proc_common_v3_00_a"/>
</file>
<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
<library xil_pn:name="proc_common_v3_00_a"/>
</file>
<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter_f.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
<library xil_pn:name="proc_common_v3_00_a"/>
</file>
<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/flex_addr_cntr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
<library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
</file>
<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/addr_reg_cntr_brst_flex.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
<library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
</file>
<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plb_address_decoder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
<library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
</file>
<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/burst_support.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
<library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
</file>
<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/wr_buffer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
<library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
</file>
<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/be_reset_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
<library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
</file>
<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plb_slave_attachment.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
<library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
</file>
<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/data_mirror_128.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
<library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
</file>
<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plbv46_slave_burst.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
<library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
</file>
<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v2_01_a/hdl/vhdl/interrupt_control.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
<library xil_pn:name="interrupt_control_v2_01_a"/>
</file>
<file xil_pn:name="ipcore_dir/buffermem.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="../../../../../../src/spi_base/spiifc.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="../../../../../../src/spi_base/spiwrap.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../../../test/spi_base/spiifc_tb.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="92"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="92"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="92"/>
</file>
<file xil_pn:name="../../../../../../test/spi_base/spiifc_tb2.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../../ucf/atlys/spiwrap.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="ipcore_dir/buffermem.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -174,6 +195,7 @@
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -298,6 +320,7 @@
<property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="non-default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -313,6 +336,7 @@
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
......@@ -349,7 +373,8 @@
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/spiifc_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.spiifc_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
......@@ -360,14 +385,14 @@
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1s" xil_pn:valueState="non-default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.spiifc_tb" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
......@@ -418,7 +443,7 @@
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|spiifc_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="spiifc" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
......@@ -434,7 +459,9 @@
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<bindings>
<binding xil_pn:location="/spiwrap" xil_pn:name="../../../../../ucf/atlys/spiwrap.ucf"/>
</bindings>
<libraries>
<library xil_pn:name="interrupt_control_v2_01_a"/>
......
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc_bitgen.xwbt 0 → 100644
View file @ 94c99edd
INTSTYLE=ise
INFILE=C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav\spiifc.ncd
OUTFILE=C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav\spiifc.bit
FAMILY=Spartan6
PART=xc6slx45-2csg324
WORKINGDIR=C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav
LICENSE=ISE
USER_INFO=179841373_174164856_206270303_042
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc_guide.ncd 0 → 100644
View file @ 94c99edd
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6
###5028:XlxV32DM 3ff1 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\ No newline at end of file
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiwrap_bitgen.xwbt 0 → 100644
View file @ 94c99edd
INTSTYLE=ise
INFILE=C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav\spiwrap.ncd
OUTFILE=C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav\spiwrap.bit
FAMILY=Spartan6
PART=xc6slx45-2csg324
WORKINGDIR=C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav
LICENSE=ISE
USER_INFO=179841373_174164856_206270303_042
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiwrap_guide.ncd 0 → 100644
View file @ 94c99edd
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6
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ECHsJBhM9kTg4LQom3t+9QZc7wHVMxD9/lagjASq1HqILM/Bo/Pcn4vHZ+LpmXgfUXoevvn3gP+KGf+/Y+bMe8rHZ91T+LxbkpwHp+fB/fPg7Dx4cB48PA8eIeqdBYey7UHR/n9bbQMe###3160:XlxV32DM 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\ No newline at end of file
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc_summary.html → projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiwrap_summary.html
View file @ 94c99edd
......@@ -74,5 +74,5 @@
</TABLE>
<br><center><b>Date Generated:</b> 03/01/2012 - 09:27:04</center>
<br><center><b>Date Generated:</b> 03/07/2012 - 09:22:39</center>
</BODY></HTML>
\ No newline at end of file
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/tb1.wcfg 0 → 100644
View file @ 94c99edd
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc_tb_isim_beh1.wdb" id="1" type="auto">
<top_modules>
<top_module name="glbl" />
<top_module name="spiifc_tb" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="19" />
<wvobject fp_name="/spiifc_tb/SPI_MISO" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SPI_MISO</obj_property>
<obj_property name="ObjectShortName">SPI_MISO</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/txMemAddr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">txMemAddr[11:0]</obj_property>
<obj_property name="ObjectShortName">txMemAddr[11:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/txMemData" type="array" db_ref_id="1">
<obj_property name="ElementShortName">txMemData[7:0]</obj_property>
<obj_property name="ObjectShortName">txMemData[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/rcMemAddr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">rcMemAddr[11:0]</obj_property>
<obj_property name="ObjectShortName">rcMemAddr[11:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/rcMemData" type="array" db_ref_id="1">
<obj_property name="ElementShortName">rcMemData[7:0]</obj_property>
<obj_property name="ObjectShortName">rcMemData[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/rcMemWE" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rcMemWE</obj_property>
<obj_property name="ObjectShortName">rcMemWE</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/debug_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">debug_out[7:0]</obj_property>
<obj_property name="ObjectShortName">debug_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/Reset" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">Reset</obj_property>
<obj_property name="ObjectShortName">Reset</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/SysClk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SysClk</obj_property>
<obj_property name="ObjectShortName">SysClk</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/SPI_CLK" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SPI_CLK</obj_property>
<obj_property name="ObjectShortName">SPI_CLK</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/SPI_MOSI" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SPI_MOSI</obj_property>
<obj_property name="ObjectShortName">SPI_MOSI</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/SPI_SS" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SPI_SS</obj_property>
<obj_property name="ObjectShortName">SPI_SS</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/SPI_CLK_en" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SPI_CLK_en</obj_property>
<obj_property name="ObjectShortName">SPI_CLK_en</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/fdRcBytes" type="array" db_ref_id="1">
<obj_property name="ElementShortName">fdRcBytes[31:0]</obj_property>
<obj_property name="ObjectShortName">fdRcBytes[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/fdTxBytes" type="array" db_ref_id="1">
<obj_property name="ElementShortName">fdTxBytes[31:0]</obj_property>
<obj_property name="ObjectShortName">fdTxBytes[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/dummy" type="array" db_ref_id="1">
<obj_property name="ElementShortName">dummy[31:0]</obj_property>
<obj_property name="ObjectShortName">dummy[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/currRcByte" type="array" db_ref_id="1">
<obj_property name="ElementShortName">currRcByte[31:0]</obj_property>
<obj_property name="ObjectShortName">currRcByte[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/rcBytesNotEmpty" type="array" db_ref_id="1">
<obj_property name="ElementShortName">rcBytesNotEmpty[31:0]</obj_property>
<obj_property name="ObjectShortName">rcBytesNotEmpty[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/rcBytesStr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">rcBytesStr[80:1]</obj_property>
<obj_property name="ObjectShortName">rcBytesStr[80:1]</obj_property>
</wvobject>
</wave_config>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/tb2.wcfg 0 → 100644
View file @ 94c99edd
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc_tb2_isim_beh1.wdb" id="1" type="auto">
<top_modules>
<top_module name="glbl" />
<top_module name="spiifc_tb2" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="19" />
<wvobject fp_name="/spiifc_tb2/SPI_MISO" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SPI_MISO</obj_property>
<obj_property name="ObjectShortName">SPI_MISO</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/txMemAddr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">txMemAddr[11:0]</obj_property>
<obj_property name="ObjectShortName">txMemAddr[11:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/txMemData" type="array" db_ref_id="1">
<obj_property name="ElementShortName">txMemData[7:0]</obj_property>
<obj_property name="ObjectShortName">txMemData[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/rcMemAddr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">rcMemAddr[11:0]</obj_property>
<obj_property name="ObjectShortName">rcMemAddr[11:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/rcMemData" type="array" db_ref_id="1">
<obj_property name="ElementShortName">rcMemData[7:0]</obj_property>
<obj_property name="ObjectShortName">rcMemData[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/rcMemWE" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rcMemWE</obj_property>
<obj_property name="ObjectShortName">rcMemWE</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/debug_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">debug_out[7:0]</obj_property>
<obj_property name="ObjectShortName">debug_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/Reset" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">Reset</obj_property>
<obj_property name="ObjectShortName">Reset</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/SysClk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SysClk</obj_property>
<obj_property name="ObjectShortName">SysClk</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/SPI_CLK" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SPI_CLK</obj_property>
<obj_property name="ObjectShortName">SPI_CLK</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/SPI_MOSI" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SPI_MOSI</obj_property>
<obj_property name="ObjectShortName">SPI_MOSI</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/SPI_SS" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SPI_SS</obj_property>
<obj_property name="ObjectShortName">SPI_SS</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/SPI_CLK_en" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SPI_CLK_en</obj_property>
<obj_property name="ObjectShortName">SPI_CLK_en</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/fdRcBytes" type="array" db_ref_id="1">
<obj_property name="ElementShortName">fdRcBytes[31:0]</obj_property>
<obj_property name="ObjectShortName">fdRcBytes[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/fdTxBytes" type="array" db_ref_id="1">
<obj_property name="ElementShortName">fdTxBytes[31:0]</obj_property>
<obj_property name="ObjectShortName">fdTxBytes[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/dummy" type="array" db_ref_id="1">
<obj_property name="ElementShortName">dummy[31:0]</obj_property>
<obj_property name="ObjectShortName">dummy[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/currRcByte" type="array" db_ref_id="1">
<obj_property name="ElementShortName">currRcByte[31:0]</obj_property>
<obj_property name="ObjectShortName">currRcByte[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/rcBytesNotEmpty" type="array" db_ref_id="1">
<obj_property name="ElementShortName">rcBytesNotEmpty[31:0]</obj_property>
<obj_property name="ObjectShortName">rcBytesNotEmpty[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/rcBytesStr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">rcBytesStr[80:1]</obj_property>
<obj_property name="ObjectShortName">rcBytesStr[80:1]</obj_property>
</wvobject>
</wave_config>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/user_logic.cmd_log 0 → 100644
View file @ 94c99edd
xst -intstyle ise -ifn "C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/user_logic.xst" -ofn "C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/user_logic.syr"
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/user_logic.ngc 0 → 100644
View file @ 94c99edd
This source diff could not be displayed because it is too large. You can view the blob instead.
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/user_logic.prj 0 → 100644
View file @ 94c99edd
verilog work "../../../../../../src/spi_base/spiifc.v"
verilog work "ipcore_dir/buffermem.v"
verilog work "../../hdl/verilog/user_logic.v"
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/user_logic.syr 0 → 100644
View file @ 94c99edd
Release 13.2 - xst O.61xd (nt64)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.27 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.28 secs
--> Reading design: user_logic.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Parsing
3) HDL Elaboration
4) HDL Synthesis
4.1) HDL Synthesis Report
5) Advanced HDL Synthesis
5.1) Advanced HDL Synthesis Report
6) Low Level Synthesis
7) Partition Report
8) Design Summary
8.1) Primitive and Black Box Usage
8.2) Device utilization summary
8.3) Partition Resource Summary
8.4) Timing Report
8.4.1) Clock Information
8.4.2) Asynchronous Control Signals Information
8.4.3) Timing Summary
8.4.4) Timing Details
8.4.5) Cross Clock Domains Report
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "user_logic.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "user_logic"
Output Format : NGC
Target Device : xc6slx45-2-csg324
---- Source Options
Top Module Name : user_logic
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : LUT
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Shift Register Extraction : YES
ROM Style : Auto
Resource Sharing : YES
Asynchronous To Synchronous : NO
Shift Register Minimum Size : 2
Use DSP Block : Auto
Automatic Register Balancing : No
---- Target Options
LUT Combining : Auto
Reduce Control Sets : Auto
Add IO Buffers : YES
Global Maximum Fanout : 100000
Add Generic Clock Buffer(BUFG) : 16
Register Duplication : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Auto
Use Synchronous Set : Auto
Use Synchronous Reset : Auto
Pack IO Registers into IOBs : Auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Power Reduction : NO
Keep Hierarchy : No
Netlist Hierarchy : As_Optimized
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : Maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
DSP48 Utilization Ratio : 100
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
---- Other Options
Cores Search Directories : {"ipcore_dir" }
=========================================================================
=========================================================================
* HDL Parsing *
=========================================================================
Analyzing Verilog file \"C:\Users\mjlyons\workspace\vSPI\src\spi_base\spiifc.v\" into library work
Parsing module <spiifc>.
Analyzing Verilog file \"C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav\ipcore_dir\buffermem.v\" into library work
Parsing module <buffermem>.
Analyzing Verilog file \"C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\hdl\verilog\user_logic.v\" into library work
Parsing module <user_logic>.
=========================================================================
* HDL Elaboration *
=========================================================================
WARNING:HDLCompiler:1016 - "C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\hdl\verilog\user_logic.v" Line 196: Port douta is not connected to this instance
WARNING:HDLCompiler:1016 - "C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\hdl\verilog\user_logic.v" Line 212: Port dina is not connected to this instance
WARNING:HDLCompiler:1016 - "C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\hdl\verilog\user_logic.v" Line 228: Port debug_out is not connected to this instance
Elaborating module <user_logic>.
Elaborating module <buffermem>.
WARNING:HDLCompiler:1499 - "C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav\ipcore_dir\buffermem.v" Line 39: Empty module <buffermem> remains a black box.
Elaborating module <spiifc>.
WARNING:HDLCompiler:413 - "C:\Users\mjlyons\workspace\vSPI\src\spi_base\spiifc.v" Line 123: Result of 32-bit expression is truncated to fit in 1-bit target.
WARNING:HDLCompiler:413 - "C:\Users\mjlyons\workspace\vSPI\src\spi_base\spiifc.v" Line 124: Result of 32-bit expression is truncated to fit in 12-bit target.
WARNING:HDLCompiler:1127 - "C:\Users\mjlyons\workspace\vSPI\src\spi_base\spiifc.v" Line 145: Assignment to ssTurnOnReg ignored, since the identifier is never used
WARNING:HDLCompiler:413 - "C:\Users\mjlyons\workspace\vSPI\src\spi_base\spiifc.v" Line 190: Result of 13-bit expression is truncated to fit in 12-bit target.
WARNING:HDLCompiler:413 - "C:\Users\mjlyons\workspace\vSPI\src\spi_base\spiifc.v" Line 192: Result of 32-bit expression is truncated to fit in 3-bit target.
WARNING:HDLCompiler:413 - "C:\Users\mjlyons\workspace\vSPI\src\spi_base\spiifc.v" Line 218: Result of 13-bit expression is truncated to fit in 12-bit target.
WARNING:HDLCompiler:1127 - "C:\Users\mjlyons\workspace\vSPI\src\spi_base\spiifc.v" Line 164: Assignment to cmd ignored, since the identifier is never used
WARNING:HDLCompiler:552 - "C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\hdl\verilog\user_logic.v" Line 212: Input port dina[7] is not connected on this instance
=========================================================================
* HDL Synthesis *
=========================================================================
Synthesizing Unit <user_logic>.
Related source file is "c:/users/mjlyons/workspace/vspi/projnav/xps/pcores/spiifc_v1_00_a/hdl/verilog/user_logic.v".
C_SLV_AWIDTH = 32
C_SLV_DWIDTH = 32
C_NUM_REG = 16
C_NUM_MEM = 2
C_NUM_INTR = 1
WARNING:Xst:647 - Input <Bus2IP_Addr<0:19>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Bus2IP_Addr<30:31>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Bus2IP_BurstLength<0:8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Bus2IP_Burst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "c:/users/mjlyons/workspace/vspi/projnav/xps/pcores/spiifc_v1_00_a/hdl/verilog/user_logic.v" line 196: Output port <douta> of the instance <mosiMem> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/users/mjlyons/workspace/vspi/projnav/xps/pcores/spiifc_v1_00_a/hdl/verilog/user_logic.v" line 228: Output port <debug_out> of the instance <spi> is unconnected or connected to loadless signal.
Found 1-bit register for signal <slv_reg0<0>>.
Found 1-bit register for signal <slv_reg0<1>>.
Found 1-bit register for signal <slv_reg0<2>>.
Found 1-bit register for signal <slv_reg0<3>>.
Found 1-bit register for signal <slv_reg0<4>>.
Found 1-bit register for signal <slv_reg0<5>>.
Found 1-bit register for signal <slv_reg0<6>>.
Found 1-bit register for signal <slv_reg0<7>>.
Found 1-bit register for signal <slv_reg0<8>>.
Found 1-bit register for signal <slv_reg0<9>>.
Found 1-bit register for signal <slv_reg0<10>>.
Found 1-bit register for signal <slv_reg0<11>>.
Found 1-bit register for signal <slv_reg0<12>>.
Found 1-bit register for signal <slv_reg0<13>>.
Found 1-bit register for signal <slv_reg0<14>>.
Found 1-bit register for signal <slv_reg0<15>>.
Found 1-bit register for signal <slv_reg0<16>>.
Found 1-bit register for signal <slv_reg0<17>>.
Found 1-bit register for signal <slv_reg0<18>>.
Found 1-bit register for signal <slv_reg0<19>>.
Found 1-bit register for signal <slv_reg0<20>>.
Found 1-bit register for signal <slv_reg0<21>>.
Found 1-bit register for signal <slv_reg0<22>>.
Found 1-bit register for signal <slv_reg0<23>>.
Found 1-bit register for signal <slv_reg0<24>>.
Found 1-bit register for signal <slv_reg0<25>>.
Found 1-bit register for signal <slv_reg0<26>>.
Found 1-bit register for signal <slv_reg0<27>>.
Found 1-bit register for signal <slv_reg0<28>>.
Found 1-bit register for signal <slv_reg0<29>>.
Found 1-bit register for signal <slv_reg0<30>>.
Found 1-bit register for signal <slv_reg0<31>>.
Found 1-bit register for signal <slv_reg1<0>>.
Found 1-bit register for signal <slv_reg1<1>>.
Found 1-bit register for signal <slv_reg1<2>>.
Found 1-bit register for signal <slv_reg1<3>>.
Found 1-bit register for signal <slv_reg1<4>>.
Found 1-bit register for signal <slv_reg1<5>>.
Found 1-bit register for signal <slv_reg1<6>>.
Found 1-bit register for signal <slv_reg1<7>>.
Found 1-bit register for signal <slv_reg1<8>>.
Found 1-bit register for signal <slv_reg1<9>>.
Found 1-bit register for signal <slv_reg1<10>>.
Found 1-bit register for signal <slv_reg1<11>>.
Found 1-bit register for signal <slv_reg1<12>>.
Found 1-bit register for signal <slv_reg1<13>>.
Found 1-bit register for signal <slv_reg1<14>>.
Found 1-bit register for signal <slv_reg1<15>>.
Found 1-bit register for signal <slv_reg1<16>>.
Found 1-bit register for signal <slv_reg1<17>>.
Found 1-bit register for signal <slv_reg1<18>>.
Found 1-bit register for signal <slv_reg1<19>>.
Found 1-bit register for signal <slv_reg1<20>>.
Found 1-bit register for signal <slv_reg1<21>>.
Found 1-bit register for signal <slv_reg1<22>>.
Found 1-bit register for signal <slv_reg1<23>>.
Found 1-bit register for signal <slv_reg1<24>>.
Found 1-bit register for signal <slv_reg1<25>>.
Found 1-bit register for signal <slv_reg1<26>>.
Found 1-bit register for signal <slv_reg1<27>>.
Found 1-bit register for signal <slv_reg1<28>>.
Found 1-bit register for signal <slv_reg1<29>>.
Found 1-bit register for signal <slv_reg1<30>>.
Found 1-bit register for signal <slv_reg1<31>>.
Found 1-bit register for signal <slv_reg2<0>>.
Found 1-bit register for signal <slv_reg2<1>>.
Found 1-bit register for signal <slv_reg2<2>>.
Found 1-bit register for signal <slv_reg2<3>>.
Found 1-bit register for signal <slv_reg2<4>>.
Found 1-bit register for signal <slv_reg2<5>>.
Found 1-bit register for signal <slv_reg2<6>>.
Found 1-bit register for signal <slv_reg2<7>>.
Found 1-bit register for signal <slv_reg2<8>>.
Found 1-bit register for signal <slv_reg2<9>>.
Found 1-bit register for signal <slv_reg2<10>>.
Found 1-bit register for signal <slv_reg2<11>>.
Found 1-bit register for signal <slv_reg2<12>>.
Found 1-bit register for signal <slv_reg2<13>>.
Found 1-bit register for signal <slv_reg2<14>>.
Found 1-bit register for signal <slv_reg2<15>>.
Found 1-bit register for signal <slv_reg2<16>>.
Found 1-bit register for signal <slv_reg2<17>>.
Found 1-bit register for signal <slv_reg2<18>>.
Found 1-bit register for signal <slv_reg2<19>>.
Found 1-bit register for signal <slv_reg2<20>>.
Found 1-bit register for signal <slv_reg2<21>>.
Found 1-bit register for signal <slv_reg2<22>>.
Found 1-bit register for signal <slv_reg2<23>>.
Found 1-bit register for signal <slv_reg2<24>>.
Found 1-bit register for signal <slv_reg2<25>>.
Found 1-bit register for signal <slv_reg2<26>>.
Found 1-bit register for signal <slv_reg2<27>>.
Found 1-bit register for signal <slv_reg2<28>>.
Found 1-bit register for signal <slv_reg2<29>>.
Found 1-bit register for signal <slv_reg2<30>>.
Found 1-bit register for signal <slv_reg2<31>>.
Found 1-bit register for signal <slv_reg3<0>>.
Found 1-bit register for signal <slv_reg3<1>>.
Found 1-bit register for signal <slv_reg3<2>>.
Found 1-bit register for signal <slv_reg3<3>>.
Found 1-bit register for signal <slv_reg3<4>>.
Found 1-bit register for signal <slv_reg3<5>>.
Found 1-bit register for signal <slv_reg3<6>>.
Found 1-bit register for signal <slv_reg3<7>>.
Found 1-bit register for signal <slv_reg3<8>>.
Found 1-bit register for signal <slv_reg3<9>>.
Found 1-bit register for signal <slv_reg3<10>>.
Found 1-bit register for signal <slv_reg3<11>>.
Found 1-bit register for signal <slv_reg3<12>>.
Found 1-bit register for signal <slv_reg3<13>>.
Found 1-bit register for signal <slv_reg3<14>>.
Found 1-bit register for signal <slv_reg3<15>>.
Found 1-bit register for signal <slv_reg3<16>>.
Found 1-bit register for signal <slv_reg3<17>>.
Found 1-bit register for signal <slv_reg3<18>>.
Found 1-bit register for signal <slv_reg3<19>>.
Found 1-bit register for signal <slv_reg3<20>>.
Found 1-bit register for signal <slv_reg3<21>>.
Found 1-bit register for signal <slv_reg3<22>>.
Found 1-bit register for signal <slv_reg3<23>>.
Found 1-bit register for signal <slv_reg3<24>>.
Found 1-bit register for signal <slv_reg3<25>>.
Found 1-bit register for signal <slv_reg3<26>>.
Found 1-bit register for signal <slv_reg3<27>>.
Found 1-bit register for signal <slv_reg3<28>>.
Found 1-bit register for signal <slv_reg3<29>>.
Found 1-bit register for signal <slv_reg3<30>>.
Found 1-bit register for signal <slv_reg3<31>>.
Found 1-bit register for signal <slv_reg4<0>>.
Found 1-bit register for signal <slv_reg4<1>>.
Found 1-bit register for signal <slv_reg4<2>>.
Found 1-bit register for signal <slv_reg4<3>>.
Found 1-bit register for signal <slv_reg4<4>>.
Found 1-bit register for signal <slv_reg4<5>>.
Found 1-bit register for signal <slv_reg4<6>>.
Found 1-bit register for signal <slv_reg4<7>>.
Found 1-bit register for signal <slv_reg4<8>>.
Found 1-bit register for signal <slv_reg4<9>>.
Found 1-bit register for signal <slv_reg4<10>>.
Found 1-bit register for signal <slv_reg4<11>>.
Found 1-bit register for signal <slv_reg4<12>>.
Found 1-bit register for signal <slv_reg4<13>>.
Found 1-bit register for signal <slv_reg4<14>>.
Found 1-bit register for signal <slv_reg4<15>>.
Found 1-bit register for signal <slv_reg4<16>>.
Found 1-bit register for signal <slv_reg4<17>>.
Found 1-bit register for signal <slv_reg4<18>>.
Found 1-bit register for signal <slv_reg4<19>>.
Found 1-bit register for signal <slv_reg4<20>>.
Found 1-bit register for signal <slv_reg4<21>>.
Found 1-bit register for signal <slv_reg4<22>>.
Found 1-bit register for signal <slv_reg4<23>>.
Found 1-bit register for signal <slv_reg4<24>>.
Found 1-bit register for signal <slv_reg4<25>>.
Found 1-bit register for signal <slv_reg4<26>>.
Found 1-bit register for signal <slv_reg4<27>>.
Found 1-bit register for signal <slv_reg4<28>>.
Found 1-bit register for signal <slv_reg4<29>>.
Found 1-bit register for signal <slv_reg4<30>>.
Found 1-bit register for signal <slv_reg4<31>>.
Found 1-bit register for signal <slv_reg5<0>>.
Found 1-bit register for signal <slv_reg5<1>>.
Found 1-bit register for signal <slv_reg5<2>>.
Found 1-bit register for signal <slv_reg5<3>>.
Found 1-bit register for signal <slv_reg5<4>>.
Found 1-bit register for signal <slv_reg5<5>>.
Found 1-bit register for signal <slv_reg5<6>>.
Found 1-bit register for signal <slv_reg5<7>>.
Found 1-bit register for signal <slv_reg5<8>>.
Found 1-bit register for signal <slv_reg5<9>>.
Found 1-bit register for signal <slv_reg5<10>>.
Found 1-bit register for signal <slv_reg5<11>>.
Found 1-bit register for signal <slv_reg5<12>>.
Found 1-bit register for signal <slv_reg5<13>>.
Found 1-bit register for signal <slv_reg5<14>>.
Found 1-bit register for signal <slv_reg5<15>>.
Found 1-bit register for signal <slv_reg5<16>>.
Found 1-bit register for signal <slv_reg5<17>>.
Found 1-bit register for signal <slv_reg5<18>>.
Found 1-bit register for signal <slv_reg5<19>>.
Found 1-bit register for signal <slv_reg5<20>>.
Found 1-bit register for signal <slv_reg5<21>>.
Found 1-bit register for signal <slv_reg5<22>>.
Found 1-bit register for signal <slv_reg5<23>>.
Found 1-bit register for signal <slv_reg5<24>>.
Found 1-bit register for signal <slv_reg5<25>>.
Found 1-bit register for signal <slv_reg5<26>>.
Found 1-bit register for signal <slv_reg5<27>>.
Found 1-bit register for signal <slv_reg5<28>>.
Found 1-bit register for signal <slv_reg5<29>>.
Found 1-bit register for signal <slv_reg5<30>>.
Found 1-bit register for signal <slv_reg5<31>>.
Found 1-bit register for signal <slv_reg6<0>>.
Found 1-bit register for signal <slv_reg6<1>>.
Found 1-bit register for signal <slv_reg6<2>>.
Found 1-bit register for signal <slv_reg6<3>>.
Found 1-bit register for signal <slv_reg6<4>>.
Found 1-bit register for signal <slv_reg6<5>>.
Found 1-bit register for signal <slv_reg6<6>>.
Found 1-bit register for signal <slv_reg6<7>>.
Found 1-bit register for signal <slv_reg6<8>>.
Found 1-bit register for signal <slv_reg6<9>>.
Found 1-bit register for signal <slv_reg6<10>>.
Found 1-bit register for signal <slv_reg6<11>>.
Found 1-bit register for signal <slv_reg6<12>>.
Found 1-bit register for signal <slv_reg6<13>>.
Found 1-bit register for signal <slv_reg6<14>>.
Found 1-bit register for signal <slv_reg6<15>>.
Found 1-bit register for signal <slv_reg6<16>>.
Found 1-bit register for signal <slv_reg6<17>>.
Found 1-bit register for signal <slv_reg6<18>>.
Found 1-bit register for signal <slv_reg6<19>>.
Found 1-bit register for signal <slv_reg6<20>>.
Found 1-bit register for signal <slv_reg6<21>>.
Found 1-bit register for signal <slv_reg6<22>>.
Found 1-bit register for signal <slv_reg6<23>>.
Found 1-bit register for signal <slv_reg6<24>>.
Found 1-bit register for signal <slv_reg6<25>>.
Found 1-bit register for signal <slv_reg6<26>>.
Found 1-bit register for signal <slv_reg6<27>>.
Found 1-bit register for signal <slv_reg6<28>>.
Found 1-bit register for signal <slv_reg6<29>>.
Found 1-bit register for signal <slv_reg6<30>>.
Found 1-bit register for signal <slv_reg6<31>>.
Found 1-bit register for signal <slv_reg7<0>>.
Found 1-bit register for signal <slv_reg7<1>>.
Found 1-bit register for signal <slv_reg7<2>>.
Found 1-bit register for signal <slv_reg7<3>>.
Found 1-bit register for signal <slv_reg7<4>>.
Found 1-bit register for signal <slv_reg7<5>>.
Found 1-bit register for signal <slv_reg7<6>>.
Found 1-bit register for signal <slv_reg7<7>>.
Found 1-bit register for signal <slv_reg7<8>>.
Found 1-bit register for signal <slv_reg7<9>>.
Found 1-bit register for signal <slv_reg7<10>>.
Found 1-bit register for signal <slv_reg7<11>>.
Found 1-bit register for signal <slv_reg7<12>>.
Found 1-bit register for signal <slv_reg7<13>>.
Found 1-bit register for signal <slv_reg7<14>>.
Found 1-bit register for signal <slv_reg7<15>>.
Found 1-bit register for signal <slv_reg7<16>>.
Found 1-bit register for signal <slv_reg7<17>>.
Found 1-bit register for signal <slv_reg7<18>>.
Found 1-bit register for signal <slv_reg7<19>>.
Found 1-bit register for signal <slv_reg7<20>>.
Found 1-bit register for signal <slv_reg7<21>>.
Found 1-bit register for signal <slv_reg7<22>>.
Found 1-bit register for signal <slv_reg7<23>>.
Found 1-bit register for signal <slv_reg7<24>>.
Found 1-bit register for signal <slv_reg7<25>>.
Found 1-bit register for signal <slv_reg7<26>>.
Found 1-bit register for signal <slv_reg7<27>>.
Found 1-bit register for signal <slv_reg7<28>>.
Found 1-bit register for signal <slv_reg7<29>>.
Found 1-bit register for signal <slv_reg7<30>>.
Found 1-bit register for signal <slv_reg7<31>>.
Found 1-bit register for signal <slv_reg8<0>>.
Found 1-bit register for signal <slv_reg8<1>>.
Found 1-bit register for signal <slv_reg8<2>>.
Found 1-bit register for signal <slv_reg8<3>>.
Found 1-bit register for signal <slv_reg8<4>>.
Found 1-bit register for signal <slv_reg8<5>>.
Found 1-bit register for signal <slv_reg8<6>>.
Found 1-bit register for signal <slv_reg8<7>>.
Found 1-bit register for signal <slv_reg8<8>>.
Found 1-bit register for signal <slv_reg8<9>>.
Found 1-bit register for signal <slv_reg8<10>>.
Found 1-bit register for signal <slv_reg8<11>>.
Found 1-bit register for signal <slv_reg8<12>>.
Found 1-bit register for signal <slv_reg8<13>>.
Found 1-bit register for signal <slv_reg8<14>>.
Found 1-bit register for signal <slv_reg8<15>>.
Found 1-bit register for signal <slv_reg8<16>>.
Found 1-bit register for signal <slv_reg8<17>>.
Found 1-bit register for signal <slv_reg8<18>>.
Found 1-bit register for signal <slv_reg8<19>>.
Found 1-bit register for signal <slv_reg8<20>>.
Found 1-bit register for signal <slv_reg8<21>>.
Found 1-bit register for signal <slv_reg8<22>>.
Found 1-bit register for signal <slv_reg8<23>>.
Found 1-bit register for signal <slv_reg8<24>>.
Found 1-bit register for signal <slv_reg8<25>>.
Found 1-bit register for signal <slv_reg8<26>>.
Found 1-bit register for signal <slv_reg8<27>>.
Found 1-bit register for signal <slv_reg8<28>>.
Found 1-bit register for signal <slv_reg8<29>>.
Found 1-bit register for signal <slv_reg8<30>>.
Found 1-bit register for signal <slv_reg8<31>>.
Found 1-bit register for signal <slv_reg9<0>>.
Found 1-bit register for signal <slv_reg9<1>>.
Found 1-bit register for signal <slv_reg9<2>>.
Found 1-bit register for signal <slv_reg9<3>>.
Found 1-bit register for signal <slv_reg9<4>>.
Found 1-bit register for signal <slv_reg9<5>>.
Found 1-bit register for signal <slv_reg9<6>>.
Found 1-bit register for signal <slv_reg9<7>>.
Found 1-bit register for signal <slv_reg9<8>>.
Found 1-bit register for signal <slv_reg9<9>>.
Found 1-bit register for signal <slv_reg9<10>>.
Found 1-bit register for signal <slv_reg9<11>>.
Found 1-bit register for signal <slv_reg9<12>>.
Found 1-bit register for signal <slv_reg9<13>>.
Found 1-bit register for signal <slv_reg9<14>>.
Found 1-bit register for signal <slv_reg9<15>>.
Found 1-bit register for signal <slv_reg9<16>>.
Found 1-bit register for signal <slv_reg9<17>>.
Found 1-bit register for signal <slv_reg9<18>>.
Found 1-bit register for signal <slv_reg9<19>>.
Found 1-bit register for signal <slv_reg9<20>>.
Found 1-bit register for signal <slv_reg9<21>>.
Found 1-bit register for signal <slv_reg9<22>>.
Found 1-bit register for signal <slv_reg9<23>>.
Found 1-bit register for signal <slv_reg9<24>>.
Found 1-bit register for signal <slv_reg9<25>>.
Found 1-bit register for signal <slv_reg9<26>>.
Found 1-bit register for signal <slv_reg9<27>>.
Found 1-bit register for signal <slv_reg9<28>>.
Found 1-bit register for signal <slv_reg9<29>>.
Found 1-bit register for signal <slv_reg9<30>>.
Found 1-bit register for signal <slv_reg9<31>>.
Found 1-bit register for signal <slv_reg10<0>>.
Found 1-bit register for signal <slv_reg10<1>>.
Found 1-bit register for signal <slv_reg10<2>>.
Found 1-bit register for signal <slv_reg10<3>>.
Found 1-bit register for signal <slv_reg10<4>>.
Found 1-bit register for signal <slv_reg10<5>>.
Found 1-bit register for signal <slv_reg10<6>>.
Found 1-bit register for signal <slv_reg10<7>>.
Found 1-bit register for signal <slv_reg10<8>>.
Found 1-bit register for signal <slv_reg10<9>>.
Found 1-bit register for signal <slv_reg10<10>>.
Found 1-bit register for signal <slv_reg10<11>>.
Found 1-bit register for signal <slv_reg10<12>>.
Found 1-bit register for signal <slv_reg10<13>>.
Found 1-bit register for signal <slv_reg10<14>>.
Found 1-bit register for signal <slv_reg10<15>>.
Found 1-bit register for signal <slv_reg10<16>>.
Found 1-bit register for signal <slv_reg10<17>>.
Found 1-bit register for signal <slv_reg10<18>>.
Found 1-bit register for signal <slv_reg10<19>>.
Found 1-bit register for signal <slv_reg10<20>>.
Found 1-bit register for signal <slv_reg10<21>>.
Found 1-bit register for signal <slv_reg10<22>>.
Found 1-bit register for signal <slv_reg10<23>>.
Found 1-bit register for signal <slv_reg10<24>>.
Found 1-bit register for signal <slv_reg10<25>>.
Found 1-bit register for signal <slv_reg10<26>>.
Found 1-bit register for signal <slv_reg10<27>>.
Found 1-bit register for signal <slv_reg10<28>>.
Found 1-bit register for signal <slv_reg10<29>>.
Found 1-bit register for signal <slv_reg10<30>>.
Found 1-bit register for signal <slv_reg10<31>>.
Found 1-bit register for signal <slv_reg11<0>>.
Found 1-bit register for signal <slv_reg11<1>>.
Found 1-bit register for signal <slv_reg11<2>>.
Found 1-bit register for signal <slv_reg11<3>>.
Found 1-bit register for signal <slv_reg11<4>>.
Found 1-bit register for signal <slv_reg11<5>>.
Found 1-bit register for signal <slv_reg11<6>>.
Found 1-bit register for signal <slv_reg11<7>>.
Found 1-bit register for signal <slv_reg11<8>>.
Found 1-bit register for signal <slv_reg11<9>>.
Found 1-bit register for signal <slv_reg11<10>>.
Found 1-bit register for signal <slv_reg11<11>>.
Found 1-bit register for signal <slv_reg11<12>>.
Found 1-bit register for signal <slv_reg11<13>>.
Found 1-bit register for signal <slv_reg11<14>>.
Found 1-bit register for signal <slv_reg11<15>>.
Found 1-bit register for signal <slv_reg11<16>>.
Found 1-bit register for signal <slv_reg11<17>>.
Found 1-bit register for signal <slv_reg11<18>>.
Found 1-bit register for signal <slv_reg11<19>>.
Found 1-bit register for signal <slv_reg11<20>>.
Found 1-bit register for signal <slv_reg11<21>>.
Found 1-bit register for signal <slv_reg11<22>>.
Found 1-bit register for signal <slv_reg11<23>>.
Found 1-bit register for signal <slv_reg11<24>>.
Found 1-bit register for signal <slv_reg11<25>>.
Found 1-bit register for signal <slv_reg11<26>>.
Found 1-bit register for signal <slv_reg11<27>>.
Found 1-bit register for signal <slv_reg11<28>>.
Found 1-bit register for signal <slv_reg11<29>>.
Found 1-bit register for signal <slv_reg11<30>>.
Found 1-bit register for signal <slv_reg11<31>>.
Found 1-bit register for signal <slv_reg12<0>>.
Found 1-bit register for signal <slv_reg12<1>>.
Found 1-bit register for signal <slv_reg12<2>>.
Found 1-bit register for signal <slv_reg12<3>>.
Found 1-bit register for signal <slv_reg12<4>>.
Found 1-bit register for signal <slv_reg12<5>>.
Found 1-bit register for signal <slv_reg12<6>>.
Found 1-bit register for signal <slv_reg12<7>>.
Found 1-bit register for signal <slv_reg12<8>>.
Found 1-bit register for signal <slv_reg12<9>>.
Found 1-bit register for signal <slv_reg12<10>>.
Found 1-bit register for signal <slv_reg12<11>>.
Found 1-bit register for signal <slv_reg12<12>>.
Found 1-bit register for signal <slv_reg12<13>>.
Found 1-bit register for signal <slv_reg12<14>>.
Found 1-bit register for signal <slv_reg12<15>>.
Found 1-bit register for signal <slv_reg12<16>>.
Found 1-bit register for signal <slv_reg12<17>>.
Found 1-bit register for signal <slv_reg12<18>>.
Found 1-bit register for signal <slv_reg12<19>>.
Found 1-bit register for signal <slv_reg12<20>>.
Found 1-bit register for signal <slv_reg12<21>>.
Found 1-bit register for signal <slv_reg12<22>>.
Found 1-bit register for signal <slv_reg12<23>>.
Found 1-bit register for signal <slv_reg12<24>>.
Found 1-bit register for signal <slv_reg12<25>>.
Found 1-bit register for signal <slv_reg12<26>>.
Found 1-bit register for signal <slv_reg12<27>>.
Found 1-bit register for signal <slv_reg12<28>>.
Found 1-bit register for signal <slv_reg12<29>>.
Found 1-bit register for signal <slv_reg12<30>>.
Found 1-bit register for signal <slv_reg12<31>>.
Found 1-bit register for signal <slv_reg13<0>>.
Found 1-bit register for signal <slv_reg13<1>>.
Found 1-bit register for signal <slv_reg13<2>>.
Found 1-bit register for signal <slv_reg13<3>>.
Found 1-bit register for signal <slv_reg13<4>>.
Found 1-bit register for signal <slv_reg13<5>>.
Found 1-bit register for signal <slv_reg13<6>>.
Found 1-bit register for signal <slv_reg13<7>>.
Found 1-bit register for signal <slv_reg13<8>>.
Found 1-bit register for signal <slv_reg13<9>>.
Found 1-bit register for signal <slv_reg13<10>>.
Found 1-bit register for signal <slv_reg13<11>>.
Found 1-bit register for signal <slv_reg13<12>>.
Found 1-bit register for signal <slv_reg13<13>>.
Found 1-bit register for signal <slv_reg13<14>>.
Found 1-bit register for signal <slv_reg13<15>>.
Found 1-bit register for signal <slv_reg13<16>>.
Found 1-bit register for signal <slv_reg13<17>>.
Found 1-bit register for signal <slv_reg13<18>>.
Found 1-bit register for signal <slv_reg13<19>>.
Found 1-bit register for signal <slv_reg13<20>>.
Found 1-bit register for signal <slv_reg13<21>>.
Found 1-bit register for signal <slv_reg13<22>>.
Found 1-bit register for signal <slv_reg13<23>>.
Found 1-bit register for signal <slv_reg13<24>>.
Found 1-bit register for signal <slv_reg13<25>>.
Found 1-bit register for signal <slv_reg13<26>>.
Found 1-bit register for signal <slv_reg13<27>>.
Found 1-bit register for signal <slv_reg13<28>>.
Found 1-bit register for signal <slv_reg13<29>>.
Found 1-bit register for signal <slv_reg13<30>>.
Found 1-bit register for signal <slv_reg13<31>>.
Found 1-bit register for signal <slv_reg14<0>>.
Found 1-bit register for signal <slv_reg14<1>>.
Found 1-bit register for signal <slv_reg14<2>>.
Found 1-bit register for signal <slv_reg14<3>>.
Found 1-bit register for signal <slv_reg14<4>>.
Found 1-bit register for signal <slv_reg14<5>>.
Found 1-bit register for signal <slv_reg14<6>>.
Found 1-bit register for signal <slv_reg14<7>>.
Found 1-bit register for signal <slv_reg14<8>>.
Found 1-bit register for signal <slv_reg14<9>>.
Found 1-bit register for signal <slv_reg14<10>>.
Found 1-bit register for signal <slv_reg14<11>>.
Found 1-bit register for signal <slv_reg14<12>>.
Found 1-bit register for signal <slv_reg14<13>>.
Found 1-bit register for signal <slv_reg14<14>>.
Found 1-bit register for signal <slv_reg14<15>>.
Found 1-bit register for signal <slv_reg14<16>>.
Found 1-bit register for signal <slv_reg14<17>>.
Found 1-bit register for signal <slv_reg14<18>>.
Found 1-bit register for signal <slv_reg14<19>>.
Found 1-bit register for signal <slv_reg14<20>>.
Found 1-bit register for signal <slv_reg14<21>>.
Found 1-bit register for signal <slv_reg14<22>>.
Found 1-bit register for signal <slv_reg14<23>>.
Found 1-bit register for signal <slv_reg14<24>>.
Found 1-bit register for signal <slv_reg14<25>>.
Found 1-bit register for signal <slv_reg14<26>>.
Found 1-bit register for signal <slv_reg14<27>>.
Found 1-bit register for signal <slv_reg14<28>>.
Found 1-bit register for signal <slv_reg14<29>>.
Found 1-bit register for signal <slv_reg14<30>>.
Found 1-bit register for signal <slv_reg14<31>>.
Found 1-bit register for signal <slv_reg15<0>>.
Found 1-bit register for signal <slv_reg15<1>>.
Found 1-bit register for signal <slv_reg15<2>>.
Found 1-bit register for signal <slv_reg15<3>>.
Found 1-bit register for signal <slv_reg15<4>>.
Found 1-bit register for signal <slv_reg15<5>>.
Found 1-bit register for signal <slv_reg15<6>>.
Found 1-bit register for signal <slv_reg15<7>>.
Found 1-bit register for signal <slv_reg15<8>>.
Found 1-bit register for signal <slv_reg15<9>>.
Found 1-bit register for signal <slv_reg15<10>>.
Found 1-bit register for signal <slv_reg15<11>>.
Found 1-bit register for signal <slv_reg15<12>>.
Found 1-bit register for signal <slv_reg15<13>>.
Found 1-bit register for signal <slv_reg15<14>>.
Found 1-bit register for signal <slv_reg15<15>>.
Found 1-bit register for signal <slv_reg15<16>>.
Found 1-bit register for signal <slv_reg15<17>>.
Found 1-bit register for signal <slv_reg15<18>>.
Found 1-bit register for signal <slv_reg15<19>>.
Found 1-bit register for signal <slv_reg15<20>>.
Found 1-bit register for signal <slv_reg15<21>>.
Found 1-bit register for signal <slv_reg15<22>>.
Found 1-bit register for signal <slv_reg15<23>>.
Found 1-bit register for signal <slv_reg15<24>>.
Found 1-bit register for signal <slv_reg15<25>>.
Found 1-bit register for signal <slv_reg15<26>>.
Found 1-bit register for signal <slv_reg15<27>>.
Found 1-bit register for signal <slv_reg15<28>>.
Found 1-bit register for signal <slv_reg15<29>>.
Found 1-bit register for signal <slv_reg15<30>>.
Found 1-bit register for signal <slv_reg15<31>>.
Found 2-bit register for signal <mem_read_prev>.
Summary:
inferred 514 D-type flip-flop(s).
inferred 530 Multiplexer(s).
Unit <user_logic> synthesized.
Synthesizing Unit <spiifc>.
Related source file is "c:/users/mjlyons/workspace/vspi/src/spi_base/spiifc.v".
AddrBits = 12
Found 1-bit register for signal <ssFastToggleReg>.
Found 1-bit register for signal <ssSlowToggle>.
Found 8-bit register for signal <rcByteReg>.
Found 1-bit register for signal <rcStarted>.
Found 3-bit register for signal <rcBitIndexReg>.
Found 8-bit register for signal <debug_reg>.
Found 8-bit register for signal <stateReg>.
Found 12-bit register for signal <rcMemAddrReg>.
Found 12-bit register for signal <txMemAddrReg>.
Found 3-bit register for signal <txBitAddr>.
Found 12-bit register for signal <rcMemAddrNext>.
Found 8-bit register for signal <rcMemDataReg>.
Found 1-bit register for signal <rcMemWEReg>.
Found 1-bit register for signal <ssPrev>.
Found 3-bit subtractor for signal <rcBitIndex[2]_GND_3_o_sub_17_OUT> created at line 184.
Found 12-bit adder for signal <txMemAddr[11]_GND_3_o_add_19_OUT> created at line 190.
Found 12-bit adder for signal <rcMemAddr[11]_GND_3_o_add_43_OUT> created at line 218.
Found 3-bit subtractor for signal <GND_3_o_GND_3_o_sub_22_OUT<2:0>> created at line 192.
Found 1-bit 8-to-1 multiplexer for signal <SPI_MISO> created at line 125.
Summary:
inferred 4 Adder/Subtractor(s).
inferred 79 D-type flip-flop(s).
inferred 28 Multiplexer(s).
Unit <spiifc> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# Adders/Subtractors : 4
12-bit adder : 2
3-bit subtractor : 2
# Registers : 31
1-bit register : 5
12-bit register : 3
2-bit register : 1
3-bit register : 2
32-bit register : 16
8-bit register : 4
# Multiplexers : 558
1-bit 2-to-1 multiplexer : 521
1-bit 8-to-1 multiplexer : 1
12-bit 2-to-1 multiplexer : 6
3-bit 2-to-1 multiplexer : 7
32-bit 2-to-1 multiplexer : 19
8-bit 2-to-1 multiplexer : 4
# Xors : 1
1-bit xor2 : 1
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
Reading core <ipcore_dir/buffermem.ngc>.
Loading core <buffermem> for timing and area information for instance <mosiMem>.
Loading core <buffermem> for timing and area information for instance <misoMem>.
WARNING:Xst:2677 - Node <rcByteReg_0> of sequential type is unconnected in block <spiifc>.
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# Adders/Subtractors : 4
12-bit adder : 2
3-bit subtractor : 2
# Registers : 592
Flip-Flops : 592
# Multiplexers : 557
1-bit 2-to-1 multiplexer : 520
1-bit 8-to-1 multiplexer : 1
12-bit 2-to-1 multiplexer : 6
3-bit 2-to-1 multiplexer : 7
32-bit 2-to-1 multiplexer : 19
8-bit 2-to-1 multiplexer : 4
# Xors : 1
1-bit xor2 : 1
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
Optimizing unit <user_logic> ...
Optimizing unit <spiifc> ...
WARNING:Xst:1710 - FF/Latch <stateReg_2> (without init value) has a constant value of 0 in block <spiifc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <stateReg_3> (without init value) has a constant value of 0 in block <spiifc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <stateReg_4> (without init value) has a constant value of 0 in block <spiifc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <stateReg_5> (without init value) has a constant value of 0 in block <spiifc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <stateReg_6> (without init value) has a constant value of 0 in block <spiifc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <stateReg_7> (without init value) has a constant value of 0 in block <spiifc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <stateReg_2> (without init value) has a constant value of 0 in block <spiifc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <stateReg_3> (without init value) has a constant value of 0 in block <spiifc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <stateReg_4> (without init value) has a constant value of 0 in block <spiifc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <stateReg_5> (without init value) has a constant value of 0 in block <spiifc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <stateReg_6> (without init value) has a constant value of 0 in block <spiifc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <stateReg_7> (without init value) has a constant value of 0 in block <spiifc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <spi/debug_reg_7> of sequential type is unconnected in block <user_logic>.
WARNING:Xst:2677 - Node <spi/debug_reg_6> of sequential type is unconnected in block <user_logic>.
WARNING:Xst:2677 - Node <spi/debug_reg_5> of sequential type is unconnected in block <user_logic>.
WARNING:Xst:2677 - Node <spi/debug_reg_4> of sequential type is unconnected in block <user_logic>.
WARNING:Xst:2677 - Node <spi/debug_reg_3> of sequential type is unconnected in block <user_logic>.
WARNING:Xst:2677 - Node <spi/debug_reg_2> of sequential type is unconnected in block <user_logic>.
WARNING:Xst:2677 - Node <spi/debug_reg_1> of sequential type is unconnected in block <user_logic>.
WARNING:Xst:2677 - Node <spi/debug_reg_0> of sequential type is unconnected in block <user_logic>.
Mapping all equations...
Building and optimizing final netlist ...
PACKER Warning: Lut spi/Mmux_n010431 is driving XOR and other loads hence can not be packed with the XOR/Carry. This would result in an extra LUT for a feedthrough.
Found area constraint ratio of 100 (+ 5) on block user_logic, actual ratio is 5.
FlipFlop spi/rcByteReg_1 has been replicated 1 time(s)
Final Macro Processing ...
=========================================================================
Final Register Report
Macro Statistics
# Registers : 579
Flip-Flops : 579
=========================================================================
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Design Summary *
=========================================================================
Top Level Output File Name : user_logic.ngc
Primitive and Black Box Usage:
------------------------------
# BELS : 1131
# GND : 3
# INV : 3
# LUT1 : 10
# LUT2 : 21
# LUT3 : 12
# LUT4 : 530
# LUT5 : 122
# LUT6 : 382
# MUXCY : 22
# MUXF7 : 1
# VCC : 1
# XORCY : 24
# FlipFlops/Latches : 579
# FD : 16
# FDE : 37
# FDR : 515
# FDRE : 8
# FDSE : 3
# RAMS : 4
# RAMB16BWER : 4
# Clock Buffers : 2
# BUFGP : 2
# IO Buffers : 123
# IBUF : 86
# OBUF : 37
PACKER Warning: Lut spi/Mmux_n010431 is driving XOR and other loads hence can not be packed with the XOR/Carry. This would result in an extra LUT for a feedthrough.
Device utilization summary:
---------------------------
Selected Device : 6slx45csg324-2
Slice Logic Utilization:
Number of Slice Registers: 579 out of 54576 1%
Number of Slice LUTs: 1080 out of 27288 3%
Number used as Logic: 1080 out of 27288 3%
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 1097
Number with an unused Flip Flop: 518 out of 1097 47%
Number with an unused LUT: 17 out of 1097 1%
Number of fully used LUT-FF pairs: 562 out of 1097 51%
Number of unique control sets: 9
IO Utilization:
Number of IOs: 158
Number of bonded IOBs: 125 out of 218 57%
Specific Feature Utilization:
Number of Block RAM/FIFO: 4 out of 116 3%
Number using Block RAM only: 4
Number of BUFG/BUFGCTRLs: 2 out of 16 12%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=========================================================================
Timing Report
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
Bus2IP_Clk | BUFGP | 520 |
SPI_CLK | BUFGP | 63 |
-----------------------------------+------------------------+-------+
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -2
Minimum period: 6.130ns (Maximum Frequency: 163.132MHz)
Minimum input arrival time before clock: 9.060ns
Maximum output required time after clock: 8.612ns
Maximum combinational path delay: 15.761ns
Timing Details:
---------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'Bus2IP_Clk'
Clock period: 5.714ns (frequency: 175.009MHz)
Total number of paths / destination ports: 562 / 537
-------------------------------------------------------------------------
Delay: 5.714ns (Levels of Logic = 4)
Source: spi/ssPrev (FF)
Destination: misoMem/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAM)
Source Clock: Bus2IP_Clk rising
Destination Clock: Bus2IP_Clk rising
Data Path: spi/ssPrev to misoMem/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 8 0.525 1.052 spi/ssPrev (spi/ssPrev)
LUT3:I1->O 9 0.250 1.204 spi/Mmux_ssFastToggle11 (spi/ssFastToggle)
LUT6:I3->O 12 0.235 1.069 spi/txMemAddrReset1 (spi/txMemAddrReset)
LUT2:I1->O 2 0.254 0.725 spi/Mmux_n010413 (misoMem_addra<11>)
begin scope: 'misoMem:addra<0>'
RAMB16BWER:ADDRA2 0.400 U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
----------------------------------------
Total 5.714ns (1.664ns logic, 4.050ns route)
(29.1% logic, 70.9% route)
=========================================================================
Timing constraint: Default period analysis for Clock 'SPI_CLK'
Clock period: 6.130ns (frequency: 163.132MHz)
Total number of paths / destination ports: 2786 / 84
-------------------------------------------------------------------------
Delay: 6.130ns (Levels of Logic = 3)
Source: spi/ssSlowToggle (FF)
Destination: spi/txMemAddrReg_11 (FF)
Source Clock: SPI_CLK rising
Destination Clock: SPI_CLK rising
Data Path: spi/ssSlowToggle to spi/txMemAddrReg_11
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 14 0.525 1.127 spi/ssSlowToggle (spi/ssSlowToggle)
LUT5:I4->O 6 0.254 1.104 spi/Mmux_state21 (spi/state<1>)
LUT6:I3->O 19 0.235 1.261 spi/Mmux_state[7]_state[7]_mux_55_OUT111 (spi/Mmux_state[7]_state[7]_mux_55_OUT11)
LUT6:I5->O 12 0.254 1.068 spi/_n0491_inv1 (spi/_n0491_inv)
FDE:CE 0.302 spi/txMemAddrReg_0
----------------------------------------
Total 6.130ns (1.570ns logic, 4.560ns route)
(25.6% logic, 74.4% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Bus2IP_Clk'
Total number of paths / destination ports: 9953 / 1179
-------------------------------------------------------------------------
Offset: 9.060ns (Levels of Logic = 6)
Source: Bus2IP_WrCE<10> (PAD)
Destination: slv_reg5_31 (FF)
Destination Clock: Bus2IP_Clk rising
Data Path: Bus2IP_WrCE<10> to slv_reg5_31
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 68 1.328 2.391 Bus2IP_WrCE_10_IBUF (Bus2IP_WrCE_10_IBUF)
LUT6:I1->O 3 0.254 0.766 slv_reg_write_sel[0]_GND_1_o_equal_80_o<0>11 (slv_reg_write_sel[0]_GND_1_o_equal_80_o<0>1)
LUT4:I3->O 5 0.254 0.841 slv_reg_write_sel[0]_GND_1_o_equal_80_o<0>211 (slv_reg_write_sel[0]_GND_1_o_equal_80_o<0>21)
LUT5:I4->O 3 0.254 0.766 slv_reg_write_sel[0]_GND_1_o_equal_84_o<0>11 (slv_reg_write_sel[0]_GND_1_o_equal_84_o<0>1)
LUT4:I3->O 32 0.254 1.628 slv_reg_write_sel[0]_GND_1_o_equal_84_o<0>2 (slv_reg_write_sel[0]_GND_1_o_equal_84_o)
LUT4:I2->O 1 0.250 0.000 Mmux__n2030161 (_n2030<23>)
FDR:D 0.074 slv_reg5_23
----------------------------------------
Total 9.060ns (2.668ns logic, 6.392ns route)
(29.4% logic, 70.6% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'SPI_CLK'
Total number of paths / destination ports: 629 / 103
-------------------------------------------------------------------------
Offset: 8.484ns (Levels of Logic = 5)
Source: SPI_SS (PAD)
Destination: spi/txMemAddrReg_11 (FF)
Destination Clock: SPI_CLK rising
Data Path: SPI_SS to spi/txMemAddrReg_11
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 11 1.328 1.267 SPI_SS_IBUF (SPI_SS_IBUF)
LUT3:I0->O 9 0.235 1.431 spi/Mmux_ssFastToggle11 (spi/ssFastToggle)
LUT6:I0->O 2 0.254 0.834 spi/rcByteValid1_1 (spi/rcByteValid1)
LUT6:I4->O 19 0.250 1.261 spi/Mmux_state[7]_state[7]_mux_55_OUT111 (spi/Mmux_state[7]_state[7]_mux_55_OUT11)
LUT6:I5->O 12 0.254 1.068 spi/_n0491_inv1 (spi/_n0491_inv)
FDE:CE 0.302 spi/txMemAddrReg_0
----------------------------------------
Total 8.484ns (2.623ns logic, 5.861ns route)
(30.9% logic, 69.1% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Bus2IP_Clk'
Total number of paths / destination ports: 650 / 34
-------------------------------------------------------------------------
Offset: 8.612ns (Levels of Logic = 5)
Source: slv_reg4_0 (FF)
Destination: IP2Bus_Data<0> (PAD)
Source Clock: Bus2IP_Clk rising
Data Path: slv_reg4_0 to IP2Bus_Data<0>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDR:C->Q 2 0.525 1.156 slv_reg4_0 (slv_reg4_0)
LUT5:I0->O 1 0.254 0.682 Mmux_IP2Bus_Data110 (Mmux_IP2Bus_Data1)
LUT6:I5->O 1 0.254 0.682 Mmux_IP2Bus_Data112 (Mmux_IP2Bus_Data12)
LUT6:I5->O 1 0.254 0.958 Mmux_IP2Bus_Data116 (Mmux_IP2Bus_Data16)
LUT6:I2->O 1 0.254 0.681 Mmux_IP2Bus_Data121 (IP2Bus_Data_0_OBUF)
OBUF:I->O 2.912 IP2Bus_Data_0_OBUF (IP2Bus_Data<0>)
----------------------------------------
Total 8.612ns (4.453ns logic, 4.159ns route)
(51.7% logic, 48.3% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'SPI_CLK'
Total number of paths / destination ports: 5 / 1
-------------------------------------------------------------------------
Offset: 5.953ns (Levels of Logic = 3)
Source: spi/txBitAddr_0 (FF)
Destination: SPI_MISO (PAD)
Source Clock: SPI_CLK rising
Data Path: spi/txBitAddr_0 to SPI_MISO
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDE:C->Q 9 0.525 1.406 spi/txBitAddr_0 (spi/txBitAddr_0)
LUT6:I1->O 1 0.254 0.000 spi/Mmux_SPI_MISO_3 (spi/Mmux_SPI_MISO_3)
MUXF7:I1->O 1 0.175 0.681 spi/Mmux_SPI_MISO_2_f7 (SPI_MISO_OBUF)
OBUF:I->O 2.912 SPI_MISO_OBUF (SPI_MISO)
----------------------------------------
Total 5.953ns (3.866ns logic, 2.087ns route)
(64.9% logic, 35.1% route)
=========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 4656 / 35
-------------------------------------------------------------------------
Delay: 15.761ns (Levels of Logic = 8)
Source: Bus2IP_RdCE<5> (PAD)
Destination: IP2Bus_Data<0> (PAD)
Data Path: Bus2IP_RdCE<5> to IP2Bus_Data<0>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 99 1.328 2.429 Bus2IP_RdCE_5_IBUF (Bus2IP_RdCE_5_IBUF)
LUT4:I1->O 33 0.235 1.537 slv_reg_read_sel[0]_GND_1_o_equal_129_o<0>21 (slv_reg_read_sel[0]_GND_1_o_equal_129_o<0>2)
LUT5:I4->O 35 0.254 1.846 slv_reg_read_sel[0]_GND_1_o_equal_136_o<0>11 (slv_reg_read_sel[0]_GND_1_o_equal_136_o<0>1)
LUT4:I0->O 32 0.254 1.950 slv_reg_read_sel[0]_GND_1_o_equal_140_o<0>11 (slv_reg_read_sel[0]_GND_1_o_equal_140_o<0>1)
LUT5:I0->O 1 0.254 0.682 Mmux_IP2Bus_Data119 (Mmux_IP2Bus_Data19)
LUT6:I5->O 1 0.254 0.910 Mmux_IP2Bus_Data120 (Mmux_IP2Bus_Data110)
LUT6:I3->O 1 0.235 0.681 Mmux_IP2Bus_Data121 (IP2Bus_Data_0_OBUF)
OBUF:I->O 2.912 IP2Bus_Data_0_OBUF (IP2Bus_Data<0>)
----------------------------------------
Total 15.761ns (5.726ns logic, 10.035ns route)
(36.3% logic, 63.7% route)
=========================================================================
Cross Clock Domains Report:
--------------------------
Clock to Setup on destination clock Bus2IP_Clk
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
Bus2IP_Clk | 5.714| | | |
SPI_CLK | 5.667| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock SPI_CLK
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
Bus2IP_Clk | 7.481| | | |
SPI_CLK | 6.130| | | |
---------------+---------+---------+---------+---------+
=========================================================================
Total REAL time to Xst completion: 24.00 secs
Total CPU time to Xst completion: 23.64 secs
-->
Total memory usage is 255080 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 37 ( 0 filtered)
Number of infos : 2 ( 0 filtered)
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/user_logic.xst 0 → 100644
View file @ 94c99edd
set -tmpdir "xst/projnav.tmp"
set -xsthdpdir "xst"
run
-ifn user_logic.prj
-ifmt mixed
-ofn user_logic
-ofmt NGC
-p xc6slx45-2-csg324
-top user_logic
-opt_mode Speed
-opt_level 1
-power NO
-iuc NO
-keep_hierarchy No
-netlist_hierarchy As_Optimized
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-sd {"ipcore_dir" }
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case Maintain
-slice_utilization_ratio 100
-bram_utilization_ratio 100
-dsp_utilization_ratio 100
-lc Auto
-reduce_control_sets Auto
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-fsm_style LUT
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-shreg_extract YES
-rom_style Auto
-auto_bram_packing NO
-resource_sharing YES
-async_to_sync NO
-shreg_min_size 2
-use_dsp48 Auto
-iobuf YES
-max_fanout 100000
-bufg 16
-register_duplication YES
-register_balancing No
-optimize_primitives NO
-use_clock_enable Auto
-use_sync_set Auto
-use_sync_reset Auto
-iob Auto
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/user_logic_xst.xrpt 0 → 100644
View file @ 94c99edd
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="nt64" product="ISE" version="13.2">
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The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Xst" timeStamp="Thu Mar 01 10:48:00 2012">
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<item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC"/>
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<item stringID="variable" value="XILINX_DSP"/>
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<item stringID="variable" value="XILINX_EDK"/>
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<item stringID="variable" value="XILINX_PLANAHEAD"/>
<item stringID="value" value="C:\Xilinx\13.2\ISE_DS\PlanAhead"/>
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</table>
<item stringID="User_EnvOs" value="OS Information">
<item stringID="User_EnvOsname" value="Microsoft Windows 7 , 64-bit"/>
<item stringID="User_EnvOsrelease" value="Service Pack 1 (build 7601)"/>
</item>
<item stringID="User_EnvHost" value="WIN-MEQROG0RPAS"/>
<table stringID="User_EnvCpu">
<column stringID="arch"/>
<column stringID="speed"/>
<row stringID="row" value="0">
<item stringID="arch" value="Intel(R) Core(TM) i5-2400S CPU @ 2.50GHz"/>
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</table>
</section>
<section stringID="XST_OPTION_SUMMARY">
<item DEFAULT="" label="-ifn" stringID="XST_IFN" value="user_logic.prj"/>
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<item AVAILABLE="27288" dataType="int" label="Number used as Logic" stringID="XST_NUMBER_USED_AS_LOGIC" value="1080"/>
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="XST_NUMBER_OF_LUT_FLIP_FLOP_PAIRS_USED" value="1097"/>
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<item AVAILABLE="218" dataType="int" label="Number of bonded IOBs" stringID="XST_NUMBER_OF_BONDED_IOBS" value="125"/>
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<item dataType="int" label="Number using Block RAM only" stringID="XST_NUMBER_USING_BLOCK_RAM_ONLY" value="4"/>
<item AVAILABLE="16" dataType="int" label="Number of BUFG/BUFGCTRLs" stringID="XST_NUMBER_OF_BUFGBUFGCTRLS" value="2"/>
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<section stringID="XST_PARTITION_RESOURCE_SUMMARY">
<section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
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<section stringID="XST_ERRORS_STATISTICS">
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<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="37"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="2"/>
</section>
</application>
</document>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/webtalk_impact.xml 0 → 100644
View file @ 94c99edd
<?xml version="1.0" encoding="UTF-8" ?>
<document>
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="impact" timeStamp="Tue Mar 06 15:24:19 2012">
<section name="Project Information" visible="false">
<property name="ProjectID" value="5ea5de4132cd436698ae1e90d83ce606"/>
<property name="ProjectIteration" value="1"/>
</section>
<section name="iMPACT Project Info" visible="true">
<property name="Use Project File" value="Yes"/>
<property name="Project Entry" value="ise"/>
<property name="OS Name" value="Microsoft Windows 7 (64 Bit)"/>
<property name="User Lic. Info" value="179841373_174164856_206270303_042"/>
</section>
<section name="iMPACT One Step SVF File Mode" visible="true">
<item name="Chain Summary">
<property name="Number of device" value="1"/>
<property name="Number of Xilinx device" value="1"/>
<property name="Number of Non-Xilinx device" value="0"/>
</item>
<item name="Chain Description">
<property name="Device1" value="spartan6"/>
<property name="Part1" value="xc6slx45"/>
</item>
<item name="Boundary Scan Operations Statistics">
<property name="BSCAN Operation" value="Program -p 0
"/>
<property name="BSCAN Operation" value="Program -p 0
"/>
<property name="BSCAN Operation" value="Program -p 0
"/>
</item>
<item name="Cable Summary">
<property name="Cable Type" value="Platform Cable USB"/>
<property name="Cable Speed" value="6 MHz"/>
<property name="Port" value="usb-hs"/>
<property name="Local_Server_Mode" value="Local"/>
</item>
</section>
</application>
</document>
projnav/xps/pcores/spiifc_v1_00_a/hdl/verilog/spiifc.v 0 → 100644
View file @ 94c99edd
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:24:33 10/18/2011
// Design Name:
// Module Name: spiifc
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module spiifc(
Reset,
SysClk,
SPI_CLK,
SPI_MISO,
SPI_MOSI,
SPI_SS,
txMemAddr,
txMemData,
rcMemAddr,
rcMemData,
rcMemWE,
debug_out
);
//
// Parameters
//
parameter AddrBits = 12;
// Defines
`define CMD_READ_START 8'd1
`define CMD_READ_MORE 8'd2
`define CMD_WRITE_START 8'd3
`define STATE_GET_CMD 8'd0
`define STATE_READING 8'd1
`define STATE_WRITING 8'd2
//
// Input/Output defs
//
input Reset;
input SysClk;
input SPI_CLK;
output SPI_MISO;
input SPI_MOSI;
input SPI_SS;
output [AddrBits-1:0] txMemAddr;
input [7:0] txMemData;
output [AddrBits-1:0] rcMemAddr;
output [7:0] rcMemData;
output rcMemWE;
output [7:0] debug_out;
//
// Registers
//
reg [ 7: 0] debug_reg;
reg [ 7: 0] rcByteReg;
reg rcStarted;
reg [ 2: 0] rcBitIndexReg;
reg [11: 0] rcMemAddrReg;
reg [11: 0] rcMemAddrNext;
reg [ 7: 0] rcMemDataReg;
reg rcMemWEReg;
reg ssPrev;
reg ssFastToggleReg;
reg ssSlowToggle;
reg ssTurnOnReg;
reg ssTurnOnHandled;
reg [ 7: 0] cmd;
reg [ 7: 0] stateReg;
reg [11: 0] txMemAddrReg;
reg [ 2: 0] txBitAddr;
//
// Wires
//
wire rcByteValid;
wire [ 7: 0] rcByte;
wire rcStarting;
wire [ 2: 0] rcBitIndex;
wire ssTurnOn;
wire ssFastToggle;
wire [ 7: 0] state;
wire txMemAddrReset;
//
// Output assigns
//
assign debug_out = debug_reg;
assign rcMemAddr = rcMemAddrReg;
assign rcMemData = rcMemDataReg;
assign rcMemWE = rcMemWEReg;
assign txMemAddrReset = (rcByteValid && rcByte == `CMD_WRITE_START ? 1 : 0);
assign txMemAddr = (txMemAddrReset ? 0 : txMemAddrReg);
assign SPI_MISO = txMemData[txBitAddr];
assign ssFastToggle =
(ssPrev == 1 && SPI_SS == 0 ? ~ssFastToggleReg : ssFastToggleReg);
//
// Wire assigns
//
assign rcByteValid = rcStarted && rcBitIndex == 0;
assign rcByte = {rcByteReg[7:1], SPI_MOSI};
assign rcStarting = ssTurnOn;
assign rcBitIndex = (rcStarting ? 3'd7 : rcBitIndexReg);
assign ssTurnOn = ssSlowToggle ^ ssFastToggle;
assign state = (rcStarting ? `STATE_GET_CMD : stateReg);
initial begin
ssSlowToggle <= 0;
end
always @(posedge SysClk) begin
ssPrev <= SPI_SS;
if (Reset) begin
ssTurnOnReg <= 0;
ssFastToggleReg <= 0;
end else begin
if (ssPrev & (~SPI_SS)) begin
ssTurnOnReg <= 1;
ssFastToggleReg <= ~ssFastToggleReg;
end else if (ssTurnOnHandled) begin
ssTurnOnReg <= 0;
end
end
end
always @(posedge SPI_CLK) begin
ssSlowToggle <= ssFastToggle;
if (Reset) begin
// Resetting
rcByteReg <= 8'h00;
rcStarted <= 0;
rcBitIndexReg <= 3'd7;
ssTurnOnHandled <= 0;
debug_reg <= 8'hFF;
end else begin
// Not resetting
ssTurnOnHandled <= ssTurnOn;
stateReg <= state;
rcMemAddrReg <= rcMemAddrNext;
if (~SPI_SS) begin
rcByteReg[rcBitIndex] <= SPI_MOSI;
rcBitIndexReg <= rcBitIndex - 3'd1;
rcStarted <= 1;
// Update txBitAddr if writing out
if (`STATE_WRITING == state) begin
if (txBitAddr == 3'd1) begin
txMemAddrReg <= txMemAddr + 1;
end
txBitAddr <= txBitAddr - 1;
end
end
// We've just received a byte (well, currently receiving the last bit)
if (rcByteValid) begin
// For now, just display on LEDs
debug_reg <= rcByte;
if (`STATE_GET_CMD == state) begin
cmd <= rcByte; // Will take effect next cycle
if (`CMD_READ_START == rcByte) begin
rcMemAddrNext <= 0;
stateReg <= `STATE_READING;
end else if (`CMD_READ_MORE == rcByte) begin
stateReg <= `STATE_READING;
end else if (`CMD_WRITE_START == rcByte) begin
txBitAddr <= 3'd7;
stateReg <= `STATE_WRITING;
txMemAddrReg <= txMemAddr; // Keep at 0
end
end else if (`STATE_READING == state) begin
rcMemDataReg <= rcByte;
rcMemAddrNext <= rcMemAddr + 1;
rcMemWEReg <= 1;
// end else if (`STATE_WRITING == state) begin
// txBitAddr <= 3'd7;
// stateReg <= `STATE_WRITING;
end
end else begin
// Not a valid byte
rcMemWEReg <= 0;
end // valid/valid' byte
end // Reset/Reset'
end
/*
reg rcByte_valid;
wire rcClockBridgeEmpty;
wire readRcByte;
assign getRcByte = ~rcClockBridgeEmpty;
wire rcClockBridgeReadValid;
wire rcClockBridgeFull;
wire [7:0] rcByte;
clock_bridge recvClockBridge (
.rst(Reset), // input rst
.wr_clk(~SPI_CLK), // input wr_clk
.rd_clk(SysClk), // input rd_clk
.din(SPI_MOSI), // input [0 : 0] din
.wr_en(~SPI_SS), // input wr_en
.rd_en(getRcByte), // input rd_en
.dout(rcByte), // output [7 : 0] dout
.full(rcClockBridgeFull), // output full
.empty(rcClockBridgeEmpty), // output empty
.valid(rcClockBridgeReadValid) // output valid
);
always @(posedge SysClk) begin
rcByte_valid <= getRcByte;
end
wire txCmdClkBridgeEmpty;
wire txCmdClkBridgeFull;
wire [7:0] txCmd;
wire txCmdValid;
assign txCmdValid = ~txCmdClkBridgeEmpty;
wire postTxCmd;
assign postTxCmd =
fifo_8bit_to_8bit txCmdClkBridge(
.rst(Reset), // input rst
.wr_clk(SysClk), // input wr_clk
.rd_clk(SPI_CLK), // input rd_clk
.din(din), // input [7 : 0] din
.wr_en(post), // input wr_en
.rd_en(txCmdValid), // input rd_en
.dout(txCmd), // output [7 : 0] dout
.full(txCmdClkBridgeFull), // output full
.empty(txCmdClkBridgeEmpty) // output empty
);
//
// TRANSMIT: FPGA TO PC
//
assign SPI_MISO = txMemData[bitIndex];
reg [2:0] bitIndex;
reg [AddrBits-1:0] byteAddr;
assign txMemAddr = byteAddr;
reg [7:0] debug_reg;
assign debug_out = debug_reg;
initial begin
debug_reg <= 8'h00;
//rcState <= 0;
end
//
// Clocked logic
//
always @(posedge SPI_CLK) begin
if (Reset) begin
bitIndex <= 3'd0;
byteAddr <= 0;
end else if (SPI_SS == 1'b0) begin
bitIndex <= bitIndex - 3'd1;
if (bitIndex == 3'd1) begin
byteAddr <= byteAddr + 1;
end
end
end
//
// RECEIVE: PC TO FPGA
//
// Detect start of receive
reg ss_prev;
wire ss_negedge;
always @(posedge SysClk) begin
ss_prev <= SPI_SS;
end
assign ss_negedge = (ss_prev == 1'b1 && SPI_SS == 1'b0 ? 1'b1 : 1'b0);
`define RC_MODE_GET_STATUS 8'd0
`define RC_MODE_GET_BUFFER 8'd1
`define RC_MODE_PUT_BUFFER 8'd2
reg [7:0] rcMode;
`define RC_STATE_CMD 8'd0
`define RC_STATE_SIZE 8'd1
`define RC_STATE_PAYLOAD 8'd2
reg [7:0] rcState;
reg [31:0] rcByteCount;
reg [31:0] rcByteSize;
reg [7:0] rcMemData_reg;
reg [AddrBits-1:0] rcMemAddr_reg;
reg rcMemWE_reg;
assign rcMemData = rcMemData_reg;
assign rcMemAddr = rcMemAddr_reg;
assign rcMemWE = rcMemWE_reg;
always @(posedge SysClk) begin
// // About to receive
// if (ss_negedge) begin
// rcBitIndex <= 3'd7;
// rcState <= `RC_STATE_CMD;
//
// debug_reg[0] <= 1;
// end
//
// // Receiving
// if (receiving) begin
// rcByte[rcBitIndex] <= SPI_MOSI;
// rcBitIndex <= rcBitIndex - 3'd1;
// end
// rcByte_valid <= (receiving && rcBitIndex == 3'd0 ? 1'b1 : 1'b0);
// Handle the complete incoming byte
if (rcByte_valid) begin
debug_reg[7:4] <= rcByte[3:0];
// First byte: the command
if (`RC_STATE_CMD == rcState || ss_negedge) begin
// Disable writing to the read buffer (will be left on if the prev
// cycle was writing to it)
rcMemWE_reg <= 1'b0;
debug_reg[0] <= 1;
// Decode the SPI command
case (rcByte)
`RC_MODE_GET_STATUS: begin end // no status yet
`RC_MODE_GET_BUFFER: begin rcMode <= `RC_MODE_GET_BUFFER; rcState <= `RC_STATE_SIZE; end
`RC_MODE_PUT_BUFFER: begin rcMode <= `RC_MODE_PUT_BUFFER; rcState <= `RC_STATE_SIZE; end
endcase
// Initialize counters
rcByteCount <= 32'd0;
rcByteSize <= 32'd0;
end
// Record size (in bytes) of payload
if (`RC_STATE_SIZE == rcState) begin
debug_reg[1] <= 1;
case (rcByteCount)
32'd0: begin rcByteSize[31:24] <= rcByte; rcByteCount <= 32'd1; end
32'd1: begin rcByteSize[23:16] <= rcByte; rcByteCount <= 32'd2; end
32'd2: begin rcByteSize[15: 8] <= rcByte; rcByteCount <= 32'd3; end
32'd3: begin
rcByteSize[ 7: 0] <= rcByte;
rcByteCount <= 32'd0;
rcState <= `RC_STATE_PAYLOAD;
rcByteCount <= 32'd0;
if (`RC_MODE_GET_BUFFER == rcMode) begin
// TODO: want reset tx byte addr here probably
end
end
endcase
end
// The payload
if (rcState == `RC_STATE_PAYLOAD) begin
debug_reg[2] <= 1;
case (rcMode)
`RC_MODE_GET_BUFFER: begin
// IGNORE EVERYTHING SO STUFF CAN BE READ OUT
end
`RC_MODE_PUT_BUFFER: begin
//debug_reg[4] <= 1;
rcMemWE_reg <= 1'b1;
rcMemData_reg <= rcByte;
rcMemAddr_reg <= rcByteCount[AddrBits-1:0];
end
endcase
if (rcByteCount == rcByteSize - 1) begin
rcState <= `RC_STATE_CMD;
//debug_reg[5] <= 1;
end else begin
rcByteCount <= rcByteCount + 32'd1;
end
end
end
else begin // not valid byte
if (ss_negedge) begin
rcState <= `RC_STATE_CMD;
end
end
end
//reg [7:0] rcByteReg;
//wire [7:0] rcByte;
//assign rcByte = {rcByteReg[7:1], (SPI_SS == 1'b0 && bitIndex ==
// //
// // Receive (GPU to SPI)
// //
// reg SPI_SS_prev_cycle;
//
// // This is the register backing rcByteId. It is always one cycle
// // behind the true value of rcByteId, which we have to do a little
// // work to get instantaneously correct using wire logic.
// reg [31:0] rcByteIdPrev;
// wire [31:0] rcByteId;
// assign rcByteId = (SPI_SS_prev_cycle == 1 && SPI_SS == 0 ? 32'd0 : 32'd1 + rcByteIdPrev);
//
// // 1 if we're receiving from GPC, 0 if not.
// wire isRecv;
// assign isRecv = ~SPI_SS;
//
// // Bits to Byte aggregator
// reg [2:0] rcBitId;
// reg [7:0] rcByte;
//
//
// reg [31:0] rcSizeBytes;
//
// always @(posedge SPI_CLK) begin
// if (1 == isRecv) begin
// case (rcByteId)
// 0: rcSizeBytes[ 7: 0] <=
// end
//
// // Update registers for next cycle
// SPI_SS_prev_cycle <= SPI_SS;
// rcByteId <= rcByteIdPrev;
// end
*/
endmodule
projnav/xps/pcores/spiifc_v1_00_a/hdl/verilog/user_logic.v
View file @ 94c99edd
......@@ -52,6 +52,10 @@ module user_logic
(
// -- ADD USER PORTS BELOW THIS LINE ---------------
// --USER ports added here
SPI_CLK,
SPI_MOSI,
SPI_MISO,
SPI_SS,
// -- ADD USER PORTS ABOVE THIS LINE ---------------
// -- DO NOT EDIT BELOW THIS LINE ------------------
......@@ -93,6 +97,10 @@ parameter C_NUM_INTR = 1;
// -- ADD USER PORTS BELOW THIS LINE -----------------
// --USER ports added here
input SPI_CLK;
input SPI_MOSI;
output SPI_MISO;
input SPI_SS;
// -- ADD USER PORTS ABOVE THIS LINE -----------------
// -- DO NOT EDIT BELOW THIS LINE --------------------
......@@ -125,7 +133,6 @@ output [0 : C_NUM_INTR-1] IP2Bus_IntrEvent;
// --USER nets declarations added here, as needed for user logic
// Memmap memory logic lines
wire [0 : C_NUM_MEM-1 ] mem_ena; // Port A: spiifc
wire [0 : C_NUM_MEM-1 ] mem_enb; // Port B: sysbus/dma
wire [0 : C_NUM_MEM-1 ] mem_web;
wire [0 : C_NUM_MEM-1] mem_write;
......@@ -133,6 +140,7 @@ output [0 : C_NUM_INTR-1] IP2Bus_IntrEvent;
reg [0 : C_NUM_MEM-1 ] mem_read_prev;
// mosiMem (mem0): data received from master
wire mosiMem_wea;
wire [0 : 11] mosiMem_addra;
wire [0 : 7 ] mosiMem_dina;
wire [0 : 9 ] mosiMem_addrb;
......@@ -172,14 +180,10 @@ output [0 : C_NUM_INTR-1] IP2Bus_IntrEvent;
// --USER logic implementation added here
// memory interface logic
assign mem_ena = 2'd0; // TODO: interface with spiifc
assign mem_enb = mem_write | mem_read /*& {C_NUM_MEM{Bus2IP_RdReq | Bus2IP_WrReq}}*/;
assign mem_web = mem_write;
assign mosiMem_addra = 12'h000; // TODO: interface with spiifc
assign mosiMem_dina = 8'd00; // TODO: interface with spiifc
assign mosiMem_addrb = Bus2IP_Addr[20:29];
assign mosiMem_dinb = Bus2IP_Data;
assign misoMem_addra = 12'h000; // TODO: interface with spiifc
assign misoMem_addrb = Bus2IP_Addr[20:29];
assign misoMem_dinb = Bus2IP_Data;
......@@ -192,9 +196,9 @@ output [0 : C_NUM_INTR-1] IP2Bus_IntrEvent;
// Mem0: Memory buffer storing data coming from master
buffermem mosiMem (
.clka(Bus2IP_Clk), // input clka
.ena(mem_ena[0]), // input ena
.wea(1'b1), // Always writing, never reading
.clka(SPI_CLK), // input clka
.ena(1'b1), // input ena
.wea(mosiMem_wea), // Always writing, never reading
.addra({mosiMem_addra}), // input [11 : 0] addra
.dina({mosiMem_dina}), // input [7 : 0] dina
// .douta(mosiMem_douta), // NEVER USED: output [7 : 0] douta
......@@ -208,8 +212,8 @@ output [0 : C_NUM_INTR-1] IP2Bus_IntrEvent;
// Mem1: Memory buffer storing data to send to master
buffermem misoMem (
.clka(Bus2IP_Clk), // input clka
.ena(mem_ena[1]), // input ena
.clka(SPI_CLK), // input clka
.ena(1'b1), // input ena
.wea(1'b0), // Always reading, never writing
.addra({misoMem_addra}), // input [11 : 0] addra
// .dina(dina), // input [7 : 0] dina
......@@ -221,6 +225,20 @@ output [0 : C_NUM_INTR-1] IP2Bus_IntrEvent;
.dinb({misoMem_dinb}), // input [31 : 0] dinb
.doutb({misoMem_doutb}) // output [31 : 0] doutb
);
spiifc spi (
.Reset(Bus2IP_Reset),
.SysClk(Bus2IP_Clk),
.SPI_CLK(SPI_CLK),
.SPI_MISO(SPI_MISO),
.SPI_MOSI(SPI_MOSI),
.SPI_SS(SPI_SS),
.txMemAddr(misoMem_addra),
.txMemData(misoMem_douta),
.rcMemAddr(mosiMem_addra),
.rcMemData(mosiMem_dina),
.rcMemWE(mosiMem_wea)
);
// ------------------------------------------------------
// Example code to read/write user logic slave model s/w accessible registers
......
projnav/xps/pcores/spiifc_v1_00_a/hdl/vhdl/spiifc.vhd
View file @ 94c99edd
......@@ -171,7 +171,10 @@ entity spiifc is
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
SPI_CLK : in std_logic;
SPI_MOSI : in std_logic;
SPI_MISO : out std_logic;
SPI_SS : in std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
......@@ -414,7 +417,10 @@ architecture IMP of spiifc is
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
SPI_CLK : in std_logic;
SPI_MOSI : in std_logic;
SPI_MISO : out std_logic;
SPI_SS : in std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
......@@ -589,7 +595,10 @@ begin
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
SPI_CLK => SPI_CLK,
SPI_MOSI => SPI_MOSI,
SPI_MISO => SPI_MISO,
SPI_SS => SPI_SS,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
......
projnav/xps/system.mhs
View file @ 94c99edd
......@@ -20,6 +20,10 @@
PORT fpga_0_Push_Buttons_5Bits_GPIO_IO_I_pin = fpga_0_Push_Buttons_5Bits_GPIO_IO_I_pin, DIR = I, VEC = [0:4]
PORT fpga_0_clk_1_sys_clk_pin = CLK_S, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
PORT fpga_0_rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 0
PORT spiifc_0_SPI_CLK_pin = spiifc_0_SPI_CLK, DIR = I, SIGIS = CLK, CLK_FREQ = 50000000
PORT spiifc_0_SPI_MISO_pin = spiifc_0_SPI_MISO, DIR = O
PORT spiifc_0_SPI_MOSI_pin = spiifc_0_SPI_MOSI, DIR = I
PORT spiifc_0_SPI_SS_pin = spiifc_0_SPI_SS, DIR = I
BEGIN microblaze
......@@ -170,6 +174,10 @@ BEGIN spiifc
PARAMETER C_MEM1_BASEADDR = 0x85011000
PARAMETER C_MEM1_HIGHADDR = 0x85011FFF
BUS_INTERFACE SPLB = mb_plb
PORT SPI_CLK = spiifc_0_SPI_CLK
PORT SPI_MOSI = spiifc_0_SPI_MOSI
PORT SPI_MISO = spiifc_0_SPI_MISO
PORT SPI_SS = spiifc_0_SPI_SS
END
BEGIN xps_central_dma
......
src/spi_base/spiifc.v
View file @ 94c99edd
......@@ -218,9 +218,9 @@ module spiifc(
rcMemAddrNext <= rcMemAddr + 1;
rcMemWEReg <= 1;
// end else if (`STATE_WRITING == state) begin
// txBitAddr <= 3'd7;
// stateReg <= `STATE_WRITING;
end else if (`STATE_WRITING == state) begin
txBitAddr <= 3'd7;
stateReg <= `STATE_WRITING;
end
end else begin
......
src/spi_base/spiifc_fastclock.v 0 → 100644
View file @ 94c99edd
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:46:12 03/02/2012
// Design Name:
// Module Name: spiifc
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module spiifc(
Reset,
SysClk,
SPI_CLK,
SPI_MISO,
SPI_MOSI,
SPI_SS,
txMemAddr,
txMemData,
rcMemAddr,
rcMemData,
rcMemWE,
debug_out
);
//
// Parameters
//
parameter AddrBits = 12;
//
// Defines
//
`define CMD_READ_START 8'd1
`define CMD_READ_MORE 8'd2
`define CMD_WRITE_START 8'd3
`define CMD_WRITE_MORE 8'd4
`define CMD_INTERRUPT 8'd5
`define STATE_GET_CMD 8'd0
`define STATE_READING 8'd1
`define STATE_WRITING 8'd2
`define STATE_WRITE_INTR 8'd3
//
// Input/Outputs
//
input Reset;
input SysClk;
input SPI_CLK;
output SPI_MISO; // outgoing (from respect of this module)
input SPI_MOSI; // incoming (from respect of this module)
input SPI_SS;
output [AddrBits-1:0] txMemAddr; // outgoing data
input [7:0] txMemData;
output [AddrBits-1:0] rcMemAddr; // incoming data
output [7:0] rcMemData;
output rcMemWE;
output [7:0] debug_out;
//
// Registers
//
reg prev_spiClk; // Value of SPI_CLK during last SysClk cycle
reg prev_spiSS; // Value of SPI_SS during last SysClk cycle
reg [7:0] state_reg; // Register backing the 'state' wire
reg [7:0] rcByte_reg; // Register backing 'rcByte'
reg [2:0] rcBitIndex_reg; // Register backing 'rcBitIndex'
reg [AddrBits-1:0] rcMemAddr_reg; // Byte addr to write MOSI data to
//
// Wires
//
wire risingSpiClk; // Did the SPI_CLK rise since last SysClk cycle?
wire validSpiBit; // Are the SPI MOSI/MISO bits new and valid?
reg state; // Current state in the module's state machine (always @* effectively wire)
wire rcByteValid; // rcByte is valid and new
wire [7:0] rcByte; // Byte received from master
wire [2:0] rcBitIndex; // Bit of rcByte to write to next
// Detect new valid bit
always @(posedge SysClk) begin
prev_spiClk <= SPI_CLK;
end
assign risingSpiClk = SPI_CLK & (~prev_spiClk);
assign validSpiBit = risingSpiClk & (~SPI_SS);
// Detect new SPI packet (SS dropped low)
always @(posedge SysClk) begin
prev_spiSS <= SPI_SS;
end
assign packetStart = prev_spiSS & (~SPI_SS);
// Build incoming byte
always @(posedge SysClk) begin
if (validSpiBit) begin
rcByte_reg[rcBitIndex] <= SPI_MOSI;
rcBitIndex_reg <= (rcBitIndex > 0 ? rcBitIndex - 1 : 7);
end else begin
rcBitIndex_reg <= rcBitIndex;
end
end
assign rcBitIndex = (Reset || packetStart ? 7 : rcBitIndex_reg);
assign rcByte = {rcByte_reg[7:1], SPI_MOSI};
assign rcByteValid = (validSpiBit && rcBitIndex == 0 ? 1 : 0);
// Incoming MOSI data buffer management
assign rcMemAddr = rcMemAddr_reg;
assign rcMemData = rcByte;
assign rcMemWE = (state == `STATE_READING && rcByteValid ? 1 : 0);
always @(posedge SysClk) begin
if (Reset || (`STATE_GET_CMD == state && rcByteValid)) begin
rcMemAddr_reg <= 0;
end else if (rcMemWE) begin
rcMemAddr_reg <= rcMemAddr + 1;
end else begin
rcMemAddr_reg <= rcMemAddr;
end
end
// State machine
always @(*) begin
if (Reset || packetStart) begin
state <= `STATE_GET_CMD;
end else if (state_reg == `STATE_GET_CMD && rcByteValid) begin
state <= rcByte;
end else begin
state <= state_reg;
end
end
always @(posedge SysClk) begin
if (`STATE_GET_CMD == state && rcByteValid) begin
if (`CMD_READ_START == rcByte) begin
state_reg <= `STATE_READING;
end else if (`CMD_READ_MORE == rcByte) begin
state_reg <= `STATE_READING;
end else if (`CMD_WRITE_START == rcByte) begin
state_reg <= `STATE_WRITING;
end else if (`CMD_WRITE_MORE == rcByte) begin
state_reg <= `STATE_WRITING;
end else if (`CMD_INTERRUPT == rcByte) begin
// TODO: NYI
end
end else begin
state_reg <= state;
end
end
endmodule
src/spi_base/spiwrap.v
View file @ 94c99edd
......@@ -59,19 +59,19 @@ always @(posedge SysClk) begin
end
end
spimem spiMemTx (
.clka(SysClk), // input clka
.ena(1'b1), // input ena
.wea(initMem), // input [0 : 0] wea
.addra(initMemAddr), // input [9 : 0] addra
.dina(initMemData), // input [31 : 0] dina
.douta(douta_dummy), // output [31 : 0] douta
.clkb(spi_clk), // input clkb
.enb(1'b1), // input enb
.web(1'b0), // input [0 : 0] web
.addrb(spi_addr), // input [11 : 0] addrb
.dinb(8'h00), // input [7 : 0] dinb
.doutb(spi_data) // output [7 : 0] doutb
buffermem spiMemTx (
.clka(spi_clk), // input clkb
.ena(1'b1), // input enb
.wea(1'b0), // input [0 : 0] web
.addra(spi_addr), // input [11 : 0] addrb
.dina(8'h00), // input [7 : 0] dinb
.douta(spi_data), // output [7 : 0] doutb
.clkb(SysClk), // input clka
.enb(1'b1), // input ena
.web(initMem), // input [0 : 0] wea
.addrb(initMemAddr), // input [9 : 0] addra
.dinb(initMemData), // input [31 : 0] dina
.doutb(douta_dummy) // output [31 : 0] douta
);
wire spi_rcMem_we;
......@@ -79,18 +79,18 @@ wire [11:0] spi_rcMem_addr;
wire [ 7:0] spi_rcMem_data;
wire [ 7:0] debug_out;
wire [ 7:0] spi_rcMem_doutb_dummy;
spimem spiMemRc (
.clka(SysClk),
buffermem spiMemRc (
.clka(spi_clk),
.ena(1'b1),
.wea(1'b0),
.addra(10'h001),
.douta(rcMem_douta),
.clkb(spi_clk),
.wea(spi_rcMem_we),
.addra(spi_rcMem_addr),
.dina(spi_rcMem_data),
.douta(spi_rcMem_doutb_dummy),
.clkb(SysClk),
.enb(1'b1),
.web(spi_rcMem_we),
.addrb(spi_rcMem_addr),
.dinb(spi_rcMem_data),
.doutb(spi_rcMem_doutb_dummy)
.web(1'b0),
.addrb(10'h001),
.doutb(rcMem_douta)
);
spiifc mySpiIfc (
......@@ -108,8 +108,6 @@ spiifc mySpiIfc (
.debug_out(debug_out)
);
assign leds = rcMem_douta[31:24];
assign leds = /*rcMem_douta[31:24]*/ debug_out;
endmodule
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