Added DMAC to XPS system, use it in XSDK to test DMA support in Spiifc

projnav/xps/SDK/SDK_Export/hw/system_bd.bmm

@@ -22,37 +22,37 @@ ADDRESS_MAP microblaze_0 MICROBLAZE 100
     ADDRESS_SPACE lmb_bram_combined RAMB16 [0x00000000:0x0000FFFF]
         BUS_BLOCK
             lmb_bram/lmb_bram/ramb16bwer_0 [31:31] INPUT = lmb_bram_combined_0.mem PLACED = X2Y46;
-            lmb_bram/lmb_bram/ramb16bwer_1 [30:30] INPUT = lmb_bram_combined_1.mem PLACED = X2Y50;
-            lmb_bram/lmb_bram/ramb16bwer_2 [29:29] INPUT = lmb_bram_combined_2.mem PLACED = X3Y46;
-            lmb_bram/lmb_bram/ramb16bwer_3 [28:28] INPUT = lmb_bram_combined_3.mem PLACED = X1Y40;
-            lmb_bram/lmb_bram/ramb16bwer_4 [27:27] INPUT = lmb_bram_combined_4.mem PLACED = X2Y48;
-            lmb_bram/lmb_bram/ramb16bwer_5 [26:26] INPUT = lmb_bram_combined_5.mem PLACED = X3Y44;
-            lmb_bram/lmb_bram/ramb16bwer_6 [25:25] INPUT = lmb_bram_combined_6.mem PLACED = X2Y44;
-            lmb_bram/lmb_bram/ramb16bwer_7 [24:24] INPUT = lmb_bram_combined_7.mem PLACED = X3Y42;
-            lmb_bram/lmb_bram/ramb16bwer_8 [23:23] INPUT = lmb_bram_combined_8.mem PLACED = X2Y36;
-            lmb_bram/lmb_bram/ramb16bwer_9 [22:22] INPUT = lmb_bram_combined_9.mem PLACED = X1Y34;
-            lmb_bram/lmb_bram/ramb16bwer_10 [21:21] INPUT = lmb_bram_combined_10.mem PLACED = X1Y32;
-            lmb_bram/lmb_bram/ramb16bwer_11 [20:20] INPUT = lmb_bram_combined_11.mem PLACED = X1Y36;
+            lmb_bram/lmb_bram/ramb16bwer_1 [30:30] INPUT = lmb_bram_combined_1.mem PLACED = X2Y44;
+            lmb_bram/lmb_bram/ramb16bwer_2 [29:29] INPUT = lmb_bram_combined_2.mem PLACED = X2Y42;
+            lmb_bram/lmb_bram/ramb16bwer_3 [28:28] INPUT = lmb_bram_combined_3.mem PLACED = X3Y42;
+            lmb_bram/lmb_bram/ramb16bwer_4 [27:27] INPUT = lmb_bram_combined_4.mem PLACED = X2Y40;
+            lmb_bram/lmb_bram/ramb16bwer_5 [26:26] INPUT = lmb_bram_combined_5.mem PLACED = X2Y38;
+            lmb_bram/lmb_bram/ramb16bwer_6 [25:25] INPUT = lmb_bram_combined_6.mem PLACED = X2Y32;
+            lmb_bram/lmb_bram/ramb16bwer_7 [24:24] INPUT = lmb_bram_combined_7.mem PLACED = X3Y40;
+            lmb_bram/lmb_bram/ramb16bwer_8 [23:23] INPUT = lmb_bram_combined_8.mem PLACED = X3Y38;
+            lmb_bram/lmb_bram/ramb16bwer_9 [22:22] INPUT = lmb_bram_combined_9.mem PLACED = X3Y36;
+            lmb_bram/lmb_bram/ramb16bwer_10 [21:21] INPUT = lmb_bram_combined_10.mem PLACED = X2Y36;
+            lmb_bram/lmb_bram/ramb16bwer_11 [20:20] INPUT = lmb_bram_combined_11.mem PLACED = X2Y34;
             lmb_bram/lmb_bram/ramb16bwer_12 [19:19] INPUT = lmb_bram_combined_12.mem PLACED = X1Y30;
-            lmb_bram/lmb_bram/ramb16bwer_13 [18:18] INPUT = lmb_bram_combined_13.mem PLACED = X2Y30;
-            lmb_bram/lmb_bram/ramb16bwer_14 [17:17] INPUT = lmb_bram_combined_14.mem PLACED = X2Y28;
-            lmb_bram/lmb_bram/ramb16bwer_15 [16:16] INPUT = lmb_bram_combined_15.mem PLACED = X1Y28;
-            lmb_bram/lmb_bram/ramb16bwer_16 [15:15] INPUT = lmb_bram_combined_16.mem PLACED = X3Y28;
-            lmb_bram/lmb_bram/ramb16bwer_17 [14:14] INPUT = lmb_bram_combined_17.mem PLACED = X2Y32;
-            lmb_bram/lmb_bram/ramb16bwer_18 [13:13] INPUT = lmb_bram_combined_18.mem PLACED = X1Y38;
-            lmb_bram/lmb_bram/ramb16bwer_19 [12:12] INPUT = lmb_bram_combined_19.mem PLACED = X2Y34;
-            lmb_bram/lmb_bram/ramb16bwer_20 [11:11] INPUT = lmb_bram_combined_20.mem PLACED = X2Y26;
-            lmb_bram/lmb_bram/ramb16bwer_21 [10:10] INPUT = lmb_bram_combined_21.mem PLACED = X3Y30;
-            lmb_bram/lmb_bram/ramb16bwer_22 [9:9] INPUT = lmb_bram_combined_22.mem PLACED = X3Y26;
-            lmb_bram/lmb_bram/ramb16bwer_23 [8:8] INPUT = lmb_bram_combined_23.mem PLACED = X2Y24;
-            lmb_bram/lmb_bram/ramb16bwer_24 [7:7] INPUT = lmb_bram_combined_24.mem PLACED = X3Y34;
-            lmb_bram/lmb_bram/ramb16bwer_25 [6:6] INPUT = lmb_bram_combined_25.mem PLACED = X3Y40;
-            lmb_bram/lmb_bram/ramb16bwer_26 [5:5] INPUT = lmb_bram_combined_26.mem PLACED = X2Y42;
-            lmb_bram/lmb_bram/ramb16bwer_27 [4:4] INPUT = lmb_bram_combined_27.mem PLACED = X3Y38;
-            lmb_bram/lmb_bram/ramb16bwer_28 [3:3] INPUT = lmb_bram_combined_28.mem PLACED = X3Y36;
-            lmb_bram/lmb_bram/ramb16bwer_29 [2:2] INPUT = lmb_bram_combined_29.mem PLACED = X2Y40;
-            lmb_bram/lmb_bram/ramb16bwer_30 [1:1] INPUT = lmb_bram_combined_30.mem PLACED = X3Y32;
-            lmb_bram/lmb_bram/ramb16bwer_31 [0:0] INPUT = lmb_bram_combined_31.mem PLACED = X2Y38;
+            lmb_bram/lmb_bram/ramb16bwer_13 [18:18] INPUT = lmb_bram_combined_13.mem PLACED = X3Y24;
+            lmb_bram/lmb_bram/ramb16bwer_14 [17:17] INPUT = lmb_bram_combined_14.mem PLACED = X2Y26;
+            lmb_bram/lmb_bram/ramb16bwer_15 [16:16] INPUT = lmb_bram_combined_15.mem PLACED = X1Y26;
+            lmb_bram/lmb_bram/ramb16bwer_16 [15:15] INPUT = lmb_bram_combined_16.mem PLACED = X3Y32;
+            lmb_bram/lmb_bram/ramb16bwer_17 [14:14] INPUT = lmb_bram_combined_17.mem PLACED = X1Y32;
+            lmb_bram/lmb_bram/ramb16bwer_18 [13:13] INPUT = lmb_bram_combined_18.mem PLACED = X1Y28;
+            lmb_bram/lmb_bram/ramb16bwer_19 [12:12] INPUT = lmb_bram_combined_19.mem PLACED = X3Y34;
+            lmb_bram/lmb_bram/ramb16bwer_20 [11:11] INPUT = lmb_bram_combined_20.mem PLACED = X2Y24;
+            lmb_bram/lmb_bram/ramb16bwer_21 [10:10] INPUT = lmb_bram_combined_21.mem PLACED = X2Y18;
+            lmb_bram/lmb_bram/ramb16bwer_22 [9:9] INPUT = lmb_bram_combined_22.mem PLACED = X2Y20;
+            lmb_bram/lmb_bram/ramb16bwer_23 [8:8] INPUT = lmb_bram_combined_23.mem PLACED = X2Y22;
+            lmb_bram/lmb_bram/ramb16bwer_24 [7:7] INPUT = lmb_bram_combined_24.mem PLACED = X3Y26;
+            lmb_bram/lmb_bram/ramb16bwer_25 [6:6] INPUT = lmb_bram_combined_25.mem PLACED = X3Y30;
+            lmb_bram/lmb_bram/ramb16bwer_26 [5:5] INPUT = lmb_bram_combined_26.mem PLACED = X2Y28;
+            lmb_bram/lmb_bram/ramb16bwer_27 [4:4] INPUT = lmb_bram_combined_27.mem PLACED = X3Y28;
+            lmb_bram/lmb_bram/ramb16bwer_28 [3:3] INPUT = lmb_bram_combined_28.mem PLACED = X3Y22;
+            lmb_bram/lmb_bram/ramb16bwer_29 [2:2] INPUT = lmb_bram_combined_29.mem PLACED = X2Y30;
+            lmb_bram/lmb_bram/ramb16bwer_30 [1:1] INPUT = lmb_bram_combined_30.mem PLACED = X2Y14;
+            lmb_bram/lmb_bram/ramb16bwer_31 [0:0] INPUT = lmb_bram_combined_31.mem PLACED = X2Y16;
         END_BUS_BLOCK;
     END_ADDRESS_SPACE;
 

projnav/xps/SDK/SDK_Workspace/demo/src/main.cc

@@ -3,46 +3,172 @@
  */
 
 #include <stdio.h>
+
 #include "xil_types.h"
+#include "xparameters.h"
+#include "xdmacentral.h"
+
+#define DMA_DEVICE_ID			XPAR_DMACENTRAL_0_DEVICE_ID
+
+#define DMA_BUFFER_BYTE_SIZE	4096
+
+static XDmaCentral Dma;
 
 u32 * pSpiifcBase = (u32 *)0x85000000;
-u32 * pMosiBase = (u32 *)0x85010000;
-u32 * pMisoBase = (u32 *)0x85011000;
+u32 * pMosiBase   = (u32 *)0x85010000;
+u32 * pMisoBase   = (u32 *)0x85011000;
+
+//
+// Initializes DMA controller
+//
+int InitDma();
+
+//
+// Copies a block of data between two burst-mode enabled memory regions. Uses
+// XPS Central DMA controller. Function spins while waiting for copy to complete.
+//
+int DmaCopy(void * pSrc, void * pDest, size_t byteCount);
+
+//
+// Writes to the three memmap regions in the Spiifc peripheral
+// (regs, mosi/miso buffers). Verifies the writes stuck using a read.
+//
+void SpiifcPioTest();
+
+//
+// DMA copies from mosi to miso buffers and verifies result using PIO.
+//
+void SpiifcDmaTest();
+
+//
+// InitDma - Initializes DMA controller
+//
+int InitDma()
+{
+	XDmaCentral_Config *pDmaCfg;
+	int status;
+
+	// Configure DMA controller
+	pDmaCfg = XDmaCentral_LookupConfig(DMA_DEVICE_ID);
+	if (NULL == pDmaCfg) { return XST_FAILURE; }
+	status = XDmaCentral_CfgInitialize(&Dma, pDmaCfg, pDmaCfg->BaseAddress);
+	if (XST_SUCCESS != status) { return status; }
+
+	// Reset DMAC
+	XDmaCentral_Reset(&Dma);
+
+	// Setup DMAC control register to increment src & dest addr
+	XDmaCentral_SetControl(
+			&Dma,
+			XDMC_DMACR_SOURCE_INCR_MASK | XDMC_DMACR_DEST_INCR_MASK);
+
+	// DMAC does not raise interrupts (when transfer completes)
+	XDmaCentral_InterruptEnableSet(&Dma, 0);
+
+	return XST_SUCCESS;
+}
+
+int DmaCopy(void * pSrc, void * pDest, size_t byteCount)
+{
+	u32 regValue;
+	XDmaCentral_Transfer(&Dma, pSrc, pDest, byteCount);
+	do {	// Wait for DMA transfer to complete
+		regValue = XDmaCentral_GetStatus(&Dma);
+	} while ((regValue & XDMC_DMASR_BUSY_MASK) == XDMC_DMASR_BUSY_MASK);
+	if (regValue & XDMC_DMASR_BUS_ERROR_MASK) {
+		xil_printf("DMA_BUS_ERROR\n");
+		return XST_FAILURE;
+	}
+
+	return XST_SUCCESS;
+}
 
 int main()
 {
-	xil_printf("Reg0 @ 0x%08X\n", pSpiifcBase);
-	xil_printf("Saving word to Reg0... ");
-	*pSpiifcBase = 0x87654321;
-	xil_printf("done... verifying... ");
+	int status;
+
+	// Initialize system
+	if (XST_SUCCESS != (status = InitDma())) {
+		xil_printf("[FAIL] InitDma() failed. Exiting.\n");
+		return status;
+	}
+
+	// Perform Programmed IO tests
+	SpiifcPioTest();
+
+	// Test DMA
+	SpiifcDmaTest();
+
+}
+
+void SpiifcPioTest()
+{
+	xil_printf("Testing Spiifc PIO...\n");
+
+	// PIO Write to Spiifc memmap regions
+	pSpiifcBase[0] = 0x87654321;
+    pMosiBase[0] = 0x12345678;
+    pMisoBase[0] = 0xFEEDFACE;
+    pMisoBase[1] = 0xBEEFBABE;
+    pMisoBase[2] = 0xBEEFBEEF;
+
+	xil_printf("Reg0 @ 0x%08X: verifying PIO... ", pSpiifcBase);
 	if (0x87654321 == *pSpiifcBase) {
-		xil_printf("PASS.\n");
+		xil_printf("[PASS]\n");
 	} else {
-		xil_printf("FAIL. (actual=0x%08X)\n", *pSpiifcBase);
+		xil_printf("[FAIL] (actual=0x%08X)\n", *pSpiifcBase);
 	}
-	xil_printf("\n");
 
-	xil_printf("MOSI @ 0x%08X\n", pMosiBase);
-	xil_printf("Saving word to Mem0 (MOSI)...");
-    *pMosiBase = 0x12345678;
-    xil_printf("done... verifying... ");
+	xil_printf("MOSI @ 0x%08X: verifying PIO... ", pMosiBase);
     if (0x12345678 == *pMosiBase) {
-    	xil_printf("PASS.\n");
+    	xil_printf("[PASS]\n");
     } else {
-    	xil_printf("FAIL. (actual=0x%08X)\n", *pMosiBase);
+    	xil_printf("[FAIL] (actual=0x%08X)\n", *pMosiBase);
     }
-    xil_printf("\n");
 
-    xil_printf("MISO @ 0x%08X\n", pMisoBase);
-    xil_printf("Saving word to Mem1 (MISO)... ");
-    *pMisoBase = 0xFEEDFACE;
-    xil_printf("done... verifying... ");
+    xil_printf("MISO @ 0x%08X: verifying PIO... ", pMisoBase);
     if (0xFEEDFACE == *pMisoBase) {
-    	xil_printf("PASS.\n");
+    	xil_printf("[PASS]\n");
     } else {
-    	xil_printf("FAIL. (actual=0x%08X)\n", *pMosiBase);
+    	xil_printf("[FAIL] (actual=0x%08X)\n", *pMisoBase);
     }
     xil_printf("\n");
+}
+
+void SpiifcDmaTest()
+{
+	int status;
+	u32 i;
+
+	// Pattern DMA memory buffer
+	for(i = 0; i < DMA_BUFFER_BYTE_SIZE/4; i++) {
+		pMosiBase[i] = ((i*4)   & 0xFF) << 24 |
+				       ((i*4+1) & 0xFF) << 16 |
+				       ((i*4+2) & 0xFF) << 8  |
+				       ((i*4+3) & 0xFF);
+	}
+
+	// DMA buffer to Spiifc.MISO buffer
+	if (XST_SUCCESS != (status =
+			DmaCopy(pMosiBase, pMisoBase, DMA_BUFFER_BYTE_SIZE))) {
+		xil_printf("[FAIL] DmaCopy() failed. Exiting.\n");
+	}
 
-	return 0;
+	// Check DMAC copied Spiifc.MOSI --> Spiifc.MISO buffer
+	u32 expectedDmaWord = 0;
+	int failWords = 0;
+	for (i = 0; i < (DMA_BUFFER_BYTE_SIZE/4); i++) {
+		expectedDmaWord = ((i*4+0) & 0xFF) << 24 |
+				          ((i*4+1) & 0xFF) << 16 |
+				          ((i*4+2) & 0xFF) << 8  |
+				          ((i*4+3) & 0xFF) << 0;
+		if (pMisoBase[i] != expectedDmaWord) {
+			xil_printf(
+					"[FAIL] DMA mem word [i]: expected=0x%08X, actual=0x%08X\n",
+					expectedDmaWord, pMisoBase);
+		}
+	}
+	if (0 == failWords) {
+		xil_printf("[PASS] DMA transfer from MOSI to MISO memory\n");
+	}
 }

projnav/xps/SDK/SDK_Workspace/demobsp/system.mss

@@ -60,4 +60,10 @@ BEGIN DRIVER
  PARAMETER HW_INSTANCE = spiifc_0
 END
 
+BEGIN DRIVER
+ PARAMETER DRIVER_NAME = dmacentral
+ PARAMETER DRIVER_VER = 2.00.a
+ PARAMETER HW_INSTANCE = xps_central_dma_0
+END
+
 

projnav/xps/SDK/SDK_Workspace/xps_hw_platform/system_bd.bmm

@@ -22,37 +22,37 @@ ADDRESS_MAP microblaze_0 MICROBLAZE 100
     ADDRESS_SPACE lmb_bram_combined RAMB16 [0x00000000:0x0000FFFF]
         BUS_BLOCK
             lmb_bram/lmb_bram/ramb16bwer_0 [31:31] INPUT = lmb_bram_combined_0.mem PLACED = X2Y46;
-            lmb_bram/lmb_bram/ramb16bwer_1 [30:30] INPUT = lmb_bram_combined_1.mem PLACED = X2Y50;
-            lmb_bram/lmb_bram/ramb16bwer_2 [29:29] INPUT = lmb_bram_combined_2.mem PLACED = X3Y46;
-            lmb_bram/lmb_bram/ramb16bwer_3 [28:28] INPUT = lmb_bram_combined_3.mem PLACED = X1Y40;
-            lmb_bram/lmb_bram/ramb16bwer_4 [27:27] INPUT = lmb_bram_combined_4.mem PLACED = X2Y48;
-            lmb_bram/lmb_bram/ramb16bwer_5 [26:26] INPUT = lmb_bram_combined_5.mem PLACED = X3Y44;
-            lmb_bram/lmb_bram/ramb16bwer_6 [25:25] INPUT = lmb_bram_combined_6.mem PLACED = X2Y44;
-            lmb_bram/lmb_bram/ramb16bwer_7 [24:24] INPUT = lmb_bram_combined_7.mem PLACED = X3Y42;
-            lmb_bram/lmb_bram/ramb16bwer_8 [23:23] INPUT = lmb_bram_combined_8.mem PLACED = X2Y36;
-            lmb_bram/lmb_bram/ramb16bwer_9 [22:22] INPUT = lmb_bram_combined_9.mem PLACED = X1Y34;
-            lmb_bram/lmb_bram/ramb16bwer_10 [21:21] INPUT = lmb_bram_combined_10.mem PLACED = X1Y32;
-            lmb_bram/lmb_bram/ramb16bwer_11 [20:20] INPUT = lmb_bram_combined_11.mem PLACED = X1Y36;
+            lmb_bram/lmb_bram/ramb16bwer_1 [30:30] INPUT = lmb_bram_combined_1.mem PLACED = X2Y44;
+            lmb_bram/lmb_bram/ramb16bwer_2 [29:29] INPUT = lmb_bram_combined_2.mem PLACED = X2Y42;
+            lmb_bram/lmb_bram/ramb16bwer_3 [28:28] INPUT = lmb_bram_combined_3.mem PLACED = X3Y42;
+            lmb_bram/lmb_bram/ramb16bwer_4 [27:27] INPUT = lmb_bram_combined_4.mem PLACED = X2Y40;
+            lmb_bram/lmb_bram/ramb16bwer_5 [26:26] INPUT = lmb_bram_combined_5.mem PLACED = X2Y38;
+            lmb_bram/lmb_bram/ramb16bwer_6 [25:25] INPUT = lmb_bram_combined_6.mem PLACED = X2Y32;
+            lmb_bram/lmb_bram/ramb16bwer_7 [24:24] INPUT = lmb_bram_combined_7.mem PLACED = X3Y40;
+            lmb_bram/lmb_bram/ramb16bwer_8 [23:23] INPUT = lmb_bram_combined_8.mem PLACED = X3Y38;
+            lmb_bram/lmb_bram/ramb16bwer_9 [22:22] INPUT = lmb_bram_combined_9.mem PLACED = X3Y36;
+            lmb_bram/lmb_bram/ramb16bwer_10 [21:21] INPUT = lmb_bram_combined_10.mem PLACED = X2Y36;
+            lmb_bram/lmb_bram/ramb16bwer_11 [20:20] INPUT = lmb_bram_combined_11.mem PLACED = X2Y34;
             lmb_bram/lmb_bram/ramb16bwer_12 [19:19] INPUT = lmb_bram_combined_12.mem PLACED = X1Y30;
-            lmb_bram/lmb_bram/ramb16bwer_13 [18:18] INPUT = lmb_bram_combined_13.mem PLACED = X2Y30;
-            lmb_bram/lmb_bram/ramb16bwer_14 [17:17] INPUT = lmb_bram_combined_14.mem PLACED = X2Y28;
-            lmb_bram/lmb_bram/ramb16bwer_15 [16:16] INPUT = lmb_bram_combined_15.mem PLACED = X1Y28;
-            lmb_bram/lmb_bram/ramb16bwer_16 [15:15] INPUT = lmb_bram_combined_16.mem PLACED = X3Y28;
-            lmb_bram/lmb_bram/ramb16bwer_17 [14:14] INPUT = lmb_bram_combined_17.mem PLACED = X2Y32;
-            lmb_bram/lmb_bram/ramb16bwer_18 [13:13] INPUT = lmb_bram_combined_18.mem PLACED = X1Y38;
-            lmb_bram/lmb_bram/ramb16bwer_19 [12:12] INPUT = lmb_bram_combined_19.mem PLACED = X2Y34;
-            lmb_bram/lmb_bram/ramb16bwer_20 [11:11] INPUT = lmb_bram_combined_20.mem PLACED = X2Y26;
-            lmb_bram/lmb_bram/ramb16bwer_21 [10:10] INPUT = lmb_bram_combined_21.mem PLACED = X3Y30;
-            lmb_bram/lmb_bram/ramb16bwer_22 [9:9] INPUT = lmb_bram_combined_22.mem PLACED = X3Y26;
-            lmb_bram/lmb_bram/ramb16bwer_23 [8:8] INPUT = lmb_bram_combined_23.mem PLACED = X2Y24;
-            lmb_bram/lmb_bram/ramb16bwer_24 [7:7] INPUT = lmb_bram_combined_24.mem PLACED = X3Y34;
-            lmb_bram/lmb_bram/ramb16bwer_25 [6:6] INPUT = lmb_bram_combined_25.mem PLACED = X3Y40;
-            lmb_bram/lmb_bram/ramb16bwer_26 [5:5] INPUT = lmb_bram_combined_26.mem PLACED = X2Y42;
-            lmb_bram/lmb_bram/ramb16bwer_27 [4:4] INPUT = lmb_bram_combined_27.mem PLACED = X3Y38;
-            lmb_bram/lmb_bram/ramb16bwer_28 [3:3] INPUT = lmb_bram_combined_28.mem PLACED = X3Y36;
-            lmb_bram/lmb_bram/ramb16bwer_29 [2:2] INPUT = lmb_bram_combined_29.mem PLACED = X2Y40;
-            lmb_bram/lmb_bram/ramb16bwer_30 [1:1] INPUT = lmb_bram_combined_30.mem PLACED = X3Y32;
-            lmb_bram/lmb_bram/ramb16bwer_31 [0:0] INPUT = lmb_bram_combined_31.mem PLACED = X2Y38;
+            lmb_bram/lmb_bram/ramb16bwer_13 [18:18] INPUT = lmb_bram_combined_13.mem PLACED = X3Y24;
+            lmb_bram/lmb_bram/ramb16bwer_14 [17:17] INPUT = lmb_bram_combined_14.mem PLACED = X2Y26;
+            lmb_bram/lmb_bram/ramb16bwer_15 [16:16] INPUT = lmb_bram_combined_15.mem PLACED = X1Y26;
+            lmb_bram/lmb_bram/ramb16bwer_16 [15:15] INPUT = lmb_bram_combined_16.mem PLACED = X3Y32;
+            lmb_bram/lmb_bram/ramb16bwer_17 [14:14] INPUT = lmb_bram_combined_17.mem PLACED = X1Y32;
+            lmb_bram/lmb_bram/ramb16bwer_18 [13:13] INPUT = lmb_bram_combined_18.mem PLACED = X1Y28;
+            lmb_bram/lmb_bram/ramb16bwer_19 [12:12] INPUT = lmb_bram_combined_19.mem PLACED = X3Y34;
+            lmb_bram/lmb_bram/ramb16bwer_20 [11:11] INPUT = lmb_bram_combined_20.mem PLACED = X2Y24;
+            lmb_bram/lmb_bram/ramb16bwer_21 [10:10] INPUT = lmb_bram_combined_21.mem PLACED = X2Y18;
+            lmb_bram/lmb_bram/ramb16bwer_22 [9:9] INPUT = lmb_bram_combined_22.mem PLACED = X2Y20;
+            lmb_bram/lmb_bram/ramb16bwer_23 [8:8] INPUT = lmb_bram_combined_23.mem PLACED = X2Y22;
+            lmb_bram/lmb_bram/ramb16bwer_24 [7:7] INPUT = lmb_bram_combined_24.mem PLACED = X3Y26;
+            lmb_bram/lmb_bram/ramb16bwer_25 [6:6] INPUT = lmb_bram_combined_25.mem PLACED = X3Y30;
+            lmb_bram/lmb_bram/ramb16bwer_26 [5:5] INPUT = lmb_bram_combined_26.mem PLACED = X2Y28;
+            lmb_bram/lmb_bram/ramb16bwer_27 [4:4] INPUT = lmb_bram_combined_27.mem PLACED = X3Y28;
+            lmb_bram/lmb_bram/ramb16bwer_28 [3:3] INPUT = lmb_bram_combined_28.mem PLACED = X3Y22;
+            lmb_bram/lmb_bram/ramb16bwer_29 [2:2] INPUT = lmb_bram_combined_29.mem PLACED = X2Y30;
+            lmb_bram/lmb_bram/ramb16bwer_30 [1:1] INPUT = lmb_bram_combined_30.mem PLACED = X2Y14;
+            lmb_bram/lmb_bram/ramb16bwer_31 [0:0] INPUT = lmb_bram_combined_31.mem PLACED = X2Y16;
         END_BUS_BLOCK;
     END_ADDRESS_SPACE;
 

projnav/xps/__xps/ise/system.xreport

 <?xml version='1.0' encoding='UTF-8'?>
 <report-views version="2.0" >
  <header>
-  <DateModified>2012-02-28T19:36:43</DateModified>
+  <DateModified>2012-03-01T09:28:38</DateModified>
   <ModuleName>system</ModuleName>
-  <SummaryTimeStamp>2012-02-28T19:36:42</SummaryTimeStamp>
+  <SummaryTimeStamp>2012-03-01T09:28:36</SummaryTimeStamp>
   <SavedFilePath>C:/Users/mjlyons/workspace/vSPI/projnav/xps/__xps/ise/system.xreport</SavedFilePath>
   <FilterFile>filter.filter</FilterFile>
   <SavedFilterFilePath>C:/Users/mjlyons/workspace/vSPI/projnav/xps/__xps/ise</SavedFilterFilePath>

projnav/xps/etc/system.filters

@@ -98,7 +98,7 @@
 
   <SET CLASS="PROJECT" VIEW_ID="PORT">
     <HEADERS HSCROLL="0" VSCROLL="0">
-      <VARIABLE COL_INDEX="0" COL_WIDTH="376" IS_VISIBLE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="HEADER"/>
+      <VARIABLE COL_INDEX="0" COL_WIDTH="485" IS_VISIBLE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="HEADER"/>
     </HEADERS>
     <SET CLASS="FILTER_GROUP" ID="By Interface" IS_EXPANDED="TRUE">
       <VARIABLE NAME="By Interface" VALUE="By Interface" VIEWDISP="Port Filters" VIEWTYPE="STATIC"/>

projnav/xps/etc/system.gui

@@ -15,6 +15,7 @@
     </HEADERS>
     <SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="180,450,180" VERSION="0"/>
     <SET ID="spiifc_0" IS_EXPANDED="TRUE"/>
+    <SET ID="xps_central_dma_0" IS_EXPANDED="TRUE"/>
     <STATUS>
       <SELECTIONS/>
     </STATUS>
@@ -26,13 +27,14 @@
       <VARIABLE ID="dlmb_cntlr" ROW_INDEX="5"/>
       <VARIABLE ID="ilmb_cntlr" ROW_INDEX="6"/>
       <VARIABLE ID="lmb_bram" ROW_INDEX="4"/>
-      <VARIABLE ID="DIP_Switches_8Bits" ROW_INDEX="9"/>
-      <VARIABLE ID="LEDs_8Bits" ROW_INDEX="10"/>
-      <VARIABLE ID="Push_Buttons_5Bits" ROW_INDEX="11"/>
-      <VARIABLE ID="clock_generator_0" ROW_INDEX="12"/>
+      <VARIABLE ID="DIP_Switches_8Bits" ROW_INDEX="10"/>
+      <VARIABLE ID="LEDs_8Bits" ROW_INDEX="11"/>
+      <VARIABLE ID="Push_Buttons_5Bits" ROW_INDEX="12"/>
+      <VARIABLE ID="clock_generator_0" ROW_INDEX="13"/>
       <VARIABLE ID="mdm_0" ROW_INDEX="8"/>
-      <VARIABLE ID="proc_sys_reset_0" ROW_INDEX="13"/>
+      <VARIABLE ID="proc_sys_reset_0" ROW_INDEX="14"/>
       <VARIABLE ID="spiifc_0" IS_EXPANDED="TRUE" ROW_INDEX="7"/>
+      <VARIABLE ID="xps_central_dma_0" IS_EXPANDED="TRUE" ROW_INDEX="9"/>
     </SEQUENCES>
   </SET>
 
@@ -93,6 +95,7 @@
     </HEADERS>
     <SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="0,630,180" VERSION="0"/>
     <SET ID="spiifc_0" IS_EXPANDED="TRUE"/>
+    <SET ID="xps_central_dma_0" IS_EXPANDED="TRUE"/>
     <STATUS>
       <SELECTIONS/>
     </STATUS>
@@ -105,13 +108,14 @@
       <VARIABLE ID="dlmb_cntlr" ROW_INDEX="6"/>
       <VARIABLE ID="ilmb_cntlr" ROW_INDEX="7"/>
       <VARIABLE ID="lmb_bram" ROW_INDEX="5"/>
-      <VARIABLE ID="DIP_Switches_8Bits" ROW_INDEX="10"/>
-      <VARIABLE ID="LEDs_8Bits" ROW_INDEX="11"/>
-      <VARIABLE ID="Push_Buttons_5Bits" ROW_INDEX="12"/>
-      <VARIABLE ID="clock_generator_0" ROW_INDEX="13"/>
+      <VARIABLE ID="DIP_Switches_8Bits" ROW_INDEX="11"/>
+      <VARIABLE ID="LEDs_8Bits" ROW_INDEX="12"/>
+      <VARIABLE ID="Push_Buttons_5Bits" ROW_INDEX="13"/>
+      <VARIABLE ID="clock_generator_0" ROW_INDEX="14"/>
       <VARIABLE ID="mdm_0" ROW_INDEX="9"/>
-      <VARIABLE ID="proc_sys_reset_0" ROW_INDEX="14"/>
+      <VARIABLE ID="proc_sys_reset_0" ROW_INDEX="15"/>
       <VARIABLE ID="spiifc_0" IS_EXPANDED="TRUE" ROW_INDEX="8"/>
+      <VARIABLE ID="xps_central_dma_0" IS_EXPANDED="TRUE" ROW_INDEX="10"/>
     </SEQUENCES>
   </SET>
 

projnav/xps/implementation/system_summary.html

@@ -31,7 +31,7 @@
 <TR ALIGN=LEFT><TD>Platgen Log File</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
 <TR ALIGN=LEFT><TD>Simgen Log File</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
 <TR ALIGN=LEFT><TD>BitInit Log File</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/mjlyons/workspace/vSPI/projnav/xps\system.log'>System Log File</A></TD><TD>Tue Feb 28 19:37:57 2012</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/mjlyons/workspace/vSPI/projnav/xps\system.log'>System Log File</A></TD><TD>Thu Mar 1 09:29:13 2012</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
 </TABLE>
 
 
@@ -57,5 +57,5 @@
 </TABLE>
 
 
-<br><center><b>Date Generated:</b> 02/28/2012 - 19:37:57</center>
+<br><center><b>Date Generated:</b> 03/01/2012 - 09:29:13</center>
 </BODY></HTML>
\ No newline at end of file

projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/iseconfig/spiifc.projectmgr

@@ -7,16 +7,17 @@
    <ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" >
       <ClosedNodes>
          <ClosedNodesVersion>2</ClosedNodesVersion>
+         <ClosedNode>/spiifc - IMP C:|Users|mjlyons|workspace|vSPI|projnav|xps|pcores|spiifc_v1_00_a|hdl|vhdl|spiifc.vhd/PLBV46_SLAVE_BURST_I - plbv46_slave_burst - implementation</ClosedNode>
          <ClosedNode>/spiifc - IMP C:|Users|mjlyons|workspace|vSPI|projnav|xps|pcores|spiifc_v1_00_a|hdl|vhdl|spiifc.vhd/PLBV46_SLAVE_BURST_I - plbv46_slave_burst - implementation/I_SLAVE_ATTACHMENT - plb_slave_attachment - implementation</ClosedNode>
       </ClosedNodes>
       <SelectedItems>
-         <SelectedItem>spiifc - IMP (C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/hdl/vhdl/spiifc.vhd)</SelectedItem>
+         <SelectedItem>USER_LOGIC_I - user_logic (C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/hdl/verilog/user_logic.v)</SelectedItem>
       </SelectedItems>
       <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
       <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
-      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000258000000020000000000000000000000000200000064ffffffff000000810000000300000002000002580000000100000003000000000000000100000003</ViewHeaderState>
+      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000225000000020000000000000000000000000200000064ffffffff000000810000000300000002000002250000000100000003000000000000000100000003</ViewHeaderState>
       <UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
-      <CurrentItem>spiifc - IMP (C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/hdl/vhdl/spiifc.vhd)</CurrentItem>
+      <CurrentItem>USER_LOGIC_I - user_logic (C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/hdl/verilog/user_logic.v)</CurrentItem>
    </ItemView>
    <ItemView engineview="SynthesisOnly" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
       <ClosedNodes>
@@ -86,7 +87,7 @@
       </SelectedItems>
       <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
       <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
-      <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000e7000000010000000100000000000000000000000064ffffffff000000810000000000000001000000e70000000100000000</ViewHeaderState>
+      <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f8000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000</ViewHeaderState>
       <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
       <CurrentItem></CurrentItem>
    </ItemView>

projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/iseconfig/spiifc.xreport

 <?xml version='1.0' encoding='UTF-8'?>
 <report-views version="2.0" >
  <header>
-  <DateModified>2012-02-28T19:36:06</DateModified>
+  <DateModified>2012-03-01T09:27:04</DateModified>
   <ModuleName>spiifc</ModuleName>
-  <SummaryTimeStamp>2012-02-28T16:04:44</SummaryTimeStamp>
+  <SummaryTimeStamp>2012-02-29T17:29:17</SummaryTimeStamp>
   <SavedFilePath>C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/iseconfig/spiifc.xreport</SavedFilePath>
   <ImplementationReportsDirectory>C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav\</ImplementationReportsDirectory>
-  <DateInitialized>2012-02-28T19:36:05</DateInitialized>
+  <DateInitialized>2012-02-29T17:30:10</DateInitialized>
   <EnableMessageFiltering>false</EnableMessageFiltering>
  </header>
  <body>

projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc.gise

@@ -23,6 +23,11 @@
 
   <files xmlns="http://www.xilinx.com/XMLSchema"/>
 
-  <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+  <transforms xmlns="http://www.xilinx.com/XMLSchema">
+    <transform xil_pn:name="TRAN_SubProjectAbstractToPreProxy">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+  </transforms>
 
 </generated_project>

projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc.xise

@@ -17,100 +17,100 @@
   <files>
     <file xil_pn:name="../../hdl/vhdl/spiifc.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="../../hdl/verilog/user_logic.v" xil_pn:type="FILE_VERILOG">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
     </file>
     <file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/proc_common_pkg.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
       <library xil_pn:name="proc_common_v3_00_a"/>
     </file>
     <file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ipif_pkg.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
       <library xil_pn:name="proc_common_v3_00_a"/>
     </file>
     <file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_muxcy.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
       <library xil_pn:name="proc_common_v3_00_a"/>
     </file>
     <file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_gate128.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
       <library xil_pn:name="proc_common_v3_00_a"/>
     </file>
     <file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/family_support.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
       <library xil_pn:name="proc_common_v3_00_a"/>
     </file>
     <file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
       <library xil_pn:name="proc_common_v3_00_a"/>
     </file>
     <file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter_f.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
       <library xil_pn:name="proc_common_v3_00_a"/>
     </file>
     <file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/flex_addr_cntr.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
       <library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
     </file>
     <file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/addr_reg_cntr_brst_flex.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
       <library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
     </file>
     <file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plb_address_decoder.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
       <library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
     </file>
     <file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/burst_support.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
       <library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
     </file>
     <file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/wr_buffer.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
       <library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
     </file>
     <file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/be_reset_gen.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
       <library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
     </file>
     <file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plb_slave_attachment.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
       <library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
     </file>
     <file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/data_mirror_128.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
       <library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
     </file>
     <file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plbv46_slave_burst.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
       <library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
     </file>
     <file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v2_01_a/hdl/vhdl/interrupt_control.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
       <library xil_pn:name="interrupt_control_v2_01_a"/>
     </file>
     <file xil_pn:name="ipcore_dir/buffermem.xco" xil_pn:type="FILE_COREGEN">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
     </file>
     <file xil_pn:name="ipcore_dir/buffermem.xise" xil_pn:type="FILE_COREGENISE">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>

projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc_summary.html

@@ -74,5 +74,5 @@
 </TABLE>
 
 
-<br><center><b>Date Generated:</b> 02/28/2012 - 19:36:06</center>
+<br><center><b>Date Generated:</b> 03/01/2012 - 09:27:04</center>
 </BODY></HTML>
\ No newline at end of file

projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/user_logic_summary.html

-<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
-<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
-<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
-<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
-<TD ALIGN=CENTER COLSPAN='4'><B>spiifc Project Status</B></TD></TR>
-<TR ALIGN=LEFT>
-<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
-<TD>spiifc.xise</TD>
-<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
-</TR>
-<TR ALIGN=LEFT>
-<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
-<TD>user_logic</TD>
-<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
-<TD>New</TD>
-</TR>
-<TR ALIGN=LEFT>
-<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
-<TD>xc6slx45-2csg324</TD>
-<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
-<TD>&nbsp;</TD>
-</TR>
-<TR ALIGN=LEFT>
-<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 13.2</TD>
-<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
-<TD>&nbsp;</TD>
-</TR>
-<TR ALIGN=LEFT>
-<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
-<TD>Balanced</TD>
-<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
-<TD>
-&nbsp;</TD>
-</TR>
-<TR ALIGN=LEFT>
-<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
-<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
-<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
-<TD>&nbsp;</TD>
-</TR>
-<TR ALIGN=LEFT>
-<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
-<TD>&nbsp;</TD>
-<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
-<TD>&nbsp;&nbsp;</TD>
-</TR>
-</TABLE>
-
-
-
-
-
-
-
-
-
-
-
-&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
-<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
-<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
-<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
-<TR ALIGN=LEFT><TD>Synthesis Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-</TABLE>
-&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
-<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
-<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
-</TABLE>
-
-
-<br><center><b>Date Generated:</b> 02/28/2012 - 19:35:55</center>
-</BODY></HTML>
\ No newline at end of file

projnav/xps/system.mhs

@@ -172,3 +172,12 @@ BEGIN spiifc
  BUS_INTERFACE SPLB = mb_plb
 END
 
+BEGIN xps_central_dma
+ PARAMETER INSTANCE = xps_central_dma_0
+ PARAMETER HW_VER = 2.03.a
+ PARAMETER C_BASEADDR = 0x86000000
+ PARAMETER C_HIGHADDR = 0x8600FFFF
+ BUS_INTERFACE MPLB = mb_plb
+ BUS_INTERFACE SPLB = mb_plb
+END
+

projnav/xps/system_incl.make

@@ -73,7 +73,8 @@ implementation/push_buttons_5bits_wrapper.ngc \
 implementation/clock_generator_0_wrapper.ngc \
 implementation/mdm_0_wrapper.ngc \
 implementation/proc_sys_reset_0_wrapper.ngc \
-implementation/spiifc_0_wrapper.ngc
+implementation/spiifc_0_wrapper.ngc \
+implementation/xps_central_dma_0_wrapper.ngc
 
 POSTSYN_NETLIST = implementation/$(SYSTEM).ngc