Skip to content

V
vSPI
Commit 94c99edd authored by Mike Lyons's avatar Mike Lyons
Browse files
Options

SPI adapter working, but occasionally buggy, in xps/xsdk

parent 928419df
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 3262 additions and 376 deletions
projnav/ucf/atlys/spiwrap.ucf 0 → 100644
View file @ 94c99edd
Net Reset LOC=N4 | IOSTANDARD=LVCMOS18;
Net SysClk LOC=L15 | IOSTANDARD=LVCMOS33;
# SPI Port
Net spi_miso LOC=U16 | IOSTANDARD=LVCMOS33;
Net spi_mosi LOC=U15 | IOSTANDARD=LVCMOS33;
Net spi_clk LOC=R10 | IOSTANDARD=LVCMOS33;
Net spi_ss LOC=M11 | IOSTANDARD=LVCMOS33;
# LEDs
Net leds<0> LOC=U18 | IOSTANDARD=LVCMOS33;
Net leds<1> LOC=M14 | IOSTANDARD=LVCMOS33;
Net leds<2> LOC=N14 | IOSTANDARD=LVCMOS33;
Net leds<3> LOC=L14 | IOSTANDARD=LVCMOS33;
Net leds<4> LOC=M13 | IOSTANDARD=LVCMOS33;
Net leds<5> LOC=D4 | IOSTANDARD=LVCMOS33;
Net leds<6> LOC=P16 | IOSTANDARD=LVCMOS33;
Net leds<7> LOC=N12 | IOSTANDARD=LVCMOS33;
projnav/xps/SDK/SDK_Export/hw/system.xml
View file @ 94c99edd
This diff is collapsed.
projnav/xps/SDK/SDK_Export/hw/system_bd.bmm
View file @ 94c99edd
......@@ -21,38 +21,38 @@ ADDRESS_MAP microblaze_0 MICROBLAZE 100
ADDRESS_SPACE lmb_bram_combined RAMB16 [0x00000000:0x0000FFFF]
BUS_BLOCK
lmb_bram/lmb_bram/ramb16bwer_0 [31:31] INPUT = lmb_bram_combined_0.mem PLACED = X2Y46;
lmb_bram/lmb_bram/ramb16bwer_1 [30:30] INPUT = lmb_bram_combined_1.mem PLACED = X2Y44;
lmb_bram/lmb_bram/ramb16bwer_2 [29:29] INPUT = lmb_bram_combined_2.mem PLACED = X2Y42;
lmb_bram/lmb_bram/ramb16bwer_3 [28:28] INPUT = lmb_bram_combined_3.mem PLACED = X3Y42;
lmb_bram/lmb_bram/ramb16bwer_4 [27:27] INPUT = lmb_bram_combined_4.mem PLACED = X2Y40;
lmb_bram/lmb_bram/ramb16bwer_5 [26:26] INPUT = lmb_bram_combined_5.mem PLACED = X2Y38;
lmb_bram/lmb_bram/ramb16bwer_6 [25:25] INPUT = lmb_bram_combined_6.mem PLACED = X2Y32;
lmb_bram/lmb_bram/ramb16bwer_7 [24:24] INPUT = lmb_bram_combined_7.mem PLACED = X3Y40;
lmb_bram/lmb_bram/ramb16bwer_8 [23:23] INPUT = lmb_bram_combined_8.mem PLACED = X3Y38;
lmb_bram/lmb_bram/ramb16bwer_9 [22:22] INPUT = lmb_bram_combined_9.mem PLACED = X3Y36;
lmb_bram/lmb_bram/ramb16bwer_10 [21:21] INPUT = lmb_bram_combined_10.mem PLACED = X2Y36;
lmb_bram/lmb_bram/ramb16bwer_11 [20:20] INPUT = lmb_bram_combined_11.mem PLACED = X2Y34;
lmb_bram/lmb_bram/ramb16bwer_12 [19:19] INPUT = lmb_bram_combined_12.mem PLACED = X1Y30;
lmb_bram/lmb_bram/ramb16bwer_13 [18:18] INPUT = lmb_bram_combined_13.mem PLACED = X3Y24;
lmb_bram/lmb_bram/ramb16bwer_14 [17:17] INPUT = lmb_bram_combined_14.mem PLACED = X2Y26;
lmb_bram/lmb_bram/ramb16bwer_15 [16:16] INPUT = lmb_bram_combined_15.mem PLACED = X1Y26;
lmb_bram/lmb_bram/ramb16bwer_16 [15:15] INPUT = lmb_bram_combined_16.mem PLACED = X3Y32;
lmb_bram/lmb_bram/ramb16bwer_17 [14:14] INPUT = lmb_bram_combined_17.mem PLACED = X1Y32;
lmb_bram/lmb_bram/ramb16bwer_18 [13:13] INPUT = lmb_bram_combined_18.mem PLACED = X1Y28;
lmb_bram/lmb_bram/ramb16bwer_19 [12:12] INPUT = lmb_bram_combined_19.mem PLACED = X3Y34;
lmb_bram/lmb_bram/ramb16bwer_20 [11:11] INPUT = lmb_bram_combined_20.mem PLACED = X2Y24;
lmb_bram/lmb_bram/ramb16bwer_21 [10:10] INPUT = lmb_bram_combined_21.mem PLACED = X2Y18;
lmb_bram/lmb_bram/ramb16bwer_22 [9:9] INPUT = lmb_bram_combined_22.mem PLACED = X2Y20;
lmb_bram/lmb_bram/ramb16bwer_23 [8:8] INPUT = lmb_bram_combined_23.mem PLACED = X2Y22;
lmb_bram/lmb_bram/ramb16bwer_24 [7:7] INPUT = lmb_bram_combined_24.mem PLACED = X3Y26;
lmb_bram/lmb_bram/ramb16bwer_25 [6:6] INPUT = lmb_bram_combined_25.mem PLACED = X3Y30;
lmb_bram/lmb_bram/ramb16bwer_26 [5:5] INPUT = lmb_bram_combined_26.mem PLACED = X2Y28;
lmb_bram/lmb_bram/ramb16bwer_27 [4:4] INPUT = lmb_bram_combined_27.mem PLACED = X3Y28;
lmb_bram/lmb_bram/ramb16bwer_28 [3:3] INPUT = lmb_bram_combined_28.mem PLACED = X3Y22;
lmb_bram/lmb_bram/ramb16bwer_29 [2:2] INPUT = lmb_bram_combined_29.mem PLACED = X2Y30;
lmb_bram/lmb_bram/ramb16bwer_30 [1:1] INPUT = lmb_bram_combined_30.mem PLACED = X2Y14;
lmb_bram/lmb_bram/ramb16bwer_31 [0:0] INPUT = lmb_bram_combined_31.mem PLACED = X2Y16;
lmb_bram/lmb_bram/ramb16bwer_0 [31:31] INPUT = lmb_bram_combined_0.mem PLACED = X2Y44;
lmb_bram/lmb_bram/ramb16bwer_1 [30:30] INPUT = lmb_bram_combined_1.mem PLACED = X3Y42;
lmb_bram/lmb_bram/ramb16bwer_2 [29:29] INPUT = lmb_bram_combined_2.mem PLACED = X2Y48;
lmb_bram/lmb_bram/ramb16bwer_3 [28:28] INPUT = lmb_bram_combined_3.mem PLACED = X2Y40;
lmb_bram/lmb_bram/ramb16bwer_4 [27:27] INPUT = lmb_bram_combined_4.mem PLACED = X3Y40;
lmb_bram/lmb_bram/ramb16bwer_5 [26:26] INPUT = lmb_bram_combined_5.mem PLACED = X2Y46;
lmb_bram/lmb_bram/ramb16bwer_6 [25:25] INPUT = lmb_bram_combined_6.mem PLACED = X2Y42;
lmb_bram/lmb_bram/ramb16bwer_7 [24:24] INPUT = lmb_bram_combined_7.mem PLACED = X3Y38;
lmb_bram/lmb_bram/ramb16bwer_8 [23:23] INPUT = lmb_bram_combined_8.mem PLACED = X1Y38;
lmb_bram/lmb_bram/ramb16bwer_9 [22:22] INPUT = lmb_bram_combined_9.mem PLACED = X2Y38;
lmb_bram/lmb_bram/ramb16bwer_10 [21:21] INPUT = lmb_bram_combined_10.mem PLACED = X3Y36;
lmb_bram/lmb_bram/ramb16bwer_11 [20:20] INPUT = lmb_bram_combined_11.mem PLACED = X3Y34;
lmb_bram/lmb_bram/ramb16bwer_12 [19:19] INPUT = lmb_bram_combined_12.mem PLACED = X2Y26;
lmb_bram/lmb_bram/ramb16bwer_13 [18:18] INPUT = lmb_bram_combined_13.mem PLACED = X3Y28;
lmb_bram/lmb_bram/ramb16bwer_14 [17:17] INPUT = lmb_bram_combined_14.mem PLACED = X2Y30;
lmb_bram/lmb_bram/ramb16bwer_15 [16:16] INPUT = lmb_bram_combined_15.mem PLACED = X2Y28;
lmb_bram/lmb_bram/ramb16bwer_16 [15:15] INPUT = lmb_bram_combined_16.mem PLACED = X2Y32;
lmb_bram/lmb_bram/ramb16bwer_17 [14:14] INPUT = lmb_bram_combined_17.mem PLACED = X0Y32;
lmb_bram/lmb_bram/ramb16bwer_18 [13:13] INPUT = lmb_bram_combined_18.mem PLACED = X1Y32;
lmb_bram/lmb_bram/ramb16bwer_19 [12:12] INPUT = lmb_bram_combined_19.mem PLACED = X1Y34;
lmb_bram/lmb_bram/ramb16bwer_20 [11:11] INPUT = lmb_bram_combined_20.mem PLACED = X2Y22;
lmb_bram/lmb_bram/ramb16bwer_21 [10:10] INPUT = lmb_bram_combined_21.mem PLACED = X2Y24;
lmb_bram/lmb_bram/ramb16bwer_22 [9:9] INPUT = lmb_bram_combined_22.mem PLACED = X1Y28;
lmb_bram/lmb_bram/ramb16bwer_23 [8:8] INPUT = lmb_bram_combined_23.mem PLACED = X3Y24;
lmb_bram/lmb_bram/ramb16bwer_24 [7:7] INPUT = lmb_bram_combined_24.mem PLACED = X3Y32;
lmb_bram/lmb_bram/ramb16bwer_25 [6:6] INPUT = lmb_bram_combined_25.mem PLACED = X1Y36;
lmb_bram/lmb_bram/ramb16bwer_26 [5:5] INPUT = lmb_bram_combined_26.mem PLACED = X2Y36;
lmb_bram/lmb_bram/ramb16bwer_27 [4:4] INPUT = lmb_bram_combined_27.mem PLACED = X2Y34;
lmb_bram/lmb_bram/ramb16bwer_28 [3:3] INPUT = lmb_bram_combined_28.mem PLACED = X3Y30;
lmb_bram/lmb_bram/ramb16bwer_29 [2:2] INPUT = lmb_bram_combined_29.mem PLACED = X3Y26;
lmb_bram/lmb_bram/ramb16bwer_30 [1:1] INPUT = lmb_bram_combined_30.mem PLACED = X1Y26;
lmb_bram/lmb_bram/ramb16bwer_31 [0:0] INPUT = lmb_bram_combined_31.mem PLACED = X1Y30;
END_BUS_BLOCK;
END_ADDRESS_SPACE;
......
projnav/xps/SDK/SDK_Workspace/demo/.cproject
View file @ 94c99edd
......@@ -32,7 +32,7 @@
<option id="xilinx.gnu.mb.compiler.inferred.usepcmp.2025998320" superClass="xilinx.gnu.mb.compiler.inferred.usepcmp" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.compiler.inferred.mul.759631855" superClass="xilinx.gnu.mb.compiler.inferred.mul" value="xilinx.gnu.mb.compiler.inferred.mul.32bit" valueType="enumerated"/>
<option id="xilinx.gnu.compiler.inferred.swplatform.includes.8831996" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">
<listOptionValue builtIn="false" value="../../demobsp/microblaze_0/include"/>
<listOptionValue builtIn="false" value="../../standalone_bsp_0/microblaze_0/include"/>
</option>
<inputType id="xilinx.gnu.compiler.input.347712346" name="C source files" superClass="xilinx.gnu.compiler.input"/>
</tool>
......@@ -44,7 +44,7 @@
<option id="xilinx.gnu.mb.compiler.inferred.usepcmp.1786658605" superClass="xilinx.gnu.mb.compiler.inferred.usepcmp" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.compiler.inferred.mul.1923590513" superClass="xilinx.gnu.mb.compiler.inferred.mul" value="xilinx.gnu.mb.compiler.inferred.mul.32bit" valueType="enumerated"/>
<option id="xilinx.gnu.compiler.inferred.swplatform.includes.807993403" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">
<listOptionValue builtIn="false" value="../../demobsp/microblaze_0/include"/>
<listOptionValue builtIn="false" value="../../standalone_bsp_0/microblaze_0/include"/>
</option>
<inputType id="xilinx.gnu.mb.cxx.compiler.input.648873885" name="C++ source files" superClass="xilinx.gnu.mb.cxx.compiler.input"/>
</tool>
......@@ -55,7 +55,7 @@
<option id="xilinx.gnu.mb.linker.inferred.usepcmp.1889097504" superClass="xilinx.gnu.mb.linker.inferred.usepcmp" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.linker.inferred.mul.1038478631" superClass="xilinx.gnu.mb.linker.inferred.mul" value="xilinx.gnu.mb.linker.inferred.mul.32bit" valueType="enumerated"/>
<option id="xilinx.gnu.linker.inferred.swplatform.lpath.1046693538" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">
<listOptionValue builtIn="false" value="../../demobsp/microblaze_0/lib"/>
<listOptionValue builtIn="false" value="../../standalone_bsp_0/microblaze_0/lib"/>
</option>
<inputType id="xilinx.gnu.linker.input.59786092" superClass="xilinx.gnu.linker.input">
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
......@@ -69,7 +69,7 @@
<option id="xilinx.gnu.mb.linker.inferred.usepcmp.683225781" superClass="xilinx.gnu.mb.linker.inferred.usepcmp" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.linker.inferred.mul.1665375810" superClass="xilinx.gnu.mb.linker.inferred.mul" value="xilinx.gnu.mb.linker.inferred.mul.32bit" valueType="enumerated"/>
<option id="xilinx.gnu.linker.inferred.swplatform.lpath.648441665" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">
<listOptionValue builtIn="false" value="../../demobsp/microblaze_0/lib"/>
<listOptionValue builtIn="false" value="../../standalone_bsp_0/microblaze_0/lib"/>
</option>
<inputType id="xilinx.gnu.linker.input.308356398" superClass="xilinx.gnu.linker.input">
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
......@@ -702,6 +702,9 @@
</scannerConfigBuildInfo>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
<storageModule moduleId="org.eclipse.cdt.core.language.mapping"/>
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
</cconfiguration>
<cconfiguration id="xilinx.gnu.mb.exe.release.1874379234">
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="xilinx.gnu.mb.exe.release.1874379234" moduleId="org.eclipse.cdt.core.settings" name="Release">
......@@ -732,7 +735,7 @@
<option id="xilinx.gnu.mb.compiler.inferred.usepcmp.2117022726" superClass="xilinx.gnu.mb.compiler.inferred.usepcmp" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.compiler.inferred.mul.1935521183" superClass="xilinx.gnu.mb.compiler.inferred.mul" value="xilinx.gnu.mb.compiler.inferred.mul.32bit" valueType="enumerated"/>
<option id="xilinx.gnu.compiler.inferred.swplatform.includes.866562977" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">
<listOptionValue builtIn="false" value="../../demobsp/microblaze_0/include"/>
<listOptionValue builtIn="false" value="../../standalone_bsp_0/microblaze_0/include"/>
</option>
<inputType id="xilinx.gnu.compiler.input.794413244" name="C source files" superClass="xilinx.gnu.compiler.input"/>
</tool>
......@@ -744,7 +747,7 @@
<option id="xilinx.gnu.mb.compiler.inferred.usepcmp.1558683552" superClass="xilinx.gnu.mb.compiler.inferred.usepcmp" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.compiler.inferred.mul.13660006" superClass="xilinx.gnu.mb.compiler.inferred.mul" value="xilinx.gnu.mb.compiler.inferred.mul.32bit" valueType="enumerated"/>
<option id="xilinx.gnu.compiler.inferred.swplatform.includes.1802910256" superClass="xilinx.gnu.compiler.inferred.swplatform.includes" valueType="includePath">
<listOptionValue builtIn="false" value="../../demobsp/microblaze_0/include"/>
<listOptionValue builtIn="false" value="../../standalone_bsp_0/microblaze_0/include"/>
</option>
<inputType id="xilinx.gnu.mb.cxx.compiler.input.2035748458" name="C++ source files" superClass="xilinx.gnu.mb.cxx.compiler.input"/>
</tool>
......@@ -755,7 +758,7 @@
<option id="xilinx.gnu.mb.linker.inferred.usepcmp.2060796612" superClass="xilinx.gnu.mb.linker.inferred.usepcmp" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.linker.inferred.mul.1077867032" superClass="xilinx.gnu.mb.linker.inferred.mul" value="xilinx.gnu.mb.linker.inferred.mul.32bit" valueType="enumerated"/>
<option id="xilinx.gnu.linker.inferred.swplatform.lpath.1203525340" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">
<listOptionValue builtIn="false" value="../../demobsp/microblaze_0/lib"/>
<listOptionValue builtIn="false" value="../../standalone_bsp_0/microblaze_0/lib"/>
</option>
<inputType id="xilinx.gnu.linker.input.1104704384" superClass="xilinx.gnu.linker.input">
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
......@@ -769,7 +772,7 @@
<option id="xilinx.gnu.mb.linker.inferred.usepcmp.1468747866" superClass="xilinx.gnu.mb.linker.inferred.usepcmp" value="true" valueType="boolean"/>
<option id="xilinx.gnu.mb.linker.inferred.mul.1150761071" superClass="xilinx.gnu.mb.linker.inferred.mul" value="xilinx.gnu.mb.linker.inferred.mul.32bit" valueType="enumerated"/>
<option id="xilinx.gnu.linker.inferred.swplatform.lpath.1133642997" superClass="xilinx.gnu.linker.inferred.swplatform.lpath" valueType="libPaths">
<listOptionValue builtIn="false" value="../../demobsp/microblaze_0/lib"/>
<listOptionValue builtIn="false" value="../../standalone_bsp_0/microblaze_0/lib"/>
</option>
<inputType id="xilinx.gnu.linker.input.300985381" superClass="xilinx.gnu.linker.input">
<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
......@@ -1402,6 +1405,9 @@
</scannerConfigBuildInfo>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
<storageModule moduleId="org.eclipse.cdt.core.language.mapping"/>
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
</cconfiguration>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
......
projnav/xps/SDK/SDK_Workspace/demo/.project
View file @ 94c99edd
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>demo</name>
<comment>demobsp - microblaze_0</comment>
<comment></comment>
<projects>
<project>standalone_bsp_0</project>
<project>demobsp</project>
</projects>
<buildSpec>
......
projnav/xps/SDK/SDK_Workspace/demo/Debug/makefile
View file @ 94c99edd
......@@ -50,7 +50,7 @@ all: demo.elf secondary-outputs
demo.elf: $(OBJS) $(USER_OBJS)
@echo Building target: $@
@echo Invoking: MicroBlaze g++ linker
mb-g++ -L../../demobsp/microblaze_0/lib -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.20.a -mno-xl-soft-mul -o"demo.elf" $(OBJS) $(USER_OBJS) $(LIBS)
mb-g++ -L../../standalone_bsp_0/microblaze_0/lib -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.20.a -mno-xl-soft-mul -o"demo.elf" $(OBJS) $(USER_OBJS) $(LIBS)
@echo Finished building target: $@
@echo ' '
......
projnav/xps/SDK/SDK_Workspace/demo/Debug/src/subdir.mk
View file @ 94c99edd
......@@ -17,7 +17,7 @@ CC_DEPS += \
src/%.o: ../src/%.cc
@echo Building file: $<
@echo Invoking: MicroBlaze g++ compiler
mb-g++ -Wall -O0 -g3 -c -fmessage-length=0 -I../../demobsp/microblaze_0/include -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.20.a -mno-xl-soft-mul -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -o"$@" "$<"
mb-g++ -Wall -O0 -g3 -c -fmessage-length=0 -I../../standalone_bsp_0/microblaze_0/include -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.20.a -mno-xl-soft-mul -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -o"$@" "$<"
@echo Finished building: $<
@echo ' '
......
projnav/xps/SDK/SDK_Workspace/demo/src/main.cc
View file @ 94c99edd
......@@ -85,7 +85,7 @@ int DmaCopy(void * pSrc, void * pDest, size_t byteCount)
int main()
{
int status;
int status, i;
// Initialize system
if (XST_SUCCESS != (status = InitDma())) {
......@@ -99,6 +99,42 @@ int main()
// Test DMA
SpiifcDmaTest();
// Spiifc loopback: anything sent to spiifc is sent back
while (1) {
/*
for (i = 0; i < 1024; i++) {
pMisoBase[i] = pMosiBase[i];
}
*/
xil_printf(
"pMosiBase = [ 0x%08x 0x%08x 0x%08x ... ]\n"
"pMisoBase = [ 0x%08x 0x%08x 0x%08x ... ]\n"
"\n",
pMosiBase[0], pMosiBase[1], pMosiBase[2],
pMisoBase[0], pMisoBase[1], pMisoBase[2]);
DmaCopy(pMosiBase, pMisoBase, DMA_BUFFER_BYTE_SIZE);
//xil_printf("debug_out: 0x%08X\n", pSpiifcBase[0]);
/*
xil_printf("pMosiBase = [ 0x%02X 0x%02X 0x%02X 0x%02X ]\n",
pMosiBase[0] & 0xFF, (pMosiBase[0] >> 8) & 0xFF,
(pMosiBase[0] >> 16) & 0xFF, (pMosiBase[0] >> 24) & 0xFF);
xil_printf("pMisoBase = [ 0x%02X 0x%02X 0x%02X 0x%02X ]\n",
pMisoBase[0] & 0xFF, (pMisoBase[0] >> 8) & 0xFF,
(pMisoBase[0] >> 16) & 0xFF, (pMisoBase[0] >> 24) & 0xFF);
*/
}
/*
int i = 0;
for (i = 0; i < 40000000; i++) { ; }
for (i = 0; i < 1024; i++) {
xil_printf("pMOSI[i] = 0x%08X\n", pMosiBase[i]);
}
*/
}
void SpiifcPioTest()
......@@ -142,10 +178,14 @@ void SpiifcDmaTest()
// Pattern DMA memory buffer
for(i = 0; i < DMA_BUFFER_BYTE_SIZE/4; i++) {
pMosiBase[i] = ((i*4) & 0xFF) << 24 |
((i*4+1) & 0xFF) << 16 |
((i*4+2) & 0xFF) << 8 |
((i*4+3) & 0xFF);
pMosiBase[i] = ((i*4+3) & 0xFF) << 24 |
((i*4+2) & 0xFF) << 16 |
((i*4+1) & 0xFF) << 8 |
((i*4+0) & 0xFF);
//pMosiBase[i] = 0xAABBCCDD;
//xil_printf("0x%08X\n", pMosiBase[i]);
}
// DMA buffer to Spiifc.MISO buffer
......@@ -158,14 +198,15 @@ void SpiifcDmaTest()
u32 expectedDmaWord = 0;
int failWords = 0;
for (i = 0; i < (DMA_BUFFER_BYTE_SIZE/4); i++) {
expectedDmaWord = ((i*4+0) & 0xFF) << 24 |
((i*4+1) & 0xFF) << 16 |
((i*4+2) & 0xFF) << 8 |
((i*4+3) & 0xFF) << 0;
expectedDmaWord = ((i*4+3) & 0xFF) << 24 |
((i*4+2) & 0xFF) << 16 |
((i*4+1) & 0xFF) << 8 |
((i*4+0) & 0xFF) << 0;
if (pMisoBase[i] != expectedDmaWord) {
xil_printf(
"[FAIL] DMA mem word [i]: expected=0x%08X, actual=0x%08X\n",
expectedDmaWord, pMisoBase);
expectedDmaWord, pMisoBase[i]);
}
}
if (0 == failWords) {
......
projnav/xps/SDK/SDK_Workspace/demobsp/.cproject → projnav/xps/SDK/SDK_Workspace/standalone_bsp_0/.cproject
View file @ 94c99edd
......@@ -3,8 +3,8 @@
<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
<storageModule moduleId="org.eclipse.cdt.core.settings">
<cconfiguration id="org.eclipse.cdt.core.default.config.948582058">
<storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.948582058" moduleId="org.eclipse.cdt.core.settings" name="Configuration">
<cconfiguration id="org.eclipse.cdt.core.default.config.1065451617">
<storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.1065451617" moduleId="org.eclipse.cdt.core.settings" name="Configuration">
<externalSettings/>
<extensions/>
</storageModule>
......
projnav/xps/SDK/SDK_Workspace/demobsp/.project → projnav/xps/SDK/SDK_Workspace/standalone_bsp_0/.project
View file @ 94c99edd
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>demobsp</name>
<name>standalone_bsp_0</name>
<comment></comment>
<projects>
<project>xps_hw_platform</project>
......
projnav/xps/SDK/SDK_Workspace/standalone_bsp_0/libgen.log 0 → 100644
View file @ 94c99edd
Release 13.2 - libgen Xilinx EDK 13.2 Build EDK_O.61xd
(nt64)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
Command Line: libgen -hw ../xps_hw_platform/system.xml -pe microblaze_0 -log
libgen.log system.mss
Staging source files.
Running DRCs.
Running generate.
Running post_generate.
Running include - 'make -s include "COMPILER=mb-gcc" "ARCHIVER=mb-ar"
"COMPILER_FLAGS=-mno-xl-soft-mul -mxl-barrel-shift -mxl-pattern-compare
-mcpu=v8.20.a -O2 -c" "EXTRA_COMPILER_FLAGS=-g"'.
Running libs - 'make -s libs "COMPILER=mb-gcc" "ARCHIVER=mb-ar"
"COMPILER_FLAGS=-mno-xl-soft-mul -mxl-barrel-shift -mxl-pattern-compare
-mcpu=v8.20.a -O2 -c" "EXTRA_COMPILER_FLAGS=-g"'.
Running execs_generate.
projnav/xps/SDK/SDK_Workspace/xps_hw_platform/system_bd.bmm
View file @ 94c99edd
......@@ -21,38 +21,38 @@ ADDRESS_MAP microblaze_0 MICROBLAZE 100
ADDRESS_SPACE lmb_bram_combined RAMB16 [0x00000000:0x0000FFFF]
BUS_BLOCK
lmb_bram/lmb_bram/ramb16bwer_0 [31:31] INPUT = lmb_bram_combined_0.mem PLACED = X2Y46;
lmb_bram/lmb_bram/ramb16bwer_1 [30:30] INPUT = lmb_bram_combined_1.mem PLACED = X2Y44;
lmb_bram/lmb_bram/ramb16bwer_2 [29:29] INPUT = lmb_bram_combined_2.mem PLACED = X2Y42;
lmb_bram/lmb_bram/ramb16bwer_3 [28:28] INPUT = lmb_bram_combined_3.mem PLACED = X3Y42;
lmb_bram/lmb_bram/ramb16bwer_4 [27:27] INPUT = lmb_bram_combined_4.mem PLACED = X2Y40;
lmb_bram/lmb_bram/ramb16bwer_5 [26:26] INPUT = lmb_bram_combined_5.mem PLACED = X2Y38;
lmb_bram/lmb_bram/ramb16bwer_6 [25:25] INPUT = lmb_bram_combined_6.mem PLACED = X2Y32;
lmb_bram/lmb_bram/ramb16bwer_7 [24:24] INPUT = lmb_bram_combined_7.mem PLACED = X3Y40;
lmb_bram/lmb_bram/ramb16bwer_8 [23:23] INPUT = lmb_bram_combined_8.mem PLACED = X3Y38;
lmb_bram/lmb_bram/ramb16bwer_9 [22:22] INPUT = lmb_bram_combined_9.mem PLACED = X3Y36;
lmb_bram/lmb_bram/ramb16bwer_10 [21:21] INPUT = lmb_bram_combined_10.mem PLACED = X2Y36;
lmb_bram/lmb_bram/ramb16bwer_11 [20:20] INPUT = lmb_bram_combined_11.mem PLACED = X2Y34;
lmb_bram/lmb_bram/ramb16bwer_12 [19:19] INPUT = lmb_bram_combined_12.mem PLACED = X1Y30;
lmb_bram/lmb_bram/ramb16bwer_13 [18:18] INPUT = lmb_bram_combined_13.mem PLACED = X3Y24;
lmb_bram/lmb_bram/ramb16bwer_14 [17:17] INPUT = lmb_bram_combined_14.mem PLACED = X2Y26;
lmb_bram/lmb_bram/ramb16bwer_15 [16:16] INPUT = lmb_bram_combined_15.mem PLACED = X1Y26;
lmb_bram/lmb_bram/ramb16bwer_16 [15:15] INPUT = lmb_bram_combined_16.mem PLACED = X3Y32;
lmb_bram/lmb_bram/ramb16bwer_17 [14:14] INPUT = lmb_bram_combined_17.mem PLACED = X1Y32;
lmb_bram/lmb_bram/ramb16bwer_18 [13:13] INPUT = lmb_bram_combined_18.mem PLACED = X1Y28;
lmb_bram/lmb_bram/ramb16bwer_19 [12:12] INPUT = lmb_bram_combined_19.mem PLACED = X3Y34;
lmb_bram/lmb_bram/ramb16bwer_20 [11:11] INPUT = lmb_bram_combined_20.mem PLACED = X2Y24;
lmb_bram/lmb_bram/ramb16bwer_21 [10:10] INPUT = lmb_bram_combined_21.mem PLACED = X2Y18;
lmb_bram/lmb_bram/ramb16bwer_22 [9:9] INPUT = lmb_bram_combined_22.mem PLACED = X2Y20;
lmb_bram/lmb_bram/ramb16bwer_23 [8:8] INPUT = lmb_bram_combined_23.mem PLACED = X2Y22;
lmb_bram/lmb_bram/ramb16bwer_24 [7:7] INPUT = lmb_bram_combined_24.mem PLACED = X3Y26;
lmb_bram/lmb_bram/ramb16bwer_25 [6:6] INPUT = lmb_bram_combined_25.mem PLACED = X3Y30;
lmb_bram/lmb_bram/ramb16bwer_26 [5:5] INPUT = lmb_bram_combined_26.mem PLACED = X2Y28;
lmb_bram/lmb_bram/ramb16bwer_27 [4:4] INPUT = lmb_bram_combined_27.mem PLACED = X3Y28;
lmb_bram/lmb_bram/ramb16bwer_28 [3:3] INPUT = lmb_bram_combined_28.mem PLACED = X3Y22;
lmb_bram/lmb_bram/ramb16bwer_29 [2:2] INPUT = lmb_bram_combined_29.mem PLACED = X2Y30;
lmb_bram/lmb_bram/ramb16bwer_30 [1:1] INPUT = lmb_bram_combined_30.mem PLACED = X2Y14;
lmb_bram/lmb_bram/ramb16bwer_31 [0:0] INPUT = lmb_bram_combined_31.mem PLACED = X2Y16;
lmb_bram/lmb_bram/ramb16bwer_0 [31:31] INPUT = lmb_bram_combined_0.mem PLACED = X2Y44;
lmb_bram/lmb_bram/ramb16bwer_1 [30:30] INPUT = lmb_bram_combined_1.mem PLACED = X3Y42;
lmb_bram/lmb_bram/ramb16bwer_2 [29:29] INPUT = lmb_bram_combined_2.mem PLACED = X2Y48;
lmb_bram/lmb_bram/ramb16bwer_3 [28:28] INPUT = lmb_bram_combined_3.mem PLACED = X2Y40;
lmb_bram/lmb_bram/ramb16bwer_4 [27:27] INPUT = lmb_bram_combined_4.mem PLACED = X3Y40;
lmb_bram/lmb_bram/ramb16bwer_5 [26:26] INPUT = lmb_bram_combined_5.mem PLACED = X2Y46;
lmb_bram/lmb_bram/ramb16bwer_6 [25:25] INPUT = lmb_bram_combined_6.mem PLACED = X2Y42;
lmb_bram/lmb_bram/ramb16bwer_7 [24:24] INPUT = lmb_bram_combined_7.mem PLACED = X3Y38;
lmb_bram/lmb_bram/ramb16bwer_8 [23:23] INPUT = lmb_bram_combined_8.mem PLACED = X1Y38;
lmb_bram/lmb_bram/ramb16bwer_9 [22:22] INPUT = lmb_bram_combined_9.mem PLACED = X2Y38;
lmb_bram/lmb_bram/ramb16bwer_10 [21:21] INPUT = lmb_bram_combined_10.mem PLACED = X3Y36;
lmb_bram/lmb_bram/ramb16bwer_11 [20:20] INPUT = lmb_bram_combined_11.mem PLACED = X3Y34;
lmb_bram/lmb_bram/ramb16bwer_12 [19:19] INPUT = lmb_bram_combined_12.mem PLACED = X2Y26;
lmb_bram/lmb_bram/ramb16bwer_13 [18:18] INPUT = lmb_bram_combined_13.mem PLACED = X3Y28;
lmb_bram/lmb_bram/ramb16bwer_14 [17:17] INPUT = lmb_bram_combined_14.mem PLACED = X2Y30;
lmb_bram/lmb_bram/ramb16bwer_15 [16:16] INPUT = lmb_bram_combined_15.mem PLACED = X2Y28;
lmb_bram/lmb_bram/ramb16bwer_16 [15:15] INPUT = lmb_bram_combined_16.mem PLACED = X2Y32;
lmb_bram/lmb_bram/ramb16bwer_17 [14:14] INPUT = lmb_bram_combined_17.mem PLACED = X0Y32;
lmb_bram/lmb_bram/ramb16bwer_18 [13:13] INPUT = lmb_bram_combined_18.mem PLACED = X1Y32;
lmb_bram/lmb_bram/ramb16bwer_19 [12:12] INPUT = lmb_bram_combined_19.mem PLACED = X1Y34;
lmb_bram/lmb_bram/ramb16bwer_20 [11:11] INPUT = lmb_bram_combined_20.mem PLACED = X2Y22;
lmb_bram/lmb_bram/ramb16bwer_21 [10:10] INPUT = lmb_bram_combined_21.mem PLACED = X2Y24;
lmb_bram/lmb_bram/ramb16bwer_22 [9:9] INPUT = lmb_bram_combined_22.mem PLACED = X1Y28;
lmb_bram/lmb_bram/ramb16bwer_23 [8:8] INPUT = lmb_bram_combined_23.mem PLACED = X3Y24;
lmb_bram/lmb_bram/ramb16bwer_24 [7:7] INPUT = lmb_bram_combined_24.mem PLACED = X3Y32;
lmb_bram/lmb_bram/ramb16bwer_25 [6:6] INPUT = lmb_bram_combined_25.mem PLACED = X1Y36;
lmb_bram/lmb_bram/ramb16bwer_26 [5:5] INPUT = lmb_bram_combined_26.mem PLACED = X2Y36;
lmb_bram/lmb_bram/ramb16bwer_27 [4:4] INPUT = lmb_bram_combined_27.mem PLACED = X2Y34;
lmb_bram/lmb_bram/ramb16bwer_28 [3:3] INPUT = lmb_bram_combined_28.mem PLACED = X3Y30;
lmb_bram/lmb_bram/ramb16bwer_29 [2:2] INPUT = lmb_bram_combined_29.mem PLACED = X3Y26;
lmb_bram/lmb_bram/ramb16bwer_30 [1:1] INPUT = lmb_bram_combined_30.mem PLACED = X1Y26;
lmb_bram/lmb_bram/ramb16bwer_31 [0:0] INPUT = lmb_bram_combined_31.mem PLACED = X1Y30;
END_BUS_BLOCK;
END_ADDRESS_SPACE;
......
projnav/xps/__xps/ise/system.xreport
View file @ 94c99edd
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2012-03-01T09:28:38</DateModified>
<DateModified>2012-03-06T18:05:57</DateModified>
<ModuleName>system</ModuleName>
<SummaryTimeStamp>2012-03-01T09:28:36</SummaryTimeStamp>
<SummaryTimeStamp>2012-03-06T18:05:56</SummaryTimeStamp>
<SavedFilePath>C:/Users/mjlyons/workspace/vSPI/projnav/xps/__xps/ise/system.xreport</SavedFilePath>
<FilterFile>filter.filter</FilterFile>
<SavedFilterFilePath>C:/Users/mjlyons/workspace/vSPI/projnav/xps/__xps/ise</SavedFilterFilePath>
......
projnav/xps/__xps/system.xml
View file @ 94c99edd
This diff is collapsed.
projnav/xps/data/system.ucf
View file @ 94c99edd
......@@ -25,3 +25,9 @@ TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100000 kHz;
Net fpga_0_clk_1_sys_clk_pin LOC=L15 | IOSTANDARD=LVCMOS33;
Net fpga_0_rst_1_sys_rst_pin TIG;
Net fpga_0_rst_1_sys_rst_pin LOC=T15 | IOSTANDARD=LVCMOS33;
# SPI
NET "spiifc_0_SPI_CLK_pin" LOC = R10 | IOSTANDARD = LVCMOS33;
NET "spiifc_0_SPI_MISO_pin" LOC = U16 | IOSTANDARD = LVCMOS33;
NET "spiifc_0_SPI_MOSI_pin" LOC = U15 | IOSTANDARD = LVCMOS33;
NET "spiifc_0_SPI_SS_pin" LOC = M11 | IOSTANDARD = LVCMOS33;
projnav/xps/etc/system.gui
View file @ 94c99edd
......@@ -9,7 +9,7 @@
<VARIABLE COL_INDEX="1" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Bus Name" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="2" IS_VISIBLE="FALSE" VIEWDISP="Bus Standard" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="3" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="4" COL_WIDTH="813" IS_VISIBLE="TRUE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="4" COL_WIDTH="726" IS_VISIBLE="TRUE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="5" IS_VISIBLE="FALSE" VIEWDISP="IP Classification" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="6" IS_VISIBLE="FALSE" VIEWDISP="Type" VIEWTYPE="HEADER"/>
</HEADERS>
......@@ -81,26 +81,26 @@
<SET CLASS="PROJECT" DISPLAYMODE="TREE" VIEW_ID="PORT">
<HEADERS HSCROLL="0" VSCROLL="0">
<VARIABLE COL_INDEX="0" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Name" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="1" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Net" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="0" COL_WIDTH="201" IS_VISIBLE="TRUE" VIEWDISP="Name" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="1" COL_WIDTH="180" IS_VISIBLE="TRUE" VIEWDISP="Net" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="2" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Direction" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="3" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Range" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="4" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Class" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="5" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Frequency(Hz)" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="6" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Reset Polarity" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="7" COL_WIDTH="413" IS_VISIBLE="TRUE" VIEWDISP="Sensitivity" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="8" COL_WIDTH="213" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="8" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="9" IS_VISIBLE="FALSE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="10" IS_VISIBLE="TRUE" VIEWDISP="IP Classification" VIEWTYPE="HEADER"/>
</HEADERS>
<SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="0,630,180" VERSION="0"/>
<SET ID="ExternalPorts" IS_EXPANDED="TRUE"/>
<SET ID="spiifc_0" IS_EXPANDED="TRUE"/>
<SET ID="xps_central_dma_0" IS_EXPANDED="TRUE"/>
<STATUS>
<SELECTIONS/>
</STATUS>
<SEQUENCES IS_DEF_SEQUENCES="TRUE">
<VARIABLE ID="ExternalPorts" ROW_INDEX="0"/>
<VARIABLE ID="ExternalPorts" IS_EXPANDED="TRUE" ROW_INDEX="0"/>
<VARIABLE ID="microblaze_0" ROW_INDEX="4"/>
<VARIABLE ID="mb_plb" ROW_INDEX="3"/>
<VARIABLE ID="ilmb" ROW_INDEX="2"/>
......@@ -115,7 +115,7 @@
<VARIABLE ID="mdm_0" ROW_INDEX="9"/>
<VARIABLE ID="proc_sys_reset_0" ROW_INDEX="15"/>
<VARIABLE ID="spiifc_0" IS_EXPANDED="TRUE" ROW_INDEX="8"/>
<VARIABLE ID="xps_central_dma_0" IS_EXPANDED="TRUE" ROW_INDEX="10"/>
<VARIABLE ID="xps_central_dma_0" ROW_INDEX="10"/>
</SEQUENCES>
</SET>
......
projnav/xps/implementation/system_summary.html
View file @ 94c99edd
......@@ -31,7 +31,7 @@
<TR ALIGN=LEFT><TD>Platgen Log File</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Simgen Log File</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>BitInit Log File</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/mjlyons/workspace/vSPI/projnav/xps\system.log'>System Log File</A></TD><TD>Thu Mar 1 09:29:13 2012</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/mjlyons/workspace/vSPI/projnav/xps\system.log'>System Log File</A></TD><TD>Wed Mar 7 09:21:12 2012</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
</TABLE>
......@@ -57,5 +57,5 @@
</TABLE>
<br><center><b>Date Generated:</b> 03/01/2012 - 09:29:13</center>
<br><center><b>Date Generated:</b> 03/07/2012 - 09:21:12</center>
</BODY></HTML>
\ No newline at end of file
projnav/xps/pcores/spiifc.prj
View file @ 94c99edd
......@@ -13,6 +13,7 @@ vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPL
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_slave_burst_v1_01_a\hdl\vhdl\addr_reg_cntr_brst_flex.vhd"
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_slave_burst_v1_01_a\hdl\vhdl\plb_slave_attachment.vhd"
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_slave_burst_v1_01_a\hdl\vhdl\data_mirror_128.vhd"
verilog spiifc_v1_00_a "C:\Users\mjlyons\workspace\vSPI\src\spi_base\spiifc.v"
verilog spiifc_v1_00_a "C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav\ipcore_dir\buffermem.v"
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_slave_burst_v1_01_a\hdl\vhdl\plbv46_slave_burst.vhd"
vhdl interrupt_control_v2_01_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\interrupt_control_v2_01_a\hdl\vhdl\interrupt_control.vhd"
......
projnav/xps/pcores/spiifc_v1_00_a/data/spiifc_v2_1_0.bbd
View file @ 94c99edd
##############################################################################
## Filename: C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores/spiifc_v1_00_a/data/spiifc_v2_1_0.bbd
## Description: Black Box Definition
## Date: Tue Feb 28 16:31:09 2012 (by Create and Import Peripheral Wizard)
## Date: Tue Mar 06 14:12:58 2012 (by Create and Import Peripheral Wizard)
##############################################################################
Files
......
projnav/xps/pcores/spiifc_v1_00_a/data/spiifc_v2_1_0.mpd
View file @ 94c99edd
......@@ -40,6 +40,10 @@ PARAMETER C_MEM1_BASEADDR = 0xffffffff, DT = std_logic_vector, PAIR = C_MEM1_HIG
PARAMETER C_MEM1_HIGHADDR = 0x00000000, DT = std_logic_vector, PAIR = C_MEM1_BASEADDR, ADDRESS = HIGH, BUS = SPLB, ADDR_TYPE = MEMORY
## Ports
PORT SPI_CLK = "", DIR = I
PORT SPI_MOSI = "", DIR = I
PORT SPI_MISO = "", DIR = O
PORT SPI_SS = "", DIR = I
PORT SPLB_Clk = "", DIR = I, SIGIS = CLK, BUS = SPLB
PORT SPLB_Rst = SPLB_Rst, DIR = I, SIGIS = RST, BUS = SPLB
PORT PLB_ABus = PLB_ABus, DIR = I, VEC = [0:31], BUS = SPLB
......
projnav/xps/pcores/spiifc_v1_00_a/data/spiifc_v2_1_0.pao
View file @ 94c99edd
##############################################################################
## Filename: C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores/spiifc_v1_00_a/data/spiifc_v2_1_0.pao
## Description: Peripheral Analysis Order
## Date: Tue Feb 28 16:31:09 2012 (by Create and Import Peripheral Wizard)
## Date: Tue Mar 06 14:12:58 2012 (by Create and Import Peripheral Wizard)
##############################################################################
lib proc_common_v3_00_a proc_common_pkg vhdl
......@@ -19,6 +19,7 @@ lib plbv46_slave_burst_v1_01_a be_reset_gen vhdl
lib plbv46_slave_burst_v1_01_a addr_reg_cntr_brst_flex vhdl
lib plbv46_slave_burst_v1_01_a plb_slave_attachment vhdl
lib plbv46_slave_burst_v1_01_a data_mirror_128 vhdl
lib spiifc_v1_00_a spiifc verilog
lib spiifc_v1_00_a buffermem verilog
lib plbv46_slave_burst_v1_01_a plbv46_slave_burst vhdl
lib interrupt_control_v2_01_a interrupt_control vhdl
......
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/fuse.xmsgs 0 → 100644
View file @ 94c99edd
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
</messages>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/fuseRelaunch.cmd 0 → 100644
View file @ 94c99edd
-intstyle "ise" -incremental -lib "unisims_ver" -lib "unimacro_ver" -lib "xilinxcorelib_ver" -lib "secureip" -o "C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc_tb_isim_beh.exe" -prj "C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc_tb_beh.prj" "work.spiifc_tb" "work.glbl"
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/impact.xsl 0 → 100644
View file @ 94c99edd
<xsl:stylesheet
xmlns:xsl="http://www.w3.org/1999/XSL/Transform"
version="1.0">
<xsl:output method="html"/>
<xsl:template match="/">
<b>
<xsl:text>Current iMPACT Usage Statistics.</xsl:text>
<br></br>
<xsl:text>Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.</xsl:text>
</b>
<br></br>
<br></br>
<xsl:text>This page displays the current iMPACT device usage statistics that will be sent to Xilinx using WebTalk.</xsl:text>
<table width = "100%" border="1" CELLSPACING="0" cols="50% 50%">
<xsl:for-each select="document/application/section">
<tr>
<th COLSPAN="2" BGCOLOR="#99CCFF"><xsl:value-of select="@name"/></th>
</tr>
<xsl:for-each select="property">
<tr>
<td><xsl:value-of select="@name"/></td>
<td><xsl:value-of select="@value"/></td>
</tr>
</xsl:for-each>
<xsl:for-each select="item">
<tr>
<td COLSPAN="2" BGCOLOR="#FFFF99"><b><xsl:value-of select="@name"/></b></td>
</tr>
<xsl:value-of select="@value"/>
<xsl:for-each select="property">
<tr>
<td><xsl:value-of select="@name"/></td>
<td><xsl:value-of select="@value"/>&#x20;</td>
</tr>
</xsl:for-each>
</xsl:for-each>
</xsl:for-each>
</table>
</xsl:template>
</xsl:stylesheet>
<!--
<xsl:if test="position() != last()"> <h1><xsl:text> </xsl:text></h1></xsl:if>
-->
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/impact_impact.xwbt 0 → 100644
View file @ 94c99edd
INTSTYLE=impact
INFILE=C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav\impact.xsl
OUTFILE=C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav\impact.xsl
FAMILY=Single
PART=Single
WORKINGDIR=C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav
LICENSE=iMPACT
USER_INFO=iMPACT
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/iseconfig/spiifc.projectmgr
View file @ 94c99edd
......@@ -11,13 +11,13 @@
<ClosedNode>/spiifc - IMP C:|Users|mjlyons|workspace|vSPI|projnav|xps|pcores|spiifc_v1_00_a|hdl|vhdl|spiifc.vhd/PLBV46_SLAVE_BURST_I - plbv46_slave_burst - implementation/I_SLAVE_ATTACHMENT - plb_slave_attachment - implementation</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem>USER_LOGIC_I - user_logic (C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/hdl/verilog/user_logic.v)</SelectedItem>
<SelectedItem>spiifc_tb2 (C:/Users/mjlyons/workspace/vSPI/test/spi_base/spiifc_tb2.v)</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000225000000020000000000000000000000000200000064ffffffff000000810000000300000002000002250000000100000003000000000000000100000003</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
<CurrentItem>USER_LOGIC_I - user_logic (C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/hdl/verilog/user_logic.v)</CurrentItem>
<CurrentItem>spiifc_tb2 (C:/Users/mjlyons/workspace/vSPI/test/spi_base/spiifc_tb2.v)</CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
<ClosedNodes>
......@@ -29,13 +29,13 @@
<ClosedNode>User Constraints</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem></SelectedItem>
<SelectedItem>Synthesize - XST</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f8000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem>
<CurrentItem>Synthesize - XST</CurrentItem>
</ItemView>
<ItemView guiview="File" >
<ClosedNodes>
......@@ -81,6 +81,11 @@
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>Design Utilities</ClosedNode>
<ClosedNode>Implement Design/Map</ClosedNode>
<ClosedNode>Implement Design/Place &amp; Route</ClosedNode>
<ClosedNode>Implement Design/Translate</ClosedNode>
<ClosedNode>Synthesize - XST</ClosedNode>
<ClosedNode>User Constraints</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem></SelectedItem>
......@@ -106,4 +111,62 @@
</ItemView>
<SourceProcessView>000000ff00000000000000020000011b0000011b01000000050100000002</SourceProcessView>
<CurrentView>Implementation</CurrentView>
<ItemView engineview="BehavioralSim" guiview="Source" compilemode="AutoCompile" >
<ClosedNodes>
<ClosedNodesVersion>2</ClosedNodesVersion>
<ClosedNode>/spiifc - IMP C:|Users|mjlyons|workspace|vSPI|projnav|xps|pcores|spiifc_v1_00_a|hdl|vhdl|spiifc.vhd</ClosedNode>
<ClosedNode>/spiifc_tb C:|Users|mjlyons|workspace|vSPI|test|spi_base|spiifc_tb.v</ClosedNode>
<ClosedNode>/spiifc_tb2 C:|Users|mjlyons|workspace|vSPI|test|spi_base|spiifc_tb2.v</ClosedNode>
<ClosedNode>/spiwrap C:|Users|mjlyons|workspace|vSPI|src|spi_base|spiwrap.v</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem>spiifc_tb (C:/Users/mjlyons/workspace/vSPI/test/spi_base/spiifc_tb.v)</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000000be000000020000000000000000000000000200000064ffffffff000000810000000300000002000000be0000000100000003000000000000000100000003</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>spiifc_tb (C:/Users/mjlyons/workspace/vSPI/test/spi_base/spiifc_tb.v)</CurrentItem>
</ItemView>
<ItemView engineview="BehavioralSim" sourcetype="" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>Design Utilities</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem/>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f8000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem/>
</ItemView>
<ItemView engineview="BehavioralSim" sourcetype="DESUT_VERILOG" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
</ClosedNodes>
<SelectedItems>
<SelectedItem>Simulate Behavioral Model</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f8000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>Simulate Behavioral Model</CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_UCF" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>User Constraints</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem></SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f8000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem>
</ItemView>
</Project>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/par_usage_statistics.html 0 → 100644
View file @ 94c99edd
<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<xtag-section name="ParStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>Par Statistics</B></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>152</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>555</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>555</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>412</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>5.4 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>6.1 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>7.0 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>8.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>9.0 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>9.0 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>9.0 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>9.0 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>9.0 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>9.0 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>4.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>9.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>3.7</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>1.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>3.2</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>3.9</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0147</xtag-par-property-value></TD></TR>
</xtag-section>
</TABLE>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/rc-bytes-tx-test.txt 0 → 100644
View file @ 94c99edd
03
00
00
00
00
00
00
00
00
\ No newline at end of file
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/rc-bytes.txt 0 → 100644
View file @ 94c99edd
01
FF
F0
33
55
12
34
56
78
9A
\ No newline at end of file
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc.gise
View file @ 94c99edd
......@@ -21,10 +21,13 @@
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="spiifc.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_NCD" xil_pn:name="spiifc_guide.ncd" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_NCD" xil_pn:name="spiwrap_guide.ncd" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:name="TRAN_SubProjectAbstractToPreProxy">
<transform xil_pn:end_ts="1331066936" xil_pn:in_ck="-8467753332869629521" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1331066936">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
......
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc_bitgen.xwbt 0 → 100644
View file @ 94c99edd
INTSTYLE=ise
INFILE=C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav\spiifc.ncd
OUTFILE=C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav\spiifc.bit
FAMILY=Spartan6
PART=xc6slx45-2csg324
WORKINGDIR=C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav
LICENSE=ISE
USER_INFO=179841373_174164856_206270303_042
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiwrap_bitgen.xwbt 0 → 100644
View file @ 94c99edd
INTSTYLE=ise
INFILE=C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav\spiwrap.ncd
OUTFILE=C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav\spiwrap.bit
FAMILY=Spartan6
PART=xc6slx45-2csg324
WORKINGDIR=C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav
LICENSE=ISE
USER_INFO=179841373_174164856_206270303_042
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc_summary.html → projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiwrap_summary.html
View file @ 94c99edd
......@@ -74,5 +74,5 @@
</TABLE>
<br><center><b>Date Generated:</b> 03/01/2012 - 09:27:04</center>
<br><center><b>Date Generated:</b> 03/07/2012 - 09:22:39</center>
</BODY></HTML>
\ No newline at end of file
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/tb1.wcfg 0 → 100644
View file @ 94c99edd
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc_tb_isim_beh1.wdb" id="1" type="auto">
<top_modules>
<top_module name="glbl" />
<top_module name="spiifc_tb" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="19" />
<wvobject fp_name="/spiifc_tb/SPI_MISO" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SPI_MISO</obj_property>
<obj_property name="ObjectShortName">SPI_MISO</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/txMemAddr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">txMemAddr[11:0]</obj_property>
<obj_property name="ObjectShortName">txMemAddr[11:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/txMemData" type="array" db_ref_id="1">
<obj_property name="ElementShortName">txMemData[7:0]</obj_property>
<obj_property name="ObjectShortName">txMemData[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/rcMemAddr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">rcMemAddr[11:0]</obj_property>
<obj_property name="ObjectShortName">rcMemAddr[11:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/rcMemData" type="array" db_ref_id="1">
<obj_property name="ElementShortName">rcMemData[7:0]</obj_property>
<obj_property name="ObjectShortName">rcMemData[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/rcMemWE" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rcMemWE</obj_property>
<obj_property name="ObjectShortName">rcMemWE</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/debug_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">debug_out[7:0]</obj_property>
<obj_property name="ObjectShortName">debug_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/Reset" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">Reset</obj_property>
<obj_property name="ObjectShortName">Reset</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/SysClk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SysClk</obj_property>
<obj_property name="ObjectShortName">SysClk</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/SPI_CLK" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SPI_CLK</obj_property>
<obj_property name="ObjectShortName">SPI_CLK</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/SPI_MOSI" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SPI_MOSI</obj_property>
<obj_property name="ObjectShortName">SPI_MOSI</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/SPI_SS" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SPI_SS</obj_property>
<obj_property name="ObjectShortName">SPI_SS</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/SPI_CLK_en" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SPI_CLK_en</obj_property>
<obj_property name="ObjectShortName">SPI_CLK_en</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/fdRcBytes" type="array" db_ref_id="1">
<obj_property name="ElementShortName">fdRcBytes[31:0]</obj_property>
<obj_property name="ObjectShortName">fdRcBytes[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/fdTxBytes" type="array" db_ref_id="1">
<obj_property name="ElementShortName">fdTxBytes[31:0]</obj_property>
<obj_property name="ObjectShortName">fdTxBytes[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/dummy" type="array" db_ref_id="1">
<obj_property name="ElementShortName">dummy[31:0]</obj_property>
<obj_property name="ObjectShortName">dummy[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/currRcByte" type="array" db_ref_id="1">
<obj_property name="ElementShortName">currRcByte[31:0]</obj_property>
<obj_property name="ObjectShortName">currRcByte[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/rcBytesNotEmpty" type="array" db_ref_id="1">
<obj_property name="ElementShortName">rcBytesNotEmpty[31:0]</obj_property>
<obj_property name="ObjectShortName">rcBytesNotEmpty[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/rcBytesStr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">rcBytesStr[80:1]</obj_property>
<obj_property name="ObjectShortName">rcBytesStr[80:1]</obj_property>
</wvobject>
</wave_config>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/tb2.wcfg 0 → 100644
View file @ 94c99edd
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc_tb2_isim_beh1.wdb" id="1" type="auto">
<top_modules>
<top_module name="glbl" />
<top_module name="spiifc_tb2" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="19" />
<wvobject fp_name="/spiifc_tb2/SPI_MISO" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SPI_MISO</obj_property>
<obj_property name="ObjectShortName">SPI_MISO</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/txMemAddr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">txMemAddr[11:0]</obj_property>
<obj_property name="ObjectShortName">txMemAddr[11:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/txMemData" type="array" db_ref_id="1">
<obj_property name="ElementShortName">txMemData[7:0]</obj_property>
<obj_property name="ObjectShortName">txMemData[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/rcMemAddr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">rcMemAddr[11:0]</obj_property>
<obj_property name="ObjectShortName">rcMemAddr[11:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/rcMemData" type="array" db_ref_id="1">
<obj_property name="ElementShortName">rcMemData[7:0]</obj_property>
<obj_property name="ObjectShortName">rcMemData[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/rcMemWE" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rcMemWE</obj_property>
<obj_property name="ObjectShortName">rcMemWE</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/debug_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">debug_out[7:0]</obj_property>
<obj_property name="ObjectShortName">debug_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/Reset" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">Reset</obj_property>
<obj_property name="ObjectShortName">Reset</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/SysClk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SysClk</obj_property>
<obj_property name="ObjectShortName">SysClk</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/SPI_CLK" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SPI_CLK</obj_property>
<obj_property name="ObjectShortName">SPI_CLK</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/SPI_MOSI" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SPI_MOSI</obj_property>
<obj_property name="ObjectShortName">SPI_MOSI</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/SPI_SS" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SPI_SS</obj_property>
<obj_property name="ObjectShortName">SPI_SS</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/SPI_CLK_en" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SPI_CLK_en</obj_property>
<obj_property name="ObjectShortName">SPI_CLK_en</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/fdRcBytes" type="array" db_ref_id="1">
<obj_property name="ElementShortName">fdRcBytes[31:0]</obj_property>
<obj_property name="ObjectShortName">fdRcBytes[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/fdTxBytes" type="array" db_ref_id="1">
<obj_property name="ElementShortName">fdTxBytes[31:0]</obj_property>
<obj_property name="ObjectShortName">fdTxBytes[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/dummy" type="array" db_ref_id="1">
<obj_property name="ElementShortName">dummy[31:0]</obj_property>
<obj_property name="ObjectShortName">dummy[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/currRcByte" type="array" db_ref_id="1">
<obj_property name="ElementShortName">currRcByte[31:0]</obj_property>
<obj_property name="ObjectShortName">currRcByte[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/rcBytesNotEmpty" type="array" db_ref_id="1">
<obj_property name="ElementShortName">rcBytesNotEmpty[31:0]</obj_property>
<obj_property name="ObjectShortName">rcBytesNotEmpty[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/rcBytesStr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">rcBytesStr[80:1]</obj_property>
<obj_property name="ObjectShortName">rcBytesStr[80:1]</obj_property>
</wvobject>
</wave_config>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/user_logic.cmd_log 0 → 100644
View file @ 94c99edd
xst -intstyle ise -ifn "C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/user_logic.xst" -ofn "C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/user_logic.syr"
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/user_logic.ngc 0 → 100644
View file @ 94c99edd
This diff is collapsed.
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/user_logic.prj 0 → 100644
View file @ 94c99edd
verilog work "../../../../../../src/spi_base/spiifc.v"
verilog work "ipcore_dir/buffermem.v"
verilog work "../../hdl/verilog/user_logic.v"
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/user_logic.syr 0 → 100644
View file @ 94c99edd
This diff is collapsed.
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/user_logic.xst 0 → 100644
View file @ 94c99edd
set -tmpdir "xst/projnav.tmp"
set -xsthdpdir "xst"
run
-ifn user_logic.prj
-ifmt mixed
-ofn user_logic
-ofmt NGC
-p xc6slx45-2-csg324
-top user_logic
-opt_mode Speed
-opt_level 1
-power NO
-iuc NO
-keep_hierarchy No
-netlist_hierarchy As_Optimized
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-sd {"ipcore_dir" }
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case Maintain
-slice_utilization_ratio 100
-bram_utilization_ratio 100
-dsp_utilization_ratio 100
-lc Auto
-reduce_control_sets Auto
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-fsm_style LUT
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-shreg_extract YES
-rom_style Auto
-auto_bram_packing NO
-resource_sharing YES
-async_to_sync NO
-shreg_min_size 2
-use_dsp48 Auto
-iobuf YES
-max_fanout 100000
-bufg 16
-register_duplication YES
-register_balancing No
-optimize_primitives NO
-use_clock_enable Auto
-use_sync_set Auto
-use_sync_reset Auto
-iob Auto
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/webtalk_impact.xml 0 → 100644
View file @ 94c99edd
<?xml version="1.0" encoding="UTF-8" ?>
<document>
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="impact" timeStamp="Tue Mar 06 15:24:19 2012">
<section name="Project Information" visible="false">
<property name="ProjectID" value="5ea5de4132cd436698ae1e90d83ce606"/>
<property name="ProjectIteration" value="1"/>
</section>
<section name="iMPACT Project Info" visible="true">
<property name="Use Project File" value="Yes"/>
<property name="Project Entry" value="ise"/>
<property name="OS Name" value="Microsoft Windows 7 (64 Bit)"/>
<property name="User Lic. Info" value="179841373_174164856_206270303_042"/>
</section>
<section name="iMPACT One Step SVF File Mode" visible="true">
<item name="Chain Summary">
<property name="Number of device" value="1"/>
<property name="Number of Xilinx device" value="1"/>
<property name="Number of Non-Xilinx device" value="0"/>
</item>
<item name="Chain Description">
<property name="Device1" value="spartan6"/>
<property name="Part1" value="xc6slx45"/>
</item>
<item name="Boundary Scan Operations Statistics">
<property name="BSCAN Operation" value="Program -p 0
"/>
<property name="BSCAN Operation" value="Program -p 0
"/>
<property name="BSCAN Operation" value="Program -p 0
"/>
</item>
<item name="Cable Summary">
<property name="Cable Type" value="Platform Cable USB"/>
<property name="Cable Speed" value="6 MHz"/>
<property name="Port" value="usb-hs"/>
<property name="Local_Server_Mode" value="Local"/>
</item>
</section>
</application>
</document>
projnav/xps/pcores/spiifc_v1_00_a/hdl/verilog/spiifc.v 0 → 100644
View file @ 94c99edd
This diff is collapsed.
projnav/xps/pcores/spiifc_v1_00_a/hdl/verilog/user_logic.v
View file @ 94c99edd
......@@ -52,6 +52,10 @@ module user_logic
(
// -- ADD USER PORTS BELOW THIS LINE ---------------
// --USER ports added here
SPI_CLK,
SPI_MOSI,
SPI_MISO,
SPI_SS,
// -- ADD USER PORTS ABOVE THIS LINE ---------------
// -- DO NOT EDIT BELOW THIS LINE ------------------
......@@ -93,6 +97,10 @@ parameter C_NUM_INTR = 1;
// -- ADD USER PORTS BELOW THIS LINE -----------------
// --USER ports added here
input SPI_CLK;
input SPI_MOSI;
output SPI_MISO;
input SPI_SS;
// -- ADD USER PORTS ABOVE THIS LINE -----------------
// -- DO NOT EDIT BELOW THIS LINE --------------------
......@@ -125,7 +133,6 @@ output [0 : C_NUM_INTR-1] IP2Bus_IntrEvent;
// --USER nets declarations added here, as needed for user logic
// Memmap memory logic lines
wire [0 : C_NUM_MEM-1 ] mem_ena; // Port A: spiifc
wire [0 : C_NUM_MEM-1 ] mem_enb; // Port B: sysbus/dma
wire [0 : C_NUM_MEM-1 ] mem_web;
wire [0 : C_NUM_MEM-1] mem_write;
......@@ -133,6 +140,7 @@ output [0 : C_NUM_INTR-1] IP2Bus_IntrEvent;
reg [0 : C_NUM_MEM-1 ] mem_read_prev;
// mosiMem (mem0): data received from master
wire mosiMem_wea;
wire [0 : 11] mosiMem_addra;
wire [0 : 7 ] mosiMem_dina;
wire [0 : 9 ] mosiMem_addrb;
......@@ -172,14 +180,10 @@ output [0 : C_NUM_INTR-1] IP2Bus_IntrEvent;
// --USER logic implementation added here
// memory interface logic
assign mem_ena = 2'd0; // TODO: interface with spiifc
assign mem_enb = mem_write | mem_read /*& {C_NUM_MEM{Bus2IP_RdReq | Bus2IP_WrReq}}*/;
assign mem_web = mem_write;
assign mosiMem_addra = 12'h000; // TODO: interface with spiifc
assign mosiMem_dina = 8'd00; // TODO: interface with spiifc
assign mosiMem_addrb = Bus2IP_Addr[20:29];
assign mosiMem_dinb = Bus2IP_Data;
assign misoMem_addra = 12'h000; // TODO: interface with spiifc
assign misoMem_addrb = Bus2IP_Addr[20:29];
assign misoMem_dinb = Bus2IP_Data;
......@@ -192,9 +196,9 @@ output [0 : C_NUM_INTR-1] IP2Bus_IntrEvent;
// Mem0: Memory buffer storing data coming from master
buffermem mosiMem (
.clka(Bus2IP_Clk), // input clka
.ena(mem_ena[0]), // input ena
.wea(1'b1), // Always writing, never reading
.clka(SPI_CLK), // input clka
.ena(1'b1), // input ena
.wea(mosiMem_wea), // Always writing, never reading
.addra({mosiMem_addra}), // input [11 : 0] addra
.dina({mosiMem_dina}), // input [7 : 0] dina
// .douta(mosiMem_douta), // NEVER USED: output [7 : 0] douta
......@@ -208,8 +212,8 @@ output [0 : C_NUM_INTR-1] IP2Bus_IntrEvent;
// Mem1: Memory buffer storing data to send to master
buffermem misoMem (
.clka(Bus2IP_Clk), // input clka
.ena(mem_ena[1]), // input ena
.clka(SPI_CLK), // input clka
.ena(1'b1), // input ena
.wea(1'b0), // Always reading, never writing
.addra({misoMem_addra}), // input [11 : 0] addra
// .dina(dina), // input [7 : 0] dina
......@@ -221,6 +225,20 @@ output [0 : C_NUM_INTR-1] IP2Bus_IntrEvent;
.dinb({misoMem_dinb}), // input [31 : 0] dinb
.doutb({misoMem_doutb}) // output [31 : 0] doutb
);
spiifc spi (
.Reset(Bus2IP_Reset),
.SysClk(Bus2IP_Clk),
.SPI_CLK(SPI_CLK),
.SPI_MISO(SPI_MISO),
.SPI_MOSI(SPI_MOSI),
.SPI_SS(SPI_SS),
.txMemAddr(misoMem_addra),
.txMemData(misoMem_douta),
.rcMemAddr(mosiMem_addra),
.rcMemData(mosiMem_dina),
.rcMemWE(mosiMem_wea)
);
// ------------------------------------------------------
// Example code to read/write user logic slave model s/w accessible registers
......
projnav/xps/pcores/spiifc_v1_00_a/hdl/vhdl/spiifc.vhd
View file @ 94c99edd
......@@ -171,7 +171,10 @@ entity spiifc is
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
SPI_CLK : in std_logic;
SPI_MOSI : in std_logic;
SPI_MISO : out std_logic;
SPI_SS : in std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
......@@ -414,7 +417,10 @@ architecture IMP of spiifc is
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
SPI_CLK : in std_logic;
SPI_MOSI : in std_logic;
SPI_MISO : out std_logic;
SPI_SS : in std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
......@@ -589,7 +595,10 @@ begin
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
--USER ports mapped here
SPI_CLK => SPI_CLK,
SPI_MOSI => SPI_MOSI,
SPI_MISO => SPI_MISO,
SPI_SS => SPI_SS,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
......
projnav/xps/system.mhs
View file @ 94c99edd
......@@ -20,6 +20,10 @@
PORT fpga_0_Push_Buttons_5Bits_GPIO_IO_I_pin = fpga_0_Push_Buttons_5Bits_GPIO_IO_I_pin, DIR = I, VEC = [0:4]
PORT fpga_0_clk_1_sys_clk_pin = CLK_S, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
PORT fpga_0_rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 0
PORT spiifc_0_SPI_CLK_pin = spiifc_0_SPI_CLK, DIR = I, SIGIS = CLK, CLK_FREQ = 50000000
PORT spiifc_0_SPI_MISO_pin = spiifc_0_SPI_MISO, DIR = O
PORT spiifc_0_SPI_MOSI_pin = spiifc_0_SPI_MOSI, DIR = I
PORT spiifc_0_SPI_SS_pin = spiifc_0_SPI_SS, DIR = I
BEGIN microblaze
......@@ -170,6 +174,10 @@ BEGIN spiifc
PARAMETER C_MEM1_BASEADDR = 0x85011000
PARAMETER C_MEM1_HIGHADDR = 0x85011FFF
BUS_INTERFACE SPLB = mb_plb
PORT SPI_CLK = spiifc_0_SPI_CLK
PORT SPI_MOSI = spiifc_0_SPI_MOSI
PORT SPI_MISO = spiifc_0_SPI_MISO
PORT SPI_SS = spiifc_0_SPI_SS
END
BEGIN xps_central_dma
......
src/spi_base/spiifc.v
View file @ 94c99edd
......@@ -218,9 +218,9 @@ module spiifc(
rcMemAddrNext <= rcMemAddr + 1;
rcMemWEReg <= 1;
// end else if (`STATE_WRITING == state) begin
// txBitAddr <= 3'd7;
// stateReg <= `STATE_WRITING;
end else if (`STATE_WRITING == state) begin
txBitAddr <= 3'd7;
stateReg <= `STATE_WRITING;
end
end else begin
......
src/spi_base/spiifc_fastclock.v 0 → 100644
View file @ 94c99edd
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:46:12 03/02/2012
// Design Name:
// Module Name: spiifc
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module spiifc(
Reset,
SysClk,
SPI_CLK,
SPI_MISO,
SPI_MOSI,
SPI_SS,
txMemAddr,
txMemData,
rcMemAddr,
rcMemData,
rcMemWE,
debug_out
);
//
// Parameters
//
parameter AddrBits = 12;
//
// Defines
//
`define CMD_READ_START 8'd1
`define CMD_READ_MORE 8'd2
`define CMD_WRITE_START 8'd3
`define CMD_WRITE_MORE 8'd4
`define CMD_INTERRUPT 8'd5
`define STATE_GET_CMD 8'd0
`define STATE_READING 8'd1
`define STATE_WRITING 8'd2
`define STATE_WRITE_INTR 8'd3
//
// Input/Outputs
//
input Reset;
input SysClk;
input SPI_CLK;
output SPI_MISO; // outgoing (from respect of this module)
input SPI_MOSI; // incoming (from respect of this module)
input SPI_SS;
output [AddrBits-1:0] txMemAddr; // outgoing data
input [7:0] txMemData;
output [AddrBits-1:0] rcMemAddr; // incoming data
output [7:0] rcMemData;
output rcMemWE;
output [7:0] debug_out;
//
// Registers
//
reg prev_spiClk; // Value of SPI_CLK during last SysClk cycle
reg prev_spiSS; // Value of SPI_SS during last SysClk cycle
reg [7:0] state_reg; // Register backing the 'state' wire
reg [7:0] rcByte_reg; // Register backing 'rcByte'
reg [2:0] rcBitIndex_reg; // Register backing 'rcBitIndex'
reg [AddrBits-1:0] rcMemAddr_reg; // Byte addr to write MOSI data to
//
// Wires
//
wire risingSpiClk; // Did the SPI_CLK rise since last SysClk cycle?
wire validSpiBit; // Are the SPI MOSI/MISO bits new and valid?
reg state; // Current state in the module's state machine (always @* effectively wire)
wire rcByteValid; // rcByte is valid and new
wire [7:0] rcByte; // Byte received from master
wire [2:0] rcBitIndex; // Bit of rcByte to write to next
// Detect new valid bit
always @(posedge SysClk) begin
prev_spiClk <= SPI_CLK;
end
assign risingSpiClk = SPI_CLK & (~prev_spiClk);
assign validSpiBit = risingSpiClk & (~SPI_SS);
// Detect new SPI packet (SS dropped low)
always @(posedge SysClk) begin
prev_spiSS <= SPI_SS;
end
assign packetStart = prev_spiSS & (~SPI_SS);
// Build incoming byte
always @(posedge SysClk) begin
if (validSpiBit) begin
rcByte_reg[rcBitIndex] <= SPI_MOSI;
rcBitIndex_reg <= (rcBitIndex > 0 ? rcBitIndex - 1 : 7);
end else begin
rcBitIndex_reg <= rcBitIndex;
end
end
assign rcBitIndex = (Reset || packetStart ? 7 : rcBitIndex_reg);
assign rcByte = {rcByte_reg[7:1], SPI_MOSI};
assign rcByteValid = (validSpiBit && rcBitIndex == 0 ? 1 : 0);
// Incoming MOSI data buffer management
assign rcMemAddr = rcMemAddr_reg;
assign rcMemData = rcByte;
assign rcMemWE = (state == `STATE_READING && rcByteValid ? 1 : 0);
always @(posedge SysClk) begin
if (Reset || (`STATE_GET_CMD == state && rcByteValid)) begin
rcMemAddr_reg <= 0;
end else if (rcMemWE) begin
rcMemAddr_reg <= rcMemAddr + 1;
end else begin
rcMemAddr_reg <= rcMemAddr;
end
end
// State machine
always @(*) begin
if (Reset || packetStart) begin
state <= `STATE_GET_CMD;
end else if (state_reg == `STATE_GET_CMD && rcByteValid) begin
state <= rcByte;
end else begin
state <= state_reg;
end
end
always @(posedge SysClk) begin
if (`STATE_GET_CMD == state && rcByteValid) begin
if (`CMD_READ_START == rcByte) begin
state_reg <= `STATE_READING;
end else if (`CMD_READ_MORE == rcByte) begin
state_reg <= `STATE_READING;
end else if (`CMD_WRITE_START == rcByte) begin
state_reg <= `STATE_WRITING;
end else if (`CMD_WRITE_MORE == rcByte) begin
state_reg <= `STATE_WRITING;
end else if (`CMD_INTERRUPT == rcByte) begin
// TODO: NYI
end
end else begin
state_reg <= state;
end
end
endmodule
src/spi_base/spiwrap.v
View file @ 94c99edd
......@@ -59,19 +59,19 @@ always @(posedge SysClk) begin
end
end
spimem spiMemTx (
.clka(SysClk), // input clka
.ena(1'b1), // input ena
.wea(initMem), // input [0 : 0] wea
.addra(initMemAddr), // input [9 : 0] addra
.dina(initMemData), // input [31 : 0] dina
.douta(douta_dummy), // output [31 : 0] douta
.clkb(spi_clk), // input clkb
.enb(1'b1), // input enb
.web(1'b0), // input [0 : 0] web
.addrb(spi_addr), // input [11 : 0] addrb
.dinb(8'h00), // input [7 : 0] dinb
.doutb(spi_data) // output [7 : 0] doutb
buffermem spiMemTx (
.clka(spi_clk), // input clkb
.ena(1'b1), // input enb
.wea(1'b0), // input [0 : 0] web
.addra(spi_addr), // input [11 : 0] addrb
.dina(8'h00), // input [7 : 0] dinb
.douta(spi_data), // output [7 : 0] doutb
.clkb(SysClk), // input clka
.enb(1'b1), // input ena
.web(initMem), // input [0 : 0] wea
.addrb(initMemAddr), // input [9 : 0] addra
.dinb(initMemData), // input [31 : 0] dina
.doutb(douta_dummy) // output [31 : 0] douta
);
wire spi_rcMem_we;
......@@ -79,18 +79,18 @@ wire [11:0] spi_rcMem_addr;
wire [ 7:0] spi_rcMem_data;
wire [ 7:0] debug_out;
wire [ 7:0] spi_rcMem_doutb_dummy;
spimem spiMemRc (
.clka(SysClk),
buffermem spiMemRc (
.clka(spi_clk),
.ena(1'b1),
.wea(1'b0),
.addra(10'h001),
.douta(rcMem_douta),
.clkb(spi_clk),
.wea(spi_rcMem_we),
.addra(spi_rcMem_addr),
.dina(spi_rcMem_data),
.douta(spi_rcMem_doutb_dummy),
.clkb(SysClk),
.enb(1'b1),
.web(spi_rcMem_we),
.addrb(spi_rcMem_addr),
.dinb(spi_rcMem_data),
.doutb(spi_rcMem_doutb_dummy)
.web(1'b0),
.addrb(10'h001),
.doutb(rcMem_douta)
);
spiifc mySpiIfc (
......@@ -108,8 +108,6 @@ spiifc mySpiIfc (
.debug_out(debug_out)
);
assign leds = rcMem_douta[31:24];
assign leds = /*rcMem_douta[31:24]*/ debug_out;
endmodule
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment