Skip to content
Projects
Groups
Snippets
Help
Loading...
Help
Contribute to GitLab
Sign in
Toggle navigation
V
vSPI
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
0
Issues
0
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Jobs
Schedules
Charts
Wiki
Wiki
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Jobs
Commits
Issue Boards
Open sidebar
rasky
vSPI
Commits
7c087d9a
Commit
7c087d9a
authored
Mar 14, 2012
by
Mike Lyons
Browse files
Options
Browse Files
Download
Plain Diff
Merge branch 'fastclock' of github.com:mjlyons/vSPI into xps_proj
parents
841aa19d
0c381349
Changes
2
Hide whitespace changes
Inline
Side-by-side
Showing
2 changed files
with
83 additions
and
23 deletions
+83
-23
spilib.py
scripts/master/spilib.py
+29
-16
spitest.py
scripts/master/spitest.py
+54
-7
No files found.
scripts/master/spilib.py
View file @
7c087d9a
...
...
@@ -7,7 +7,7 @@ class SpiComm:
_port
=
0
# Change if using multiple Cheetahs
_mode
=
3
# spiifc SPI mode
_bitrate
=
2
80
00
# kbps
_bitrate
=
2
79
00
# kbps
handle
=
None
# handle to Cheetah SPI
...
...
@@ -24,8 +24,6 @@ class SpiComm:
ch_spi_configure
(
self
.
handle
,
(
self
.
_mode
>>
1
),
self
.
_mode
&
1
,
CH_SPI_BITORDER_MSB
,
0x0
)
ch_spi_bitrate
(
self
.
handle
,
self
.
_bitrate
)
#ch_spi_queue_clear(self.handle)
#ch_spi_queue_oe(self.handle, 1)
def
__del__
(
self
):
ch_close
(
self
.
handle
)
...
...
@@ -36,34 +34,49 @@ class SpiComm:
actualByteCount
=
0
ch_spi_queue_clear
(
self
.
handle
)
ch_spi_queue_oe
(
self
.
handle
,
1
)
#ch_spi_queue_ss(self.handle, 0x2)
#ch_spi_queue_byte(self.handle, 1, 0xCC)
ch_spi_queue_ss
(
self
.
handle
,
0x1
)
ch_spi_queue_byte
(
self
.
handle
,
1
,
1
)
# Sending data to slave
for
byte
in
byteArray
:
ch_spi_queue_byte
(
self
.
handle
,
1
,
byte
)
#ch_spi_queue_ss(self.handle, 0x2)
#ch_spi_queue_byte(self.handle, 1, 0xCC)
ch_spi_queue_ss
(
self
.
handle
,
0
)
ch_spi_queue_oe
(
self
.
handle
,
0
)
(
actualByteCount
,
data_in
)
=
ch_spi_batch_shift
(
self
.
handle
,
byteCount
)
def
RecvFromSlave
(
self
,
byteCount
):
def
RecvFromSlave
(
self
,
command
,
byteCount
):
totalByteCount
=
byteCount
+
1
# Extra byte for cmd
data_in
=
array
(
'B'
,
[
0
for
i
in
range
(
totalByteCount
)])
actualByteCount
=
0
ch_spi_queue_clear
(
self
.
handle
)
ch_spi_queue_oe
(
self
.
handle
,
1
)
#ch_spi_queue_ss(self.handle, 0x2)
#ch_spi_queue_byte(self.handle, 1, 0xCC)
ch_spi_queue_ss
(
self
.
handle
,
0x1
)
ch_spi_queue_byte
(
self
.
handle
,
1
,
3
)
# Receive data from slave
ch_spi_queue_byte
(
self
.
handle
,
byteCount
,
0x56
)
#ch_spi_queue_ss(self.handle, 0x2)
#ch_spi_queue_byte(self.handle, 1, 0xCC)
ch_spi_queue_ss
(
self
.
handle
,
1
)
ch_spi_queue_byte
(
self
.
handle
,
1
,
command
)
# Receive data from slave
ch_spi_queue_byte
(
self
.
handle
,
byteCount
,
0xFF
)
ch_spi_queue_ss
(
self
.
handle
,
0x0
)
ch_spi_queue_oe
(
self
.
handle
,
0
)
(
actualByteCount
,
data_in
)
=
ch_spi_batch_shift
(
self
.
handle
,
totalByteCount
)
return
data_in
[
1
:]
def
ReadMemory
(
self
,
byteCount
):
return
self
.
RecvFromSlave
(
0x3
,
byteCount
)
def
WriteMemory
(
self
,
bytesToWrite
):
bytePacket
=
[
0x01
]
bytePacket
.
extend
(
bytesToWrite
)
return
self
.
SendToSlave
(
bytePacket
)
def
ReadReg
(
self
,
regId
):
commandCode
=
0x80
+
regId
regValBytes
=
self
.
RecvFromSlave
(
commandCode
,
4
)
regValWord
=
0
for
regValByte
in
regValBytes
:
regValWord
=
(
regValWord
*
256
)
+
regValByte
return
regValWord
def
WriteReg
(
self
,
regId
,
value
):
commandCode
=
0xC0
+
regId
bytesToSend
=
[
commandCode
,
0
,
0
,
0
,
0
]
for
sendByteId
in
range
(
4
,
0
,
-
1
):
bytesToSend
[
sendByteId
]
=
value
%
256
value
=
value
/
256
self
.
SendToSlave
(
bytesToSend
)
scripts/master/spitest.py
View file @
7c087d9a
...
...
@@ -41,7 +41,7 @@ def MultiBytePacketSendTest():
spi
.
SendToSlave
(
dataToSend
)
#
# LoopbackTest:
#
Mem
LoopbackTest:
#
# Sends randomly generated blocks of data over SPI, then reads back
# data. Assumes that slave is using a common read and write buffer
...
...
@@ -49,10 +49,10 @@ def MultiBytePacketSendTest():
# data is identical to the one sent. The test will run continuously
# until a received packet does not match the sent packet.
#
def
LoopbackTest
():
def
Mem
LoopbackTest
():
passCount
=
0
loopbackErrors
=
0
packetByteSize
=
40
96
packetByteSize
=
40
00
while
loopbackErrors
==
0
:
print
(
"PassCount:
%
d"
%
(
passCount
))
...
...
@@ -66,11 +66,11 @@ def LoopbackTest():
# Send some data to the slave
sys
.
stdout
.
write
(
"Sending data to slave..."
);
spi
.
SendToSlave
(
dataToSend
)
spi
.
WriteMemory
(
dataToSend
)
sys
.
stdout
.
write
(
"done!
\n
"
)
# Receive some data from the slave
recvData
=
spi
.
Re
cvFromSlave
(
packetByteSize
)
recvData
=
spi
.
Re
adMemory
(
packetByteSize
)
# Make sure bytes sent match bytes received
if
len
(
recvData
)
!=
packetByteSize
:
...
...
@@ -90,6 +90,51 @@ def LoopbackTest():
# Print number of passed tests before failure
print
(
"PassCount:
%
d"
%
(
passCount
))
#
# RegLoopbackTest:
#
# Randomly writes and reads to vSPI's register and makes sure
# values are as expected
#
def
RegLoopbackTest
():
# First, zero out all registers
print
(
"Zeroing all registers..."
)
for
regId
in
range
(
16
):
spi
.
WriteReg
(
regId
=
regId
,
value
=
0
)
# Second, check that all registers are zeroed
print
(
"Checking all registers are zeroed..."
)
for
regId
in
range
(
16
):
regVal
=
spi
.
ReadReg
(
regId
)
if
(
0
!=
regVal
):
sys
.
stdout
.
write
(
"ERROR: Reg
%
d was not zeroed (was 0x
%08
x)
\n
"
%
\
(
regId
,
regVal
))
return
# Local mapping of expected register values
expectedRegs
=
list
(
0
for
i
in
range
(
16
))
# Random read and writes
passCount
=
0
while
(
True
):
print
(
""
)
regWriteId
=
random
.
randint
(
0
,
15
)
regReadId
=
random
.
randint
(
0
,
15
)
regWriteVal
=
random
.
randint
(
0
,
0xFFFFFFFF
)
print
(
"Writing Reg
%
d=0x
%08
x"
%
(
regWriteId
,
regWriteVal
))
spi
.
WriteReg
(
regId
=
regWriteId
,
value
=
regWriteVal
)
expectedRegs
[
regWriteId
]
=
regWriteVal
print
(
"Checking Reg
%
d==0x
%08
x"
%
(
regReadId
,
expectedRegs
[
regReadId
]))
regReadVal
=
spi
.
ReadReg
(
regReadId
)
if
(
expectedRegs
[
regReadId
]
!=
regReadVal
):
sys
.
stderr
.
write
(
"ERROR: Reg
%
d - expected=0x
%08
x, actual=0x
%08
x
\n
"
%
\
(
expectedRegs
[
regReadId
],
regReadVal
))
return
passCount
=
passCount
+
1
print
(
"PASS [
%
d]"
%
(
passCount
))
#
# PrintCliSyntax:
...
...
@@ -103,7 +148,8 @@ Syntax:
Valid tests (case sensitive):
- SingleBytePacketsSend
- MultiBytePacketSend
- Loopback
- MemLoopback
- RegLoopback
"""
#
...
...
@@ -119,7 +165,8 @@ if len(sys.argv) < 2 or len(sys.argv) > 3:
cliTest
=
sys
.
argv
[
1
]
testMapping
=
{
'SingleBytePacketsSend'
:
[
SingleBytePacketsSendTest
],
'MultiBytePacketSend'
:
[
MultiBytePacketSendTest
],
'Loopback'
:
[
LoopbackTest
]}
'MemLoopback'
:
[
MemLoopbackTest
],
'RegLoopback'
:
[
RegLoopbackTest
]}
if
cliTest
not
in
testMapping
:
sys
.
stderr
.
write
(
'
%
s is not a valid test.
\n
'
%
(
cliTest
,))
PrintCliSyntax
()
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment