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Commit 841aa19d authored by Mike Lyons's avatar Mike Lyons
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Support for read and write registers on vSPI slave implemented, tested in testbench and on board

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projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/fuse.xmsgs
View file @ 841aa19d
......@@ -5,8 +5,5 @@
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="HDLCompiler" num="1016" delta="unknown" >"C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/../../../../../../test/spi_base/spiifc_writereg_tb.v" Line 45: Port <arg fmt="%s" index="1">regAddr</arg> is not connected to this instance
</msg>
</messages>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/fuseRelaunch.cmd
View file @ 841aa19d
-intstyle "ise" -incremental -lib "unisims_ver" -lib "unimacro_ver" -lib "xilinxcorelib_ver" -lib "secureip" -o "C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc_writereg_tb_isim_beh.exe" -prj "C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc_writereg_tb_beh.prj" "spiifc_writereg_tb" "work.glbl"
-intstyle "ise" -incremental -lib "unisims_ver" -lib "unimacro_ver" -lib "xilinxcorelib_ver" -lib "secureip" -o "C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc_writereg_tb_isim_beh.exe" -prj "C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc_writereg_tb_beh.prj" "work.spiifc_writereg_tb" "work.glbl"
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/iseconfig/spiifc.projectmgr
View file @ 841aa19d
......@@ -11,7 +11,6 @@
<ClosedNode>/spiifc - IMP C:|Users|mjlyons|workspace|vSPI|projnav|xps|pcores|spiifc_v1_00_a|hdl|vhdl|spiifc.vhd/PLBV46_SLAVE_BURST_I - plbv46_slave_burst - implementation</ClosedNode>
<ClosedNode>/spiifc - IMP C:|Users|mjlyons|workspace|vSPI|projnav|xps|pcores|spiifc_v1_00_a|hdl|vhdl|spiifc.vhd/PLBV46_SLAVE_BURST_I - plbv46_slave_burst - implementation/I_SLAVE_ATTACHMENT - plb_slave_attachment - implementation</ClosedNode>
<ClosedNode>/spiifc_tb2 C:|Users|mjlyons|workspace|vSPI|test|spi_base|spiifc_tb2.v</ClosedNode>
<ClosedNode>/spiloop C:|Users|mjlyons|workspace|vSPI|src|spi_base|spiloop.v</ClosedNode>
<ClosedNode>/spiwrap C:|Users|mjlyons|workspace|vSPI|src|spi_base|spiwrap.v</ClosedNode>
</ClosedNodes>
<SelectedItems>
......@@ -19,7 +18,7 @@
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000202000000010000000100000064000000be000000020000000000000000000000000200000064ffffffff000000810000000300000002000000be0000000100000003000000000000000100000003</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000175000000020000000000000000000000000200000064ffffffff000000810000000300000002000001750000000100000003000000000000000100000003</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
<CurrentItem>spiloop (C:/Users/mjlyons/workspace/vSPI/src/spi_base/spiloop.v)</CurrentItem>
</ItemView>
......@@ -91,29 +90,29 @@
<ClosedNode>User Constraints</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem></SelectedItem>
<SelectedItem>Generate Programming File</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f8000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem>
<CurrentItem>Generate Programming File</CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_XCO" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
</ClosedNodes>
<SelectedItems>
<SelectedItem></SelectedItem>
<SelectedItem/>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f8000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem>
<CurrentItem/>
</ItemView>
<SourceProcessView>000000ff00000000000000020000011b0000011b01000000050100000002</SourceProcessView>
<CurrentView>Behavioral Simulation</CurrentView>
<CurrentView>Implementation</CurrentView>
<ItemView engineview="BehavioralSim" guiview="Source" compilemode="AutoCompile" >
<ClosedNodes>
<ClosedNodesVersion>2</ClosedNodesVersion>
......@@ -166,13 +165,13 @@
<ClosedNode>User Constraints</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem></SelectedItem>
<SelectedItem/>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f8000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem>
<CurrentItem/>
</ItemView>
<ItemView engineview="BehavioralSim" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
<ClosedNodes>
......@@ -193,12 +192,12 @@
<ClosedNodesVersion>1</ClosedNodesVersion>
</ClosedNodes>
<SelectedItems>
<SelectedItem></SelectedItem>
<SelectedItem/>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f8000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem>
<CurrentItem/>
</ItemView>
</Project>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/iseconfig/spiloop.xreport
View file @ 841aa19d
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2012-03-07T21:28:58</DateModified>
<ModuleName>spiifc</ModuleName>
<DateModified>2012-03-13T14:31:01</DateModified>
<ModuleName>spiloop</ModuleName>
<SummaryTimeStamp>2012-03-07T21:27:48</SummaryTimeStamp>
<SavedFilePath>C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/iseconfig/spiloop.xreport</SavedFilePath>
<ImplementationReportsDirectory>C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav\</ImplementationReportsDirectory>
......
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/par_usage_statistics.html deleted 100644 → 0
View file @ 5471678e
<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<xtag-section name="ParStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>Par Statistics</B></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>121</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>419</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>419</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>384</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>5.0 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>6.0 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>6.2 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>7.8 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>8.1 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>8.1 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>8.1 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>8.1 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>8.1 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>8.1 sec</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>2.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>6.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>0.7</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>2.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>6.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>3.5</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0154</xtag-par-property-value></TD></TR>
</xtag-section>
</TABLE>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/rc-bytes-writereg.txt
View file @ 841aa19d
......@@ -2,4 +2,9 @@ C3
F0
0F
5C
C5
\ No newline at end of file
C5
83
00
00
00
00
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc.gise
View file @ 841aa19d
......@@ -27,11 +27,6 @@
<file xil_pn:fileType="FILE_NCD" xil_pn:name="spiwrap_guide.ncd" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1331173742" xil_pn:in_ck="241267088593728842" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1331173742">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
</transforms>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
</generated_project>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc.xise
View file @ 841aa19d
......@@ -202,6 +202,7 @@
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Custom Waveform Configuration File Behav" xil_pn:value="tb_writereg.wcfg" xil_pn:valueState="non-default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx45" xil_pn:valueState="non-default"/>
......@@ -438,7 +439,7 @@
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
......
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiloop_guide.ncd
View file @ 841aa19d
This source diff could not be displayed because it is too large. You can view the blob instead.
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/tb_writereg.wcfg
View file @ 841aa19d
......@@ -10,7 +10,7 @@
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="30" />
<WVObjectSize size="33" />
<wvobject fp_name="/spiifc_writereg_tb/SPI_MISO" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SPI_MISO</obj_property>
<obj_property name="ObjectShortName">SPI_MISO</obj_property>
......@@ -151,4 +151,19 @@
<obj_property name="ObjectShortName">rcWord[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_writereg_tb/uut/regReadByte_oreg" type="array" db_ref_id="1">
<obj_property name="ElementShortName">regReadByte_oreg[7:0]</obj_property>
<obj_property name="ObjectShortName">regReadByte_oreg[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_writereg_tb/uut/txBitIndex" type="array" db_ref_id="1">
<obj_property name="ElementShortName">txBitIndex[2:0]</obj_property>
<obj_property name="ObjectShortName">txBitIndex[2:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_writereg_tb/uut/txBitIndex_reg" type="array" db_ref_id="1">
<obj_property name="ElementShortName">txBitIndex_reg[2:0]</obj_property>
<obj_property name="ObjectShortName">txBitIndex_reg[2:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
</wave_config>
scripts/update-tb-vectors.sh 0 → 100644
View file @ 841aa19d
#!/bin/sh
cp ../test/spi_base/rc-bytes*.txt ../projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/
src/spi_base/spiifc.v
View file @ 841aa19d
......@@ -114,14 +114,15 @@ reg [RegAddrBits-1:0] regAddr_reg; // Address of register to read/write to
//
// Wires
//
wire risingSpiClk; // Did the SPI_CLK rise since last SysClk cycle?
wire validSpiBit; // Are the SPI MOSI/MISO bits new and valid?
reg [7:0] state; // Current state in the module's state machine (always @* effectively wire)
wire rcByteValid; // rcByte is valid and new
wire [7:0] rcByte; // Byte received from master
wire [2:0] rcBitIndex; // Bit of rcByte to write to next
reg [2:0] txBitIndex; // bit of txByte to send to master next
reg [AddrBits-1:0] txMemAddr_oreg; // Wirereg piped to txMemAddr output
wire risingSpiClk; // Did the SPI_CLK rise since last SysClk cycle?
wire validSpiBit; // Are the SPI MOSI/MISO bits new and valid?
reg [7:0] state; // Current state in the module's state machine (always @* effectively wire)
wire rcByteValid; // rcByte is valid and new
wire [7:0] rcByte; // Byte received from master
wire [2:0] rcBitIndex; // Bit of rcByte to write to next
reg [2:0] txBitIndex; // bit of txByte to send to master next
reg [AddrBits-1:0] txMemAddr_oreg; // Wirereg piped to txMemAddr output
reg [7:0] regReadByte_oreg; // Which byte of the reg word we're reading out master
// Save buffered SPI inputs
always @(posedge SysClk) begin
......@@ -172,14 +173,18 @@ end
// Outgoing MISO data buffer management
always @(*) begin
if (Reset || (state == `STATE_GET_CMD && rcByteValid && rcByte == `CMD_WRITE_START)) begin
if (Reset || (state == `STATE_GET_CMD && rcByteValid &&
(rcByte == `CMD_WRITE_START ||
rcByte[`CMD_REG_BIT:`CMD_REG_WE_BIT] == 2'b11)
)) begin
txBitIndex <= 3'd7;
txMemAddr_oreg <= 0;
end else begin
txBitIndex <= txBitIndex_reg;
//txMemAddr_oreg <= txMemAddr_reg;
if (state == `STATE_WRITING && validSpiBit && txBitIndex == 0) begin
if ((state == `STATE_WRITING || state == `STATE_SEND_WORD) &&
validSpiBit && txBitIndex == 0) begin
txMemAddr_oreg <= txMemAddr_reg + 1;
end else begin
txMemAddr_oreg <= txMemAddr_reg;
......@@ -188,7 +193,7 @@ always @(*) begin
end
end
always @(posedge SysClk) begin
if (validSpiBit && state == `STATE_WRITING) begin
if (validSpiBit && (state == `STATE_WRITING || state == `STATE_SEND_WORD)) begin
txBitIndex_reg <= (txBitIndex == 0 ? 7 : txBitIndex - 1);
end else begin
txBitIndex_reg <= txBitIndex;
......@@ -202,7 +207,7 @@ always @(posedge SysClk) begin
// end
end
assign txMemAddr = txMemAddr_oreg;
assign SPI_MISO = txMemData[txBitIndex];
assign SPI_MISO = (state == `STATE_SEND_WORD ? regReadByte_oreg[txBitIndex] : txMemData[txBitIndex]);
// State machine
always @(*) begin
......@@ -228,7 +233,6 @@ always @(posedge SysClk) begin
end else if (rcByte[`CMD_REG_BIT] != 0) begin
// Register access
rcWordByteId <= 0;
regAddr_reg <= rcByte & `CMD_REG_ID_MASK;
command <= `CMD_REG_BASE; // Write reg Read reg
state_reg <= (rcByte[`CMD_REG_WE_BIT] ? `STATE_BUILD_WORD : `STATE_SEND_WORD);
end else if (`CMD_INTERRUPT == rcByte) begin
......@@ -246,16 +250,32 @@ always @(posedge SysClk) begin
rcWordByteId <= 3;
end else if (3 == rcWordByteId) begin
rcWord[7:0] <= rcByte;
state_reg <= `STATE_GET_CMD;
end
end else if (`STATE_SEND_WORD == state && rcByteValid) begin
rcWordByteId <= rcWordByteId + 1;
state_reg <= (rcWordByteId == 3 ? `STATE_GET_CMD : `STATE_SEND_WORD);
end else begin
state_reg <= state;
end
end
// Register logic
assign regAddr = regAddr_reg;
assign regAddr = (`STATE_GET_CMD == state && rcByteValid && rcByte[`CMD_REG_BIT] ? (rcByte & `CMD_REG_ID_MASK) : regAddr_reg);
assign regWriteEn = (`STATE_BUILD_WORD == state && rcByteValid && 3 == rcWordByteId ? 1 : 0);
assign regWriteData = {rcWord[31:8], rcByte};
always @(posedge SysClk) begin
regAddr_reg <= regAddr;
end
always @(*) begin
case (rcWordByteId)
0: regReadByte_oreg <= regReadData[31:24];
1: regReadByte_oreg <= regReadData[23:16];
2: regReadByte_oreg <= regReadData[15:8];
3: regReadByte_oreg <= regReadData[7:0];
endcase
end
// Debugging
always @(posedge SysClk) begin
......
src/spi_base/spiloop.v
View file @ 841aa19d
......@@ -35,6 +35,21 @@ wire [11:0] rcMemAddr;
wire [7:0] rcMemData;
wire rcMemWE;
wire [3:0] regAddr;
wire [31:0] regWriteData;
wire regWE;
reg [31:0] regReadData_wreg;
reg [31:0] regbank [0:15];
always @(*) begin // Read reg
regReadData_wreg <= regbank[regAddr];
end
always @(posedge SysClk) begin // Write reg
if (regWE) begin
regbank[regAddr] <= regWriteData;
end
end
spiloopmem your_instance_name (
.clka(SysClk), // input clka
.ena(1'b1), // input ena
......@@ -59,6 +74,10 @@ spiifc mySpiIfc (
.rcMemAddr(rcMemAddr),
.rcMemData(rcMemData),
.rcMemWE(rcMemWE),
.regAddr(regAddr),
.regReadData(regReadData_wreg),
.regWriteData(regWriteData),
.regWriteEn(regWE),
.debug_out(debug_out)
);
......
test/spi_base/rc-bytes-writereg.txt
View file @ 841aa19d
......@@ -2,4 +2,9 @@ C3
F0
0F
5C
C5
\ No newline at end of file
C5
83
00
00
00
00
test/spi_base/spiifc_writereg_tb.v
View file @ 841aa19d
......@@ -32,7 +32,8 @@ module spiifc_writereg_tb;
reg SPI_MOSI;
reg SPI_SS;
reg [7:0] txMemData;
reg [31:0] regReadData_wreg;
// Outputs
wire SPI_MISO;
wire [11:0] txMemAddr;
......@@ -40,6 +41,13 @@ module spiifc_writereg_tb;
wire [7:0] rcMemData;
wire rcMemWE;
wire [7:0] debug_out;
wire [3:0] regAddr;
wire [31:0] regWriteData;
wire regWE;
// Register bank
reg [31:0] regbank [0:15];
// Instantiate the Unit Under Test (UUT)
spiifc uut (
......@@ -54,6 +62,10 @@ module spiifc_writereg_tb;
.rcMemAddr(rcMemAddr),
.rcMemData(rcMemData),
.rcMemWE(rcMemWE),
.regAddr(regAddr),
.regReadData(regReadData_wreg),
.regWriteData(regWriteData),
.regWriteEn(regWE),
.debug_out(debug_out)
);
......@@ -73,6 +85,16 @@ module spiifc_writereg_tb;
#20 SysClk = ~SysClk;
end
// Register bank
always @(*) begin // Read reg
regReadData_wreg <= regbank[regAddr];
end
always @(posedge SysClk) begin // Write reg
if (regWE) begin
regbank[regAddr] <= regWriteData;
end
end
reg SPI_CLK_en;
initial begin
#310
......
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