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Commit 23405448 authored by Mike Lyons's avatar Mike Lyons
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Adding support for memmap memory. Only tested PIO so far, not DMA yet

parent 7133e87e
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projnav/xps/.gitignore 0 → 100644
View file @ 23405448
system.log
psf2Edward.log
projnav/xps/SDK/SDK_Export/hw/system.xml 0 → 100644
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projnav/xps/SDK/SDK_Export/hw/system_bd.bmm 0 → 100644
View file @ 23405448
// BMM LOC annotation file.
//
// Release 13.2 - Data2MEM O.61xd, build 2.2 May 20, 2011
// Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
///////////////////////////////////////////////////////////////////////////////
//
// Processor 'microblaze_0', ID 100, memory map.
//
///////////////////////////////////////////////////////////////////////////////
ADDRESS_MAP microblaze_0 MICROBLAZE 100
///////////////////////////////////////////////////////////////////////////////
//
// Processor 'microblaze_0' address space 'lmb_bram_combined' 0x00000000:0x0000FFFF (64 KBytes).
//
///////////////////////////////////////////////////////////////////////////////
ADDRESS_SPACE lmb_bram_combined RAMB16 [0x00000000:0x0000FFFF]
BUS_BLOCK
lmb_bram/lmb_bram/ramb16bwer_0 [31:31] INPUT = lmb_bram_combined_0.mem PLACED = X2Y46;
lmb_bram/lmb_bram/ramb16bwer_1 [30:30] INPUT = lmb_bram_combined_1.mem PLACED = X2Y50;
lmb_bram/lmb_bram/ramb16bwer_2 [29:29] INPUT = lmb_bram_combined_2.mem PLACED = X3Y46;
lmb_bram/lmb_bram/ramb16bwer_3 [28:28] INPUT = lmb_bram_combined_3.mem PLACED = X1Y40;
lmb_bram/lmb_bram/ramb16bwer_4 [27:27] INPUT = lmb_bram_combined_4.mem PLACED = X2Y48;
lmb_bram/lmb_bram/ramb16bwer_5 [26:26] INPUT = lmb_bram_combined_5.mem PLACED = X3Y44;
lmb_bram/lmb_bram/ramb16bwer_6 [25:25] INPUT = lmb_bram_combined_6.mem PLACED = X2Y44;
lmb_bram/lmb_bram/ramb16bwer_7 [24:24] INPUT = lmb_bram_combined_7.mem PLACED = X3Y42;
lmb_bram/lmb_bram/ramb16bwer_8 [23:23] INPUT = lmb_bram_combined_8.mem PLACED = X2Y36;
lmb_bram/lmb_bram/ramb16bwer_9 [22:22] INPUT = lmb_bram_combined_9.mem PLACED = X1Y34;
lmb_bram/lmb_bram/ramb16bwer_10 [21:21] INPUT = lmb_bram_combined_10.mem PLACED = X1Y32;
lmb_bram/lmb_bram/ramb16bwer_11 [20:20] INPUT = lmb_bram_combined_11.mem PLACED = X1Y36;
lmb_bram/lmb_bram/ramb16bwer_12 [19:19] INPUT = lmb_bram_combined_12.mem PLACED = X1Y30;
lmb_bram/lmb_bram/ramb16bwer_13 [18:18] INPUT = lmb_bram_combined_13.mem PLACED = X2Y30;
lmb_bram/lmb_bram/ramb16bwer_14 [17:17] INPUT = lmb_bram_combined_14.mem PLACED = X2Y28;
lmb_bram/lmb_bram/ramb16bwer_15 [16:16] INPUT = lmb_bram_combined_15.mem PLACED = X1Y28;
lmb_bram/lmb_bram/ramb16bwer_16 [15:15] INPUT = lmb_bram_combined_16.mem PLACED = X3Y28;
lmb_bram/lmb_bram/ramb16bwer_17 [14:14] INPUT = lmb_bram_combined_17.mem PLACED = X2Y32;
lmb_bram/lmb_bram/ramb16bwer_18 [13:13] INPUT = lmb_bram_combined_18.mem PLACED = X1Y38;
lmb_bram/lmb_bram/ramb16bwer_19 [12:12] INPUT = lmb_bram_combined_19.mem PLACED = X2Y34;
lmb_bram/lmb_bram/ramb16bwer_20 [11:11] INPUT = lmb_bram_combined_20.mem PLACED = X2Y26;
lmb_bram/lmb_bram/ramb16bwer_21 [10:10] INPUT = lmb_bram_combined_21.mem PLACED = X3Y30;
lmb_bram/lmb_bram/ramb16bwer_22 [9:9] INPUT = lmb_bram_combined_22.mem PLACED = X3Y26;
lmb_bram/lmb_bram/ramb16bwer_23 [8:8] INPUT = lmb_bram_combined_23.mem PLACED = X2Y24;
lmb_bram/lmb_bram/ramb16bwer_24 [7:7] INPUT = lmb_bram_combined_24.mem PLACED = X3Y34;
lmb_bram/lmb_bram/ramb16bwer_25 [6:6] INPUT = lmb_bram_combined_25.mem PLACED = X3Y40;
lmb_bram/lmb_bram/ramb16bwer_26 [5:5] INPUT = lmb_bram_combined_26.mem PLACED = X2Y42;
lmb_bram/lmb_bram/ramb16bwer_27 [4:4] INPUT = lmb_bram_combined_27.mem PLACED = X3Y38;
lmb_bram/lmb_bram/ramb16bwer_28 [3:3] INPUT = lmb_bram_combined_28.mem PLACED = X3Y36;
lmb_bram/lmb_bram/ramb16bwer_29 [2:2] INPUT = lmb_bram_combined_29.mem PLACED = X2Y40;
lmb_bram/lmb_bram/ramb16bwer_30 [1:1] INPUT = lmb_bram_combined_30.mem PLACED = X3Y32;
lmb_bram/lmb_bram/ramb16bwer_31 [0:0] INPUT = lmb_bram_combined_31.mem PLACED = X2Y38;
END_BUS_BLOCK;
END_ADDRESS_SPACE;
END_ADDRESS_MAP;
projnav/xps/SDK/SDK_Workspace/demo/.cproject 0 → 100644
View file @ 23405448
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<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
</cconfiguration>
</storageModule>
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
<project id="demo.xilinx.gnu.mb.exe.1436571744" name="Xilinx MicroBlaze Executable" projectType="xilinx.gnu.mb.exe"/>
</storageModule>
</cproject>
projnav/xps/SDK/SDK_Workspace/demo/.project 0 → 100644
View file @ 23405448
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>demo</name>
<comment>demobsp - microblaze_0</comment>
<projects>
<project>demobsp</project>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
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<key>?name?</key>
<value></value>
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<dictionary>
<key>org.eclipse.cdt.make.core.append_environment</key>
<value>true</value>
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<dictionary>
<key>org.eclipse.cdt.make.core.autoBuildTarget</key>
<value>all</value>
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<dictionary>
<key>org.eclipse.cdt.make.core.buildArguments</key>
<value></value>
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<dictionary>
<key>org.eclipse.cdt.make.core.buildCommand</key>
<value>make</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.buildLocation</key>
<value>${workspace_loc:/demo/Debug}</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.cleanBuildTarget</key>
<value>clean</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.contents</key>
<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
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<dictionary>
<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
<value>true</value>
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<dictionary>
<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
<value>true</value>
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<dictionary>
<key>org.eclipse.cdt.make.core.enableFullBuild</key>
<value>true</value>
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<dictionary>
<key>org.eclipse.cdt.make.core.fullBuildTarget</key>
<value>all</value>
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<dictionary>
<key>org.eclipse.cdt.make.core.stopOnError</key>
<value>true</value>
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<dictionary>
<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
<value>true</value>
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</arguments>
</buildCommand>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
<triggers>full,incremental,</triggers>
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</arguments>
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<natures>
<nature>org.eclipse.cdt.core.cnature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
<nature>org.eclipse.cdt.core.ccnature</nature>
</natures>
</projectDescription>
projnav/xps/SDK/SDK_Workspace/demo/Debug/makefile 0 → 100644
View file @ 23405448
################################################################################
# Automatically-generated file. Do not edit!
################################################################################
-include ../makefile.init
RM := rm -rf
# All of the sources participating in the build are defined here
-include sources.mk
-include subdir.mk
-include src/subdir.mk
-include objects.mk
ifneq ($(MAKECMDGOALS),clean)
ifneq ($(strip $(C_DEPS)),)
-include $(C_DEPS)
endif
ifneq ($(strip $(CC_DEPS)),)
-include $(CC_DEPS)
endif
ifneq ($(strip $(CPP_DEPS)),)
-include $(CPP_DEPS)
endif
ifneq ($(strip $(CXX_DEPS)),)
-include $(CXX_DEPS)
endif
ifneq ($(strip $(C_UPPER_DEPS)),)
-include $(C_UPPER_DEPS)
endif
ifneq ($(strip $(S_UPPER_DEPS)),)
-include $(S_UPPER_DEPS)
endif
endif
-include ../makefile.defs
# Add inputs and outputs from these tool invocations to the build variables
ELFSIZE += \
demo.elf.size \
ELFCHECK += \
demo.elf.elfcheck \
# All Target
all: demo.elf secondary-outputs
# Tool invocations
demo.elf: $(OBJS) $(USER_OBJS)
@echo Building target: $@
@echo Invoking: MicroBlaze g++ linker
mb-g++ -L../../demobsp/microblaze_0/lib -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.20.a -mno-xl-soft-mul -o"demo.elf" $(OBJS) $(USER_OBJS) $(LIBS)
@echo Finished building target: $@
@echo ' '
demo.elf.size: demo.elf
@echo Invoking: MicroBlaze Print Size
mb-size demo.elf |tee "demo.elf.size"
@echo Finished building: $@
@echo ' '
demo.elf.elfcheck: demo.elf
@echo Invoking: Xilinx ELF Check
elfcheck demo.elf -hw ../../xps_hw_platform/system.xml -pe microblaze_0 |tee "demo.elf.elfcheck"
@echo Finished building: $@
@echo ' '
# Other Targets
clean:
-$(RM) $(OBJS)$(C_DEPS)$(CC_DEPS)$(CPP_DEPS)$(EXECUTABLES)$(ELFSIZE)$(CXX_DEPS)$(C_UPPER_DEPS)$(ELFCHECK)$(S_UPPER_DEPS) demo.elf
-@echo ' '
secondary-outputs: $(ELFSIZE) $(ELFCHECK)
.PHONY: all clean dependents
.SECONDARY:
-include ../makefile.targets
projnav/xps/SDK/SDK_Workspace/demo/Debug/objects.mk 0 → 100644
View file @ 23405448
################################################################################
# Automatically-generated file. Do not edit!
################################################################################
USER_OBJS :=
LIBS :=
projnav/xps/SDK/SDK_Workspace/demo/Debug/sources.mk 0 → 100644
View file @ 23405448
################################################################################
# Automatically-generated file. Do not edit!
################################################################################
O_SRCS :=
CPP_SRCS :=
C_UPPER_SRCS :=
C_SRCS :=
LD_SRCS :=
S_UPPER_SRCS :=
S_SRCS :=
OBJ_SRCS :=
CXX_SRCS :=
CC_SRCS :=
OBJS :=
C_DEPS :=
CC_DEPS :=
CPP_DEPS :=
EXECUTABLES :=
ELFSIZE :=
CXX_DEPS :=
C_UPPER_DEPS :=
ELFCHECK :=
S_UPPER_DEPS :=
# Every subdirectory with source files must be described here
SUBDIRS := \
src \
projnav/xps/SDK/SDK_Workspace/demo/Debug/src/subdir.mk 0 → 100644
View file @ 23405448
################################################################################
# Automatically-generated file. Do not edit!
################################################################################
# Add inputs and outputs from these tool invocations to the build variables
CC_SRCS += \
../src/main.cc
OBJS += \
./src/main.o
CC_DEPS += \
./src/main.d
# Each subdirectory must supply rules for building sources it contributes
src/%.o: ../src/%.cc
@echo Building file: $<
@echo Invoking: MicroBlaze g++ compiler
mb-g++ -Wall -O0 -g3 -c -fmessage-length=0 -I../../demobsp/microblaze_0/include -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.20.a -mno-xl-soft-mul -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -o"$@" "$<"
@echo Finished building: $<
@echo ' '
projnav/xps/SDK/SDK_Workspace/demo/src/main.cc 0 → 100644
View file @ 23405448
/*
* Empty C++ Application
*/
#include <stdio.h>
#include "xil_types.h"
u32 * pSpiifcBase = (u32 *)0x85000000;
u32 * pMosiBase = (u32 *)0x85010000;
u32 * pMisoBase = (u32 *)0x85011000;
int main()
{
xil_printf("Reg0 @ 0x%08X\n", pSpiifcBase);
xil_printf("Saving word to Reg0... ");
*pSpiifcBase = 0x87654321;
xil_printf("done... verifying... ");
if (0x87654321 == *pSpiifcBase) {
xil_printf("PASS.\n");
} else {
xil_printf("FAIL. (actual=0x%08X)\n", *pSpiifcBase);
}
xil_printf("\n");
xil_printf("MOSI @ 0x%08X\n", pMosiBase);
xil_printf("Saving word to Mem0 (MOSI)...");
*pMosiBase = 0x12345678;
xil_printf("done... verifying... ");
if (0x12345678 == *pMosiBase) {
xil_printf("PASS.\n");
} else {
xil_printf("FAIL. (actual=0x%08X)\n", *pMosiBase);
}
xil_printf("\n");
xil_printf("MISO @ 0x%08X\n", pMisoBase);
xil_printf("Saving word to Mem1 (MISO)... ");
*pMisoBase = 0xFEEDFACE;
xil_printf("done... verifying... ");
if (0xFEEDFACE == *pMisoBase) {
xil_printf("PASS.\n");
} else {
xil_printf("FAIL. (actual=0x%08X)\n", *pMosiBase);
}
xil_printf("\n");
return 0;
}
projnav/xps/SDK/SDK_Workspace/demobsp/.cproject 0 → 100644
View file @ 23405448
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<?fileVersion 4.0.0?>
<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
<storageModule moduleId="org.eclipse.cdt.core.settings">
<cconfiguration id="org.eclipse.cdt.core.default.config.948582058">
<storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.948582058" moduleId="org.eclipse.cdt.core.settings" name="Configuration">
<externalSettings/>
<extensions/>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
</cconfiguration>
</storageModule>
</cproject>
projnav/xps/SDK/SDK_Workspace/demobsp/.project 0 → 100644
View file @ 23405448
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>demobsp</name>
<comment></comment>
<projects>
<project>xps_hw_platform</project>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.cdt.make.core.makeBuilder</name>
<triggers>clean,full,incremental,</triggers>
<arguments>
<dictionary>
<key>org.eclipse.cdt.core.errorOutputParser</key>
<value>org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.VCErrorParser;org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.MakeErrorParser;</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.append_environment</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.build.arguments</key>
<value></value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.build.command</key>
<value>make</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.build.target.auto</key>
<value>all</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.build.target.clean</key>
<value>clean</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.build.target.inc</key>
<value>all</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
<value>false</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.enableFullBuild</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.enabledIncrementalBuild</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.environment</key>
<value></value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.stopOnError</key>
<value>false</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
<value>true</value>
</dictionary>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>com.xilinx.sdk.sw.SwProjectNature</nature>
<nature>org.eclipse.cdt.core.cnature</nature>
<nature>org.eclipse.cdt.make.core.makeNature</nature>
</natures>
</projectDescription>
projnav/xps/SDK/SDK_Workspace/demobsp/.sdkproject 0 → 100644
View file @ 23405448
THIRPARTY=false
PROCESSOR=microblaze_0
MSS_FILE=system.mss
projnav/xps/SDK/SDK_Workspace/demobsp/Makefile 0 → 100644
View file @ 23405448
# Makefile generated by Xilinx SDK.
-include libgen.options
LIBRARIES = ${PROCESSOR}/lib/libxil.a
MSS = system.mss
all: libs
@echo 'Finished building libraries'
libs: $(LIBRARIES)
$(LIBRARIES): $(MSS)
libgen -hw ${HWSPEC}\
${REPOSITORIES}\
-pe ${PROCESSOR} \
-log libgen.log \
$(MSS)
clean:
rm -rf ${PROCESSOR}
projnav/xps/SDK/SDK_Workspace/demobsp/libgen.options 0 → 100644
View file @ 23405448
PROCESSOR=microblaze_0
REPOSITORIES=
HWSPEC=../xps_hw_platform/system.xml
projnav/xps/SDK/SDK_Workspace/demobsp/system.mss 0 → 100644
View file @ 23405448
PARAMETER VERSION = 2.2.0
BEGIN OS
PARAMETER OS_NAME = standalone
PARAMETER OS_VER = 3.01.a
PARAMETER PROC_INSTANCE = microblaze_0
PARAMETER STDIN = mdm_0
PARAMETER STDOUT = mdm_0
END
BEGIN PROCESSOR
PARAMETER DRIVER_NAME = cpu
PARAMETER DRIVER_VER = 1.13.a
PARAMETER HW_INSTANCE = microblaze_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = gpio
PARAMETER DRIVER_VER = 3.00.a
PARAMETER HW_INSTANCE = DIP_Switches_8Bits
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = gpio
PARAMETER DRIVER_VER = 3.00.a
PARAMETER HW_INSTANCE = LEDs_8Bits
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = gpio
PARAMETER DRIVER_VER = 3.00.a
PARAMETER HW_INSTANCE = Push_Buttons_5Bits
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = bram
PARAMETER DRIVER_VER = 3.00.a
PARAMETER HW_INSTANCE = dlmb_cntlr
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = bram
PARAMETER DRIVER_VER = 3.00.a
PARAMETER HW_INSTANCE = ilmb_cntlr
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = uartlite
PARAMETER DRIVER_VER = 2.00.a
PARAMETER HW_INSTANCE = mdm_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = spiifc_0
END
projnav/xps/SDK/SDK_Workspace/xps_hw_platform/.project 0 → 100644
View file @ 23405448
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>xps_hw_platform</name>
<comment></comment>
<projects>
</projects>
<buildSpec>
</buildSpec>
<natures>
<nature>com.xilinx.sdk.hw.HwProject</nature>
</natures>
</projectDescription>
projnav/xps/SDK/SDK_Workspace/xps_hw_platform/system.xml 0 → 100644
View file @ 23405448
This source diff could not be displayed because it is too large. You can view the blob instead.
projnav/xps/SDK/SDK_Workspace/xps_hw_platform/system_bd.bmm 0 → 100644
View file @ 23405448
// BMM LOC annotation file.
//
// Release 13.2 - Data2MEM O.61xd, build 2.2 May 20, 2011
// Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
///////////////////////////////////////////////////////////////////////////////
//
// Processor 'microblaze_0', ID 100, memory map.
//
///////////////////////////////////////////////////////////////////////////////
ADDRESS_MAP microblaze_0 MICROBLAZE 100
///////////////////////////////////////////////////////////////////////////////
//
// Processor 'microblaze_0' address space 'lmb_bram_combined' 0x00000000:0x0000FFFF (64 KBytes).
//
///////////////////////////////////////////////////////////////////////////////
ADDRESS_SPACE lmb_bram_combined RAMB16 [0x00000000:0x0000FFFF]
BUS_BLOCK
lmb_bram/lmb_bram/ramb16bwer_0 [31:31] INPUT = lmb_bram_combined_0.mem PLACED = X2Y46;
lmb_bram/lmb_bram/ramb16bwer_1 [30:30] INPUT = lmb_bram_combined_1.mem PLACED = X2Y50;
lmb_bram/lmb_bram/ramb16bwer_2 [29:29] INPUT = lmb_bram_combined_2.mem PLACED = X3Y46;
lmb_bram/lmb_bram/ramb16bwer_3 [28:28] INPUT = lmb_bram_combined_3.mem PLACED = X1Y40;
lmb_bram/lmb_bram/ramb16bwer_4 [27:27] INPUT = lmb_bram_combined_4.mem PLACED = X2Y48;
lmb_bram/lmb_bram/ramb16bwer_5 [26:26] INPUT = lmb_bram_combined_5.mem PLACED = X3Y44;
lmb_bram/lmb_bram/ramb16bwer_6 [25:25] INPUT = lmb_bram_combined_6.mem PLACED = X2Y44;
lmb_bram/lmb_bram/ramb16bwer_7 [24:24] INPUT = lmb_bram_combined_7.mem PLACED = X3Y42;
lmb_bram/lmb_bram/ramb16bwer_8 [23:23] INPUT = lmb_bram_combined_8.mem PLACED = X2Y36;
lmb_bram/lmb_bram/ramb16bwer_9 [22:22] INPUT = lmb_bram_combined_9.mem PLACED = X1Y34;
lmb_bram/lmb_bram/ramb16bwer_10 [21:21] INPUT = lmb_bram_combined_10.mem PLACED = X1Y32;
lmb_bram/lmb_bram/ramb16bwer_11 [20:20] INPUT = lmb_bram_combined_11.mem PLACED = X1Y36;
lmb_bram/lmb_bram/ramb16bwer_12 [19:19] INPUT = lmb_bram_combined_12.mem PLACED = X1Y30;
lmb_bram/lmb_bram/ramb16bwer_13 [18:18] INPUT = lmb_bram_combined_13.mem PLACED = X2Y30;
lmb_bram/lmb_bram/ramb16bwer_14 [17:17] INPUT = lmb_bram_combined_14.mem PLACED = X2Y28;
lmb_bram/lmb_bram/ramb16bwer_15 [16:16] INPUT = lmb_bram_combined_15.mem PLACED = X1Y28;
lmb_bram/lmb_bram/ramb16bwer_16 [15:15] INPUT = lmb_bram_combined_16.mem PLACED = X3Y28;
lmb_bram/lmb_bram/ramb16bwer_17 [14:14] INPUT = lmb_bram_combined_17.mem PLACED = X2Y32;
lmb_bram/lmb_bram/ramb16bwer_18 [13:13] INPUT = lmb_bram_combined_18.mem PLACED = X1Y38;
lmb_bram/lmb_bram/ramb16bwer_19 [12:12] INPUT = lmb_bram_combined_19.mem PLACED = X2Y34;
lmb_bram/lmb_bram/ramb16bwer_20 [11:11] INPUT = lmb_bram_combined_20.mem PLACED = X2Y26;
lmb_bram/lmb_bram/ramb16bwer_21 [10:10] INPUT = lmb_bram_combined_21.mem PLACED = X3Y30;
lmb_bram/lmb_bram/ramb16bwer_22 [9:9] INPUT = lmb_bram_combined_22.mem PLACED = X3Y26;
lmb_bram/lmb_bram/ramb16bwer_23 [8:8] INPUT = lmb_bram_combined_23.mem PLACED = X2Y24;
lmb_bram/lmb_bram/ramb16bwer_24 [7:7] INPUT = lmb_bram_combined_24.mem PLACED = X3Y34;
lmb_bram/lmb_bram/ramb16bwer_25 [6:6] INPUT = lmb_bram_combined_25.mem PLACED = X3Y40;
lmb_bram/lmb_bram/ramb16bwer_26 [5:5] INPUT = lmb_bram_combined_26.mem PLACED = X2Y42;
lmb_bram/lmb_bram/ramb16bwer_27 [4:4] INPUT = lmb_bram_combined_27.mem PLACED = X3Y38;
lmb_bram/lmb_bram/ramb16bwer_28 [3:3] INPUT = lmb_bram_combined_28.mem PLACED = X3Y36;
lmb_bram/lmb_bram/ramb16bwer_29 [2:2] INPUT = lmb_bram_combined_29.mem PLACED = X2Y40;
lmb_bram/lmb_bram/ramb16bwer_30 [1:1] INPUT = lmb_bram_combined_30.mem PLACED = X3Y32;
lmb_bram/lmb_bram/ramb16bwer_31 [0:0] INPUT = lmb_bram_combined_31.mem PLACED = X2Y38;
END_BUS_BLOCK;
END_ADDRESS_SPACE;
END_ADDRESS_MAP;
projnav/xps/__xps/ise/system.xreport
View file @ 23405448
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2012-02-28T11:11:33</DateModified>
<DateModified>2012-02-28T19:36:43</DateModified>
<ModuleName>system</ModuleName>
<SummaryTimeStamp>2012-02-28T11:11:33</SummaryTimeStamp>
<SummaryTimeStamp>2012-02-28T19:36:42</SummaryTimeStamp>
<SavedFilePath>C:/Users/mjlyons/workspace/vSPI/projnav/xps/__xps/ise/system.xreport</SavedFilePath>
<FilterFile>filter.filter</FilterFile>
<SavedFilterFilePath>C:/Users/mjlyons/workspace/vSPI/projnav/xps/__xps/ise</SavedFilterFilePath>
......
projnav/xps/__xps/system.xml
View file @ 23405448
<EDKSYSTEM EDKVERSION="13.2" EDWVERSION="1.2" TIMESTAMP="Tue Feb 28 11:11:34 2012">
<EDKSYSTEM EDKVERSION="13.2" EDWVERSION="1.2" TIMESTAMP="Tue Feb 28 19:36:45 2012">
<SYSTEMINFO ARCH="spartan6" DEVICE="xc6slx45" PACKAGE="csg324" PART="xc6slx45csg324-2" SOURCE="C:/Users/mjlyons/workspace/vSPI/projnav/xps/system.xmp" SPEEDGRADE="-2"/>
......@@ -2052,6 +2052,21 @@
<ROUTEPNT INDEX="0" INSTANCE="mb_plb"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="2231369728" BASENAME="C_BASEADDR" BASEVALUE="0x85000000" HIGHDECIMAL="2231435263" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8500FFFF" INSTANCE="spiifc_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="mb_plb"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="2231435264" BASENAME="C_MEM0_BASEADDR" BASEVALUE="0x85010000" HIGHDECIMAL="2231439359" HIGHNAME="C_MEM0_HIGHADDR" HIGHVALUE="0x85010FFF" INSTANCE="spiifc_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="4096" SIZEABRV="4K">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="mb_plb"/>
</ACCESSROUTE>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="2231439360" BASENAME="C_MEM1_BASEADDR" BASEVALUE="0x85011000" HIGHDECIMAL="2231443455" HIGHNAME="C_MEM1_HIGHADDR" HIGHVALUE="0x85011FFF" INSTANCE="spiifc_0" IS_DATA="TRUE" IS_INSTRUCTION="TRUE" IS_VALID="TRUE" MEMTYPE="MEMORY" SIZE="4096" SIZEABRV="4K">
<ACCESSROUTE>
<ROUTEPNT INDEX="0" INSTANCE="mb_plb"/>
</ACCESSROUTE>
</MEMRANGE>
</MEMORYMAP>
<PERIPHERALS>
<PERIPHERAL INSTANCE="dlmb_cntlr"/>
......@@ -2060,6 +2075,7 @@
<PERIPHERAL INSTANCE="LEDs_8Bits"/>
<PERIPHERAL INSTANCE="Push_Buttons_5Bits"/>
<PERIPHERAL INSTANCE="mdm_0"/>
<PERIPHERAL INSTANCE="spiifc_0"/>
</PERIPHERALS>
</MODULE>
<MODULE BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" HWVERSION="1.05.a" INSTANCE="mb_plb" IPTYPE="BUS" MHS_INDEX="1" MODCLASS="BUS" MODTYPE="plb_v46">
......@@ -2071,7 +2087,7 @@
<LICENSEINFO ICON_NAME="ps_core_preferred"/>
<PARAMETERS>
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="0" NAME="C_PLBV46_NUM_MASTERS" TYPE="integer" VALUE="2"/>
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_PLBV46_NUM_SLAVES" TYPE="integer" VALUE="4"/>
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="1" NAME="C_PLBV46_NUM_SLAVES" TYPE="integer" VALUE="5"/>
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="2" NAME="C_PLBV46_MID_WIDTH" TYPE="integer" VALUE="1"/>
<PARAMETER MPD_INDEX="3" NAME="C_PLBV46_AWIDTH" TYPE="integer" VALUE="32"/>
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_PLBV46_DWIDTH" TYPE="integer" VALUE="32"/>
......@@ -2092,7 +2108,7 @@
<PORT CLKFREQUENCY="66666666" DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="PLB_Clk" SIGIS="CLK" SIGNAME="clk_66_6667MHz"/>
<PORT DIR="I" IS_INSTANTIATED="TRUE" MHS_INDEX="1" MPD_INDEX="1" NAME="SYS_Rst" SIGIS="RST" SIGNAME="sys_bus_reset"/>
<PORT DEF_SIGNAME="mb_plb_PLB_Rst" DIR="O" MPD_INDEX="2" NAME="PLB_Rst" SIGIS="RST" SIGNAME="mb_plb_PLB_Rst"/>
<PORT DEF_SIGNAME="mb_plb_SPLB_Rst" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="3" MSB="0" NAME="SPLB_Rst" RIGHT="3" SIGIS="RST" SIGNAME="mb_plb_SPLB_Rst" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/>
<PORT DEF_SIGNAME="mb_plb_SPLB_Rst" DIR="O" ENDIAN="BIG" LEFT="0" LSB="4" MPD_INDEX="3" MSB="0" NAME="SPLB_Rst" RIGHT="4" SIGIS="RST" SIGNAME="mb_plb_SPLB_Rst" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/>
<PORT DEF_SIGNAME="mb_plb_MPLB_Rst" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="4" MSB="0" NAME="MPLB_Rst" RIGHT="1" SIGIS="RST" SIGNAME="mb_plb_MPLB_Rst" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/>
<PORT BUS="SDCR" DEF_SIGNAME="__BUS__" DIR="O" MPD_INDEX="5" NAME="PLB_dcrAck" SIGNAME="__NOC__"/>
<PORT BUS="SDCR" DEF_SIGNAME="__BUS__" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="6" MSB="0" NAME="PLB_dcrDBus" RIGHT="31" SIGNAME="__NOC__" VECFORMULA="[0:C_DCR_DWIDTH-1]"/>
......@@ -2116,22 +2132,22 @@
<PORT DEF_SIGNAME="mb_plb_M_type" DIR="I" ENDIAN="BIG" LEFT="0" LSB="5" MPD_INDEX="24" MSB="0" NAME="M_type" RIGHT="5" SIGNAME="mb_plb_M_type" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*3)-1]"/>
<PORT DEF_SIGNAME="mb_plb_M_wrBurst" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="25" MSB="0" NAME="M_wrBurst" RIGHT="1" SIGNAME="mb_plb_M_wrBurst" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/>
<PORT DEF_SIGNAME="mb_plb_M_wrDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="63" MPD_INDEX="26" MSB="0" NAME="M_wrDBus" RIGHT="63" SIGNAME="mb_plb_M_wrDBus" VECFORMULA="[0:(C_PLBV46_NUM_MASTERS*C_PLBV46_DWIDTH)-1]"/>
<PORT DEF_SIGNAME="mb_plb_Sl_addrAck" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="27" MSB="0" NAME="Sl_addrAck" RIGHT="3" SIGNAME="mb_plb_Sl_addrAck" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/>
<PORT DEF_SIGNAME="mb_plb_Sl_MRdErr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="28" MSB="0" NAME="Sl_MRdErr" RIGHT="7" SIGNAME="mb_plb_Sl_MRdErr" VECFORMULA="[0:(C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1]"/>
<PORT DEF_SIGNAME="mb_plb_Sl_MWrErr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="29" MSB="0" NAME="Sl_MWrErr" RIGHT="7" SIGNAME="mb_plb_Sl_MWrErr" VECFORMULA="[0:(C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1]"/>
<PORT DEF_SIGNAME="mb_plb_Sl_MBusy" DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="30" MSB="0" NAME="Sl_MBusy" RIGHT="7" SIGNAME="mb_plb_Sl_MBusy" VECFORMULA="[0:C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS - 1 ]"/>
<PORT DEF_SIGNAME="mb_plb_Sl_rdBTerm" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="31" MSB="0" NAME="Sl_rdBTerm" RIGHT="3" SIGNAME="mb_plb_Sl_rdBTerm" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/>
<PORT DEF_SIGNAME="mb_plb_Sl_rdComp" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="32" MSB="0" NAME="Sl_rdComp" RIGHT="3" SIGNAME="mb_plb_Sl_rdComp" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/>
<PORT DEF_SIGNAME="mb_plb_Sl_rdDAck" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="33" MSB="0" NAME="Sl_rdDAck" RIGHT="3" SIGNAME="mb_plb_Sl_rdDAck" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/>
<PORT DEF_SIGNAME="mb_plb_Sl_rdDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="127" MPD_INDEX="34" MSB="0" NAME="Sl_rdDBus" RIGHT="127" SIGNAME="mb_plb_Sl_rdDBus" VECFORMULA="[0:C_PLBV46_NUM_SLAVES*C_PLBV46_DWIDTH-1]"/>
<PORT DEF_SIGNAME="mb_plb_Sl_rdWdAddr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="35" MSB="0" NAME="Sl_rdWdAddr" RIGHT="15" SIGNAME="mb_plb_Sl_rdWdAddr" VECFORMULA="[0:C_PLBV46_NUM_SLAVES*4-1]"/>
<PORT DEF_SIGNAME="mb_plb_Sl_rearbitrate" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="36" MSB="0" NAME="Sl_rearbitrate" RIGHT="3" SIGNAME="mb_plb_Sl_rearbitrate" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/>
<PORT DEF_SIGNAME="mb_plb_Sl_SSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="37" MSB="0" NAME="Sl_SSize" RIGHT="7" SIGNAME="mb_plb_Sl_SSize" VECFORMULA="[0:C_PLBV46_NUM_SLAVES*2-1]"/>
<PORT DEF_SIGNAME="mb_plb_Sl_wait" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="38" MSB="0" NAME="Sl_wait" RIGHT="3" SIGNAME="mb_plb_Sl_wait" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/>
<PORT DEF_SIGNAME="mb_plb_Sl_wrBTerm" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="39" MSB="0" NAME="Sl_wrBTerm" RIGHT="3" SIGNAME="mb_plb_Sl_wrBTerm" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/>
<PORT DEF_SIGNAME="mb_plb_Sl_wrComp" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="40" MSB="0" NAME="Sl_wrComp" RIGHT="3" SIGNAME="mb_plb_Sl_wrComp" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/>
<PORT DEF_SIGNAME="mb_plb_Sl_wrDAck" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="41" MSB="0" NAME="Sl_wrDAck" RIGHT="3" SIGNAME="mb_plb_Sl_wrDAck" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/>
<PORT DEF_SIGNAME="mb_plb_Sl_MIRQ" DIR="I" ENDIAN="BIG" LEFT="0" LSB="7" MPD_INDEX="42" MSB="0" NAME="Sl_MIRQ" RIGHT="7" SIGNAME="mb_plb_Sl_MIRQ" VECFORMULA="[0:C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS-1]"/>
<PORT DEF_SIGNAME="mb_plb_Sl_addrAck" DIR="I" ENDIAN="BIG" LEFT="0" LSB="4" MPD_INDEX="27" MSB="0" NAME="Sl_addrAck" RIGHT="4" SIGNAME="mb_plb_Sl_addrAck" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/>
<PORT DEF_SIGNAME="mb_plb_Sl_MRdErr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="9" MPD_INDEX="28" MSB="0" NAME="Sl_MRdErr" RIGHT="9" SIGNAME="mb_plb_Sl_MRdErr" VECFORMULA="[0:(C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1]"/>
<PORT DEF_SIGNAME="mb_plb_Sl_MWrErr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="9" MPD_INDEX="29" MSB="0" NAME="Sl_MWrErr" RIGHT="9" SIGNAME="mb_plb_Sl_MWrErr" VECFORMULA="[0:(C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS)-1]"/>
<PORT DEF_SIGNAME="mb_plb_Sl_MBusy" DIR="I" ENDIAN="BIG" LEFT="0" LSB="9" MPD_INDEX="30" MSB="0" NAME="Sl_MBusy" RIGHT="9" SIGNAME="mb_plb_Sl_MBusy" VECFORMULA="[0:C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS - 1 ]"/>
<PORT DEF_SIGNAME="mb_plb_Sl_rdBTerm" DIR="I" ENDIAN="BIG" LEFT="0" LSB="4" MPD_INDEX="31" MSB="0" NAME="Sl_rdBTerm" RIGHT="4" SIGNAME="mb_plb_Sl_rdBTerm" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/>
<PORT DEF_SIGNAME="mb_plb_Sl_rdComp" DIR="I" ENDIAN="BIG" LEFT="0" LSB="4" MPD_INDEX="32" MSB="0" NAME="Sl_rdComp" RIGHT="4" SIGNAME="mb_plb_Sl_rdComp" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/>
<PORT DEF_SIGNAME="mb_plb_Sl_rdDAck" DIR="I" ENDIAN="BIG" LEFT="0" LSB="4" MPD_INDEX="33" MSB="0" NAME="Sl_rdDAck" RIGHT="4" SIGNAME="mb_plb_Sl_rdDAck" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/>
<PORT DEF_SIGNAME="mb_plb_Sl_rdDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="159" MPD_INDEX="34" MSB="0" NAME="Sl_rdDBus" RIGHT="159" SIGNAME="mb_plb_Sl_rdDBus" VECFORMULA="[0:C_PLBV46_NUM_SLAVES*C_PLBV46_DWIDTH-1]"/>
<PORT DEF_SIGNAME="mb_plb_Sl_rdWdAddr" DIR="I" ENDIAN="BIG" LEFT="0" LSB="19" MPD_INDEX="35" MSB="0" NAME="Sl_rdWdAddr" RIGHT="19" SIGNAME="mb_plb_Sl_rdWdAddr" VECFORMULA="[0:C_PLBV46_NUM_SLAVES*4-1]"/>
<PORT DEF_SIGNAME="mb_plb_Sl_rearbitrate" DIR="I" ENDIAN="BIG" LEFT="0" LSB="4" MPD_INDEX="36" MSB="0" NAME="Sl_rearbitrate" RIGHT="4" SIGNAME="mb_plb_Sl_rearbitrate" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/>
<PORT DEF_SIGNAME="mb_plb_Sl_SSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="9" MPD_INDEX="37" MSB="0" NAME="Sl_SSize" RIGHT="9" SIGNAME="mb_plb_Sl_SSize" VECFORMULA="[0:C_PLBV46_NUM_SLAVES*2-1]"/>
<PORT DEF_SIGNAME="mb_plb_Sl_wait" DIR="I" ENDIAN="BIG" LEFT="0" LSB="4" MPD_INDEX="38" MSB="0" NAME="Sl_wait" RIGHT="4" SIGNAME="mb_plb_Sl_wait" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/>
<PORT DEF_SIGNAME="mb_plb_Sl_wrBTerm" DIR="I" ENDIAN="BIG" LEFT="0" LSB="4" MPD_INDEX="39" MSB="0" NAME="Sl_wrBTerm" RIGHT="4" SIGNAME="mb_plb_Sl_wrBTerm" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/>
<PORT DEF_SIGNAME="mb_plb_Sl_wrComp" DIR="I" ENDIAN="BIG" LEFT="0" LSB="4" MPD_INDEX="40" MSB="0" NAME="Sl_wrComp" RIGHT="4" SIGNAME="mb_plb_Sl_wrComp" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/>
<PORT DEF_SIGNAME="mb_plb_Sl_wrDAck" DIR="I" ENDIAN="BIG" LEFT="0" LSB="4" MPD_INDEX="41" MSB="0" NAME="Sl_wrDAck" RIGHT="4" SIGNAME="mb_plb_Sl_wrDAck" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/>
<PORT DEF_SIGNAME="mb_plb_Sl_MIRQ" DIR="I" ENDIAN="BIG" LEFT="0" LSB="9" MPD_INDEX="42" MSB="0" NAME="Sl_MIRQ" RIGHT="9" SIGNAME="mb_plb_Sl_MIRQ" VECFORMULA="[0:C_PLBV46_NUM_SLAVES*C_PLBV46_NUM_MASTERS-1]"/>
<PORT DEF_SIGNAME="mb_plb_PLB_MIRQ" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="43" MSB="0" NAME="PLB_MIRQ" RIGHT="1" SIGNAME="mb_plb_PLB_MIRQ" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/>
<PORT DEF_SIGNAME="mb_plb_PLB_ABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="44" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="mb_plb_PLB_ABus" VECFORMULA="[0:31]"/>
<PORT DEF_SIGNAME="mb_plb_PLB_UABus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="45" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="mb_plb_PLB_UABus" VECFORMULA="[0:31]"/>
......@@ -2163,13 +2179,13 @@
<PORT DEF_SIGNAME="mb_plb_PLB_rdPendReq" DIR="O" MPD_INDEX="71" NAME="PLB_rdPendReq" SIGNAME="mb_plb_PLB_rdPendReq"/>
<PORT DEF_SIGNAME="mb_plb_PLB_wrPendReq" DIR="O" MPD_INDEX="72" NAME="PLB_wrPendReq" SIGNAME="mb_plb_PLB_wrPendReq"/>
<PORT DEF_SIGNAME="mb_plb_PLB_rdBurst" DIR="O" MPD_INDEX="73" NAME="PLB_rdBurst" SIGNAME="mb_plb_PLB_rdBurst"/>
<PORT DEF_SIGNAME="mb_plb_PLB_rdPrim" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="74" MSB="0" NAME="PLB_rdPrim" RIGHT="3" SIGNAME="mb_plb_PLB_rdPrim" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/>
<PORT DEF_SIGNAME="mb_plb_PLB_rdPrim" DIR="O" ENDIAN="BIG" LEFT="0" LSB="4" MPD_INDEX="74" MSB="0" NAME="PLB_rdPrim" RIGHT="4" SIGNAME="mb_plb_PLB_rdPrim" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/>
<PORT DEF_SIGNAME="mb_plb_PLB_reqPri" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="75" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="mb_plb_PLB_reqPri" VECFORMULA="[0:1]"/>
<PORT DEF_SIGNAME="mb_plb_PLB_size" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="76" MSB="0" NAME="PLB_size" RIGHT="3" SIGNAME="mb_plb_PLB_size" VECFORMULA="[0:3]"/>
<PORT DEF_SIGNAME="mb_plb_PLB_type" DIR="O" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="77" MSB="0" NAME="PLB_type" RIGHT="2" SIGNAME="mb_plb_PLB_type" VECFORMULA="[0:2]"/>
<PORT DEF_SIGNAME="mb_plb_PLB_wrBurst" DIR="O" MPD_INDEX="78" NAME="PLB_wrBurst" SIGNAME="mb_plb_PLB_wrBurst"/>
<PORT DEF_SIGNAME="mb_plb_PLB_wrDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="79" MSB="0" NAME="PLB_wrDBus" RIGHT="31" SIGNAME="mb_plb_PLB_wrDBus" VECFORMULA="[0:C_PLBV46_DWIDTH-1]"/>
<PORT DEF_SIGNAME="mb_plb_PLB_wrPrim" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="80" MSB="0" NAME="PLB_wrPrim" RIGHT="3" SIGNAME="mb_plb_PLB_wrPrim" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/>
<PORT DEF_SIGNAME="mb_plb_PLB_wrPrim" DIR="O" ENDIAN="BIG" LEFT="0" LSB="4" MPD_INDEX="80" MSB="0" NAME="PLB_wrPrim" RIGHT="4" SIGNAME="mb_plb_PLB_wrPrim" VECFORMULA="[0:C_PLBV46_NUM_SLAVES-1]"/>
<PORT DEF_SIGNAME="mb_plb_PLB_SaddrAck" DIR="O" MPD_INDEX="81" NAME="PLB_SaddrAck" SIGNAME="mb_plb_PLB_SaddrAck"/>
<PORT DEF_SIGNAME="mb_plb_PLB_SMRdErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="82" MSB="0" NAME="PLB_SMRdErr" RIGHT="1" SIGNAME="mb_plb_PLB_SMRdErr" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/>
<PORT DEF_SIGNAME="mb_plb_PLB_SMWrErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="83" MSB="0" NAME="PLB_SMWrErr" RIGHT="1" SIGNAME="mb_plb_PLB_SMWrErr" VECFORMULA="[0:C_PLBV46_NUM_MASTERS-1]"/>
......@@ -3875,6 +3891,138 @@
<IOINTERFACE MPD_INDEX="0" NAME="reset_0"/>
</IOINTERFACES>
</MODULE>
<MODULE HWVERSION="1.00.a" INSTANCE="spiifc_0" IPTYPE="PERIPHERAL" MHS_INDEX="13" MODCLASS="MEMORY_CNTLR" MODTYPE="spiifc">
<LICENSEINFO ICON_NAME="ps_core_local"/>
<PARAMETERS>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="2" MPD_INDEX="0" NAME="C_BASEADDR" TYPE="std_logic_vector" VALUE="0x85000000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="REGISTER" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="3" MPD_INDEX="1" NAME="C_HIGHADDR" TYPE="std_logic_vector" VALUE="0x8500FFFF"/>
<PARAMETER MPD_INDEX="2" NAME="C_SPLB_AWIDTH" TYPE="INTEGER" VALUE="32"/>
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="3" NAME="C_SPLB_DWIDTH" TYPE="INTEGER" VALUE="32"/>
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="4" NAME="C_SPLB_NUM_MASTERS" TYPE="INTEGER" VALUE="2"/>
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="5" NAME="C_SPLB_MID_WIDTH" TYPE="INTEGER" VALUE="1"/>
<PARAMETER MPD_INDEX="6" NAME="C_SPLB_NATIVE_DWIDTH" TYPE="INTEGER" VALUE="32"/>
<PARAMETER MPD_INDEX="7" NAME="C_SPLB_P2P" TYPE="INTEGER" VALUE="0"/>
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="8" NAME="C_SPLB_SUPPORT_BURSTS" TYPE="INTEGER" VALUE="0"/>
<PARAMETER MPD_INDEX="9" NAME="C_SPLB_SMALLEST_MASTER" TYPE="INTEGER" VALUE="32"/>
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="10" NAME="C_SPLB_CLK_PERIOD_PS" TYPE="INTEGER" VALUE="15000"/>
<PARAMETER MPD_INDEX="11" NAME="C_INCLUDE_DPHASE_TIMER" TYPE="INTEGER" VALUE="1"/>
<PARAMETER CHANGEDBY="SYSTEM" MPD_INDEX="12" NAME="C_FAMILY" TYPE="STRING" VALUE="spartan6"/>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="4" MPD_INDEX="13" NAME="C_MEM0_BASEADDR" TYPE="std_logic_vector" VALUE="0x85010000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="5" MPD_INDEX="14" NAME="C_MEM0_HIGHADDR" TYPE="std_logic_vector" VALUE="0x85010FFF"/>
<PARAMETER ADDRESS="BASE" ADDR_TYPE="MEMORY" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="6" MPD_INDEX="15" NAME="C_MEM1_BASEADDR" TYPE="std_logic_vector" VALUE="0x85011000"/>
<PARAMETER ADDRESS="HIGH" ADDR_TYPE="MEMORY" CHANGEDBY="USER" IS_INSTANTIATED="TRUE" MHS_INDEX="7" MPD_INDEX="16" NAME="C_MEM1_HIGHADDR" TYPE="std_logic_vector" VALUE="0x85011FFF"/>
</PARAMETERS>
<PORTS>
<PORT BUS="SPLB" CLKFREQUENCY="66666666" DEF_SIGNAME="clk_66_6667MHz" DIR="I" MPD_INDEX="0" NAME="SPLB_Clk" SIGIS="CLK" SIGNAME="clk_66_6667MHz"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_SPLB_Rst" DIR="I" MPD_INDEX="1" NAME="SPLB_Rst" SIGIS="RST" SIGNAME="mb_plb_SPLB_Rst"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_ABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="2" MSB="0" NAME="PLB_ABus" RIGHT="31" SIGNAME="mb_plb_PLB_ABus" VECFORMULA="[0:31]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_UABus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="3" MSB="0" NAME="PLB_UABus" RIGHT="31" SIGNAME="mb_plb_PLB_UABus" VECFORMULA="[0:31]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_PAValid" DIR="I" MPD_INDEX="4" NAME="PLB_PAValid" SIGNAME="mb_plb_PLB_PAValid"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_SAValid" DIR="I" MPD_INDEX="5" NAME="PLB_SAValid" SIGNAME="mb_plb_PLB_SAValid"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPrim" DIR="I" MPD_INDEX="6" NAME="PLB_rdPrim" SIGNAME="mb_plb_PLB_rdPrim"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPrim" DIR="I" MPD_INDEX="7" NAME="PLB_wrPrim" SIGNAME="mb_plb_PLB_wrPrim"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_masterID" DIR="I" MPD_INDEX="8" NAME="PLB_masterID" SIGNAME="mb_plb_PLB_masterID" VECFORMULA="[0:(C_SPLB_MID_WIDTH-1)]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_abort" DIR="I" MPD_INDEX="9" NAME="PLB_abort" SIGNAME="mb_plb_PLB_abort"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_busLock" DIR="I" MPD_INDEX="10" NAME="PLB_busLock" SIGNAME="mb_plb_PLB_busLock"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_RNW" DIR="I" MPD_INDEX="11" NAME="PLB_RNW" SIGNAME="mb_plb_PLB_RNW"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_BE" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="12" MSB="0" NAME="PLB_BE" RIGHT="3" SIGNAME="mb_plb_PLB_BE" VECFORMULA="[0:((C_SPLB_DWIDTH/8)-1)]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_MSize" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="13" MSB="0" NAME="PLB_MSize" RIGHT="1" SIGNAME="mb_plb_PLB_MSize" VECFORMULA="[0:1]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_size" DIR="I" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="14" MSB="0" NAME="PLB_size" RIGHT="3" SIGNAME="mb_plb_PLB_size" VECFORMULA="[0:3]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_type" DIR="I" ENDIAN="BIG" LEFT="0" LSB="2" MPD_INDEX="15" MSB="0" NAME="PLB_type" RIGHT="2" SIGNAME="mb_plb_PLB_type" VECFORMULA="[0:2]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_lockErr" DIR="I" MPD_INDEX="16" NAME="PLB_lockErr" SIGNAME="mb_plb_PLB_lockErr"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrDBus" DIR="I" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="17" MSB="0" NAME="PLB_wrDBus" RIGHT="31" SIGNAME="mb_plb_PLB_wrDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrBurst" DIR="I" MPD_INDEX="18" NAME="PLB_wrBurst" SIGNAME="mb_plb_PLB_wrBurst"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdBurst" DIR="I" MPD_INDEX="19" NAME="PLB_rdBurst" SIGNAME="mb_plb_PLB_rdBurst"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendReq" DIR="I" MPD_INDEX="20" NAME="PLB_wrPendReq" SIGNAME="mb_plb_PLB_wrPendReq"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendReq" DIR="I" MPD_INDEX="21" NAME="PLB_rdPendReq" SIGNAME="mb_plb_PLB_rdPendReq"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_wrPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="22" MSB="0" NAME="PLB_wrPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_wrPendPri" VECFORMULA="[0:1]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_rdPendPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="23" MSB="0" NAME="PLB_rdPendPri" RIGHT="1" SIGNAME="mb_plb_PLB_rdPendPri" VECFORMULA="[0:1]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_reqPri" DIR="I" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="24" MSB="0" NAME="PLB_reqPri" RIGHT="1" SIGNAME="mb_plb_PLB_reqPri" VECFORMULA="[0:1]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_PLB_TAttribute" DIR="I" ENDIAN="BIG" LEFT="0" LSB="15" MPD_INDEX="25" MSB="0" NAME="PLB_TAttribute" RIGHT="15" SIGNAME="mb_plb_PLB_TAttribute" VECFORMULA="[0:15]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_addrAck" DIR="O" MPD_INDEX="26" NAME="Sl_addrAck" SIGNAME="mb_plb_Sl_addrAck"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_SSize" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="27" MSB="0" NAME="Sl_SSize" RIGHT="1" SIGNAME="mb_plb_Sl_SSize" VECFORMULA="[0:1]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wait" DIR="O" MPD_INDEX="28" NAME="Sl_wait" SIGNAME="mb_plb_Sl_wait"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rearbitrate" DIR="O" MPD_INDEX="29" NAME="Sl_rearbitrate" SIGNAME="mb_plb_Sl_rearbitrate"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrDAck" DIR="O" MPD_INDEX="30" NAME="Sl_wrDAck" SIGNAME="mb_plb_Sl_wrDAck"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrComp" DIR="O" MPD_INDEX="31" NAME="Sl_wrComp" SIGNAME="mb_plb_Sl_wrComp"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_wrBTerm" DIR="O" MPD_INDEX="32" NAME="Sl_wrBTerm" SIGNAME="mb_plb_Sl_wrBTerm"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDBus" DIR="O" ENDIAN="BIG" LEFT="0" LSB="31" MPD_INDEX="33" MSB="0" NAME="Sl_rdDBus" RIGHT="31" SIGNAME="mb_plb_Sl_rdDBus" VECFORMULA="[0:(C_SPLB_DWIDTH-1)]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdWdAddr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="3" MPD_INDEX="34" MSB="0" NAME="Sl_rdWdAddr" RIGHT="3" SIGNAME="mb_plb_Sl_rdWdAddr" VECFORMULA="[0:3]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdDAck" DIR="O" MPD_INDEX="35" NAME="Sl_rdDAck" SIGNAME="mb_plb_Sl_rdDAck"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdComp" DIR="O" MPD_INDEX="36" NAME="Sl_rdComp" SIGNAME="mb_plb_Sl_rdComp"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_rdBTerm" DIR="O" MPD_INDEX="37" NAME="Sl_rdBTerm" SIGNAME="mb_plb_Sl_rdBTerm"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MBusy" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="38" MSB="0" NAME="Sl_MBusy" RIGHT="1" SIGNAME="mb_plb_Sl_MBusy" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MWrErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="39" MSB="0" NAME="Sl_MWrErr" RIGHT="1" SIGNAME="mb_plb_Sl_MWrErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MRdErr" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="40" MSB="0" NAME="Sl_MRdErr" RIGHT="1" SIGNAME="mb_plb_Sl_MRdErr" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
<PORT BUS="SPLB" DEF_SIGNAME="mb_plb_Sl_MIRQ" DIR="O" ENDIAN="BIG" LEFT="0" LSB="1" MPD_INDEX="41" MSB="0" NAME="Sl_MIRQ" RIGHT="1" SIGNAME="mb_plb_Sl_MIRQ" VECFORMULA="[0:(C_SPLB_NUM_MASTERS-1)]"/>
<PORT DIR="O" MPD_INDEX="42" NAME="IP2INTC_Irpt" SENSITIVITY="LEVEL_HIGH" SIGIS="INTERRUPT" SIGNAME="__NOC__"/>
</PORTS>
<BUSINTERFACES>
<BUSINTERFACE BUSNAME="mb_plb" BUSSTD="PLBV46" BUSSTD_PSF="PLBV46" IS_INSTANTIATED="TRUE" MHS_INDEX="0" MPD_INDEX="0" NAME="SPLB" TYPE="SLAVE">
<PORTMAPS>
<PORTMAP DIR="I" PHYSICAL="SPLB_Clk"/>
<PORTMAP DIR="I" PHYSICAL="SPLB_Rst"/>
<PORTMAP DIR="I" PHYSICAL="PLB_ABus"/>
<PORTMAP DIR="I" PHYSICAL="PLB_UABus"/>
<PORTMAP DIR="I" PHYSICAL="PLB_PAValid"/>
<PORTMAP DIR="I" PHYSICAL="PLB_SAValid"/>
<PORTMAP DIR="I" PHYSICAL="PLB_rdPrim"/>
<PORTMAP DIR="I" PHYSICAL="PLB_wrPrim"/>
<PORTMAP DIR="I" PHYSICAL="PLB_masterID"/>
<PORTMAP DIR="I" PHYSICAL="PLB_abort"/>
<PORTMAP DIR="I" PHYSICAL="PLB_busLock"/>
<PORTMAP DIR="I" PHYSICAL="PLB_RNW"/>
<PORTMAP DIR="I" PHYSICAL="PLB_BE"/>
<PORTMAP DIR="I" PHYSICAL="PLB_MSize"/>
<PORTMAP DIR="I" PHYSICAL="PLB_size"/>
<PORTMAP DIR="I" PHYSICAL="PLB_type"/>
<PORTMAP DIR="I" PHYSICAL="PLB_lockErr"/>
<PORTMAP DIR="I" PHYSICAL="PLB_wrDBus"/>
<PORTMAP DIR="I" PHYSICAL="PLB_wrBurst"/>
<PORTMAP DIR="I" PHYSICAL="PLB_rdBurst"/>
<PORTMAP DIR="I" PHYSICAL="PLB_wrPendReq"/>
<PORTMAP DIR="I" PHYSICAL="PLB_rdPendReq"/>
<PORTMAP DIR="I" PHYSICAL="PLB_wrPendPri"/>
<PORTMAP DIR="I" PHYSICAL="PLB_rdPendPri"/>
<PORTMAP DIR="I" PHYSICAL="PLB_reqPri"/>
<PORTMAP DIR="I" PHYSICAL="PLB_TAttribute"/>
<PORTMAP DIR="O" PHYSICAL="Sl_addrAck"/>
<PORTMAP DIR="O" PHYSICAL="Sl_SSize"/>
<PORTMAP DIR="O" PHYSICAL="Sl_wait"/>
<PORTMAP DIR="O" PHYSICAL="Sl_rearbitrate"/>
<PORTMAP DIR="O" PHYSICAL="Sl_wrDAck"/>
<PORTMAP DIR="O" PHYSICAL="Sl_wrComp"/>
<PORTMAP DIR="O" PHYSICAL="Sl_wrBTerm"/>
<PORTMAP DIR="O" PHYSICAL="Sl_rdDBus"/>
<PORTMAP DIR="O" PHYSICAL="Sl_rdWdAddr"/>
<PORTMAP DIR="O" PHYSICAL="Sl_rdDAck"/>
<PORTMAP DIR="O" PHYSICAL="Sl_rdComp"/>
<PORTMAP DIR="O" PHYSICAL="Sl_rdBTerm"/>
<PORTMAP DIR="O" PHYSICAL="Sl_MBusy"/>
<PORTMAP DIR="O" PHYSICAL="Sl_MWrErr"/>
<PORTMAP DIR="O" PHYSICAL="Sl_MRdErr"/>
<PORTMAP DIR="O" PHYSICAL="Sl_MIRQ"/>
</PORTMAPS>
</BUSINTERFACE>
</BUSINTERFACES>
<MEMORYMAP>
<MEMRANGE BASEDECIMAL="2231369728" BASENAME="C_BASEADDR" BASEVALUE="0x85000000" HIGHDECIMAL="2231435263" HIGHNAME="C_HIGHADDR" HIGHVALUE="0x8500FFFF" MEMTYPE="REGISTER" SIZE="65536" SIZEABRV="64K">
<SLAVES>
<SLAVE BUSINTERFACE="SPLB"/>
</SLAVES>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="2231435264" BASENAME="C_MEM0_BASEADDR" BASEVALUE="0x85010000" HIGHDECIMAL="2231439359" HIGHNAME="C_MEM0_HIGHADDR" HIGHVALUE="0x85010FFF" MEMTYPE="MEMORY" SIZE="4096" SIZEABRV="4K">
<SLAVES>
<SLAVE BUSINTERFACE="SPLB"/>
</SLAVES>
</MEMRANGE>
<MEMRANGE BASEDECIMAL="2231439360" BASENAME="C_MEM1_BASEADDR" BASEVALUE="0x85011000" HIGHDECIMAL="2231443455" HIGHNAME="C_MEM1_HIGHADDR" HIGHVALUE="0x85011FFF" MEMTYPE="MEMORY" SIZE="4096" SIZEABRV="4K">
<SLAVES>
<SLAVE BUSINTERFACE="SPLB"/>
</SLAVES>
</MEMRANGE>
</MEMORYMAP>
</MODULE>
</MODULES>
</EDKSYSTEM>
\ No newline at end of file
projnav/xps/etc/system.filters
View file @ 23405448
......@@ -4,8 +4,8 @@
<IDENTIFICATION VERSION="1.2" XTLVERSION="1.2"/>
<SET CLASS="PROJECT" VIEW_ID="BUSINTERFACE">
<HEADERS>
<VARIABLE COL_WIDTH="50" IS_VISIBLE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="HEADER"/>
<HEADERS HSCROLL="0" VSCROLL="0">
<VARIABLE COL_INDEX="0" COL_WIDTH="447" IS_VISIBLE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="HEADER"/>
</HEADERS>
<SET CLASS="FILTER_GROUP" ID="By Connection" IS_EXPANDED="TRUE">
<VARIABLE NAME="By Connection" VALUE="By Connection" VIEWDISP="Bus Interface Filters" VIEWTYPE="STATIC"/>
......@@ -97,8 +97,8 @@
</SET>
<SET CLASS="PROJECT" VIEW_ID="PORT">
<HEADERS>
<VARIABLE COL_WIDTH="50" IS_VISIBLE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="HEADER"/>
<HEADERS HSCROLL="0" VSCROLL="0">
<VARIABLE COL_INDEX="0" COL_WIDTH="376" IS_VISIBLE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="HEADER"/>
</HEADERS>
<SET CLASS="FILTER_GROUP" ID="By Interface" IS_EXPANDED="TRUE">
<VARIABLE NAME="By Interface" VALUE="By Interface" VIEWDISP="Port Filters" VIEWTYPE="STATIC"/>
......
projnav/xps/etc/system.gui
View file @ 23405448
......@@ -9,11 +9,12 @@
<VARIABLE COL_INDEX="1" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Bus Name" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="2" IS_VISIBLE="FALSE" VIEWDISP="Bus Standard" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="3" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="4" COL_WIDTH="642" IS_VISIBLE="TRUE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="4" COL_WIDTH="813" IS_VISIBLE="TRUE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="5" IS_VISIBLE="FALSE" VIEWDISP="IP Classification" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="6" IS_VISIBLE="FALSE" VIEWDISP="Type" VIEWTYPE="HEADER"/>
</HEADERS>
<SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="180,450,180" VERSION="0"/>
<SET ID="spiifc_0" IS_EXPANDED="TRUE"/>
<STATUS>
<SELECTIONS/>
</STATUS>
......@@ -25,12 +26,13 @@
<VARIABLE ID="dlmb_cntlr" ROW_INDEX="5"/>
<VARIABLE ID="ilmb_cntlr" ROW_INDEX="6"/>
<VARIABLE ID="lmb_bram" ROW_INDEX="4"/>
<VARIABLE ID="DIP_Switches_8Bits" ROW_INDEX="8"/>
<VARIABLE ID="LEDs_8Bits" ROW_INDEX="9"/>
<VARIABLE ID="Push_Buttons_5Bits" ROW_INDEX="10"/>
<VARIABLE ID="clock_generator_0" ROW_INDEX="11"/>
<VARIABLE ID="mdm_0" ROW_INDEX="7"/>
<VARIABLE ID="proc_sys_reset_0" ROW_INDEX="12"/>
<VARIABLE ID="DIP_Switches_8Bits" ROW_INDEX="9"/>
<VARIABLE ID="LEDs_8Bits" ROW_INDEX="10"/>
<VARIABLE ID="Push_Buttons_5Bits" ROW_INDEX="11"/>
<VARIABLE ID="clock_generator_0" ROW_INDEX="12"/>
<VARIABLE ID="mdm_0" ROW_INDEX="8"/>
<VARIABLE ID="proc_sys_reset_0" ROW_INDEX="13"/>
<VARIABLE ID="spiifc_0" IS_EXPANDED="TRUE" ROW_INDEX="7"/>
</SEQUENCES>
</SET>
......@@ -76,20 +78,41 @@
</SET>
<SET CLASS="PROJECT" DISPLAYMODE="TREE" VIEW_ID="PORT">
<HEADERS>
<VARIABLE COL_INDEX="0" IS_VISIBLE="TRUE" VIEWDISP="Name" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="1" IS_VISIBLE="TRUE" VIEWDISP="Net" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="2" IS_VISIBLE="TRUE" VIEWDISP="Direction" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="3" IS_VISIBLE="TRUE" VIEWDISP="Range" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="4" IS_VISIBLE="TRUE" VIEWDISP="Class" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="5" IS_VISIBLE="TRUE" VIEWDISP="Frequency(Hz)" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="6" IS_VISIBLE="TRUE" VIEWDISP="Reset Polarity" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="7" IS_VISIBLE="TRUE" VIEWDISP="Sensitivity" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="8" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
<HEADERS HSCROLL="0" VSCROLL="0">
<VARIABLE COL_INDEX="0" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Name" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="1" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Net" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="2" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Direction" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="3" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Range" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="4" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Class" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="5" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Frequency(Hz)" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="6" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Reset Polarity" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="7" COL_WIDTH="413" IS_VISIBLE="TRUE" VIEWDISP="Sensitivity" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="8" COL_WIDTH="213" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="9" IS_VISIBLE="FALSE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="10" IS_VISIBLE="TRUE" VIEWDISP="IP Classification" VIEWTYPE="HEADER"/>
</HEADERS>
<SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="0,630,180" VERSION="0"/>
<SET ID="spiifc_0" IS_EXPANDED="TRUE"/>
<STATUS>
<SELECTIONS/>
</STATUS>
<SEQUENCES IS_DEF_SEQUENCES="TRUE">
<VARIABLE ID="ExternalPorts" ROW_INDEX="0"/>
<VARIABLE ID="microblaze_0" ROW_INDEX="4"/>
<VARIABLE ID="mb_plb" ROW_INDEX="3"/>
<VARIABLE ID="ilmb" ROW_INDEX="2"/>
<VARIABLE ID="dlmb" ROW_INDEX="1"/>
<VARIABLE ID="dlmb_cntlr" ROW_INDEX="6"/>
<VARIABLE ID="ilmb_cntlr" ROW_INDEX="7"/>
<VARIABLE ID="lmb_bram" ROW_INDEX="5"/>
<VARIABLE ID="DIP_Switches_8Bits" ROW_INDEX="10"/>
<VARIABLE ID="LEDs_8Bits" ROW_INDEX="11"/>
<VARIABLE ID="Push_Buttons_5Bits" ROW_INDEX="12"/>
<VARIABLE ID="clock_generator_0" ROW_INDEX="13"/>
<VARIABLE ID="mdm_0" ROW_INDEX="9"/>
<VARIABLE ID="proc_sys_reset_0" ROW_INDEX="14"/>
<VARIABLE ID="spiifc_0" IS_EXPANDED="TRUE" ROW_INDEX="8"/>
</SEQUENCES>
</SET>
<SET CLASS="PROJECT" DISPLAYMODE="FOCUS_TREE" VIEW_ID="PORT">
......@@ -159,12 +182,16 @@
<VARIABLE COL_INDEX="8" IS_VISIBLE="FALSE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="10" IS_VISIBLE="FALSE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="7" IS_VISIBLE="FALSE" VIEWDISP="Address Type" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="9" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Lock" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="9" COL_WIDTH="894" IS_VISIBLE="TRUE" VIEWDISP="Lock" VIEWTYPE="HEADER"/>
</HEADERS>
<SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="0,630,180" VERSION="0"/>
<SET ID="microblaze_0" IS_EXPANDED="TRUE"/>
<STATUS IS_EXPANDED="TRUE">
<STATUS>
<SELECTIONS/>
</STATUS>
<SEQUENCES IS_DEF_SEQUENCES="TRUE">
<VARIABLE ID="microblaze_0" IS_EXPANDED="TRUE" ROW_INDEX="0"/>
</SEQUENCES>
</SET>
<SET CLASS="PROJECT" DISPLAYMODE="FLAT" VIEW_ID="ADDRESS">
......
projnav/xps/implementation/system_summary.html
View file @ 23405448
......@@ -31,11 +31,7 @@
<TR ALIGN=LEFT><TD>Platgen Log File</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Simgen Log File</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>BitInit Log File</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/mjlyons/workspace/vSPI/projnav/xps\system.log'>System Log File</A></TD><TD>Tue Feb 28 11:11:32 2012</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>XPS Synthesis Summary (estimated values)</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=EDKSynthesisSumary"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report</B></TD><TD><B>Generated</B></TD><TD><B>Flip Flops Used</B></TD><TD><B>LUTs Used</B></TD><TD><B>BRAMS Used</B></TD><TD COLSPAN='2'><B>Errors</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/mjlyons/workspace/vSPI/projnav/xps\system.log'>System Log File</A></TD><TD>Tue Feb 28 19:37:57 2012</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
</TABLE>
......@@ -61,5 +57,5 @@
</TABLE>
<br><center><b>Date Generated:</b> 02/28/2012 - 11:11:33</center>
<br><center><b>Date Generated:</b> 02/28/2012 - 19:37:57</center>
</BODY></HTML>
\ No newline at end of file
projnav/xps/pcores/spiifc.prj 0 → 100644
View file @ 23405448
vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v3_00_a\hdl\vhdl\proc_common_pkg.vhd"
vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v3_00_a\hdl\vhdl\or_muxcy.vhd"
vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v3_00_a\hdl\vhdl\family_support.vhd"
vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v3_00_a\hdl\vhdl\pselect_f.vhd"
vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v3_00_a\hdl\vhdl\or_gate128.vhd"
vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v3_00_a\hdl\vhdl\ipif_pkg.vhd"
vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v3_00_a\hdl\vhdl\counter_f.vhd"
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_slave_burst_v1_01_a\hdl\vhdl\flex_addr_cntr.vhd"
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_slave_burst_v1_01_a\hdl\vhdl\wr_buffer.vhd"
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_slave_burst_v1_01_a\hdl\vhdl\plb_address_decoder.vhd"
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_slave_burst_v1_01_a\hdl\vhdl\burst_support.vhd"
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_slave_burst_v1_01_a\hdl\vhdl\be_reset_gen.vhd"
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_slave_burst_v1_01_a\hdl\vhdl\addr_reg_cntr_brst_flex.vhd"
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_slave_burst_v1_01_a\hdl\vhdl\plb_slave_attachment.vhd"
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_slave_burst_v1_01_a\hdl\vhdl\data_mirror_128.vhd"
verilog spiifc_v1_00_a "C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav\ipcore_dir\buffermem.v"
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_slave_burst_v1_01_a\hdl\vhdl\plbv46_slave_burst.vhd"
vhdl interrupt_control_v2_01_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\interrupt_control_v2_01_a\hdl\vhdl\interrupt_control.vhd"
verilog spiifc_v1_00_a "C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\hdl\verilog\user_logic.v"
vhdl spiifc_v1_00_a "C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\hdl\vhdl\spiifc.vhd"
projnav/xps/pcores/spiifc_v1_00_a/data/spiifc_v2_1_0.bbd 0 → 100644
View file @ 23405448
##############################################################################
## Filename: C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores/spiifc_v1_00_a/data/spiifc_v2_1_0.bbd
## Description: Black Box Definition
## Date: Tue Feb 28 16:31:09 2012 (by Create and Import Peripheral Wizard)
##############################################################################
Files
################################################################################
buffermem.ngc
projnav/xps/pcores/spiifc_v1_00_a/data/spiifc_v2_1_0.mpd
View file @ 23405448
......@@ -13,31 +13,31 @@ OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = MIXED
OPTION IP_GROUP = MICROBLAZE:PPC:USER
OPTION DESC = SPIIFC
OPTION ARCH_SUPPORT_MAP = (others=DEVELOPMENT)
OPTION STYLE = MIX
OPTION RUN_NGCBUILD = TRUE
## Bus Interfaces
BUS_INTERFACE BUS = SPLB, BUS_STD = PLBV46, BUS_TYPE = SLAVE
## Generics for VHDL or Parameters for Verilog
PARAMETER C_BASEADDR = 0xffffffff, DT = std_logic_vector, MIN_SIZE = 0x200, PAIR = C_HIGHADDR, ADDRESS = BASE, BUS = SPLB
PARAMETER C_BASEADDR = 0xffffffff, DT = std_logic_vector, PAIR = C_HIGHADDR, ADDRESS = BASE, BUS = SPLB
PARAMETER C_HIGHADDR = 0x00000000, DT = std_logic_vector, PAIR = C_BASEADDR, ADDRESS = HIGH, BUS = SPLB
PARAMETER C_SPLB_AWIDTH = 32, DT = INTEGER, BUS = SPLB, ASSIGNMENT = CONSTANT
PARAMETER C_SPLB_DWIDTH = 128, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128)
PARAMETER C_SPLB_NUM_MASTERS = 8, DT = INTEGER, BUS = SPLB, RANGE = (1:16)
PARAMETER C_SPLB_MID_WIDTH = 3, DT = INTEGER, BUS = SPLB, RANGE = (1:4)
PARAMETER C_SPLB_NATIVE_DWIDTH = 32, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128), ASSIGNMENT = CONSTANT
PARAMETER C_SPLB_P2P = 0, DT = INTEGER, BUS = SPLB, RANGE = (0, 1)
PARAMETER C_SPLB_SUPPORT_BURSTS = 1, DT = INTEGER, BUS = SPLB, RANGE = (0, 1), ASSIGNMENT = CONSTANT
PARAMETER C_SPLB_SMALLEST_MASTER = 32, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128)
PARAMETER C_SPLB_AWIDTH = 32, DT = INTEGER, BUS = SPLB
PARAMETER C_SPLB_DWIDTH = 128, DT = INTEGER, BUS = SPLB
PARAMETER C_SPLB_NUM_MASTERS = 8, DT = INTEGER, BUS = SPLB
PARAMETER C_SPLB_MID_WIDTH = 3, DT = INTEGER, BUS = SPLB
PARAMETER C_SPLB_NATIVE_DWIDTH = 32, DT = INTEGER, BUS = SPLB
PARAMETER C_SPLB_P2P = 0, DT = INTEGER, BUS = SPLB
PARAMETER C_SPLB_SUPPORT_BURSTS = 1, DT = INTEGER, BUS = SPLB
PARAMETER C_SPLB_SMALLEST_MASTER = 32, DT = INTEGER, BUS = SPLB
PARAMETER C_SPLB_CLK_PERIOD_PS = 10000, DT = INTEGER, BUS = SPLB
PARAMETER C_INCLUDE_DPHASE_TIMER = 1, DT = INTEGER, RANGE = (0, 1)
PARAMETER C_INCLUDE_DPHASE_TIMER = 1, DT = INTEGER
PARAMETER C_FAMILY = virtex6, DT = STRING
PARAMETER C_MEM0_BASEADDR = 0xffffffff, DT = std_logic_vector, PAIR = C_MEM0_HIGHADDR, ADDRESS = BASE, BUS = SPLB
PARAMETER C_MEM0_HIGHADDR = 0x00000000, DT = std_logic_vector, PAIR = C_MEM0_BASEADDR, ADDRESS = HIGH, BUS = SPLB
PARAMETER C_MEM1_BASEADDR = 0xffffffff, DT = std_logic_vector, PAIR = C_MEM1_HIGHADDR, ADDRESS = BASE, BUS = SPLB
PARAMETER C_MEM1_HIGHADDR = 0x00000000, DT = std_logic_vector, PAIR = C_MEM1_BASEADDR, ADDRESS = HIGH, BUS = SPLB
PARAMETER C_MEM0_BASEADDR = 0xffffffff, DT = std_logic_vector, PAIR = C_MEM0_HIGHADDR, ADDRESS = BASE, BUS = SPLB, ADDR_TYPE = MEMORY
PARAMETER C_MEM0_HIGHADDR = 0x00000000, DT = std_logic_vector, PAIR = C_MEM0_BASEADDR, ADDRESS = HIGH, BUS = SPLB, ADDR_TYPE = MEMORY
PARAMETER C_MEM1_BASEADDR = 0xffffffff, DT = std_logic_vector, PAIR = C_MEM1_HIGHADDR, ADDRESS = BASE, BUS = SPLB, ADDR_TYPE = MEMORY
PARAMETER C_MEM1_HIGHADDR = 0x00000000, DT = std_logic_vector, PAIR = C_MEM1_BASEADDR, ADDRESS = HIGH, BUS = SPLB, ADDR_TYPE = MEMORY
## Ports
PORT SPLB_Clk = "", DIR = I, SIGIS = CLK, BUS = SPLB
......
projnav/xps/pcores/spiifc_v1_00_a/data/spiifc_v2_1_0.pao
View file @ 23405448
##############################################################################
## Filename: C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/data/spiifc_v2_1_0.pao
## Filename: C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores/spiifc_v1_00_a/data/spiifc_v2_1_0.pao
## Description: Peripheral Analysis Order
## Date: Tue Feb 28 11:11:15 2012 (by Create and Import Peripheral Wizard)
## Date: Tue Feb 28 16:31:09 2012 (by Create and Import Peripheral Wizard)
##############################################################################
lib proc_common_v3_00_a all
lib plbv46_slave_burst_v1_01_a all
lib interrupt_control_v2_01_a all
lib proc_common_v3_00_a proc_common_pkg vhdl
lib proc_common_v3_00_a or_muxcy vhdl
lib proc_common_v3_00_a family_support vhdl
lib proc_common_v3_00_a pselect_f vhdl
lib proc_common_v3_00_a or_gate128 vhdl
lib proc_common_v3_00_a ipif_pkg vhdl
lib proc_common_v3_00_a counter_f vhdl
lib plbv46_slave_burst_v1_01_a flex_addr_cntr vhdl
lib plbv46_slave_burst_v1_01_a wr_buffer vhdl
lib plbv46_slave_burst_v1_01_a plb_address_decoder vhdl
lib plbv46_slave_burst_v1_01_a burst_support vhdl
lib plbv46_slave_burst_v1_01_a be_reset_gen vhdl
lib plbv46_slave_burst_v1_01_a addr_reg_cntr_brst_flex vhdl
lib plbv46_slave_burst_v1_01_a plb_slave_attachment vhdl
lib plbv46_slave_burst_v1_01_a data_mirror_128 vhdl
lib spiifc_v1_00_a buffermem verilog
lib plbv46_slave_burst_v1_01_a plbv46_slave_burst vhdl
lib interrupt_control_v2_01_a interrupt_control vhdl
lib spiifc_v1_00_a user_logic verilog
lib spiifc_v1_00_a spiifc vhdl
projnav/xps/pcores/spiifc_v1_00_a/devl/ipwiz.log deleted 100644 → 0
View file @ 7133e87e
----------------------------------------------------------------------------
-- Design Analysis --
----------------------------------------------------------------------------
Analyze pcore spiifc ...
----------------------------------------------------------------------------
-- Design Analysis --
----------------------------------------------------------------------------
Analyze pcore spiifc ...
----------------------------------------------------------------------------
-- Design Analysis --
----------------------------------------------------------------------------
Analyze pcore spiifc ...
----------------------------------------------------------------------------
-- File Generation --
----------------------------------------------------------------------------
Creating HDL source directory ...
Generating top peripheral VHDL template ...
Generating stub user logic Verilog template ...
HDL templates successfully generated ...
Creating data directory ...
Generating XPS inteface files ...
WARNING:HDLParsers:3497 - Ignoring Verilog File
"C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/data/../hd
l/verilog/user_logic.v"
Compiling vhdl file
"C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/family_support.vhd" in Library proc_common_v3_00_a.
Package <family_support> compiled.
Package body <family_support> compiled.
Compiling vhdl file
"C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/or_muxcy.vhd" in Library proc_common_v3_00_a.
Entity <or_muxcy> compiled.
Entity <or_muxcy> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/proc_common_pkg.vhd" in Library proc_common_v3_00_a.
Package <proc_common_pkg> compiled.
Package body <proc_common_pkg> compiled.
Compiling vhdl file
"C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/ipif_pkg.vhd" in Library proc_common_v3_00_a.
Package <ipif_pkg> compiled.
Package body <ipif_pkg> compiled.
Compiling vhdl file
"C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/or_gate128.vhd" in Library proc_common_v3_00_a.
Entity <or_gate128> compiled.
Entity <or_gate128> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/pselect_f.vhd" in Library proc_common_v3_00_a.
Entity <pselect_f> compiled.
Entity <pselect_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
l/vhdl/counter_f.vhd" in Library proc_common_v3_00_a.
Entity <counter_f> compiled.
Entity <counter_f> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_
01_a/hdl/vhdl/flex_addr_cntr.vhd" in Library plbv46_slave_burst_v1_01_a.
Entity <flex_addr_cntr> compiled.
Entity <flex_addr_cntr> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_
01_a/hdl/vhdl/be_reset_gen.vhd" in Library plbv46_slave_burst_v1_01_a.
Entity <be_reset_gen> compiled.
Entity <be_reset_gen> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_
01_a/hdl/vhdl/plb_address_decoder.vhd" in Library plbv46_slave_burst_v1_01_a.
Entity <plb_address_decoder> compiled.
Entity <plb_address_decoder> (Architecture <IMP>) compiled.
Compiling vhdl file
"C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_
01_a/hdl/vhdl/wr_buffer.vhd" in Library plbv46_slave_burst_v1_01_a.
Entity <wr_buffer> compiled.
Entity <wr_buffer> (Architecture <imp>) compiled.
Compiling vhdl file
"C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_
01_a/hdl/vhdl/burst_support.vhd" in Library plbv46_slave_burst_v1_01_a.
Entity <burst_support> compiled.
Entity <burst_support> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_
01_a/hdl/vhdl/addr_reg_cntr_brst_flex.vhd" in Library
plbv46_slave_burst_v1_01_a.
Entity <addr_reg_cntr_brst_flex> compiled.
Entity <addr_reg_cntr_brst_flex> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_
01_a/hdl/vhdl/plb_slave_attachment.vhd" in Library plbv46_slave_burst_v1_01_a.
Entity <plb_slave_attachment> compiled.
Entity <plb_slave_attachment> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_
01_a/hdl/vhdl/data_mirror_128.vhd" in Library plbv46_slave_burst_v1_01_a.
Entity <data_mirror_128> compiled.
Entity <data_mirror_128> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v2_0
1_a/hdl/vhdl/interrupt_control.vhd" in Library interrupt_control_v2_01_a.
Entity <interrupt_control> compiled.
Entity <interrupt_control> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_
01_a/hdl/vhdl/plbv46_slave_burst.vhd" in Library plbv46_slave_burst_v1_01_a.
Entity <plbv46_slave_burst> compiled.
Entity <plbv46_slave_burst> (Architecture <implementation>) compiled.
Compiling vhdl file
"C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/data/../hdl/v
hdl/spiifc.vhd" in Library spiifc_v1_00_a.
Entity <spiifc> compiled.
Entity <spiifc> (Architecture <IMP>) compiled.
Analyzing HDL attributes ...
Entity name = spiifc
INFO:EDK:1607 - IPTYPE set to value : PERIPHERAL
INFO:EDK:1511 - IMP_NETLIST set to value : TRUE
INFO:EDK:1486 - HDL set to value : VHDL
WARNING:EDK:3588 - Unable to delete temporary XST project file
C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\data\_spiif
c_xst.prj : 13
XPS interface files successfully generated ...
Creating development directory ...
Generating command option file ...
Generating readme file ...
Development misc files successfully generated ...
Creating projnav directory ...
Generating ProjNav support files ...
ProjNav support files successfully generated ...
Creating synthesis directory ...
Generating XST synthesis support files ...
XST synthesis support files successfully generated ...
No BFM simulation files will be generated at this time ...
Creating software driver data directory ...
Generating software driver XPS interface (mdd/tcl) files ...
Software driver data definition file (.mdd) successfully generated ...
Software driver data generation file (.tcl) successfully generated ...
Creating software driver src directory ...
Generating software driver template files ...
Software driver compile file (Makefile) successfully generated ...
output user slave register(s) offset to software driver header ...
output interrupt control register(s) offset to software driver header ...
Software driver header file (.h) successfully generated ...
Software driver source file (.c) successfully generated ...
Software driver SelfTest file (.c) successfully generated ...
Software driver template files successfully generated ...
----------------------------------------------------------------------------
-- Final Report --
----------------------------------------------------------------------------
Thank you for using Create and Import Peripheral Wizard! Please find your
peripheral hardware templates under
C:\Users\mjlyons\workspace\vSPI\projnav\xps/pcores/spiifc_v1_00_a and peripheral
software templates under
C:\Users\mjlyons\workspace\vSPI\projnav\xps/drivers/spiifc_v1_00_a respectively.
Peripheral Summary:
top name : spiifc
version : 1.00.a
type : PLB (v4.6) slave
features : slave attachment
interrupt control
user s/w registers
user memory spaces
Address Block Summary:
user logic slv : C_BASEADDR + 0x00000000
: C_BASEADDR + 0x000000FF
interrupt : C_BASEADDR + 0x00000100
: C_BASEADDR + 0x000001FF
user memory 0 : C_MEM0_BASEADDR
: C_MEM0_HIGHADDR
user memory 1 : C_MEM1_BASEADDR
: C_MEM1_HIGHADDR
File Summary
- HDL source -
C:\Users\mjlyons\workspace\vSPI\projnav\xps/pcores/spiifc_v1_00_a/hdl
top entity : vhdl/spiifc.vhd
user logic : verilog/user_logic.v
- XPS interface -
C:\Users\mjlyons\workspace\vSPI\projnav\xps/pcores/spiifc_v1_00_a/data
mpd : spiifc_v2_1_0.mpd
pao : spiifc_v2_1_0.pao
- ISE project -
C:\Users\mjlyons\workspace\vSPI\projnav\xps/pcores/spiifc_v1_00_a/devl/projnav
ise project : spiifc.xise
tcl script : spiifc.tcl
- XST synthesis -
C:\Users\mjlyons\workspace\vSPI\projnav\xps/pcores/spiifc_v1_00_a/devl/synthesis
xst script : spiifc_xst.scr
xst project : spiifc_xst.prj
- Misc file -
C:\Users\mjlyons\workspace\vSPI\projnav\xps/pcores/spiifc_v1_00_a/devl
help : README.txt
option : ipwiz.opt
log : ipwiz.log
- Driver source -
C:\Users\mjlyons\workspace\vSPI\projnav\xps/drivers/spiifc_v1_00_a/src
makefile : Makefile
header : spiifc.h
source : spiifc.c
selftest : spiifc_selftest.c
- Driver interface -
C:\Users\mjlyons\workspace\vSPI\projnav\xps/drivers/spiifc_v1_00_a/data
mdd : spiifc_v2_1_0.mdd
tcl : spiifc_v2_1_0.tcl
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/_xmsgs/cg.xmsgs 0 → 100644
View file @ 23405448
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="sim" num="0" delta="new" >Generating component instance &apos;<arg fmt="%s" index="1">buffermem</arg>&apos; of &apos;<arg fmt="%s" index="2">xilinx.com:ip:blk_mem_gen:6.2</arg>&apos; from &apos;<arg fmt="%s" index="3">C:\Xilinx\13.2\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\blk_mem_gen_v6_2\component.xml</arg>&apos;.
</msg>
<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Can&apos;t find &apos;Verilog&apos; synthesis view; using general synthesis view</arg>
</msg>
<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Pre-processing HDL files for &apos;buffermem&apos;...</arg>
</msg>
<msg type="info" file="sim" num="0" delta="new" >Finished FLIST file generation.
</msg>
</messages>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/_xmsgs/pn_parser.xmsgs → projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/_xmsgs/pn_parser.xmsgs
View file @ 23405448
......@@ -8,7 +8,7 @@
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v2_01_a/hdl/vhdl/interrupt_control.vhd&quot; into library interrupt_control_v2_01_a</arg>
<msg type="info" file="ProjectMgmt" num="1769" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem.v\&quot; into library work</arg>
</msg>
</messages>
......
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/blk_mem_gen_v6_2_readme.txt 0 → 100644
View file @ 23405448
Core name: Xilinx LogiCORE Block Memory Generator
Version: 6.2
Release Date: June 22, 2011
================================================================================
This document contains the following sections:
1. Introduction
2. New Features
3. Supported Devices
4. Resolved Issues
5. Known Issues
6. Technical Support
7. Core Release History
8. Legal Disclaimer
================================================================================
1. INTRODUCTION
For installation instructions for this release, please go to:
http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
For system requirements:
http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
This file contains release notes for the Xilinx LogiCORE IP Block Memory Generator v6.2
solution. For the latest core updates, see the product page at:
http://www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm
2. NEW FEATURES
- ISE 13.2 software support
- Virtex-7L, Kintex-7L, Artix-7* and Zynq-7000* device support
3. SUPPORTED DEVICES
The following device families are supported by the core for this release.
Zynq-7000*
Virtex-7
Virtex-7 XT (7vx485t)
Virtex-7 -2L
Kintex-7
Kintex-7 -2L
Artix-7*
Virtex-6 XC CXT/LXT/SXT/HXT
Virtex-6 XQ LXT/SXT
Virtex-6 -1L XQ LXT/SXT
Spartan-6 XC LX/LXT
Spartan-6 XA
Spartan-6 XQ LX/LXT
Spartan-6 -1L XQ LX
Virtex-5 XC LX/LXT/SXT/TXT/FXT
Virtex-5 XQ LX/ LXT/SXT/FXT
Virtex-4 XC LX/SX/FX
Virtex-4 XQ LX/SX/FX
Virtex-4 XQR LX/SX/FX
Spartan-3 XC
Spartan-3 XA
Spartan-3A XC 3A / 3A DSP / 3AN DSP
Spartan-3A XA 3A / 3A DSP
Spartan-3E XC
Spartan-3E XA
*To access these devices in the ISE Design Suite, contact your Xilinx FAE.
4. RESOLVED ISSUES
The following issues are resolved in Block Memory Generator v6.2:
1. Core errors in NGDBuild when the depth is too large (especially for Spartan-6 devices)
Version Fixed: v6.2
- CR 587481
- AR 39718
5. KNOWN ISSUES
The following are known issues for v6.2 of this core at time of release:
1. Virtex-6 and Spartan-6: BRAM Memory collision error, when the user selects TDP (write_mode= Read First)
Work around: The user must review the possible scenarios that causes the collission and revise
their design to avoid those situations.
- CR588505
Note: Refer to UG383, 'Conflict Avoidance' section when using TDP Memory - with
Write Mode = Read First in conjunction with asynchronous clocking
2. Power estimation figures in the datasheet are preliminary for Virtex-5 and Spartan-3.
3. Core does not generate for large memories. Depending on the
machine the ISE CORE Generator software runs on, the maximum size of the memory that
can be generated will vary. For example, a Dual Pentium-4 server
with 2 GB RAM can generate a memory core of size 1.8 MBits or 230 KBytes
- CR 415768
- AR 24034
The most recent information, including known issues, workarounds, and resolutions for
this version is provided in the IP Release Notes User Guide located at
www.xilinx.com/support/documentation/user_guides/xtp025.pdf
6. TECHNICAL SUPPORT
To obtain technical support, create a WebCase at www.xilinx.com/support.
Questions are routed to a team with expertise using this product.
Xilinx provides technical support for use of this product when used
according to the guidelines described in the core documentation, and
cannot guarantee timing, functionality, or support of this product for
designs that do not follow specified guidelines.
7. CORE RELEASE HISTORY
Date By Version Description
================================================================================
06/22/2011 Xilinx, Inc. 6.2 ISE 13.2 support;Virtex-7L,Kintex-7L,Artix7 and Zynq-7000* device support;
03/01/2011 Xilinx, Inc. 6.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; AXI4/AXI4-Lite Support
09/21/2010 Xilinx, Inc. 4.3 ISE 12.3 support
07/23/2010 Xilinx, Inc. 4.2 ISE 12.2 support
04/19/2010 Xilinx, Inc. 4.1 ISE 12.1 support
03/09/2010 Xilinx, Inc. 3.3 rev 2 Fix for V6 Memory collision issue
12/02/2009 Xilinx, Inc. 3.3 rev 1 ISE 11.4 support; Spartan-6 Low Power
Device support; Automotive Spartan 3A
DSP device support
09/16/2009 Xilinx, Inc. 3.3 Revised to v3.3
06/24/2009 Xilinx, Inc. 3.2 Revised to v3.2
04/24/2009 Xilinx, Inc. 3.1 Revised to v3.1
09/19/2008 Xilinx, Inc. 2.8 Revised to v2.8
03/24/2008 Xilinx, Inc. 2.7 10.1 support; Revised to v2.7
10/03/2007 Xilinx, Inc. 2.6 Revised to v2.6
07/2007 Xilinx, Inc. 2.5 Revised to v2.5
04/2007 Xilinx, Inc. 2.4 Revised to v2.4 rev 1
02/2007 Xilinx, Inc. 2.4 Revised to v2.4
11/2006 Xilinx, Inc. 2.3 Revised to v2.3
09/2006 Xilinx, Inc. 2.2 Revised to v2.2
06/2006 Xilinx, Inc. 2.1 Revised to v2.1
01/2006 Xilinx, Inc. 1.1 Initial release
================================================================================
8. Legal Disclaimer
(c) Copyright 2006 - 2011 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or Xilinx had been advised of the
possibility of the same.
CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of Xilinx products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem.asy 0 → 100644
View file @ 23405448
Version 4
SymbolType BLOCK
TEXT 32 32 LEFT 4 buffermem
RECTANGLE Normal 32 32 544 1376
LINE Wide 0 80 32 80
PIN 0 80 LEFT 36
PINATTR PinName addra[11:0]
PINATTR Polarity IN
LINE Wide 0 112 32 112
PIN 0 112 LEFT 36
PINATTR PinName dina[7:0]
PINATTR Polarity IN
LINE Normal 0 144 32 144
PIN 0 144 LEFT 36
PINATTR PinName ena
PINATTR Polarity IN
LINE Wide 0 208 32 208
PIN 0 208 LEFT 36
PINATTR PinName wea[0:0]
PINATTR Polarity IN
LINE Normal 0 272 32 272
PIN 0 272 LEFT 36
PINATTR PinName clka
PINATTR Polarity IN
LINE Wide 0 432 32 432
PIN 0 432 LEFT 36
PINATTR PinName addrb[9:0]
PINATTR Polarity IN
LINE Wide 0 464 32 464
PIN 0 464 LEFT 36
PINATTR PinName dinb[31:0]
PINATTR Polarity IN
LINE Normal 0 496 32 496
PIN 0 496 LEFT 36
PINATTR PinName enb
PINATTR Polarity IN
LINE Wide 0 560 32 560
PIN 0 560 LEFT 36
PINATTR PinName web[0:0]
PINATTR Polarity IN
LINE Normal 0 624 32 624
PIN 0 624 LEFT 36
PINATTR PinName clkb
PINATTR Polarity IN
LINE Wide 576 80 544 80
PIN 576 80 RIGHT 36
PINATTR PinName douta[7:0]
PINATTR Polarity OUT
LINE Wide 576 368 544 368
PIN 576 368 RIGHT 36
PINATTR PinName doutb[31:0]
PINATTR Polarity OUT
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem.gise 0 → 100644
View file @ 23405448
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="buffermem.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="blk_mem_gen_v6_2_readme.txt" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_ASY" xil_pn:name="buffermem.asy" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="buffermem.sym" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VEO" xil_pn:name="buffermem.veo" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
</generated_project>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem.ngc 0 → 100644
View file @ 23405448
XILINX-XDB 0.1 STUB 0.1 ASCII
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\ No newline at end of file
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem.sym 0 → 100644
View file @ 23405448
<?xml version="1.0" encoding="UTF-8"?>
<symbol version="7" name="buffermem">
<symboltype>BLOCK</symboltype>
<timestamp>2012-2-28T17:6:39</timestamp>
<pin polarity="Input" x="0" y="80" name="addra[11:0]" />
<pin polarity="Input" x="0" y="112" name="dina[7:0]" />
<pin polarity="Input" x="0" y="144" name="ena" />
<pin polarity="Input" x="0" y="208" name="wea[0:0]" />
<pin polarity="Input" x="0" y="272" name="clka" />
<pin polarity="Input" x="0" y="432" name="addrb[9:0]" />
<pin polarity="Input" x="0" y="464" name="dinb[31:0]" />
<pin polarity="Input" x="0" y="496" name="enb" />
<pin polarity="Input" x="0" y="560" name="web[0:0]" />
<pin polarity="Input" x="0" y="624" name="clkb" />
<pin polarity="Output" x="576" y="80" name="douta[7:0]" />
<pin polarity="Output" x="576" y="368" name="doutb[31:0]" />
<graph>
<text style="fontsize:40;fontname:Arial" x="32" y="32">buffermem</text>
<rect width="512" x="32" y="32" height="1344" />
<line x2="32" y1="80" y2="80" style="linewidth:W" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="80" type="pin addra[11:0]" />
<line x2="32" y1="112" y2="112" style="linewidth:W" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="112" type="pin dina[7:0]" />
<line x2="32" y1="144" y2="144" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="144" type="pin ena" />
<line x2="32" y1="208" y2="208" style="linewidth:W" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="208" type="pin wea[0:0]" />
<line x2="32" y1="272" y2="272" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="272" type="pin clka" />
<line x2="32" y1="432" y2="432" style="linewidth:W" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="432" type="pin addrb[9:0]" />
<line x2="32" y1="464" y2="464" style="linewidth:W" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="464" type="pin dinb[31:0]" />
<line x2="32" y1="496" y2="496" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="496" type="pin enb" />
<line x2="32" y1="560" y2="560" style="linewidth:W" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="560" type="pin web[0:0]" />
<line x2="32" y1="624" y2="624" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="624" type="pin clkb" />
<line x2="544" y1="80" y2="80" style="linewidth:W" x1="576" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="80" type="pin douta[7:0]" />
<line x2="544" y1="368" y2="368" style="linewidth:W" x1="576" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="368" type="pin doutb[31:0]" />
</graph>
</symbol>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem.v 0 → 100644
View file @ 23405448
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2012 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file buffermem.v when simulating
// the core, buffermem. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module buffermem(
clka,
ena,
wea,
addra,
dina,
douta,
clkb,
enb,
web,
addrb,
dinb,
doutb
);
input clka;
input ena;
input [0 : 0] wea;
input [11 : 0] addra;
input [7 : 0] dina;
output [7 : 0] douta;
input clkb;
input enb;
input [0 : 0] web;
input [9 : 0] addrb;
input [31 : 0] dinb;
output [31 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V6_2 #(
.C_ADDRA_WIDTH(12),
.C_ADDRB_WIDTH(10),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("spartan6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(1),
.C_HAS_ENB(1),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(2),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(4096),
.C_READ_DEPTH_B(1024),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(32),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(4096),
.C_WRITE_DEPTH_B(1024),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(32),
.C_XDEVICEFAMILY("spartan6")
)
inst (
.CLKA(clka),
.ENA(ena),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.CLKB(clkb),
.ENB(enb),
.WEB(web),
.ADDRB(addrb),
.DINB(dinb),
.DOUTB(doutb),
.RSTA(),
.REGCEA(),
.RSTB(),
.REGCEB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem.veo 0 → 100644
View file @ 23405448
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2012 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
/*******************************************************************************
* Generated from core with identifier: xilinx.com:ip:blk_mem_gen:6.2 *
* *
* The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port *
* Block Memory and Single Port Block Memory LogiCOREs, but is not a *
* direct drop-in replacement. It should be used in all new Xilinx *
* designs. The core supports RAM and ROM functions over a wide range of *
* widths and depths. Use this core to generate block memories with *
* symmetric or asymmetric read and write port widths, as well as cores *
* which can perform simultaneous write operations to separate *
* locations, and simultaneous read operations from the same location. *
* For more information on differences in interface and feature support *
* between this core and the Dual Port Block Memory and Single Port *
* Block Memory LogiCOREs, please consult the data sheet. *
*******************************************************************************/
// Interfaces:
// AXI_SLAVE_S_AXI
// AXILite_SLAVE_S_AXI
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
buffermem your_instance_name (
.clka(clka), // input clka
.ena(ena), // input ena
.wea(wea), // input [0 : 0] wea
.addra(addra), // input [11 : 0] addra
.dina(dina), // input [7 : 0] dina
.douta(douta), // output [7 : 0] douta
.clkb(clkb), // input clkb
.enb(enb), // input enb
.web(web), // input [0 : 0] web
.addrb(addrb), // input [9 : 0] addrb
.dinb(dinb), // input [31 : 0] dinb
.doutb(doutb) // output [31 : 0] doutb
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file buffermem.v when simulating
// the core, buffermem. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem.xco 0 → 100644
View file @ 23405448
##############################################################
#
# Xilinx Core Generator version 13.2
# Date: Tue Feb 28 17:05:52 2012
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:blk_mem_gen:6.2
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc6slx45
SET devicefamily = spartan6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = csg324
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.2
# END Select
# BEGIN Parameters
CSET additional_inputs_for_power_estimation=false
CSET algorithm=Minimum_Area
CSET assume_synchronous_clk=true
CSET axi_id_width=4
CSET axi_slave_type=Memory_Slave
CSET axi_type=AXI4_Full
CSET byte_size=9
CSET coe_file=no_coe_file_loaded
CSET collision_warnings=ALL
CSET component_name=buffermem
CSET disable_collision_warnings=false
CSET disable_out_of_range_warnings=false
CSET ecc=false
CSET ecctype=No_ECC
CSET enable_a=Use_ENA_Pin
CSET enable_b=Use_ENB_Pin
CSET error_injection_type=Single_Bit_Error_Injection
CSET fill_remaining_memory_locations=false
CSET interface_type=Native
CSET load_init_file=false
CSET memory_type=True_Dual_Port_RAM
CSET operating_mode_a=WRITE_FIRST
CSET operating_mode_b=WRITE_FIRST
CSET output_reset_value_a=0
CSET output_reset_value_b=0
CSET pipeline_stages=0
CSET port_a_clock=100
CSET port_a_enable_rate=100
CSET port_a_write_rate=50
CSET port_b_clock=100
CSET port_b_enable_rate=100
CSET port_b_write_rate=50
CSET primitive=8kx2
CSET read_width_a=8
CSET read_width_b=32
CSET register_porta_input_of_softecc=false
CSET register_porta_output_of_memory_core=false
CSET register_porta_output_of_memory_primitives=false
CSET register_portb_output_of_memory_core=false
CSET register_portb_output_of_memory_primitives=false
CSET register_portb_output_of_softecc=false
CSET remaining_memory_locations=0
CSET reset_memory_latch_a=false
CSET reset_memory_latch_b=false
CSET reset_priority_a=CE
CSET reset_priority_b=CE
CSET reset_type=SYNC
CSET softecc=false
CSET use_axi_id=false
CSET use_byte_write_enable=false
CSET use_error_injection_pins=false
CSET use_regcea_pin=false
CSET use_regceb_pin=false
CSET use_rsta_pin=false
CSET use_rstb_pin=false
CSET write_depth_a=4096
CSET write_width_a=8
CSET write_width_b=32
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2011-03-11T08:24:14.000Z
# END Extra information
GENERATE
# CRC: 1fb28621
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem.xise 0 → 100644
View file @ 23405448
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="13.2" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="buffermem.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="buffermem.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="5"/>
</file>
</files>
<properties>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx45" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|buffermem" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="buffermem.ngc" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/buffermem" xil_pn:valueState="non-default"/>
<property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="non-default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_DesignName" xil_pn:value="buffermem" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-02-28T12:06:44" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="154A8C82339948B49E3C581C44A6E851" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem_flist.txt 0 → 100644
View file @ 23405448
# Output products list for <buffermem>
blk_mem_gen_ds512.pdf
blk_mem_gen_v6_2_readme.txt
buffermem.asy
buffermem.gise
buffermem.ngc
buffermem.sym
buffermem.v
buffermem.veo
buffermem.xco
buffermem.xise
buffermem_flist.txt
buffermem_ste\example_design\bmg_wrapper.vhd
buffermem_ste\example_design\buffermem_top.ucf
buffermem_ste\example_design\buffermem_top.vhd
buffermem_ste\example_design\buffermem_top.xdc
buffermem_ste\implement\implement.sh
buffermem_ste\implement\planAhead_rdn.bat
buffermem_ste\implement\planAhead_rdn.sh
buffermem_ste\implement\planAhead_rdn.tcl
buffermem_ste\implement\xst.prj
buffermem_ste\implement\xst.scr
buffermem_xmdf.tcl
summary.log
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem_ste/example_design/bmg_wrapper.vhd 0 → 100644
View file @ 23405448
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v6.2 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: bmg_wrapper.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 2
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 0
-- C_INIT_FILE_NAME : no_coe_file_loaded
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 1
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 8
-- C_READ_WIDTH_A : 8
-- C_WRITE_DEPTH_A : 4096
-- C_READ_DEPTH_A : 4096
-- C_ADDRA_WIDTH : 12
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 1
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 32
-- C_READ_WIDTH_B : 32
-- C_WRITE_DEPTH_B : 1024
-- C_READ_DEPTH_B : 1024
-- C_ADDRB_WIDTH : 10
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 1
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY bmg_wrapper IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END bmg_wrapper;
ARCHITECTURE xilinx OF bmg_wrapper IS
COMPONENT buffermem_top IS
PORT (
--Port A
ENA : IN STD_LOGIC; --opt port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
ENB : IN STD_LOGIC; --opt port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : buffermem_top
PORT MAP (
--Port A
ENA => ENA,
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA,
--Port B
ENB => ENB,
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
CLKB => CLKB
);
END xilinx;
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem_ste/example_design/buffermem_top.ucf 0 → 100644
View file @ 23405448
################################################################################
#
# (c) Copyright 2002 - 2010 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
################################################################################
# Tx Core Period Constraint. This constraint can be modified, and is
# valid as long as it is met after place and route.
NET "CLKA" TNM_NET = "CLKA";
NET "CLKB" TNM_NET = "CLKB";
TIMESPEC "TS_CLKA" = PERIOD "CLKA" 25 MHZ;
TIMESPEC "TS_CLKB" = PERIOD "CLKB" 25 MHZ;
################################################################################
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem_ste/example_design/buffermem_top.vhd 0 → 100644
View file @ 23405448
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v6.2 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_wrapper.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY buffermem_top IS
PORT (
--Inputs - Port A
ENA : IN STD_LOGIC; --opt port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
ENB : IN STD_LOGIC; --opt port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END buffermem_top;
ARCHITECTURE xilinx OF buffermem_top IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT buffermem IS
PORT (
--Port A
ENA : IN STD_LOGIC; --opt port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
ENB : IN STD_LOGIC; --opt port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bufg_B : BUFG
PORT MAP (
I => CLKB,
O => CLKB_buf
);
bmg0 : buffermem
PORT MAP (
--Port A
ENA => ENA,
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf,
--Port B
ENB => ENB,
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
CLKB => CLKB_buf
);
END xilinx;
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem_ste/example_design/buffermem_top.xdc 0 → 100644
View file @ 23405448
################################################################################
#
# (c) Copyright 2002 - 2011 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
################################################################################
# Core Period Constraint. This constraint can be modified, and is
# valid as long as it is met after place and route.
create_clock -name "TS_CLKA" -period 20.0 [ get_ports CLKA ]
create_clock -name "TS_CLKB" -period 20.0 [ get_ports CLKB ]
################################################################################
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem_ste/implement/implement.sh 0 → 100644
View file @ 23405448
#!/bin/sh
# Clean up the results directory
rm -rf results
mkdir results
#Synthesize the Wrapper Files
echo 'Synthesizing XST wrapper file (core_top.vhd) with XST';
echo 'Synthesizing example design with XST';
xst -ifn xst.scr
cp buffermem_top.ngc ./results/
# Copy the netlist generated by Coregen
echo 'Copying files from the netlist directory to the results directory'
cp ../../buffermem.ngc results/
# Copy the constraints files generated by Coregen
echo 'Copying files from constraints directory to results directory'
cp ../example_design/buffermem_top.ucf results/
cd results
echo 'Running ngdbuild'
ngdbuild -p xc6slx45-csg324-2 buffermem_top
echo 'Running map'
map buffermem_top -o mapped.ncd -pr i
echo 'Running par'
par mapped.ncd routed.ncd
echo 'Running trce'
trce -e 10 routed.ncd mapped.pcf -o routed
echo 'Running design through bitgen'
bitgen -w routed
echo 'Running netgen to create gate level Verilog model'
netgen -ofmt verilog -sim -tm buffermem_top -pcf mapped.pcf -w routed.ncd routed.v
cp routed.sdf ../../production/timing/
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem_ste/implement/planAhead_rdn.bat 0 → 100644
View file @ 23405448
#!/bin/sh
rem (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
rem
rem This file contains confidential and proprietary information
rem of Xilinx, Inc. and is protected under U.S. and
rem international copyright and other intellectual property
rem laws.
rem
rem DISCLAIMER
rem This disclaimer is not a license and does not grant any
rem rights to the materials distributed herewith. Except as
rem otherwise provided in a valid license issued to you by
rem Xilinx, and to the maximum extent permitted by applicable
rem law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
rem WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
rem AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
rem BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
rem INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
rem (2) Xilinx shall not be liable (whether in contract or tort,
rem including negligence, or under any other theory of
rem liability) for any loss or damage of any kind or nature
rem related to, arising under or in connection with these
rem materials, including for any direct, or any indirect,
rem special, incidental, or consequential loss or damage
rem (including loss of data, profits, goodwill, or any type of
rem loss or damage suffered as a result of any action brought
rem by a third party) even if such damage or loss was
rem reasonably foreseeable or Xilinx had been advised of the
rem possibility of the same.
rem
rem CRITICAL APPLICATIONS
rem Xilinx products are not designed or intended to be fail-
rem safe, or for use in any application requiring fail-safe
rem performance, such as life-support or safety devices or
rem systems, Class III medical devices, nuclear facilities,
rem applications related to the deployment of airbags, or any
rem other applications that could lead to death, personal
rem injury, or severe property or environmental damage
rem (individually and collectively, "Critical
rem Applications"). Customer assumes the sole risk and
rem liability of any use of Xilinx products in Critical
rem Applications, subject only to applicable laws and
rem regulations governing limitations on product liability.
rem
rem THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
rem PART OF THIS FILE AT ALL TIMES.
rem -----------------------------------------------------------------------------
rem Script to synthesize and implement the Coregen FIFO Generator
rem -----------------------------------------------------------------------------
rmdir /S /Q results
mkdir results
cd results
copy ..\..\..\tmp\buffermem.edf .
planAhead -mode batch -source ..\planAhead_rdn.tcl
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem_ste/implement/planAhead_rdn.sh 0 → 100644
View file @ 23405448
#!/bin/sh
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#-----------------------------------------------------------------------------
# Script to synthesize and implement the Coregen FIFO Generator
#-----------------------------------------------------------------------------
rm -rf results
mkdir results
cd results
cp ../../../tmp/buffermem.edf .
planAhead -mode batch -source ../planAhead_rdn.tcl
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem_ste/implement/planAhead_rdn.tcl 0 → 100644
View file @ 23405448
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
set device xc6slx45csg324-2
set projName buffermem
set design buffermem
set projDir [file dirname [info script]]
create_project $projName $projDir/results/$projName -part $device -force
set_property design_mode RTL [current_fileset -srcset]
set top_module buffermem_top
add_files -norecurse {../../example_design/buffermem_top.vhd}
add_files -norecurse {./buffermem.edf}
import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/buffermem_top.xdc}
set_property top buffermem_top [get_property srcset [current_run]]
synth_design
opt_design
place_design
route_design
write_sdf -rename_top_module buffermem_top -file routed.sdf
write_verilog -nolib -mode sim -sdf_anno false -rename_top_module buffermem_top routed.v
report_timing -nworst 30 -path_type full -file routed.twr
report_drc -file routed.drc
#write_bitstream
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem_ste/implement/xst.scr 0 → 100644
View file @ 23405448
run
-ifmt VHDL
-ent buffermem_top
-p xc6slx45-csg324-2
-ifn xst.prj
-write_timing_constraints No
-iobuf YES
-max_fanout 100
-ofn buffermem_top
-ofmt NGC
-bus_delimiter ()
-hierarchy_separator /
-case Maintain
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem_xmdf.tcl 0 → 100644
View file @ 23405448
# The package naming convention is <core_name>_xmdf
package provide buffermem_xmdf 1.0
# This includes some utilities that support common XMDF operations
package require utilities_xmdf
# Define a namespace for this package. The name of the name space
# is <core_name>_xmdf
namespace eval ::buffermem_xmdf {
# Use this to define any statics
}
# Function called by client to rebuild the params and port arrays
# Optional when the use context does not require the param or ports
# arrays to be available.
proc ::buffermem_xmdf::xmdfInit { instance } {
# Variable containing name of library into which module is compiled
# Recommendation: <module_name>
# Required
utilities_xmdf::xmdfSetData $instance Module Attributes Name buffermem
}
# ::buffermem_xmdf::xmdfInit
# Function called by client to fill in all the xmdf* data variables
# based on the current settings of the parameters
proc ::buffermem_xmdf::xmdfApplyParams { instance } {
set fcount 0
# Array containing libraries that are assumed to exist
# Examples include unisim and xilinxcorelib
# Optional
# In this example, we assume that the unisim library will
# be available to the simulation and synthesis tool
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_ds512.pdf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v6_2_readme.txt
utilities_xmdf::xmdfSetData $instance FileSet $fcount type text
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path buffermem.asy
utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path buffermem.ngc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path buffermem.sym
utilities_xmdf::xmdfSetData $instance FileSet $fcount type symbol
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path buffermem.v
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path buffermem.veo
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path buffermem.xco
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path buffermem_ste/example_design/bmg_wrapper.vhd
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path buffermem_ste/example_design/buffermem_top.ucf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path buffermem_ste/example_design/buffermem_top.vhd
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path buffermem_ste/example_design/buffermem_top.xdc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path buffermem_ste/implement/implement.sh
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path buffermem_ste/implement/planAhead_rdn.bat
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path buffermem_ste/implement/planAhead_rdn.sh
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path buffermem_ste/implement/planAhead_rdn.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path buffermem_ste/implement/xst.prj
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path buffermem_ste/implement/xst.scr
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path buffermem_xmdf.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path summary.log
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module buffermem
incr fcount
}
# ::gen_comp_name_xmdf::xmdfApplyParams
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/coregen.cgp 0 → 100644
View file @ 23405448
SET busformat = BusFormatAngleBracketNotRipped
SET designentry = Verilog
SET device = xc6slx45
SET devicefamily = spartan6
SET flowvendor = Other
SET package = csg324
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = false
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/create_buffermem.tcl 0 → 100644
View file @ 23405448
##
## Core Generator Run Script, generator for Project Navigator create command
##
proc findRtfPath { relativePath } {
set xilenv ""
if { [info exists ::env(XILINX) ] } {
if { [info exists ::env(MYXILINX)] } {
set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]
} else {
set xilenv $::env(XILINX)
}
}
foreach path [ split $xilenv $::xilinx::path_sep ] {
set fullPath [ file join $path $relativePath ]
if { [ file exists $fullPath ] } {
return $fullPath
}
}
return ""
}
source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
set result [ run_cg_create "xilinx.com:ip:blk_mem_gen:6.2" "buffermem" "Block Memory Generator" "Block Memory Generator (xilinx.com:ip:blk_mem_gen:6.2) generated by Project Navigator" xc6slx45-2csg324 Verilog ]
if { $result == 0 } {
puts "Core Generator create command completed successfully."
} elseif { $result == 1 } {
puts "Core Generator create command failed."
} elseif { $result == 3 || $result == 4 } {
# convert 'version check' result to real return range, bypassing any messages.
set result [ expr $result - 3 ]
} else {
puts "Core Generator create cancelled."
}
exit $result
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_xmsgs/ngcbuild.xmsgs 0 → 100644
View file @ 23405448
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
</messages>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_xmsgs/pn_parser.xmsgs 0 → 100644
View file @ 23405448
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated -->
<!-- by the Xilinx ISE software. Any direct editing or -->
<!-- changes made to this file may result in unpredictable -->
<!-- behavior or data corruption. It is strongly advised that -->
<!-- users do not edit the contents of this file. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
<messages>
<msg type="info" file="ProjectMgmt" num="1769" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_cg/buffermem.v\&quot; into library work</arg>
</msg>
</messages>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_xmsgs/xst.xmsgs 0 → 100644
View file @ 23405448
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="UtilitiesC" num="159" delta="new" >Message file &quot;<arg fmt="%s" index="1">usenglish/ip.msg</arg>&quot; wasn&apos;t found.
</msg>
<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">0</arg>: (<arg fmt="%d" index="2">0</arg>,<arg fmt="%d" index="3">0</arg>) : <arg fmt="%d" index="4">4</arg>x<arg fmt="%d" index="5">4096</arg> u:<arg fmt="%d" index="6">4</arg>
</msg>
<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">1</arg>: (<arg fmt="%d" index="2">4</arg>,<arg fmt="%d" index="3">0</arg>) : <arg fmt="%d" index="4">4</arg>x<arg fmt="%d" index="5">4096</arg> u:<arg fmt="%d" index="6">4</arg>
</msg>
<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">0</arg>: (<arg fmt="%d" index="2">0</arg>,<arg fmt="%d" index="3">0</arg>) : <arg fmt="%d" index="4">4</arg>x<arg fmt="%d" index="5">4096</arg> u:<arg fmt="%d" index="6">4</arg>
</msg>
<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">1</arg>: (<arg fmt="%d" index="2">4</arg>,<arg fmt="%d" index="3">0</arg>) : <arg fmt="%d" index="4">4</arg>x<arg fmt="%d" index="5">4096</arg> u:<arg fmt="%d" index="6">4</arg>
</msg>
<msg type="warning" file="HDLCompiler" num="321" delta="new" >"C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v6_2\blk_mem_input_block.vhd" Line 691: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
</msg>
<msg type="warning" file="HDLCompiler" num="321" delta="new" >"C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v6_2\blk_mem_input_block.vhd" Line 707: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
</msg>
<msg type="warning" file="HDLCompiler" num="746" delta="new" >"C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v6_2\blk_mem_gen_prim_width.vhd" Line 977: Range is empty (null range)
</msg>
<msg type="warning" file="HDLCompiler" num="220" delta="new" >"C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v6_2\blk_mem_gen_prim_width.vhd" Line 977: Assignment ignored
</msg>
<msg type="warning" file="HDLCompiler" num="746" delta="new" >"C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v6_2\blk_mem_gen_prim_width.vhd" Line 978: Range is empty (null range)
</msg>
<msg type="warning" file="HDLCompiler" num="220" delta="new" >"C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v6_2\blk_mem_gen_prim_width.vhd" Line 978: Assignment ignored
</msg>
<msg type="warning" file="HDLCompiler" num="634" delta="new" >"C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v6_2\blk_mem_gen_prim_width.vhd" Line 433: Net &lt;<arg fmt="%s" index="1">dinb_pad[17]</arg>&gt; does not have a driver.
</msg>
<msg type="warning" file="HDLCompiler" num="321" delta="new" >"C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v6_2\blk_mem_gen_generic_cstr.vhd" Line 1544: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
</msg>
<msg type="warning" file="HDLCompiler" num="321" delta="new" >"C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v6_2\blk_mem_gen_generic_cstr.vhd" Line 1557: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">c:/users/mjlyons/workspace/vspi/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_cg/_dbg/buffermem.vhd</arg>&quot; line <arg fmt="%s" index="2">166</arg>: Output port &lt;<arg fmt="%s" index="3">rdaddrecc</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">c:/users/mjlyons/workspace/vspi/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_cg/_dbg/buffermem.vhd</arg>&quot; line <arg fmt="%s" index="2">166</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_bid</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">c:/users/mjlyons/workspace/vspi/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_cg/_dbg/buffermem.vhd</arg>&quot; line <arg fmt="%s" index="2">166</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_bresp</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">c:/users/mjlyons/workspace/vspi/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_cg/_dbg/buffermem.vhd</arg>&quot; line <arg fmt="%s" index="2">166</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_rid</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">c:/users/mjlyons/workspace/vspi/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_cg/_dbg/buffermem.vhd</arg>&quot; line <arg fmt="%s" index="2">166</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_rdata</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">c:/users/mjlyons/workspace/vspi/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_cg/_dbg/buffermem.vhd</arg>&quot; line <arg fmt="%s" index="2">166</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_rresp</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">c:/users/mjlyons/workspace/vspi/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_cg/_dbg/buffermem.vhd</arg>&quot; line <arg fmt="%s" index="2">166</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_rdaddrecc</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">c:/users/mjlyons/workspace/vspi/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_cg/_dbg/buffermem.vhd</arg>&quot; line <arg fmt="%s" index="2">166</arg>: Output port &lt;<arg fmt="%s" index="3">sbiterr</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">c:/users/mjlyons/workspace/vspi/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_cg/_dbg/buffermem.vhd</arg>&quot; line <arg fmt="%s" index="2">166</arg>: Output port &lt;<arg fmt="%s" index="3">dbiterr</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">c:/users/mjlyons/workspace/vspi/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_cg/_dbg/buffermem.vhd</arg>&quot; line <arg fmt="%s" index="2">166</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_awready</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">c:/users/mjlyons/workspace/vspi/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_cg/_dbg/buffermem.vhd</arg>&quot; line <arg fmt="%s" index="2">166</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_wready</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">c:/users/mjlyons/workspace/vspi/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_cg/_dbg/buffermem.vhd</arg>&quot; line <arg fmt="%s" index="2">166</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_bvalid</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">c:/users/mjlyons/workspace/vspi/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_cg/_dbg/buffermem.vhd</arg>&quot; line <arg fmt="%s" index="2">166</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_arready</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">c:/users/mjlyons/workspace/vspi/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_cg/_dbg/buffermem.vhd</arg>&quot; line <arg fmt="%s" index="2">166</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_rlast</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">c:/users/mjlyons/workspace/vspi/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_cg/_dbg/buffermem.vhd</arg>&quot; line <arg fmt="%s" index="2">166</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_rvalid</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">c:/users/mjlyons/workspace/vspi/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_cg/_dbg/buffermem.vhd</arg>&quot; line <arg fmt="%s" index="2">166</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_sbiterr</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">c:/users/mjlyons/workspace/vspi/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_cg/_dbg/buffermem.vhd</arg>&quot; line <arg fmt="%s" index="2">166</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_dbiterr</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">S_AXI_AWID&lt;3:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">S_AXI_AWADDR&lt;31:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">S_AXI_AWLEN&lt;7:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">S_AXI_AWSIZE&lt;2:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">S_AXI_AWBURST&lt;1:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">S_AXI_WDATA&lt;7:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">S_AXI_WSTRB&lt;0:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">S_AXI_ARID&lt;3:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">S_AXI_ARADDR&lt;31:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">S_AXI_ARLEN&lt;7:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">S_AXI_ARSIZE&lt;2:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">S_AXI_ARBURST&lt;1:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">S_AClk</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">S_ARESETN</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">S_AXI_AWVALID</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">S_AXI_WLAST</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">S_AXI_WVALID</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">S_AXI_BREADY</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">S_AXI_ARVALID</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">S_AXI_RREADY</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">S_AXI_INJECTSBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">S_AXI_INJECTDBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="2935" delta="new" >Signal &apos;<arg fmt="%s" index="1">S_AXI_BID</arg>&apos;, unconnected in block &apos;<arg fmt="%s" index="2">blk_mem_gen_v6_2_xst</arg>&apos;, is tied to its initial value (<arg fmt="%s" index="3">0000</arg>).
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">S_AXI_BRESP</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="2935" delta="new" >Signal &apos;<arg fmt="%s" index="1">S_AXI_RID</arg>&apos;, unconnected in block &apos;<arg fmt="%s" index="2">blk_mem_gen_v6_2_xst</arg>&apos;, is tied to its initial value (<arg fmt="%s" index="3">0000</arg>).
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">S_AXI_RDATA</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">S_AXI_RRESP</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">S_AXI_RDADDRECC</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">S_AXI_AWREADY</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">S_AXI_WREADY</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">S_AXI_BVALID</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">S_AXI_ARREADY</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">S_AXI_RLAST</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">S_AXI_RVALID</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">S_AXI_SBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">S_AXI_DBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">RSTA</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">REGCEA</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">RSTB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">REGCEB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">INJECTDBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">INJECTSBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">INJECTDBITERR_I</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">INJECTSBITERR_I</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">REGCEA&lt;0:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">REGCEB&lt;0:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">WEB&lt;3:1&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">INJECTSBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">INJECTDBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">c:/users/mjlyons/workspace/vspi/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1341</arg>: Output port &lt;<arg fmt="%s" index="3">SBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[0].ram.r</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">c:/users/mjlyons/workspace/vspi/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1341</arg>: Output port &lt;<arg fmt="%s" index="3">DBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[0].ram.r</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">c:/users/mjlyons/workspace/vspi/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1341</arg>: Output port &lt;<arg fmt="%s" index="3">SBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[1].ram.r</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">c:/users/mjlyons/workspace/vspi/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1341</arg>: Output port &lt;<arg fmt="%s" index="3">DBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[1].ram.r</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">RDADDRECC</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">SBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">DBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">INJECTSBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">INJECTDBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="2935" delta="new" >Signal &apos;<arg fmt="%s" index="1">dinb_pad&lt;17&gt;</arg>&apos;, unconnected in block &apos;<arg fmt="%s" index="2">blk_mem_gen_prim_width_1</arg>&apos;, is tied to its initial value (<arg fmt="%s" index="3">0</arg>).
</msg>
<msg type="warning" file="Xst" num="2935" delta="new" >Signal &apos;<arg fmt="%s" index="1">dinb_pad&lt;8&gt;</arg>&apos;, unconnected in block &apos;<arg fmt="%s" index="2">blk_mem_gen_prim_width_1</arg>&apos;, is tied to its initial value (<arg fmt="%s" index="3">0</arg>).
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">SBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">DBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">INJECTSBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">INJECTDBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="2935" delta="new" >Signal &apos;<arg fmt="%s" index="1">dinb_pad&lt;17&gt;</arg>&apos;, unconnected in block &apos;<arg fmt="%s" index="2">blk_mem_gen_prim_width_2</arg>&apos;, is tied to its initial value (<arg fmt="%s" index="3">0</arg>).
</msg>
<msg type="warning" file="Xst" num="2935" delta="new" >Signal &apos;<arg fmt="%s" index="1">dinb_pad&lt;8&gt;</arg>&apos;, unconnected in block &apos;<arg fmt="%s" index="2">blk_mem_gen_prim_width_2</arg>&apos;, is tied to its initial value (<arg fmt="%s" index="3">0</arg>).
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">SBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">DBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">RDADDRECC_I&lt;9:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">CLKB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">SBITERR_I</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">DBITERR_I</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">RDADDRECC</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">SBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="new" >Signal &lt;<arg fmt="%s" index="1">DBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="info" file="Xst" num="2169" delta="new" >HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
</msg>
</messages>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/iseconfig/spiifc.projectmgr 0 → 100644
View file @ 23405448
<?xml version='1.0' encoding='utf-8'?>
<!--This is an ISE project configuration file.-->
<!--It holds project specific layout data for the projectmgr plugin.-->
<!--Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.-->
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<!--This is an ISE project configuration file.-->
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<ClosedNode>/spiifc - IMP C:|Users|mjlyons|workspace|vSPI|projnav|xps|pcores|spiifc_v1_00_a|hdl|vhdl|spiifc.vhd/PLBV46_SLAVE_BURST_I - plbv46_slave_burst - implementation/I_SLAVE_ATTACHMENT - plb_slave_attachment - implementation</ClosedNode>
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projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/iseconfig/spiifc.xreport 0 → 100644
View file @ 23405448
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2012-02-28T19:36:06</DateModified>
<ModuleName>spiifc</ModuleName>
<SummaryTimeStamp>2012-02-28T16:04:44</SummaryTimeStamp>
<SavedFilePath>C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/iseconfig/spiifc.xreport</SavedFilePath>
<ImplementationReportsDirectory>C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav\</ImplementationReportsDirectory>
<DateInitialized>2012-02-28T19:36:05</DateInitialized>
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<body>
<viewgroup label="Design Overview" >
<view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="spiifc_summary.html" label="Summary" >
<toc-item title="Design Overview" target="Design Overview" />
<toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
<toc-item title="Performance Summary" target="Performance Summary" />
<toc-item title="Failing Constraints" target="Failing Constraints" />
<toc-item title="Detailed Reports" target="Detailed Reports" />
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<view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="spiifc_envsettings.html" label="System Settings" />
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<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="spiifc_map.xrpt" label="Control Set Information" />
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<view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="spiifc.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
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<view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="spiifc.twx" label="Static Timing" />
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="spiifc_html/fit/report.htm" label="CPLD Fitter Report" />
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="spiifc_html/tim/report.htm" label="CPLD Timing Report" />
</viewgroup>
<viewgroup label="XPS Errors and Warnings" >
<view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" />
<view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" />
<view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" />
</viewgroup>
<viewgroup label="XPS Reports" >
<view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" />
<view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
<view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
<view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="spiifc.log" label="System Log File" />
</viewgroup>
<viewgroup label="Errors and Warnings" >
<view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
<view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" />
<view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" />
<view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" />
<view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" />
<view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" />
<view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" />
<view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" />
<view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" />
<view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages" />
<view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" />
</viewgroup>
<viewgroup label="Detailed Reports" >
<view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="spiifc.syr" label="Synthesis Report" >
<toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
<toc-item title="Synthesis Options Summary" target=" Synthesis Options Summary " />
<toc-item title="HDL Compilation" target=" HDL Compilation " />
<toc-item title="Design Hierarchy Analysis" target=" Design Hierarchy Analysis " />
<toc-item title="HDL Analysis" target=" HDL Analysis " />
<toc-item title="HDL Parsing" target=" HDL Parsing " />
<toc-item title="HDL Elaboration" target=" HDL Elaboration " />
<toc-item title="HDL Synthesis" target=" HDL Synthesis " />
<toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" />
<toc-item title="Advanced HDL Synthesis" target=" Advanced HDL Synthesis " searchDir="Backward" />
<toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" />
<toc-item title="Low Level Synthesis" target=" Low Level Synthesis " />
<toc-item title="Partition Report" target=" Partition Report " />
<toc-item title="Final Report" target=" Final Report " />
<toc-item title="Design Summary" target=" Design Summary " />
<toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" />
<toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" />
<toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" />
<toc-item title="Timing Report" target="Timing Report" subItemLevel="1" />
<toc-item title="Clock Information" target="Clock Information" subItemLevel="2" />
<toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" />
<toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" />
<toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
<toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
</view>
<view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="spiifc.srr" label="Synplify Report" />
<view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="spiifc.prec_log" label="Precision Report" />
<view inputState="Synthesized" program="ngdbuild" type="Report" file="spiifc.bld" label="Translation Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Command Line" target="Command Line:" />
<toc-item title="Partition Status" target="Partition Implementation Status" />
<toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
</view>
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="spiifc_map.mrp" label="Map Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
<toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
<toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
<toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" />
<toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" />
<toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" />
<toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" />
<toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" />
<toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" />
<toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" />
<toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" />
<toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" />
<toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
<toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="spiifc.par" label="Place and Route Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Device Utilization" target="Device Utilization Summary:" />
<toc-item title="Router Information" target="Starting Router" />
<toc-item title="Partition Status" target="Partition Implementation Status" />
<toc-item title="Clock Report" target="Generating Clock Report" />
<toc-item title="Timing Results" target="Timing Score:" />
<toc-item title="Final Summary" target="Peak Memory Usage:" />
</view>
<view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="spiifc.twr" label="Post-PAR Static Timing Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Timing Report Description" target="Device,package,speed:" />
<toc-item title="Informational Messages" target="INFO:" />
<toc-item title="Warning Messages" target="WARNING:" />
<toc-item title="Timing Constraints" target="Timing constraint:" />
<toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
<toc-item title="Data Sheet Report" target="Data Sheet report:" />
<toc-item title="Timing Summary" target="Timing summary:" />
<toc-item title="Trace Settings" target="Trace Settings:" />
</view>
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="spiifc.rpt" label="CPLD Fitter Report (Text)" >
<toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
<toc-item title="Resources Summary" target="** Mapped Resource Summary **" />
<toc-item title="Pin Resources" target="** Pin Resources **" />
<toc-item title="Global Resources" target="** Global Control Resources **" />
</view>
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="spiifc.tim" label="CPLD Timing Report (Text)" >
<toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
<toc-item title="Performance Summary" target="Performance Summary:" />
</view>
<view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="spiifc.pwr" label="Power Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Power summary" target="Power summary" />
<toc-item title="Thermal summary" target="Thermal summary" />
</view>
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="spiifc.bgn" label="Bitgen Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
<toc-item title="Final Summary" target="DRC detected" />
</view>
</viewgroup>
<viewgroup label="Secondary Reports" >
<view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
<view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/spiifc_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/spiifc_translate.nlf" label="Post-Translate Simulation Model Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="spiifc_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="spiifc_map.map" label="Map Log File" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
<toc-item title="Design Information" target="Design Information" />
<toc-item title="Design Summary" target="Design Summary" />
</view>
<view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
<view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spiifc_preroute.twr" label="Post-Map Static Timing Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Timing Report Description" target="Device,package,speed:" />
<toc-item title="Informational Messages" target="INFO:" />
<toc-item title="Warning Messages" target="WARNING:" />
<toc-item title="Timing Constraints" target="Timing constraint:" />
<toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
<toc-item title="Data Sheet Report" target="Data Sheet report:" />
<toc-item title="Timing Summary" target="Timing summary:" />
<toc-item title="Trace Settings" target="Trace Settings:" />
</view>
<view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/spiifc_map.nlf" label="Post-Map Simulation Model Report" />
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spiifc_map.psr" label="Physical Synthesis Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="spiifc_pad.txt" label="Pad Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="spiifc.unroutes" label="Unroutes Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spiifc_preroute.tsi" label="Post-Map Constraints Interaction Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spiifc.grf" label="Guide Results Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spiifc.dly" label="Asynchronous Delay Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spiifc.clk_rgn" label="Clock Region Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spiifc.tsi" label="Post-Place and Route Constraints Interaction Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="spiifc_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
<view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/spiifc_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="spiifc_sta.nlf" label="Primetime Netlist Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="spiifc.ibs" label="IBIS Model" >
<toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
<toc-item title="Component" target="Component " />
</view>
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spiifc.lck" label="Back-annotate Pin Report" >
<toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
<toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
</view>
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spiifc.lpc" label="Locked Pin Constraints" >
<toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
<toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
</view>
<view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/spiifc_timesim.nlf" label="Post-Fit Simulation Model Report" />
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
</viewgroup>
</body>
</report-views>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc.xise
View file @ 23405448
......@@ -17,97 +17,104 @@
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
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<file xil_pn:name="../../hdl/verilog/user_logic.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
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<library xil_pn:name="proc_common_v3_00_a"/>
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<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ipif_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
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<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_muxcy.vhd" xil_pn:type="FILE_VHDL">
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<library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
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<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plb_slave_attachment.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
<library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
</file>
<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/data_mirror_128.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
<library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
</file>
<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plbv46_slave_burst.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
<library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
</file>
<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v2_01_a/hdl/vhdl/interrupt_control.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
<library xil_pn:name="interrupt_control_v2_01_a"/>
</file>
<file xil_pn:name="ipcore_dir/buffermem.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="ipcore_dir/buffermem.xise" xil_pn:type="FILE_COREGENISE">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
</files>
<properties>
......@@ -122,7 +129,7 @@
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -134,17 +141,12 @@
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/>
<property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Collapsing Input Limit (4-40)" xil_pn:value="32" xil_pn:valueState="default"/>
<property xil_pn:name="Collapsing Pterm Limit (3-56)" xil_pn:value="28" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile uni9000 (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
......@@ -153,14 +155,12 @@
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="Low" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx45" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
......@@ -188,7 +188,6 @@
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
......@@ -196,7 +195,6 @@
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Function Block Input Limit (4-40)" xil_pn:value="38" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
......@@ -211,8 +209,6 @@
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Fit Power Data" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Fit Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
......@@ -225,13 +221,10 @@
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="HDL Equations Style" xil_pn:value="Source" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="I/O Voltage Standard" xil_pn:value="LVCMOS18" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Template" xil_pn:value="Optimize Density" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|spiifc|IMP" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../../hdl/vhdl/spiifc.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/spiifc" xil_pn:valueState="non-default"/>
......@@ -240,7 +233,6 @@
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Input and tristate I/O Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
......@@ -248,15 +240,15 @@
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy CPLD" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Logic Optimization" xil_pn:value="Density" xil_pn:valueState="default"/>
<property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
......@@ -282,7 +274,6 @@
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
......@@ -293,18 +284,14 @@
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Programming Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Fit" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Timing Report Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="spiifc" xil_pn:valueState="default"/>
<property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
......@@ -325,7 +312,6 @@
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
......@@ -382,7 +368,6 @@
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
......@@ -392,17 +377,14 @@
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused I/O Pad Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -411,38 +393,28 @@
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Data Gate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Direct Input for Input Registers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
<property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
......
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc_summary.html 0 → 100644
View file @ 23405448
<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>spiifc Project Status</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>spiifc.xise</TD>
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
<TD>spiifc</TD>
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
<TD>New</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD>xc6slx45-2csg324</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 13.2</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
<TD>Balanced</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
<TD>
&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
<TD>&nbsp;</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
<TD>&nbsp;&nbsp;</TD>
</TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD>Synthesis Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
</TABLE>
<br><center><b>Date Generated:</b> 02/28/2012 - 19:36:06</center>
</BODY></HTML>
\ No newline at end of file
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/user_logic_summary.html 0 → 100644
View file @ 23405448
<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>spiifc Project Status</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>spiifc.xise</TD>
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
<TD>user_logic</TD>
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
<TD>New</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD>xc6slx45-2csg324</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 13.2</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
<TD>Balanced</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
<TD>
&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
<TD>&nbsp;</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
<TD>&nbsp;&nbsp;</TD>
</TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD>Synthesis Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
</TABLE>
<br><center><b>Date Generated:</b> 02/28/2012 - 19:35:55</center>
</BODY></HTML>
\ No newline at end of file
projnav/xps/pcores/spiifc_v1_00_a/hdl/verilog/buffermem.v 0 → 100644
View file @ 23405448
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2012 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file buffermem.v when simulating
// the core, buffermem. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module buffermem(
clka,
ena,
wea,
addra,
dina,
douta,
clkb,
enb,
web,
addrb,
dinb,
doutb
);
input clka;
input ena;
input [0 : 0] wea;
input [11 : 0] addra;
input [7 : 0] dina;
output [7 : 0] douta;
input clkb;
input enb;
input [0 : 0] web;
input [9 : 0] addrb;
input [31 : 0] dinb;
output [31 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V6_2 #(
.C_ADDRA_WIDTH(12),
.C_ADDRB_WIDTH(10),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("spartan6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(1),
.C_HAS_ENB(1),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(2),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(4096),
.C_READ_DEPTH_B(1024),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(32),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(4096),
.C_WRITE_DEPTH_B(1024),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(32),
.C_XDEVICEFAMILY("spartan6")
)
inst (
.CLKA(clka),
.ENA(ena),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.CLKB(clkb),
.ENB(enb),
.WEB(web),
.ADDRB(addrb),
.DINB(dinb),
.DOUTB(doutb),
.RSTA(),
.REGCEA(),
.RSTB(),
.REGCEB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
projnav/xps/pcores/spiifc_v1_00_a/hdl/verilog/user_logic.v
View file @ 23405448
......@@ -124,6 +124,24 @@ output [0 : C_NUM_INTR-1] IP2Bus_IntrEvent;
// --USER nets declarations added here, as needed for user logic
// Memmap memory logic lines
wire [0 : 1 ] mem_ena; // Port A: spiifc
wire [0 : 1 ] mem_enb; // Port B: sysbus/dma
wire mem_web;
reg [0 : 1 ] mem_read_prev;
// mosiMem (mem0): data received from master
wire [0 : 11] mosiMem_addra;
wire [0 : 7 ] mosiMem_dina;
wire [0 : 9 ] mosiMem_addrb;
wire [0 : 31] mosiMem_dinb;
wire [0 : 31] mosiMem_doutb;
// misoMem (mem1): data to send to master
wire [0 : 11] misoMem_addra;
wire [0 : 7 ] misoMem_douta;
wire [0 : 9 ] misoMem_addrb;
wire [0 : 31] misoMem_dinb;
wire [0 : 31] misoMem_doutb;
// Nets for user logic slave model s/w accessible register example
reg [0 : C_SLV_DWIDTH-1] slv_reg0;
reg [0 : C_SLV_DWIDTH-1] slv_reg1;
......@@ -150,6 +168,54 @@ output [0 : C_NUM_INTR-1] IP2Bus_IntrEvent;
// --USER logic implementation added here
// memory interface logic
assign mem_ena = 2'd0; // TODO: interface with spiifc
assign mem_enb = Bus2IP_CS & {C_NUM_MEM{Bus2IP_RdReq | Bus2IP_WrReq}};
assign mem_web = (~Bus2IP_RNW) & Bus2IP_WrReq;
assign mosiMem_addra = 12'h000; // TODO: interface with spiifc
assign mosiMem_dina = 8'd00; // TODO: interface with spiifc
assign mosiMem_addrb = Bus2IP_Addr[2:11];
assign mosiMem_dinb = Bus2IP_Data;
assign misoMem_addra = 12'h000; // TODO: interface with spiifc
assign misoMem_addrb = Bus2IP_Addr[2:11];
assign misoMem_dinb = Bus2IP_Data;
always @(posedge Bus2IP_Clk) begin
mem_read_prev <= mem_enb & {C_NUM_MEM{Bus2IP_RdReq & (~mem_web)}};
end
// Mem0: Memory buffer storing data coming from master
buffermem mosiMem (
.clka(Bus2IP_Clk), // input clka
.ena(mem_ena[0]), // input ena
.wea(1'b1), // Always writing, never reading
.addra({mosiMem_addra}), // input [11 : 0] addra
.dina({mosiMem_dina}), // input [7 : 0] dina
// NEVER USED: .douta(mosiMem_douta), // output [7 : 0] douta
.clkb(Bus2IP_Clk), // input clkb
.enb(mem_enb[0]), // input enb
.web(mem_web), // input [0 : 0] web
.addrb({mosiMem_addrb}), // input [9 : 0] addrb
.dinb({mosiMem_dinb}), // input [31 : 0] dinb
.doutb({mosiMem_doutb}) // output [31 : 0] doutb
);
// Mem1: Memory buffer storing data to send to master
buffermem misoMem (
.clka(Bus2IP_Clk), // input clka
.ena(mem_ena[1]), // input ena
.wea(1'b0), // Always reading, never writing
.addra({misoMem_addra}), // input [11 : 0] addra
// NEVER USED: .dina(dina), // input [7 : 0] dina
.douta({misoMem_douta}), // output [7 : 0] douta
.clkb(Bus2IP_Clk), // input clkb
.enb(mem_enb[1]), // input enb
.web(mem_web), // input [0 : 0] web
.addrb({misoMem_addrb}), // input [9 : 0] addrb
.dinb({misoMem_dinb}), // input [31 : 0] dinb
.doutb({misoMem_doutb}) // output [31 : 0] doutb
);
// ------------------------------------------------------
// Example code to read/write user logic slave model s/w accessible registers
//
......@@ -172,8 +238,8 @@ output [0 : C_NUM_INTR-1] IP2Bus_IntrEvent;
assign
slv_reg_write_sel = Bus2IP_WrCE[0:15],
slv_reg_read_sel = Bus2IP_RdCE[0:15],
slv_write_ack = Bus2IP_WrCE[0] || Bus2IP_WrCE[1] || Bus2IP_WrCE[2] || Bus2IP_WrCE[3] || Bus2IP_WrCE[4] || Bus2IP_WrCE[5] || Bus2IP_WrCE[6] || Bus2IP_WrCE[7] || Bus2IP_WrCE[8] || Bus2IP_WrCE[9] || Bus2IP_WrCE[10] || Bus2IP_WrCE[11] || Bus2IP_WrCE[12] || Bus2IP_WrCE[13] || Bus2IP_WrCE[14] || Bus2IP_WrCE[15],
slv_read_ack = Bus2IP_RdCE[0] || Bus2IP_RdCE[1] || Bus2IP_RdCE[2] || Bus2IP_RdCE[3] || Bus2IP_RdCE[4] || Bus2IP_RdCE[5] || Bus2IP_RdCE[6] || Bus2IP_RdCE[7] || Bus2IP_RdCE[8] || Bus2IP_RdCE[9] || Bus2IP_RdCE[10] || Bus2IP_RdCE[11] || Bus2IP_RdCE[12] || Bus2IP_RdCE[13] || Bus2IP_RdCE[14] || Bus2IP_RdCE[15];
slv_write_ack = ((|(mem_enb)) & mem_web) || Bus2IP_WrCE[0] || Bus2IP_WrCE[1] || Bus2IP_WrCE[2] || Bus2IP_WrCE[3] || Bus2IP_WrCE[4] || Bus2IP_WrCE[5] || Bus2IP_WrCE[6] || Bus2IP_WrCE[7] || Bus2IP_WrCE[8] || Bus2IP_WrCE[9] || Bus2IP_WrCE[10] || Bus2IP_WrCE[11] || Bus2IP_WrCE[12] || Bus2IP_WrCE[13] || Bus2IP_WrCE[14] || Bus2IP_WrCE[15],
slv_read_ack = mem_read_prev || Bus2IP_RdCE[0] || Bus2IP_RdCE[1] || Bus2IP_RdCE[2] || Bus2IP_RdCE[3] || Bus2IP_RdCE[4] || Bus2IP_RdCE[5] || Bus2IP_RdCE[6] || Bus2IP_RdCE[7] || Bus2IP_RdCE[8] || Bus2IP_RdCE[9] || Bus2IP_RdCE[10] || Bus2IP_RdCE[11] || Bus2IP_RdCE[12] || Bus2IP_RdCE[13] || Bus2IP_RdCE[14] || Bus2IP_RdCE[15];
// implement slave model register(s)
always @( posedge Bus2IP_Clk )
......@@ -316,7 +382,9 @@ output [0 : C_NUM_INTR-1] IP2Bus_IntrEvent;
// ------------------------------------------------------------
assign IP2Bus_AddrAck = slv_write_ack || slv_read_ack;
assign IP2Bus_Data = slv_ip2bus_data;
assign IP2Bus_Data = (mem_read_prev[0] ? mosiMem_doutb : (
mem_read_prev[1] ? misoMem_doutb :
slv_ip2bus_data));
assign IP2Bus_WrAck = slv_write_ack;
assign IP2Bus_RdAck = slv_read_ack;
assign IP2Bus_Error = 0;
......
projnav/xps/pcores/spiifc_v1_00_a/netlist/buffermem.ngc 0 → 100644
View file @ 23405448
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6e
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\ No newline at end of file
projnav/xps/pcores/spiifc_v1_00_a/netlist/spiifc.ngc 0 → 100644
View file @ 23405448
This source diff could not be displayed because it is too large. You can view the blob instead.
projnav/xps/platgen.opt 0 → 100644
View file @ 23405448
-p
xc6slx45csg324-2
-lang
vhdl
-msg
__xps/ise/xmsgprops.lst
system.mhs
projnav/xps/system.log deleted 100644 → 0
View file @ 7133e87e
Xilinx Platform Studio (XPS)
Xilinx EDK 13.2 Build EDK_O.61xd
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
********************************************************************************
At Local date and time: Tue Feb 28 11:00:26 2012
make -f system.make clean started...
rm -f implementation/system.ngc
rm -f platgen.log
rm -f __xps/ise/_xmsgs/platgen.xmsgs
rm -f implementation/system.bmm
rm -f implementation/system.bit
rm -f implementation/system.ncd
rm -f implementation/system_bd.bmm
rm -f implementation/system_map.ncd
rm -f implementation/download.bit
rm -f __xps/system_routed
rm -rf implementation synthesis xst hdl
rm -rf xst.srp system.srp
rm -f __xps/ise/_xmsgs/bitinit.xmsgs
rm -rf simulation/behavioral
rm -f simgen.log
rm -f __xps/ise/_xmsgs/simgen.xmsgs
rm -f _impact.cmd
Done!
********************************************************************************
At Local date and time: Tue Feb 28 11:00:42 2012
make -f system.make hwclean started...
rm -f implementation/system.ngc
rm -f platgen.log
rm -f __xps/ise/_xmsgs/platgen.xmsgs
rm -f implementation/system.bmm
rm -f implementation/system.bit
rm -f implementation/system.ncd
rm -f implementation/system_bd.bmm
rm -f implementation/system_map.ncd
rm -f implementation/download.bit
rm -f __xps/system_routed
rm -rf implementation synthesis xst hdl
rm -rf xst.srp system.srp
rm -f __xps/ise/_xmsgs/bitinit.xmsgs
Done!
Writing filter settings....
Done writing filter settings to:
C:\Users\mjlyons\workspace\vSPI\projnav\xps\etc\system.filters
Done writing Tab View settings to:
C:\Users\mjlyons\workspace\vSPI\projnav\xps\etc\system.gui
Xilinx Platform Studio (XPS)
Xilinx EDK 13.2 Build EDK_O.61xd
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
Writing filter settings....
Done writing filter settings to:
C:\Users\mjlyons\workspace\vSPI\projnav\xps\etc\system.filters
Done writing Tab View settings to:
C:\Users\mjlyons\workspace\vSPI\projnav\xps\etc\system.gui
Writing filter settings....
Done writing filter settings to:
C:\Users\mjlyons\workspace\vSPI\projnav\xps\etc\system.filters
Done writing Tab View settings to:
C:\Users\mjlyons\workspace\vSPI\projnav\xps\etc\system.gui
projnav/xps/system.mhs
View file @ 23405448
......@@ -160,3 +160,15 @@ BEGIN proc_sys_reset
PORT Peripheral_Reset = sys_periph_reset
END
BEGIN spiifc
PARAMETER INSTANCE = spiifc_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0x85000000
PARAMETER C_HIGHADDR = 0x8500FFFF
PARAMETER C_MEM0_BASEADDR = 0x85010000
PARAMETER C_MEM0_HIGHADDR = 0x85010FFF
PARAMETER C_MEM1_BASEADDR = 0x85011000
PARAMETER C_MEM1_HIGHADDR = 0x85011FFF
BUS_INTERFACE SPLB = mb_plb
END
projnav/xps/system_incl.make
View file @ 23405448
......@@ -72,7 +72,8 @@ implementation/leds_8bits_wrapper.ngc \
implementation/push_buttons_5bits_wrapper.ngc \
implementation/clock_generator_0_wrapper.ngc \
implementation/mdm_0_wrapper.ngc \
implementation/proc_sys_reset_0_wrapper.ngc
implementation/proc_sys_reset_0_wrapper.ngc \
implementation/spiifc_0_wrapper.ngc
POSTSYN_NETLIST = implementation/$(SYSTEM).ngc
......
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