Adding the spiifc xps pcore skeleton to xps project

projnav/xps/__xps/ise/system.xreport

 <?xml version='1.0' encoding='UTF-8'?>
 <report-views version="2.0" >
  <header>
-  <DateModified>2012-02-28T10:59:37</DateModified>
+  <DateModified>2012-02-28T11:11:33</DateModified>
   <ModuleName>system</ModuleName>
-  <SummaryTimeStamp>2012-02-28T10:59:37</SummaryTimeStamp>
+  <SummaryTimeStamp>2012-02-28T11:11:33</SummaryTimeStamp>
   <SavedFilePath>C:/Users/mjlyons/workspace/vSPI/projnav/xps/__xps/ise/system.xreport</SavedFilePath>
   <FilterFile>filter.filter</FilterFile>
   <SavedFilterFilePath>C:/Users/mjlyons/workspace/vSPI/projnav/xps/__xps/ise</SavedFilterFilePath>

projnav/xps/__xps/system.xml

 
-<EDKSYSTEM EDKVERSION="13.2" EDWVERSION="1.2" TIMESTAMP="Tue Feb 28 10:59:38 2012">
+<EDKSYSTEM EDKVERSION="13.2" EDWVERSION="1.2" TIMESTAMP="Tue Feb 28 11:11:34 2012">
 
   <SYSTEMINFO ARCH="spartan6" DEVICE="xc6slx45" PACKAGE="csg324" PART="xc6slx45csg324-2" SOURCE="C:/Users/mjlyons/workspace/vSPI/projnav/xps/system.xmp" SPEEDGRADE="-2"/>
 

projnav/xps/drivers/spiifc_v1_00_a/data/spiifc_v2_1_0.mdd

+##############################################################################
+## Filename:          C:\Users\mjlyons\workspace\vSPI\projnav\xps/drivers/spiifc_v1_00_a/data/spiifc_v2_1_0.mdd
+## Description:       Microprocessor Driver Definition
+## Date:              Tue Feb 28 11:11:28 2012 (by Create and Import Peripheral Wizard)
+##############################################################################
+
+OPTION psf_version = 2.1.0;
+
+BEGIN DRIVER spiifc
+
+  OPTION supported_peripherals = (spiifc);
+  OPTION depends = (common_v1_00_a);
+  OPTION copyfiles = all;
+
+  BEGIN ARRAY interrupt_handler
+    PROPERTY desc = "Interrupt Handler Information";
+    PROPERTY size = 1, permit = none;
+    PARAM name = int_handler, default = SPIIFC_Intr_DefaultHandler, desc = "Name of Interrupt Handler", type = string;
+    PARAM name = int_port, default = IP2INTC_Irpt, desc = "Interrupt pin associated with the interrupt handler", permit = none;
+
+  END ARRAY
+
+END DRIVER

projnav/xps/drivers/spiifc_v1_00_a/data/spiifc_v2_1_0.tcl

+##############################################################################
+## Filename:          C:\Users\mjlyons\workspace\vSPI\projnav\xps/drivers/spiifc_v1_00_a/data/spiifc_v2_1_0.tcl
+## Description:       Microprocess Driver Command (tcl)
+## Date:              Tue Feb 28 11:11:28 2012 (by Create and Import Peripheral Wizard)
+##############################################################################
+
+#uses "xillib.tcl"
+
+proc generate {drv_handle} {
+  xdefine_include_file $drv_handle "xparameters.h" "spiifc" "NUM_INSTANCES" "DEVICE_ID" "C_BASEADDR" "C_HIGHADDR" "C_MEM0_BASEADDR" "C_MEM0_HIGHADDR" "C_MEM1_BASEADDR" "C_MEM1_HIGHADDR" 
+}

projnav/xps/drivers/spiifc_v1_00_a/src/Makefile

+##############################################################################
+## Filename:          C:\Users\mjlyons\workspace\vSPI\projnav\xps/drivers/spiifc_v1_00_a/src/Makefile
+## Description:       Microprocessor Driver Makefile
+## Date:              Tue Feb 28 11:11:28 2012 (by Create and Import Peripheral Wizard)
+##############################################################################
+
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+INCLUDEFILES=*.h
+LIBSOURCES=*.c
+OUTS = *.o
+
+libs:
+	echo "Compiling spiifc"
+	$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
+	make clean
+
+include:
+	${CP} $(INCLUDEFILES) $(INCLUDEDIR)
+
+clean:
+	rm -rf ${OUTS}

projnav/xps/drivers/spiifc_v1_00_a/src/spiifc.c

+/*****************************************************************************
+* Filename:          C:\Users\mjlyons\workspace\vSPI\projnav\xps/drivers/spiifc_v1_00_a/src/spiifc.c
+* Version:           1.00.a
+* Description:       spiifc Driver Source File
+* Date:              Tue Feb 28 11:11:28 2012 (by Create and Import Peripheral Wizard)
+*****************************************************************************/
+
+
+/***************************** Include Files *******************************/
+
+#include "spiifc.h"
+
+/************************** Function Definitions ***************************/
+
+/**
+ *
+ * Enable all possible interrupts from SPIIFC device.
+ *
+ * @param   baseaddr_p is the base address of the SPIIFC device.
+ *
+ * @return  None.
+ *
+ * @note    None.
+ *
+ */
+void SPIIFC_EnableInterrupt(void * baseaddr_p)
+{
+  Xuint32 baseaddr;
+  baseaddr = (Xuint32) baseaddr_p;
+
+  /*
+   * Enable all interrupt source from user logic.
+   */
+  SPIIFC_mWriteReg(baseaddr, SPIIFC_INTR_IPIER_OFFSET, 0x00000001);
+
+  /*
+   * Set global interrupt enable.
+   */
+  SPIIFC_mWriteReg(baseaddr, SPIIFC_INTR_DGIER_OFFSET, INTR_GIE_MASK);
+}
+
+/**
+ *
+ * Example interrupt controller handler for SPIIFC device.
+ * This is to show example of how to toggle write back ISR to clear interrupts.
+ *
+ * @param   baseaddr_p is the base address of the SPIIFC device.
+ *
+ * @return  None.
+ *
+ * @note    None.
+ *
+ */
+void SPIIFC_Intr_DefaultHandler(void * baseaddr_p)
+{
+  Xuint32 baseaddr;
+  Xuint32 IntrStatus;
+Xuint32 IpStatus;
+  baseaddr = (Xuint32) baseaddr_p;
+
+  {
+    xil_printf("User logic interrupt! \n\r");
+    IpStatus = SPIIFC_mReadReg(baseaddr, SPIIFC_INTR_IPISR_OFFSET);
+    SPIIFC_mWriteReg(baseaddr, SPIIFC_INTR_IPISR_OFFSET, IpStatus);
+  }
+
+}
+

projnav/xps/drivers/spiifc_v1_00_a/src/spiifc_selftest.c

+/*****************************************************************************
+* Filename:          C:\Users\mjlyons\workspace\vSPI\projnav\xps/drivers/spiifc_v1_00_a/src/spiifc_selftest.c
+* Version:           1.00.a
+* Description:       Contains a diagnostic self-test function for the spiifc driver
+* Date:              Tue Feb 28 11:11:28 2012 (by Create and Import Peripheral Wizard)
+*****************************************************************************/
+
+
+/***************************** Include Files *******************************/
+
+#include "spiifc.h"
+
+/************************** Constant Definitions ***************************/
+
+
+/************************** Variable Definitions ****************************/
+
+extern Xuint32 LocalBRAM; /* User logic local memory (BRAM) base address */
+
+/************************** Function Definitions ***************************/
+
+/**
+ *
+ * Run a self-test on the driver/device. Note this may be a destructive test if
+ * resets of the device are performed.
+ *
+ * If the hardware system is not built correctly, this function may never
+ * return to the caller.
+ *
+ * @param   baseaddr_p is the base address of the SPIIFC instance to be worked on.
+ *
+ * @return
+ *
+ *    - XST_SUCCESS   if all self-test code passed
+ *    - XST_FAILURE   if any self-test code failed
+ *
+ * @note    Caching must be turned off for this function to work.
+ * @note    Self test may fail if data memory and device are not on the same bus.
+ *
+ */
+XStatus SPIIFC_SelfTest(void * baseaddr_p)
+{
+  int     Index;
+  Xuint32 baseaddr;
+  Xuint8  Reg8Value;
+  Xuint16 Reg16Value;
+  Xuint32 Reg32Value;
+  Xuint32 Mem32Value;
+
+  /*
+   * Check and get the device address
+   */
+  /*
+   * Base Address maybe 0. Up to developer to uncomment line below.
+  XASSERT_NONVOID(baseaddr_p != XNULL);
+   */
+  baseaddr = (Xuint32) baseaddr_p;
+
+  xil_printf("******************************\n\r");
+  xil_printf("* User Peripheral Self Test\n\r");
+  xil_printf("******************************\n\n\r");
+
+  /*
+   * Write to user logic slave module register(s) and read back
+   */
+  xil_printf("User logic slave module test...\n\r");
+  xil_printf("   - write 1 to slave register 0 word 0\n\r");
+  SPIIFC_mWriteSlaveReg0(baseaddr, 0, 1);
+  Reg32Value = SPIIFC_mReadSlaveReg0(baseaddr, 0);
+  xil_printf("   - read %d from register 0 word 0\n\r", Reg32Value);
+  if ( Reg32Value != (Xuint32) 1 )
+  {
+    xil_printf("   - slave register 0 word 0 write/read failed\n\r");
+    return XST_FAILURE;
+  }
+  xil_printf("   - write 2 to slave register 1 word 0\n\r");
+  SPIIFC_mWriteSlaveReg1(baseaddr, 0, 2);
+  Reg32Value = SPIIFC_mReadSlaveReg1(baseaddr, 0);
+  xil_printf("   - read %d from register 1 word 0\n\r", Reg32Value);
+  if ( Reg32Value != (Xuint32) 2 )
+  {
+    xil_printf("   - slave register 1 word 0 write/read failed\n\r");
+    return XST_FAILURE;
+  }
+  xil_printf("   - write 3 to slave register 2 word 0\n\r");
+  SPIIFC_mWriteSlaveReg2(baseaddr, 0, 3);
+  Reg32Value = SPIIFC_mReadSlaveReg2(baseaddr, 0);
+  xil_printf("   - read %d from register 2 word 0\n\r", Reg32Value);
+  if ( Reg32Value != (Xuint32) 3 )
+  {
+    xil_printf("   - slave register 2 word 0 write/read failed\n\r");
+    return XST_FAILURE;
+  }
+  xil_printf("   - write 4 to slave register 3 word 0\n\r");
+  SPIIFC_mWriteSlaveReg3(baseaddr, 0, 4);
+  Reg32Value = SPIIFC_mReadSlaveReg3(baseaddr, 0);
+  xil_printf("   - read %d from register 3 word 0\n\r", Reg32Value);
+  if ( Reg32Value != (Xuint32) 4 )
+  {
+    xil_printf("   - slave register 3 word 0 write/read failed\n\r");
+    return XST_FAILURE;
+  }
+  xil_printf("   - write 5 to slave register 4 word 0\n\r");
+  SPIIFC_mWriteSlaveReg4(baseaddr, 0, 5);
+  Reg32Value = SPIIFC_mReadSlaveReg4(baseaddr, 0);
+  xil_printf("   - read %d from register 4 word 0\n\r", Reg32Value);
+  if ( Reg32Value != (Xuint32) 5 )
+  {
+    xil_printf("   - slave register 4 word 0 write/read failed\n\r");
+    return XST_FAILURE;
+  }
+  xil_printf("   - write 6 to slave register 5 word 0\n\r");
+  SPIIFC_mWriteSlaveReg5(baseaddr, 0, 6);
+  Reg32Value = SPIIFC_mReadSlaveReg5(baseaddr, 0);
+  xil_printf("   - read %d from register 5 word 0\n\r", Reg32Value);
+  if ( Reg32Value != (Xuint32) 6 )
+  {
+    xil_printf("   - slave register 5 word 0 write/read failed\n\r");
+    return XST_FAILURE;
+  }
+  xil_printf("   - write 7 to slave register 6 word 0\n\r");
+  SPIIFC_mWriteSlaveReg6(baseaddr, 0, 7);
+  Reg32Value = SPIIFC_mReadSlaveReg6(baseaddr, 0);
+  xil_printf("   - read %d from register 6 word 0\n\r", Reg32Value);
+  if ( Reg32Value != (Xuint32) 7 )
+  {
+    xil_printf("   - slave register 6 word 0 write/read failed\n\r");
+    return XST_FAILURE;
+  }
+  xil_printf("   - write 8 to slave register 7 word 0\n\r");
+  SPIIFC_mWriteSlaveReg7(baseaddr, 0, 8);
+  Reg32Value = SPIIFC_mReadSlaveReg7(baseaddr, 0);
+  xil_printf("   - read %d from register 7 word 0\n\r", Reg32Value);
+  if ( Reg32Value != (Xuint32) 8 )
+  {
+    xil_printf("   - slave register 7 word 0 write/read failed\n\r");
+    return XST_FAILURE;
+  }
+  xil_printf("   - write 9 to slave register 8 word 0\n\r");
+  SPIIFC_mWriteSlaveReg8(baseaddr, 0, 9);
+  Reg32Value = SPIIFC_mReadSlaveReg8(baseaddr, 0);
+  xil_printf("   - read %d from register 8 word 0\n\r", Reg32Value);
+  if ( Reg32Value != (Xuint32) 9 )
+  {
+    xil_printf("   - slave register 8 word 0 write/read failed\n\r");
+    return XST_FAILURE;
+  }
+  xil_printf("   - write 10 to slave register 9 word 0\n\r");
+  SPIIFC_mWriteSlaveReg9(baseaddr, 0, 10);
+  Reg32Value = SPIIFC_mReadSlaveReg9(baseaddr, 0);
+  xil_printf("   - read %d from register 9 word 0\n\r", Reg32Value);
+  if ( Reg32Value != (Xuint32) 10 )
+  {
+    xil_printf("   - slave register 9 word 0 write/read failed\n\r");
+    return XST_FAILURE;
+  }
+  xil_printf("   - write 11 to slave register 10 word 0\n\r");
+  SPIIFC_mWriteSlaveReg10(baseaddr, 0, 11);
+  Reg32Value = SPIIFC_mReadSlaveReg10(baseaddr, 0);
+  xil_printf("   - read %d from register 10 word 0\n\r", Reg32Value);
+  if ( Reg32Value != (Xuint32) 11 )
+  {
+    xil_printf("   - slave register 10 word 0 write/read failed\n\r");
+    return XST_FAILURE;
+  }
+  xil_printf("   - write 12 to slave register 11 word 0\n\r");
+  SPIIFC_mWriteSlaveReg11(baseaddr, 0, 12);
+  Reg32Value = SPIIFC_mReadSlaveReg11(baseaddr, 0);
+  xil_printf("   - read %d from register 11 word 0\n\r", Reg32Value);
+  if ( Reg32Value != (Xuint32) 12 )
+  {
+    xil_printf("   - slave register 11 word 0 write/read failed\n\r");
+    return XST_FAILURE;
+  }
+  xil_printf("   - write 13 to slave register 12 word 0\n\r");
+  SPIIFC_mWriteSlaveReg12(baseaddr, 0, 13);
+  Reg32Value = SPIIFC_mReadSlaveReg12(baseaddr, 0);
+  xil_printf("   - read %d from register 12 word 0\n\r", Reg32Value);
+  if ( Reg32Value != (Xuint32) 13 )
+  {
+    xil_printf("   - slave register 12 word 0 write/read failed\n\r");
+    return XST_FAILURE;
+  }
+  xil_printf("   - write 14 to slave register 13 word 0\n\r");
+  SPIIFC_mWriteSlaveReg13(baseaddr, 0, 14);
+  Reg32Value = SPIIFC_mReadSlaveReg13(baseaddr, 0);
+  xil_printf("   - read %d from register 13 word 0\n\r", Reg32Value);
+  if ( Reg32Value != (Xuint32) 14 )
+  {
+    xil_printf("   - slave register 13 word 0 write/read failed\n\r");
+    return XST_FAILURE;
+  }
+  xil_printf("   - write 15 to slave register 14 word 0\n\r");
+  SPIIFC_mWriteSlaveReg14(baseaddr, 0, 15);
+  Reg32Value = SPIIFC_mReadSlaveReg14(baseaddr, 0);
+  xil_printf("   - read %d from register 14 word 0\n\r", Reg32Value);
+  if ( Reg32Value != (Xuint32) 15 )
+  {
+    xil_printf("   - slave register 14 word 0 write/read failed\n\r");
+    return XST_FAILURE;
+  }
+  xil_printf("   - write 16 to slave register 15 word 0\n\r");
+  SPIIFC_mWriteSlaveReg15(baseaddr, 0, 16);
+  Reg32Value = SPIIFC_mReadSlaveReg15(baseaddr, 0);
+  xil_printf("   - read %d from register 15 word 0\n\r", Reg32Value);
+  if ( Reg32Value != (Xuint32) 16 )
+  {
+    xil_printf("   - slave register 15 word 0 write/read failed\n\r");
+    return XST_FAILURE;
+  }
+  xil_printf("   - slave register write/read passed\n\n\r");
+
+  /*
+   * Write data to user logic BRAMs and read back
+   */
+  xil_printf("User logic BRAM test...\n\r");
+  xil_printf("   - local BRAM address is 0x%08x\n\r", LocalBRAM);
+  xil_printf("   - write pattern to local BRAM and read back\n\r");
+  for ( Index = 0; Index < 256; Index++ )
+  {
+    SPIIFC_mWriteMemory(LocalBRAM+4*Index, 0xDEADBEEF);
+    Mem32Value = SPIIFC_mReadMemory(LocalBRAM+4*Index);
+    if ( Mem32Value != 0xDEADBEEF )
+    {
+      xil_printf("   - write/read BRAM failed on address 0x%08x\n\r", LocalBRAM+4*Index);
+      return XST_FAILURE;
+    }
+  }
+  xil_printf("   - write/read BRAM passed\n\n\r");
+
+  /*
+   * Enable all possible interrupts and clear interrupt status register(s)
+   */
+  xil_printf("Interrupt controller test...\n\r");
+  Reg32Value = SPIIFC_mReadReg(baseaddr, SPIIFC_INTR_IPISR_OFFSET);
+  xil_printf("   - IP (user logic) interrupt status : 0x%08x\n\r", Reg32Value);
+  xil_printf("   - clear IP (user logic) interrupt status register\n\r");
+  SPIIFC_mWriteReg(baseaddr, SPIIFC_INTR_IPISR_OFFSET, Reg32Value);
+  xil_printf("   - enable all possible interrupt(s)\n\r");
+  SPIIFC_EnableInterrupt(baseaddr_p);
+  xil_printf("   - write/read interrupt register passed\n\n\r");
+
+  return XST_SUCCESS;
+}

projnav/xps/implementation/system_summary.html

@@ -31,7 +31,11 @@
 <TR ALIGN=LEFT><TD>Platgen Log File</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
 <TR ALIGN=LEFT><TD>Simgen Log File</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
 <TR ALIGN=LEFT><TD>BitInit Log File</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/mjlyons/workspace/vSPI/projnav/xps\system.log'>System Log File</A></TD><TD>Tue Feb 28 11:00:43 2012</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/mjlyons/workspace/vSPI/projnav/xps\system.log'>System Log File</A></TD><TD>Tue Feb 28 11:11:32 2012</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+</TABLE>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>XPS Synthesis Summary (estimated values)</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=EDKSynthesisSumary"><B>[-]</B></a></TD></TR>
+<TR BGCOLOR='#FFFF99'><TD><B>Report</B></TD><TD><B>Generated</B></TD><TD><B>Flip Flops Used</B></TD><TD><B>LUTs Used</B></TD><TD><B>BRAMS Used</B></TD><TD COLSPAN='2'><B>Errors</B></TD></TR>
 </TABLE>
 
 
@@ -57,5 +61,5 @@
 </TABLE>
 
 
-<br><center><b>Date Generated:</b> 02/28/2012 - 11:00:44</center>
+<br><center><b>Date Generated:</b> 02/28/2012 - 11:11:33</center>
 </BODY></HTML>
\ No newline at end of file

projnav/xps/pcores/spiifc_v1_00_a/data/_spiifc_xst.prj

+vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/proc_common_pkg.vhd"
+vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ipif_pkg.vhd"
+vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_muxcy.vhd"
+vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_gate128.vhd"
+vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/family_support.vhd"
+vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd"
+vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter_f.vhd"
+vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/flex_addr_cntr.vhd"
+vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/addr_reg_cntr_brst_flex.vhd"
+vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plb_address_decoder.vhd"
+vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/burst_support.vhd"
+vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/wr_buffer.vhd"
+vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/be_reset_gen.vhd"
+vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plb_slave_attachment.vhd"
+vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/data_mirror_128.vhd"
+vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plbv46_slave_burst.vhd"
+vhdl interrupt_control_v2_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v2_01_a/hdl/vhdl/interrupt_control.vhd"
+verilog spiifc_v1_00_a "../hdl/verilog/user_logic.v"
+vhdl spiifc_v1_00_a "../hdl/vhdl/spiifc.vhd"

projnav/xps/pcores/spiifc_v1_00_a/data/spiifc_v2_1_0.mpd

+###################################################################
+##
+## Name     : spiifc
+## Desc     : Microprocessor Peripheral Description
+##          : Automatically generated by PsfUtility
+##
+###################################################################
+
+BEGIN spiifc
+
+## Peripheral Options
+OPTION IPTYPE = PERIPHERAL
+OPTION IMP_NETLIST = TRUE
+OPTION HDL = MIXED
+OPTION IP_GROUP = MICROBLAZE:PPC:USER
+OPTION DESC = SPIIFC
+OPTION ARCH_SUPPORT_MAP = (others=DEVELOPMENT)
+
+
+## Bus Interfaces
+BUS_INTERFACE BUS = SPLB, BUS_STD = PLBV46, BUS_TYPE = SLAVE
+
+## Generics for VHDL or Parameters for Verilog
+PARAMETER C_BASEADDR = 0xffffffff, DT = std_logic_vector, MIN_SIZE = 0x200, PAIR = C_HIGHADDR, ADDRESS = BASE, BUS = SPLB
+PARAMETER C_HIGHADDR = 0x00000000, DT = std_logic_vector, PAIR = C_BASEADDR, ADDRESS = HIGH, BUS = SPLB
+PARAMETER C_SPLB_AWIDTH = 32, DT = INTEGER, BUS = SPLB, ASSIGNMENT = CONSTANT
+PARAMETER C_SPLB_DWIDTH = 128, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128)
+PARAMETER C_SPLB_NUM_MASTERS = 8, DT = INTEGER, BUS = SPLB, RANGE = (1:16)
+PARAMETER C_SPLB_MID_WIDTH = 3, DT = INTEGER, BUS = SPLB, RANGE = (1:4)
+PARAMETER C_SPLB_NATIVE_DWIDTH = 32, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128), ASSIGNMENT = CONSTANT
+PARAMETER C_SPLB_P2P = 0, DT = INTEGER, BUS = SPLB, RANGE = (0, 1)
+PARAMETER C_SPLB_SUPPORT_BURSTS = 1, DT = INTEGER, BUS = SPLB, RANGE = (0, 1), ASSIGNMENT = CONSTANT
+PARAMETER C_SPLB_SMALLEST_MASTER = 32, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128)
+PARAMETER C_SPLB_CLK_PERIOD_PS = 10000, DT = INTEGER, BUS = SPLB
+PARAMETER C_INCLUDE_DPHASE_TIMER = 1, DT = INTEGER, RANGE = (0, 1)
+PARAMETER C_FAMILY = virtex6, DT = STRING
+PARAMETER C_MEM0_BASEADDR = 0xffffffff, DT = std_logic_vector, PAIR = C_MEM0_HIGHADDR, ADDRESS = BASE, BUS = SPLB
+PARAMETER C_MEM0_HIGHADDR = 0x00000000, DT = std_logic_vector, PAIR = C_MEM0_BASEADDR, ADDRESS = HIGH, BUS = SPLB
+PARAMETER C_MEM1_BASEADDR = 0xffffffff, DT = std_logic_vector, PAIR = C_MEM1_HIGHADDR, ADDRESS = BASE, BUS = SPLB
+PARAMETER C_MEM1_HIGHADDR = 0x00000000, DT = std_logic_vector, PAIR = C_MEM1_BASEADDR, ADDRESS = HIGH, BUS = SPLB
+
+## Ports
+PORT SPLB_Clk = "", DIR = I, SIGIS = CLK, BUS = SPLB
+PORT SPLB_Rst = SPLB_Rst, DIR = I, SIGIS = RST, BUS = SPLB
+PORT PLB_ABus = PLB_ABus, DIR = I, VEC = [0:31], BUS = SPLB
+PORT PLB_UABus = PLB_UABus, DIR = I, VEC = [0:31], BUS = SPLB
+PORT PLB_PAValid = PLB_PAValid, DIR = I, BUS = SPLB
+PORT PLB_SAValid = PLB_SAValid, DIR = I, BUS = SPLB
+PORT PLB_rdPrim = PLB_rdPrim, DIR = I, BUS = SPLB
+PORT PLB_wrPrim = PLB_wrPrim, DIR = I, BUS = SPLB
+PORT PLB_masterID = PLB_masterID, DIR = I, VEC = [0:(C_SPLB_MID_WIDTH-1)], BUS = SPLB
+PORT PLB_abort = PLB_abort, DIR = I, BUS = SPLB
+PORT PLB_busLock = PLB_busLock, DIR = I, BUS = SPLB
+PORT PLB_RNW = PLB_RNW, DIR = I, BUS = SPLB
+PORT PLB_BE = PLB_BE, DIR = I, VEC = [0:((C_SPLB_DWIDTH/8)-1)], BUS = SPLB
+PORT PLB_MSize = PLB_MSize, DIR = I, VEC = [0:1], BUS = SPLB
+PORT PLB_size = PLB_size, DIR = I, VEC = [0:3], BUS = SPLB
+PORT PLB_type = PLB_type, DIR = I, VEC = [0:2], BUS = SPLB
+PORT PLB_lockErr = PLB_lockErr, DIR = I, BUS = SPLB
+PORT PLB_wrDBus = PLB_wrDBus, DIR = I, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB
+PORT PLB_wrBurst = PLB_wrBurst, DIR = I, BUS = SPLB
+PORT PLB_rdBurst = PLB_rdBurst, DIR = I, BUS = SPLB
+PORT PLB_wrPendReq = PLB_wrPendReq, DIR = I, BUS = SPLB
+PORT PLB_rdPendReq = PLB_rdPendReq, DIR = I, BUS = SPLB
+PORT PLB_wrPendPri = PLB_wrPendPri, DIR = I, VEC = [0:1], BUS = SPLB
+PORT PLB_rdPendPri = PLB_rdPendPri, DIR = I, VEC = [0:1], BUS = SPLB
+PORT PLB_reqPri = PLB_reqPri, DIR = I, VEC = [0:1], BUS = SPLB
+PORT PLB_TAttribute = PLB_TAttribute, DIR = I, VEC = [0:15], BUS = SPLB
+PORT Sl_addrAck = Sl_addrAck, DIR = O, BUS = SPLB
+PORT Sl_SSize = Sl_SSize, DIR = O, VEC = [0:1], BUS = SPLB
+PORT Sl_wait = Sl_wait, DIR = O, BUS = SPLB
+PORT Sl_rearbitrate = Sl_rearbitrate, DIR = O, BUS = SPLB
+PORT Sl_wrDAck = Sl_wrDAck, DIR = O, BUS = SPLB
+PORT Sl_wrComp = Sl_wrComp, DIR = O, BUS = SPLB
+PORT Sl_wrBTerm = Sl_wrBTerm, DIR = O, BUS = SPLB
+PORT Sl_rdDBus = Sl_rdDBus, DIR = O, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB
+PORT Sl_rdWdAddr = Sl_rdWdAddr, DIR = O, VEC = [0:3], BUS = SPLB
+PORT Sl_rdDAck = Sl_rdDAck, DIR = O, BUS = SPLB
+PORT Sl_rdComp = Sl_rdComp, DIR = O, BUS = SPLB
+PORT Sl_rdBTerm = Sl_rdBTerm, DIR = O, BUS = SPLB
+PORT Sl_MBusy = Sl_MBusy, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
+PORT Sl_MWrErr = Sl_MWrErr, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
+PORT Sl_MRdErr = Sl_MRdErr, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
+PORT Sl_MIRQ = Sl_MIRQ, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
+PORT IP2INTC_Irpt = "", DIR = O, SIGIS = INTERRUPT, SENSITIVITY = LEVEL_HIGH
+
+END

projnav/xps/pcores/spiifc_v1_00_a/data/spiifc_v2_1_0.pao

+##############################################################################
+## Filename:          C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/data/spiifc_v2_1_0.pao
+## Description:       Peripheral Analysis Order
+## Date:              Tue Feb 28 11:11:15 2012 (by Create and Import Peripheral Wizard)
+##############################################################################
+
+lib proc_common_v3_00_a  all 
+lib plbv46_slave_burst_v1_01_a  all 
+lib interrupt_control_v2_01_a  all 
+lib spiifc_v1_00_a user_logic verilog
+lib spiifc_v1_00_a spiifc vhdl

projnav/xps/pcores/spiifc_v1_00_a/devl/create.cip

+CipWiz::SetVersion "13.2";
+CipWiz::SetFlow "CREATE";
+CipWiz::SetParameter "ProjectDir" "C:\Users\mjlyons\workspace\vSPI\projnav\xps";
+CipWiz::SetParameter "IpName" "spiifc";
+CipWiz::SetParameter "IpVersion" "1.00.a";
+CipWiz::SetParameter "HdlLanguage" "2";
+CipWiz::SetParameter "BusType" "64";
+CipWiz::SetParameter "IncludeIseFile" "TRUE";
+CipWiz::SetParameter "IncludeXpsFile" "TRUE";
+CipWiz::SetParameter "IncludeSoftwareDriverFile" "TRUE";
+CipWiz::SetParameter "IncludeBFMSimulationFile" "FALSE";
+CipWiz::SetParameter "IncludeSlaveAttachmentSupport" "TRUE";
+CipWiz::SetParameter "IncludeMasterAttachmentSupport" "FALSE";
+CipWiz::SetParameter "IncludeMirResetRegister" "FALSE";
+CipWiz::SetParameter "IncludeFifoSupport" "FALSE";
+CipWiz::SetParameter "IncludeInterruptSupport" "TRUE";
+CipWiz::SetParameter "IncludeDMASupport" "FALSE";
+CipWiz::SetParameter "IncludeBurstSupport" "FALSE";
+CipWiz::SetParameter "IncludeUserRegisterSupport" "TRUE";
+CipWiz::SetParameter "IncludeUserMasterSupport" "FALSE";
+CipWiz::SetParameter "IncludeUserMemorySupport" "TRUE";
+CipWiz::SetParameter "UseSlaveBurst" "TRUE";
+CipWiz::SetParameter "UseMasterBurst" "FALSE";
+CipWiz::SetParameter "UseReadFifo" "FALSE";
+CipWiz::SetParameter "UseWriteFifo" "FALSE";
+CipWiz::SetParameter "UseReadFifoPacketMode" "FALSE";
+CipWiz::SetParameter "UseWriteFifoPacketMode" "FALSE";
+CipWiz::SetParameter "UseReadFifoVacancyCalculation" "FALSE";
+CipWiz::SetParameter "UseWriteFifoVacancyCalculation" "FALSE";
+CipWiz::SetParameter "WriteFifoDataWidth" "0";
+CipWiz::SetParameter "WriteFifoDepth" "0";
+CipWiz::SetParameter "ReadFifoDataWidth" "0";
+CipWiz::SetParameter "ReadFifoDepth" "0";
+CipWiz::SetParameter "UseDeviceISC" "FALSE";
+CipWiz::SetParameter "UseDevicePriorityEncoder" "FALSE";
+CipWiz::SetParameter "NumberOfInterrupt" "1";
+CipWiz::SetParameter "TypeOfInterrupt" "1";
+CipWiz::SetParameter "TypeOfDMA" "0";
+CipWiz::SetParameter "UseFastTransferProtocol" "FALSE";
+CipWiz::SetParameter "BurstMaxSize" "0";
+CipWiz::SetParameter "BurstPageSize" "0";
+CipWiz::SetParameter "IncludeDPhaseTimer" "TRUE";
+CipWiz::SetParameter "SlaveSideNativeDataWidth" "32";
+CipWiz::SetParameter "SlaveBurstWriteBufferDepth" "16";
+CipWiz::SetParameter "MasterSideNativeDataWidth" "0";
+CipWiz::SetParameter "AXIMasterMaxBurstSize" "0";
+CipWiz::SetParameter "AXIMasterWidthOfPort" "0";
+CipWiz::SetParameter "AXIMasterAddrPipelineDepth" "0";
+CipWiz::SetParameter "NumberOfUserRegister" "16";
+CipWiz::SetParameter "UserRegisterDataWidth" "0";
+CipWiz::SetParameter "WriteMode" "0";
+CipWiz::SetParameter "HasInputFSL" "0";
+CipWiz::SetParameter "HasOutputFSL" "0";
+CipWiz::SetParameter "TotalInputData" "0";
+CipWiz::SetParameter "TotalOutputData" "0";
+CipWiz::SetParameter "NumOfInputArgs" "0";
+CipWiz::SetParameter "NumOfOutputArgs" "0";
+CipWiz::SetParameter "NumberOfUserMemoryBank" "2";
+CipWiz::SetParameter "UserMemoryBankDataWidth" "0";
+CipWiz::SetParameter "IpicSelectedPortNames" "Bus2IP_Clk|Bus2IP_Reset|Bus2IP_Addr|Bus2IP_CS|Bus2IP_RNW|Bus2IP_Data|Bus2IP_BE|Bus2IP_RdCE|Bus2IP_WrCE|Bus2IP_Burst|Bus2IP_BurstLength|Bus2IP_RdReq|Bus2IP_WrReq|IP2Bus_AddrAck|IP2Bus_Data|IP2Bus_RdAck|IP2Bus_WrAck|IP2Bus_Error|IP2Bus_IntrEvent|";
+CipWiz::SetParameter "UserLogicModuleName" "0";
+CipWiz::SetParameter "TypeOfUserLogicSource" "user_logic";

projnav/xps/pcores/spiifc_v1_00_a/devl/ipwiz.opt

+-batch 
+-create spiifc 
+-ver 1.00.a 
+-dir "C:\Users\mjlyons\workspace\vSPI\projnav\xps" 
+-lang verilog 
+-bus plbv46 s 
+-burst s 32 
+-isc 1 
+-intrn 1 1 
+-reg 16 
+-mem 2 
+-wrbuf 16 
+-xps 
+-ise 
+-driver 

projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/_xmsgs/pn_parser.xmsgs

+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated   -->
+<!--     by the Xilinx ISE software.  Any direct editing or        -->
+<!--     changes made to this file may result in unpredictable     -->
+<!--     behavior or data corruption.  It is strongly advised that -->
+<!--     users do not edit the contents of this file.              -->
+<!--                                                               -->
+<!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.    -->
+
+<messages>
+<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v2_01_a/hdl/vhdl/interrupt_control.vhd&quot; into library interrupt_control_v2_01_a</arg>
+</msg>
+
+</messages>
+

projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc.gise

+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <!--                                                          -->
+
+  <!--             For tool use only. Do not edit.              -->
+
+  <!--                                                          -->
+
+  <!-- ProjectNavigator created generated project file.         -->
+
+  <!-- For use in tracking generated file and other information -->
+
+  <!-- allowing preservation of process status.                 -->
+
+  <!--                                                          -->
+
+  <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
+
+  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="spiifc.xise"/>
+
+  <files xmlns="http://www.xilinx.com/XMLSchema"/>
+
+  <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>

projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc.tcl

+project new C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc.xise;
+project set family spartan6;
+project set device xc6slx45;
+project set package csg324;
+project set speed -2;
+project set top_level_module_type HDL;
+project set synthesis_tool "XST (VHDL/Verilog)";
+lib_vhdl new spiifc_v1_00_a;
+xfile add C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/hdl/vhdl/spiifc.vhd;
+xfile add C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/hdl/verilog/user_logic.v;
+lib_vhdl new proc_common_v3_00_a;
+xfile add C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/proc_common_pkg.vhd -lib_vhdl proc_common_v3_00_a;
+xfile add C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ipif_pkg.vhd -lib_vhdl proc_common_v3_00_a;
+xfile add C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_muxcy.vhd -lib_vhdl proc_common_v3_00_a;
+xfile add C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_gate128.vhd -lib_vhdl proc_common_v3_00_a;
+xfile add C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/family_support.vhd -lib_vhdl proc_common_v3_00_a;
+xfile add C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd -lib_vhdl proc_common_v3_00_a;
+xfile add C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter_f.vhd -lib_vhdl proc_common_v3_00_a;
+lib_vhdl new plbv46_slave_burst_v1_01_a;
+xfile add C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/flex_addr_cntr.vhd -lib_vhdl plbv46_slave_burst_v1_01_a;
+xfile add C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/addr_reg_cntr_brst_flex.vhd -lib_vhdl plbv46_slave_burst_v1_01_a;
+xfile add C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plb_address_decoder.vhd -lib_vhdl plbv46_slave_burst_v1_01_a;
+xfile add C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/burst_support.vhd -lib_vhdl plbv46_slave_burst_v1_01_a;
+xfile add C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/wr_buffer.vhd -lib_vhdl plbv46_slave_burst_v1_01_a;
+xfile add C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/be_reset_gen.vhd -lib_vhdl plbv46_slave_burst_v1_01_a;
+xfile add C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plb_slave_attachment.vhd -lib_vhdl plbv46_slave_burst_v1_01_a;
+xfile add C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/data_mirror_128.vhd -lib_vhdl plbv46_slave_burst_v1_01_a;
+xfile add C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plbv46_slave_burst.vhd -lib_vhdl plbv46_slave_burst_v1_01_a;
+lib_vhdl new interrupt_control_v2_01_a;
+xfile add C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v2_01_a/hdl/vhdl/interrupt_control.vhd -lib_vhdl interrupt_control_v2_01_a;
+project close;

projnav/xps/pcores/spiifc_v1_00_a/devl/synthesis/spiifc_xst.prj

+vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/proc_common_pkg.vhd"
+vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ipif_pkg.vhd"
+vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_muxcy.vhd"
+vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_gate128.vhd"
+vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/family_support.vhd"
+vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd"
+vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter_f.vhd"
+vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/flex_addr_cntr.vhd"
+vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/addr_reg_cntr_brst_flex.vhd"
+vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plb_address_decoder.vhd"
+vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/burst_support.vhd"
+vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/wr_buffer.vhd"
+vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/be_reset_gen.vhd"
+vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plb_slave_attachment.vhd"
+vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/data_mirror_128.vhd"
+vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plbv46_slave_burst.vhd"
+vhdl interrupt_control_v2_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v2_01_a/hdl/vhdl/interrupt_control.vhd"
+verilog spiifc_v1_00_a "../../hdl/verilog/user_logic.v"
+vhdl spiifc_v1_00_a "../../hdl/vhdl/spiifc.vhd"

projnav/xps/pcores/spiifc_v1_00_a/devl/synthesis/spiifc_xst.scr

+run
+-opt_level 2
+-opt_mode speed
+-ifmt mixed
+-ifn "C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\synthesis\spiifc_xst.prj"
+-top spiifc
+-p virtex6
+-ofn "C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\synthesis\spiifc_xst.ngc"
+-iobuf NO
+-rtlview YES
+-hierarchy_separator /
+-work_lib spiifc_v1_00_a

projnav/xps/system.log

@@ -47,3 +47,17 @@ Done writing filter settings to:
 	C:\Users\mjlyons\workspace\vSPI\projnav\xps\etc\system.filters
 Done writing Tab View settings to:
 	C:\Users\mjlyons\workspace\vSPI\projnav\xps\etc\system.gui
+Xilinx Platform Studio (XPS)
+Xilinx EDK 13.2 Build EDK_O.61xd
+Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
+
+Writing filter settings....
+Done writing filter settings to:
+	C:\Users\mjlyons\workspace\vSPI\projnav\xps\etc\system.filters
+Done writing Tab View settings to:
+	C:\Users\mjlyons\workspace\vSPI\projnav\xps\etc\system.gui
+Writing filter settings....
+Done writing filter settings to:
+	C:\Users\mjlyons\workspace\vSPI\projnav\xps\etc\system.filters
+Done writing Tab View settings to:
+	C:\Users\mjlyons\workspace\vSPI\projnav\xps\etc\system.gui