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Commit 23405448 authored by Mike Lyons's avatar Mike Lyons
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Adding support for memmap memory. Only tested PIO so far, not DMA yet

parent 7133e87e
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projnav/xps/.gitignore 0 → 100644
View file @ 23405448
system.log
psf2Edward.log
projnav/xps/SDK/SDK_Export/hw/system.xml 0 → 100644
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projnav/xps/SDK/SDK_Export/hw/system_bd.bmm 0 → 100644
View file @ 23405448
// BMM LOC annotation file.
//
// Release 13.2 - Data2MEM O.61xd, build 2.2 May 20, 2011
// Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
///////////////////////////////////////////////////////////////////////////////
//
// Processor 'microblaze_0', ID 100, memory map.
//
///////////////////////////////////////////////////////////////////////////////
ADDRESS_MAP microblaze_0 MICROBLAZE 100
///////////////////////////////////////////////////////////////////////////////
//
// Processor 'microblaze_0' address space 'lmb_bram_combined' 0x00000000:0x0000FFFF (64 KBytes).
//
///////////////////////////////////////////////////////////////////////////////
ADDRESS_SPACE lmb_bram_combined RAMB16 [0x00000000:0x0000FFFF]
BUS_BLOCK
lmb_bram/lmb_bram/ramb16bwer_0 [31:31] INPUT = lmb_bram_combined_0.mem PLACED = X2Y46;
lmb_bram/lmb_bram/ramb16bwer_1 [30:30] INPUT = lmb_bram_combined_1.mem PLACED = X2Y50;
lmb_bram/lmb_bram/ramb16bwer_2 [29:29] INPUT = lmb_bram_combined_2.mem PLACED = X3Y46;
lmb_bram/lmb_bram/ramb16bwer_3 [28:28] INPUT = lmb_bram_combined_3.mem PLACED = X1Y40;
lmb_bram/lmb_bram/ramb16bwer_4 [27:27] INPUT = lmb_bram_combined_4.mem PLACED = X2Y48;
lmb_bram/lmb_bram/ramb16bwer_5 [26:26] INPUT = lmb_bram_combined_5.mem PLACED = X3Y44;
lmb_bram/lmb_bram/ramb16bwer_6 [25:25] INPUT = lmb_bram_combined_6.mem PLACED = X2Y44;
lmb_bram/lmb_bram/ramb16bwer_7 [24:24] INPUT = lmb_bram_combined_7.mem PLACED = X3Y42;
lmb_bram/lmb_bram/ramb16bwer_8 [23:23] INPUT = lmb_bram_combined_8.mem PLACED = X2Y36;
lmb_bram/lmb_bram/ramb16bwer_9 [22:22] INPUT = lmb_bram_combined_9.mem PLACED = X1Y34;
lmb_bram/lmb_bram/ramb16bwer_10 [21:21] INPUT = lmb_bram_combined_10.mem PLACED = X1Y32;
lmb_bram/lmb_bram/ramb16bwer_11 [20:20] INPUT = lmb_bram_combined_11.mem PLACED = X1Y36;
lmb_bram/lmb_bram/ramb16bwer_12 [19:19] INPUT = lmb_bram_combined_12.mem PLACED = X1Y30;
lmb_bram/lmb_bram/ramb16bwer_13 [18:18] INPUT = lmb_bram_combined_13.mem PLACED = X2Y30;
lmb_bram/lmb_bram/ramb16bwer_14 [17:17] INPUT = lmb_bram_combined_14.mem PLACED = X2Y28;
lmb_bram/lmb_bram/ramb16bwer_15 [16:16] INPUT = lmb_bram_combined_15.mem PLACED = X1Y28;
lmb_bram/lmb_bram/ramb16bwer_16 [15:15] INPUT = lmb_bram_combined_16.mem PLACED = X3Y28;
lmb_bram/lmb_bram/ramb16bwer_17 [14:14] INPUT = lmb_bram_combined_17.mem PLACED = X2Y32;
lmb_bram/lmb_bram/ramb16bwer_18 [13:13] INPUT = lmb_bram_combined_18.mem PLACED = X1Y38;
lmb_bram/lmb_bram/ramb16bwer_19 [12:12] INPUT = lmb_bram_combined_19.mem PLACED = X2Y34;
lmb_bram/lmb_bram/ramb16bwer_20 [11:11] INPUT = lmb_bram_combined_20.mem PLACED = X2Y26;
lmb_bram/lmb_bram/ramb16bwer_21 [10:10] INPUT = lmb_bram_combined_21.mem PLACED = X3Y30;
lmb_bram/lmb_bram/ramb16bwer_22 [9:9] INPUT = lmb_bram_combined_22.mem PLACED = X3Y26;
lmb_bram/lmb_bram/ramb16bwer_23 [8:8] INPUT = lmb_bram_combined_23.mem PLACED = X2Y24;
lmb_bram/lmb_bram/ramb16bwer_24 [7:7] INPUT = lmb_bram_combined_24.mem PLACED = X3Y34;
lmb_bram/lmb_bram/ramb16bwer_25 [6:6] INPUT = lmb_bram_combined_25.mem PLACED = X3Y40;
lmb_bram/lmb_bram/ramb16bwer_26 [5:5] INPUT = lmb_bram_combined_26.mem PLACED = X2Y42;
lmb_bram/lmb_bram/ramb16bwer_27 [4:4] INPUT = lmb_bram_combined_27.mem PLACED = X3Y38;
lmb_bram/lmb_bram/ramb16bwer_28 [3:3] INPUT = lmb_bram_combined_28.mem PLACED = X3Y36;
lmb_bram/lmb_bram/ramb16bwer_29 [2:2] INPUT = lmb_bram_combined_29.mem PLACED = X2Y40;
lmb_bram/lmb_bram/ramb16bwer_30 [1:1] INPUT = lmb_bram_combined_30.mem PLACED = X3Y32;
lmb_bram/lmb_bram/ramb16bwer_31 [0:0] INPUT = lmb_bram_combined_31.mem PLACED = X2Y38;
END_BUS_BLOCK;
END_ADDRESS_SPACE;
END_ADDRESS_MAP;
projnav/xps/SDK/SDK_Workspace/demo/.cproject 0 → 100644
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projnav/xps/SDK/SDK_Workspace/demo/.project 0 → 100644
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<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>demo</name>
<comment>demobsp - microblaze_0</comment>
<projects>
<project>demobsp</project>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
<arguments>
<dictionary>
<key>?name?</key>
<value></value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.append_environment</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.autoBuildTarget</key>
<value>all</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.buildArguments</key>
<value></value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.buildCommand</key>
<value>make</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.buildLocation</key>
<value>${workspace_loc:/demo/Debug}</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.cleanBuildTarget</key>
<value>clean</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.contents</key>
<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.enableFullBuild</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.fullBuildTarget</key>
<value>all</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.stopOnError</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
<value>true</value>
</dictionary>
</arguments>
</buildCommand>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
<triggers>full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>org.eclipse.cdt.core.cnature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
<nature>org.eclipse.cdt.core.ccnature</nature>
</natures>
</projectDescription>
projnav/xps/SDK/SDK_Workspace/demo/Debug/makefile 0 → 100644
View file @ 23405448
################################################################################
# Automatically-generated file. Do not edit!
################################################################################
-include ../makefile.init
RM := rm -rf
# All of the sources participating in the build are defined here
-include sources.mk
-include subdir.mk
-include src/subdir.mk
-include objects.mk
ifneq ($(MAKECMDGOALS),clean)
ifneq ($(strip $(C_DEPS)),)
-include $(C_DEPS)
endif
ifneq ($(strip $(CC_DEPS)),)
-include $(CC_DEPS)
endif
ifneq ($(strip $(CPP_DEPS)),)
-include $(CPP_DEPS)
endif
ifneq ($(strip $(CXX_DEPS)),)
-include $(CXX_DEPS)
endif
ifneq ($(strip $(C_UPPER_DEPS)),)
-include $(C_UPPER_DEPS)
endif
ifneq ($(strip $(S_UPPER_DEPS)),)
-include $(S_UPPER_DEPS)
endif
endif
-include ../makefile.defs
# Add inputs and outputs from these tool invocations to the build variables
ELFSIZE += \
demo.elf.size \
ELFCHECK += \
demo.elf.elfcheck \
# All Target
all: demo.elf secondary-outputs
# Tool invocations
demo.elf: $(OBJS) $(USER_OBJS)
@echo Building target: $@
@echo Invoking: MicroBlaze g++ linker
mb-g++ -L../../demobsp/microblaze_0/lib -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.20.a -mno-xl-soft-mul -o"demo.elf" $(OBJS) $(USER_OBJS) $(LIBS)
@echo Finished building target: $@
@echo ' '
demo.elf.size: demo.elf
@echo Invoking: MicroBlaze Print Size
mb-size demo.elf |tee "demo.elf.size"
@echo Finished building: $@
@echo ' '
demo.elf.elfcheck: demo.elf
@echo Invoking: Xilinx ELF Check
elfcheck demo.elf -hw ../../xps_hw_platform/system.xml -pe microblaze_0 |tee "demo.elf.elfcheck"
@echo Finished building: $@
@echo ' '
# Other Targets
clean:
-$(RM) $(OBJS)$(C_DEPS)$(CC_DEPS)$(CPP_DEPS)$(EXECUTABLES)$(ELFSIZE)$(CXX_DEPS)$(C_UPPER_DEPS)$(ELFCHECK)$(S_UPPER_DEPS) demo.elf
-@echo ' '
secondary-outputs: $(ELFSIZE) $(ELFCHECK)
.PHONY: all clean dependents
.SECONDARY:
-include ../makefile.targets
projnav/xps/SDK/SDK_Workspace/demo/Debug/objects.mk 0 → 100644
View file @ 23405448
################################################################################
# Automatically-generated file. Do not edit!
################################################################################
USER_OBJS :=
LIBS :=
projnav/xps/SDK/SDK_Workspace/demo/Debug/sources.mk 0 → 100644
View file @ 23405448
################################################################################
# Automatically-generated file. Do not edit!
################################################################################
O_SRCS :=
CPP_SRCS :=
C_UPPER_SRCS :=
C_SRCS :=
LD_SRCS :=
S_UPPER_SRCS :=
S_SRCS :=
OBJ_SRCS :=
CXX_SRCS :=
CC_SRCS :=
OBJS :=
C_DEPS :=
CC_DEPS :=
CPP_DEPS :=
EXECUTABLES :=
ELFSIZE :=
CXX_DEPS :=
C_UPPER_DEPS :=
ELFCHECK :=
S_UPPER_DEPS :=
# Every subdirectory with source files must be described here
SUBDIRS := \
src \
projnav/xps/SDK/SDK_Workspace/demo/Debug/src/subdir.mk 0 → 100644
View file @ 23405448
################################################################################
# Automatically-generated file. Do not edit!
################################################################################
# Add inputs and outputs from these tool invocations to the build variables
CC_SRCS += \
../src/main.cc
OBJS += \
./src/main.o
CC_DEPS += \
./src/main.d
# Each subdirectory must supply rules for building sources it contributes
src/%.o: ../src/%.cc
@echo Building file: $<
@echo Invoking: MicroBlaze g++ compiler
mb-g++ -Wall -O0 -g3 -c -fmessage-length=0 -I../../demobsp/microblaze_0/include -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.20.a -mno-xl-soft-mul -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -o"$@" "$<"
@echo Finished building: $<
@echo ' '
projnav/xps/SDK/SDK_Workspace/demo/src/main.cc 0 → 100644
View file @ 23405448
/*
* Empty C++ Application
*/
#include <stdio.h>
#include "xil_types.h"
u32 * pSpiifcBase = (u32 *)0x85000000;
u32 * pMosiBase = (u32 *)0x85010000;
u32 * pMisoBase = (u32 *)0x85011000;
int main()
{
xil_printf("Reg0 @ 0x%08X\n", pSpiifcBase);
xil_printf("Saving word to Reg0... ");
*pSpiifcBase = 0x87654321;
xil_printf("done... verifying... ");
if (0x87654321 == *pSpiifcBase) {
xil_printf("PASS.\n");
} else {
xil_printf("FAIL. (actual=0x%08X)\n", *pSpiifcBase);
}
xil_printf("\n");
xil_printf("MOSI @ 0x%08X\n", pMosiBase);
xil_printf("Saving word to Mem0 (MOSI)...");
*pMosiBase = 0x12345678;
xil_printf("done... verifying... ");
if (0x12345678 == *pMosiBase) {
xil_printf("PASS.\n");
} else {
xil_printf("FAIL. (actual=0x%08X)\n", *pMosiBase);
}
xil_printf("\n");
xil_printf("MISO @ 0x%08X\n", pMisoBase);
xil_printf("Saving word to Mem1 (MISO)... ");
*pMisoBase = 0xFEEDFACE;
xil_printf("done... verifying... ");
if (0xFEEDFACE == *pMisoBase) {
xil_printf("PASS.\n");
} else {
xil_printf("FAIL. (actual=0x%08X)\n", *pMosiBase);
}
xil_printf("\n");
return 0;
}
projnav/xps/SDK/SDK_Workspace/demobsp/.cproject 0 → 100644
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<?fileVersion 4.0.0?>
<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
<storageModule moduleId="org.eclipse.cdt.core.settings">
<cconfiguration id="org.eclipse.cdt.core.default.config.948582058">
<storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.948582058" moduleId="org.eclipse.cdt.core.settings" name="Configuration">
<externalSettings/>
<extensions/>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
</cconfiguration>
</storageModule>
</cproject>
projnav/xps/SDK/SDK_Workspace/demobsp/.project 0 → 100644
View file @ 23405448
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>demobsp</name>
<comment></comment>
<projects>
<project>xps_hw_platform</project>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.cdt.make.core.makeBuilder</name>
<triggers>clean,full,incremental,</triggers>
<arguments>
<dictionary>
<key>org.eclipse.cdt.core.errorOutputParser</key>
<value>org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.VCErrorParser;org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.MakeErrorParser;</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.append_environment</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.build.arguments</key>
<value></value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.build.command</key>
<value>make</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.build.target.auto</key>
<value>all</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.build.target.clean</key>
<value>clean</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.build.target.inc</key>
<value>all</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
<value>false</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.enableFullBuild</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.enabledIncrementalBuild</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.environment</key>
<value></value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.stopOnError</key>
<value>false</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
<value>true</value>
</dictionary>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>com.xilinx.sdk.sw.SwProjectNature</nature>
<nature>org.eclipse.cdt.core.cnature</nature>
<nature>org.eclipse.cdt.make.core.makeNature</nature>
</natures>
</projectDescription>
projnav/xps/SDK/SDK_Workspace/demobsp/.sdkproject 0 → 100644
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THIRPARTY=false
PROCESSOR=microblaze_0
MSS_FILE=system.mss
projnav/xps/SDK/SDK_Workspace/demobsp/Makefile 0 → 100644
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# Makefile generated by Xilinx SDK.
-include libgen.options
LIBRARIES = ${PROCESSOR}/lib/libxil.a
MSS = system.mss
all: libs
@echo 'Finished building libraries'
libs: $(LIBRARIES)
$(LIBRARIES): $(MSS)
libgen -hw ${HWSPEC}\
${REPOSITORIES}\
-pe ${PROCESSOR} \
-log libgen.log \
$(MSS)
clean:
rm -rf ${PROCESSOR}
projnav/xps/SDK/SDK_Workspace/demobsp/libgen.options 0 → 100644
View file @ 23405448
PROCESSOR=microblaze_0
REPOSITORIES=
HWSPEC=../xps_hw_platform/system.xml
projnav/xps/SDK/SDK_Workspace/demobsp/system.mss 0 → 100644
View file @ 23405448
PARAMETER VERSION = 2.2.0
BEGIN OS
PARAMETER OS_NAME = standalone
PARAMETER OS_VER = 3.01.a
PARAMETER PROC_INSTANCE = microblaze_0
PARAMETER STDIN = mdm_0
PARAMETER STDOUT = mdm_0
END
BEGIN PROCESSOR
PARAMETER DRIVER_NAME = cpu
PARAMETER DRIVER_VER = 1.13.a
PARAMETER HW_INSTANCE = microblaze_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = gpio
PARAMETER DRIVER_VER = 3.00.a
PARAMETER HW_INSTANCE = DIP_Switches_8Bits
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = gpio
PARAMETER DRIVER_VER = 3.00.a
PARAMETER HW_INSTANCE = LEDs_8Bits
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = gpio
PARAMETER DRIVER_VER = 3.00.a
PARAMETER HW_INSTANCE = Push_Buttons_5Bits
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = bram
PARAMETER DRIVER_VER = 3.00.a
PARAMETER HW_INSTANCE = dlmb_cntlr
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = bram
PARAMETER DRIVER_VER = 3.00.a
PARAMETER HW_INSTANCE = ilmb_cntlr
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = uartlite
PARAMETER DRIVER_VER = 2.00.a
PARAMETER HW_INSTANCE = mdm_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = spiifc_0
END
projnav/xps/SDK/SDK_Workspace/xps_hw_platform/.project 0 → 100644
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<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>xps_hw_platform</name>
<comment></comment>
<projects>
</projects>
<buildSpec>
</buildSpec>
<natures>
<nature>com.xilinx.sdk.hw.HwProject</nature>
</natures>
</projectDescription>
projnav/xps/SDK/SDK_Workspace/xps_hw_platform/system.xml 0 → 100644
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This diff is collapsed.
projnav/xps/SDK/SDK_Workspace/xps_hw_platform/system_bd.bmm 0 → 100644
View file @ 23405448
// BMM LOC annotation file.
//
// Release 13.2 - Data2MEM O.61xd, build 2.2 May 20, 2011
// Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
///////////////////////////////////////////////////////////////////////////////
//
// Processor 'microblaze_0', ID 100, memory map.
//
///////////////////////////////////////////////////////////////////////////////
ADDRESS_MAP microblaze_0 MICROBLAZE 100
///////////////////////////////////////////////////////////////////////////////
//
// Processor 'microblaze_0' address space 'lmb_bram_combined' 0x00000000:0x0000FFFF (64 KBytes).
//
///////////////////////////////////////////////////////////////////////////////
ADDRESS_SPACE lmb_bram_combined RAMB16 [0x00000000:0x0000FFFF]
BUS_BLOCK
lmb_bram/lmb_bram/ramb16bwer_0 [31:31] INPUT = lmb_bram_combined_0.mem PLACED = X2Y46;
lmb_bram/lmb_bram/ramb16bwer_1 [30:30] INPUT = lmb_bram_combined_1.mem PLACED = X2Y50;
lmb_bram/lmb_bram/ramb16bwer_2 [29:29] INPUT = lmb_bram_combined_2.mem PLACED = X3Y46;
lmb_bram/lmb_bram/ramb16bwer_3 [28:28] INPUT = lmb_bram_combined_3.mem PLACED = X1Y40;
lmb_bram/lmb_bram/ramb16bwer_4 [27:27] INPUT = lmb_bram_combined_4.mem PLACED = X2Y48;
lmb_bram/lmb_bram/ramb16bwer_5 [26:26] INPUT = lmb_bram_combined_5.mem PLACED = X3Y44;
lmb_bram/lmb_bram/ramb16bwer_6 [25:25] INPUT = lmb_bram_combined_6.mem PLACED = X2Y44;
lmb_bram/lmb_bram/ramb16bwer_7 [24:24] INPUT = lmb_bram_combined_7.mem PLACED = X3Y42;
lmb_bram/lmb_bram/ramb16bwer_8 [23:23] INPUT = lmb_bram_combined_8.mem PLACED = X2Y36;
lmb_bram/lmb_bram/ramb16bwer_9 [22:22] INPUT = lmb_bram_combined_9.mem PLACED = X1Y34;
lmb_bram/lmb_bram/ramb16bwer_10 [21:21] INPUT = lmb_bram_combined_10.mem PLACED = X1Y32;
lmb_bram/lmb_bram/ramb16bwer_11 [20:20] INPUT = lmb_bram_combined_11.mem PLACED = X1Y36;
lmb_bram/lmb_bram/ramb16bwer_12 [19:19] INPUT = lmb_bram_combined_12.mem PLACED = X1Y30;
lmb_bram/lmb_bram/ramb16bwer_13 [18:18] INPUT = lmb_bram_combined_13.mem PLACED = X2Y30;
lmb_bram/lmb_bram/ramb16bwer_14 [17:17] INPUT = lmb_bram_combined_14.mem PLACED = X2Y28;
lmb_bram/lmb_bram/ramb16bwer_15 [16:16] INPUT = lmb_bram_combined_15.mem PLACED = X1Y28;
lmb_bram/lmb_bram/ramb16bwer_16 [15:15] INPUT = lmb_bram_combined_16.mem PLACED = X3Y28;
lmb_bram/lmb_bram/ramb16bwer_17 [14:14] INPUT = lmb_bram_combined_17.mem PLACED = X2Y32;
lmb_bram/lmb_bram/ramb16bwer_18 [13:13] INPUT = lmb_bram_combined_18.mem PLACED = X1Y38;
lmb_bram/lmb_bram/ramb16bwer_19 [12:12] INPUT = lmb_bram_combined_19.mem PLACED = X2Y34;
lmb_bram/lmb_bram/ramb16bwer_20 [11:11] INPUT = lmb_bram_combined_20.mem PLACED = X2Y26;
lmb_bram/lmb_bram/ramb16bwer_21 [10:10] INPUT = lmb_bram_combined_21.mem PLACED = X3Y30;
lmb_bram/lmb_bram/ramb16bwer_22 [9:9] INPUT = lmb_bram_combined_22.mem PLACED = X3Y26;
lmb_bram/lmb_bram/ramb16bwer_23 [8:8] INPUT = lmb_bram_combined_23.mem PLACED = X2Y24;
lmb_bram/lmb_bram/ramb16bwer_24 [7:7] INPUT = lmb_bram_combined_24.mem PLACED = X3Y34;
lmb_bram/lmb_bram/ramb16bwer_25 [6:6] INPUT = lmb_bram_combined_25.mem PLACED = X3Y40;
lmb_bram/lmb_bram/ramb16bwer_26 [5:5] INPUT = lmb_bram_combined_26.mem PLACED = X2Y42;
lmb_bram/lmb_bram/ramb16bwer_27 [4:4] INPUT = lmb_bram_combined_27.mem PLACED = X3Y38;
lmb_bram/lmb_bram/ramb16bwer_28 [3:3] INPUT = lmb_bram_combined_28.mem PLACED = X3Y36;
lmb_bram/lmb_bram/ramb16bwer_29 [2:2] INPUT = lmb_bram_combined_29.mem PLACED = X2Y40;
lmb_bram/lmb_bram/ramb16bwer_30 [1:1] INPUT = lmb_bram_combined_30.mem PLACED = X3Y32;
lmb_bram/lmb_bram/ramb16bwer_31 [0:0] INPUT = lmb_bram_combined_31.mem PLACED = X2Y38;
END_BUS_BLOCK;
END_ADDRESS_SPACE;
END_ADDRESS_MAP;
projnav/xps/__xps/ise/system.xreport
View file @ 23405448
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2012-02-28T11:11:33</DateModified>
<DateModified>2012-02-28T19:36:43</DateModified>
<ModuleName>system</ModuleName>
<SummaryTimeStamp>2012-02-28T11:11:33</SummaryTimeStamp>
<SummaryTimeStamp>2012-02-28T19:36:42</SummaryTimeStamp>
<SavedFilePath>C:/Users/mjlyons/workspace/vSPI/projnav/xps/__xps/ise/system.xreport</SavedFilePath>
<FilterFile>filter.filter</FilterFile>
<SavedFilterFilePath>C:/Users/mjlyons/workspace/vSPI/projnav/xps/__xps/ise</SavedFilterFilePath>
......
projnav/xps/__xps/system.xml
View file @ 23405448
This diff is collapsed.
projnav/xps/etc/system.filters
View file @ 23405448
......@@ -4,8 +4,8 @@
<IDENTIFICATION VERSION="1.2" XTLVERSION="1.2"/>
<SET CLASS="PROJECT" VIEW_ID="BUSINTERFACE">
<HEADERS>
<VARIABLE COL_WIDTH="50" IS_VISIBLE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="HEADER"/>
<HEADERS HSCROLL="0" VSCROLL="0">
<VARIABLE COL_INDEX="0" COL_WIDTH="447" IS_VISIBLE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="HEADER"/>
</HEADERS>
<SET CLASS="FILTER_GROUP" ID="By Connection" IS_EXPANDED="TRUE">
<VARIABLE NAME="By Connection" VALUE="By Connection" VIEWDISP="Bus Interface Filters" VIEWTYPE="STATIC"/>
......@@ -97,8 +97,8 @@
</SET>
<SET CLASS="PROJECT" VIEW_ID="PORT">
<HEADERS>
<VARIABLE COL_WIDTH="50" IS_VISIBLE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="HEADER"/>
<HEADERS HSCROLL="0" VSCROLL="0">
<VARIABLE COL_INDEX="0" COL_WIDTH="376" IS_VISIBLE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="HEADER"/>
</HEADERS>
<SET CLASS="FILTER_GROUP" ID="By Interface" IS_EXPANDED="TRUE">
<VARIABLE NAME="By Interface" VALUE="By Interface" VIEWDISP="Port Filters" VIEWTYPE="STATIC"/>
......
projnav/xps/etc/system.gui
View file @ 23405448
......@@ -9,11 +9,12 @@
<VARIABLE COL_INDEX="1" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Bus Name" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="2" IS_VISIBLE="FALSE" VIEWDISP="Bus Standard" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="3" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="4" COL_WIDTH="642" IS_VISIBLE="TRUE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="4" COL_WIDTH="813" IS_VISIBLE="TRUE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="5" IS_VISIBLE="FALSE" VIEWDISP="IP Classification" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="6" IS_VISIBLE="FALSE" VIEWDISP="Type" VIEWTYPE="HEADER"/>
</HEADERS>
<SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="180,450,180" VERSION="0"/>
<SET ID="spiifc_0" IS_EXPANDED="TRUE"/>
<STATUS>
<SELECTIONS/>
</STATUS>
......@@ -25,12 +26,13 @@
<VARIABLE ID="dlmb_cntlr" ROW_INDEX="5"/>
<VARIABLE ID="ilmb_cntlr" ROW_INDEX="6"/>
<VARIABLE ID="lmb_bram" ROW_INDEX="4"/>
<VARIABLE ID="DIP_Switches_8Bits" ROW_INDEX="8"/>
<VARIABLE ID="LEDs_8Bits" ROW_INDEX="9"/>
<VARIABLE ID="Push_Buttons_5Bits" ROW_INDEX="10"/>
<VARIABLE ID="clock_generator_0" ROW_INDEX="11"/>
<VARIABLE ID="mdm_0" ROW_INDEX="7"/>
<VARIABLE ID="proc_sys_reset_0" ROW_INDEX="12"/>
<VARIABLE ID="DIP_Switches_8Bits" ROW_INDEX="9"/>
<VARIABLE ID="LEDs_8Bits" ROW_INDEX="10"/>
<VARIABLE ID="Push_Buttons_5Bits" ROW_INDEX="11"/>
<VARIABLE ID="clock_generator_0" ROW_INDEX="12"/>
<VARIABLE ID="mdm_0" ROW_INDEX="8"/>
<VARIABLE ID="proc_sys_reset_0" ROW_INDEX="13"/>
<VARIABLE ID="spiifc_0" IS_EXPANDED="TRUE" ROW_INDEX="7"/>
</SEQUENCES>
</SET>
......@@ -76,20 +78,41 @@
</SET>
<SET CLASS="PROJECT" DISPLAYMODE="TREE" VIEW_ID="PORT">
<HEADERS>
<VARIABLE COL_INDEX="0" IS_VISIBLE="TRUE" VIEWDISP="Name" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="1" IS_VISIBLE="TRUE" VIEWDISP="Net" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="2" IS_VISIBLE="TRUE" VIEWDISP="Direction" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="3" IS_VISIBLE="TRUE" VIEWDISP="Range" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="4" IS_VISIBLE="TRUE" VIEWDISP="Class" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="5" IS_VISIBLE="TRUE" VIEWDISP="Frequency(Hz)" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="6" IS_VISIBLE="TRUE" VIEWDISP="Reset Polarity" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="7" IS_VISIBLE="TRUE" VIEWDISP="Sensitivity" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="8" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
<HEADERS HSCROLL="0" VSCROLL="0">
<VARIABLE COL_INDEX="0" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Name" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="1" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Net" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="2" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Direction" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="3" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Range" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="4" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Class" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="5" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Frequency(Hz)" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="6" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Reset Polarity" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="7" COL_WIDTH="413" IS_VISIBLE="TRUE" VIEWDISP="Sensitivity" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="8" COL_WIDTH="213" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="9" IS_VISIBLE="FALSE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="10" IS_VISIBLE="TRUE" VIEWDISP="IP Classification" VIEWTYPE="HEADER"/>
</HEADERS>
<SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="0,630,180" VERSION="0"/>
<SET ID="spiifc_0" IS_EXPANDED="TRUE"/>
<STATUS>
<SELECTIONS/>
</STATUS>
<SEQUENCES IS_DEF_SEQUENCES="TRUE">
<VARIABLE ID="ExternalPorts" ROW_INDEX="0"/>
<VARIABLE ID="microblaze_0" ROW_INDEX="4"/>
<VARIABLE ID="mb_plb" ROW_INDEX="3"/>
<VARIABLE ID="ilmb" ROW_INDEX="2"/>
<VARIABLE ID="dlmb" ROW_INDEX="1"/>
<VARIABLE ID="dlmb_cntlr" ROW_INDEX="6"/>
<VARIABLE ID="ilmb_cntlr" ROW_INDEX="7"/>
<VARIABLE ID="lmb_bram" ROW_INDEX="5"/>
<VARIABLE ID="DIP_Switches_8Bits" ROW_INDEX="10"/>
<VARIABLE ID="LEDs_8Bits" ROW_INDEX="11"/>
<VARIABLE ID="Push_Buttons_5Bits" ROW_INDEX="12"/>
<VARIABLE ID="clock_generator_0" ROW_INDEX="13"/>
<VARIABLE ID="mdm_0" ROW_INDEX="9"/>
<VARIABLE ID="proc_sys_reset_0" ROW_INDEX="14"/>
<VARIABLE ID="spiifc_0" IS_EXPANDED="TRUE" ROW_INDEX="8"/>
</SEQUENCES>
</SET>
<SET CLASS="PROJECT" DISPLAYMODE="FOCUS_TREE" VIEW_ID="PORT">
......@@ -159,12 +182,16 @@
<VARIABLE COL_INDEX="8" IS_VISIBLE="FALSE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="10" IS_VISIBLE="FALSE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="7" IS_VISIBLE="FALSE" VIEWDISP="Address Type" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="9" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Lock" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="9" COL_WIDTH="894" IS_VISIBLE="TRUE" VIEWDISP="Lock" VIEWTYPE="HEADER"/>
</HEADERS>
<SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="0,630,180" VERSION="0"/>
<SET ID="microblaze_0" IS_EXPANDED="TRUE"/>
<STATUS IS_EXPANDED="TRUE">
<STATUS>
<SELECTIONS/>
</STATUS>
<SEQUENCES IS_DEF_SEQUENCES="TRUE">
<VARIABLE ID="microblaze_0" IS_EXPANDED="TRUE" ROW_INDEX="0"/>
</SEQUENCES>
</SET>
<SET CLASS="PROJECT" DISPLAYMODE="FLAT" VIEW_ID="ADDRESS">
......
projnav/xps/implementation/system_summary.html
View file @ 23405448
......@@ -31,11 +31,7 @@
<TR ALIGN=LEFT><TD>Platgen Log File</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Simgen Log File</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>BitInit Log File</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/mjlyons/workspace/vSPI/projnav/xps\system.log'>System Log File</A></TD><TD>Tue Feb 28 11:11:32 2012</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>XPS Synthesis Summary (estimated values)</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=EDKSynthesisSumary"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report</B></TD><TD><B>Generated</B></TD><TD><B>Flip Flops Used</B></TD><TD><B>LUTs Used</B></TD><TD><B>BRAMS Used</B></TD><TD COLSPAN='2'><B>Errors</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/mjlyons/workspace/vSPI/projnav/xps\system.log'>System Log File</A></TD><TD>Tue Feb 28 19:37:57 2012</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
</TABLE>
......@@ -61,5 +57,5 @@
</TABLE>
<br><center><b>Date Generated:</b> 02/28/2012 - 11:11:33</center>
<br><center><b>Date Generated:</b> 02/28/2012 - 19:37:57</center>
</BODY></HTML>
\ No newline at end of file
projnav/xps/pcores/spiifc.prj 0 → 100644
View file @ 23405448
vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v3_00_a\hdl\vhdl\proc_common_pkg.vhd"
vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v3_00_a\hdl\vhdl\or_muxcy.vhd"
vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v3_00_a\hdl\vhdl\family_support.vhd"
vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v3_00_a\hdl\vhdl\pselect_f.vhd"
vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v3_00_a\hdl\vhdl\or_gate128.vhd"
vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v3_00_a\hdl\vhdl\ipif_pkg.vhd"
vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v3_00_a\hdl\vhdl\counter_f.vhd"
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_slave_burst_v1_01_a\hdl\vhdl\flex_addr_cntr.vhd"
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_slave_burst_v1_01_a\hdl\vhdl\wr_buffer.vhd"
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_slave_burst_v1_01_a\hdl\vhdl\plb_address_decoder.vhd"
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_slave_burst_v1_01_a\hdl\vhdl\burst_support.vhd"
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_slave_burst_v1_01_a\hdl\vhdl\be_reset_gen.vhd"
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_slave_burst_v1_01_a\hdl\vhdl\addr_reg_cntr_brst_flex.vhd"
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_slave_burst_v1_01_a\hdl\vhdl\plb_slave_attachment.vhd"
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_slave_burst_v1_01_a\hdl\vhdl\data_mirror_128.vhd"
verilog spiifc_v1_00_a "C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav\ipcore_dir\buffermem.v"
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_slave_burst_v1_01_a\hdl\vhdl\plbv46_slave_burst.vhd"
vhdl interrupt_control_v2_01_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\interrupt_control_v2_01_a\hdl\vhdl\interrupt_control.vhd"
verilog spiifc_v1_00_a "C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\hdl\verilog\user_logic.v"
vhdl spiifc_v1_00_a "C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\hdl\vhdl\spiifc.vhd"
projnav/xps/pcores/spiifc_v1_00_a/data/spiifc_v2_1_0.bbd 0 → 100644
View file @ 23405448
##############################################################################
## Filename: C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores/spiifc_v1_00_a/data/spiifc_v2_1_0.bbd
## Description: Black Box Definition
## Date: Tue Feb 28 16:31:09 2012 (by Create and Import Peripheral Wizard)
##############################################################################
Files
################################################################################
buffermem.ngc
projnav/xps/pcores/spiifc_v1_00_a/data/spiifc_v2_1_0.mpd
View file @ 23405448
......@@ -13,31 +13,31 @@ OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = MIXED
OPTION IP_GROUP = MICROBLAZE:PPC:USER
OPTION DESC = SPIIFC
OPTION ARCH_SUPPORT_MAP = (others=DEVELOPMENT)
OPTION STYLE = MIX
OPTION RUN_NGCBUILD = TRUE
## Bus Interfaces
BUS_INTERFACE BUS = SPLB, BUS_STD = PLBV46, BUS_TYPE = SLAVE
## Generics for VHDL or Parameters for Verilog
PARAMETER C_BASEADDR = 0xffffffff, DT = std_logic_vector, MIN_SIZE = 0x200, PAIR = C_HIGHADDR, ADDRESS = BASE, BUS = SPLB
PARAMETER C_BASEADDR = 0xffffffff, DT = std_logic_vector, PAIR = C_HIGHADDR, ADDRESS = BASE, BUS = SPLB
PARAMETER C_HIGHADDR = 0x00000000, DT = std_logic_vector, PAIR = C_BASEADDR, ADDRESS = HIGH, BUS = SPLB
PARAMETER C_SPLB_AWIDTH = 32, DT = INTEGER, BUS = SPLB, ASSIGNMENT = CONSTANT
PARAMETER C_SPLB_DWIDTH = 128, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128)
PARAMETER C_SPLB_NUM_MASTERS = 8, DT = INTEGER, BUS = SPLB, RANGE = (1:16)
PARAMETER C_SPLB_MID_WIDTH = 3, DT = INTEGER, BUS = SPLB, RANGE = (1:4)
PARAMETER C_SPLB_NATIVE_DWIDTH = 32, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128), ASSIGNMENT = CONSTANT
PARAMETER C_SPLB_P2P = 0, DT = INTEGER, BUS = SPLB, RANGE = (0, 1)
PARAMETER C_SPLB_SUPPORT_BURSTS = 1, DT = INTEGER, BUS = SPLB, RANGE = (0, 1), ASSIGNMENT = CONSTANT
PARAMETER C_SPLB_SMALLEST_MASTER = 32, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128)
PARAMETER C_SPLB_AWIDTH = 32, DT = INTEGER, BUS = SPLB
PARAMETER C_SPLB_DWIDTH = 128, DT = INTEGER, BUS = SPLB
PARAMETER C_SPLB_NUM_MASTERS = 8, DT = INTEGER, BUS = SPLB
PARAMETER C_SPLB_MID_WIDTH = 3, DT = INTEGER, BUS = SPLB
PARAMETER C_SPLB_NATIVE_DWIDTH = 32, DT = INTEGER, BUS = SPLB
PARAMETER C_SPLB_P2P = 0, DT = INTEGER, BUS = SPLB
PARAMETER C_SPLB_SUPPORT_BURSTS = 1, DT = INTEGER, BUS = SPLB
PARAMETER C_SPLB_SMALLEST_MASTER = 32, DT = INTEGER, BUS = SPLB
PARAMETER C_SPLB_CLK_PERIOD_PS = 10000, DT = INTEGER, BUS = SPLB
PARAMETER C_INCLUDE_DPHASE_TIMER = 1, DT = INTEGER, RANGE = (0, 1)
PARAMETER C_INCLUDE_DPHASE_TIMER = 1, DT = INTEGER
PARAMETER C_FAMILY = virtex6, DT = STRING
PARAMETER C_MEM0_BASEADDR = 0xffffffff, DT = std_logic_vector, PAIR = C_MEM0_HIGHADDR, ADDRESS = BASE, BUS = SPLB
PARAMETER C_MEM0_HIGHADDR = 0x00000000, DT = std_logic_vector, PAIR = C_MEM0_BASEADDR, ADDRESS = HIGH, BUS = SPLB
PARAMETER C_MEM1_BASEADDR = 0xffffffff, DT = std_logic_vector, PAIR = C_MEM1_HIGHADDR, ADDRESS = BASE, BUS = SPLB
PARAMETER C_MEM1_HIGHADDR = 0x00000000, DT = std_logic_vector, PAIR = C_MEM1_BASEADDR, ADDRESS = HIGH, BUS = SPLB
PARAMETER C_MEM0_BASEADDR = 0xffffffff, DT = std_logic_vector, PAIR = C_MEM0_HIGHADDR, ADDRESS = BASE, BUS = SPLB, ADDR_TYPE = MEMORY
PARAMETER C_MEM0_HIGHADDR = 0x00000000, DT = std_logic_vector, PAIR = C_MEM0_BASEADDR, ADDRESS = HIGH, BUS = SPLB, ADDR_TYPE = MEMORY
PARAMETER C_MEM1_BASEADDR = 0xffffffff, DT = std_logic_vector, PAIR = C_MEM1_HIGHADDR, ADDRESS = BASE, BUS = SPLB, ADDR_TYPE = MEMORY
PARAMETER C_MEM1_HIGHADDR = 0x00000000, DT = std_logic_vector, PAIR = C_MEM1_BASEADDR, ADDRESS = HIGH, BUS = SPLB, ADDR_TYPE = MEMORY
## Ports
PORT SPLB_Clk = "", DIR = I, SIGIS = CLK, BUS = SPLB
......
projnav/xps/pcores/spiifc_v1_00_a/data/spiifc_v2_1_0.pao
View file @ 23405448
##############################################################################
## Filename: C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/data/spiifc_v2_1_0.pao
## Filename: C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores/spiifc_v1_00_a/data/spiifc_v2_1_0.pao
## Description: Peripheral Analysis Order
## Date: Tue Feb 28 11:11:15 2012 (by Create and Import Peripheral Wizard)
## Date: Tue Feb 28 16:31:09 2012 (by Create and Import Peripheral Wizard)
##############################################################################
lib proc_common_v3_00_a all
lib plbv46_slave_burst_v1_01_a all
lib interrupt_control_v2_01_a all
lib proc_common_v3_00_a proc_common_pkg vhdl
lib proc_common_v3_00_a or_muxcy vhdl
lib proc_common_v3_00_a family_support vhdl
lib proc_common_v3_00_a pselect_f vhdl
lib proc_common_v3_00_a or_gate128 vhdl
lib proc_common_v3_00_a ipif_pkg vhdl
lib proc_common_v3_00_a counter_f vhdl
lib plbv46_slave_burst_v1_01_a flex_addr_cntr vhdl
lib plbv46_slave_burst_v1_01_a wr_buffer vhdl
lib plbv46_slave_burst_v1_01_a plb_address_decoder vhdl
lib plbv46_slave_burst_v1_01_a burst_support vhdl
lib plbv46_slave_burst_v1_01_a be_reset_gen vhdl
lib plbv46_slave_burst_v1_01_a addr_reg_cntr_brst_flex vhdl
lib plbv46_slave_burst_v1_01_a plb_slave_attachment vhdl
lib plbv46_slave_burst_v1_01_a data_mirror_128 vhdl
lib spiifc_v1_00_a buffermem verilog
lib plbv46_slave_burst_v1_01_a plbv46_slave_burst vhdl
lib interrupt_control_v2_01_a interrupt_control vhdl
lib spiifc_v1_00_a user_logic verilog
lib spiifc_v1_00_a spiifc vhdl
projnav/xps/pcores/spiifc_v1_00_a/devl/ipwiz.log deleted 100644 → 0
View file @ 7133e87e
This diff is collapsed.
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/_xmsgs/cg.xmsgs 0 → 100644
View file @ 23405448
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="sim" num="0" delta="new" >Generating component instance &apos;<arg fmt="%s" index="1">buffermem</arg>&apos; of &apos;<arg fmt="%s" index="2">xilinx.com:ip:blk_mem_gen:6.2</arg>&apos; from &apos;<arg fmt="%s" index="3">C:\Xilinx\13.2\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\blk_mem_gen_v6_2\component.xml</arg>&apos;.
</msg>
<msg type="warning" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Can&apos;t find &apos;Verilog&apos; synthesis view; using general synthesis view</arg>
</msg>
<msg type="info" file="sim" num="0" delta="new" ><arg fmt="%s" index="1">Pre-processing HDL files for &apos;buffermem&apos;...</arg>
</msg>
<msg type="info" file="sim" num="0" delta="new" >Finished FLIST file generation.
</msg>
</messages>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/_xmsgs/pn_parser.xmsgs → projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/_xmsgs/pn_parser.xmsgs
View file @ 23405448
......@@ -8,7 +8,7 @@
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v2_01_a/hdl/vhdl/interrupt_control.vhd&quot; into library interrupt_control_v2_01_a</arg>
<msg type="info" file="ProjectMgmt" num="1769" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem.v\&quot; into library work</arg>
</msg>
</messages>
......
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/blk_mem_gen_v6_2_readme.txt 0 → 100644
View file @ 23405448
Core name: Xilinx LogiCORE Block Memory Generator
Version: 6.2
Release Date: June 22, 2011
================================================================================
This document contains the following sections:
1. Introduction
2. New Features
3. Supported Devices
4. Resolved Issues
5. Known Issues
6. Technical Support
7. Core Release History
8. Legal Disclaimer
================================================================================
1. INTRODUCTION
For installation instructions for this release, please go to:
http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
For system requirements:
http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
This file contains release notes for the Xilinx LogiCORE IP Block Memory Generator v6.2
solution. For the latest core updates, see the product page at:
http://www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm
2. NEW FEATURES
- ISE 13.2 software support
- Virtex-7L, Kintex-7L, Artix-7* and Zynq-7000* device support
3. SUPPORTED DEVICES
The following device families are supported by the core for this release.
Zynq-7000*
Virtex-7
Virtex-7 XT (7vx485t)
Virtex-7 -2L
Kintex-7
Kintex-7 -2L
Artix-7*
Virtex-6 XC CXT/LXT/SXT/HXT
Virtex-6 XQ LXT/SXT
Virtex-6 -1L XQ LXT/SXT
Spartan-6 XC LX/LXT
Spartan-6 XA
Spartan-6 XQ LX/LXT
Spartan-6 -1L XQ LX
Virtex-5 XC LX/LXT/SXT/TXT/FXT
Virtex-5 XQ LX/ LXT/SXT/FXT
Virtex-4 XC LX/SX/FX
Virtex-4 XQ LX/SX/FX
Virtex-4 XQR LX/SX/FX
Spartan-3 XC
Spartan-3 XA
Spartan-3A XC 3A / 3A DSP / 3AN DSP
Spartan-3A XA 3A / 3A DSP
Spartan-3E XC
Spartan-3E XA
*To access these devices in the ISE Design Suite, contact your Xilinx FAE.
4. RESOLVED ISSUES
The following issues are resolved in Block Memory Generator v6.2:
1. Core errors in NGDBuild when the depth is too large (especially for Spartan-6 devices)
Version Fixed: v6.2
- CR 587481
- AR 39718
5. KNOWN ISSUES
The following are known issues for v6.2 of this core at time of release:
1. Virtex-6 and Spartan-6: BRAM Memory collision error, when the user selects TDP (write_mode= Read First)
Work around: The user must review the possible scenarios that causes the collission and revise
their design to avoid those situations.
- CR588505
Note: Refer to UG383, 'Conflict Avoidance' section when using TDP Memory - with
Write Mode = Read First in conjunction with asynchronous clocking
2. Power estimation figures in the datasheet are preliminary for Virtex-5 and Spartan-3.
3. Core does not generate for large memories. Depending on the
machine the ISE CORE Generator software runs on, the maximum size of the memory that
can be generated will vary. For example, a Dual Pentium-4 server
with 2 GB RAM can generate a memory core of size 1.8 MBits or 230 KBytes
- CR 415768
- AR 24034
The most recent information, including known issues, workarounds, and resolutions for
this version is provided in the IP Release Notes User Guide located at
www.xilinx.com/support/documentation/user_guides/xtp025.pdf
6. TECHNICAL SUPPORT
To obtain technical support, create a WebCase at www.xilinx.com/support.
Questions are routed to a team with expertise using this product.
Xilinx provides technical support for use of this product when used
according to the guidelines described in the core documentation, and
cannot guarantee timing, functionality, or support of this product for
designs that do not follow specified guidelines.
7. CORE RELEASE HISTORY
Date By Version Description
================================================================================
06/22/2011 Xilinx, Inc. 6.2 ISE 13.2 support;Virtex-7L,Kintex-7L,Artix7 and Zynq-7000* device support;
03/01/2011 Xilinx, Inc. 6.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; AXI4/AXI4-Lite Support
09/21/2010 Xilinx, Inc. 4.3 ISE 12.3 support
07/23/2010 Xilinx, Inc. 4.2 ISE 12.2 support
04/19/2010 Xilinx, Inc. 4.1 ISE 12.1 support
03/09/2010 Xilinx, Inc. 3.3 rev 2 Fix for V6 Memory collision issue
12/02/2009 Xilinx, Inc. 3.3 rev 1 ISE 11.4 support; Spartan-6 Low Power
Device support; Automotive Spartan 3A
DSP device support
09/16/2009 Xilinx, Inc. 3.3 Revised to v3.3
06/24/2009 Xilinx, Inc. 3.2 Revised to v3.2
04/24/2009 Xilinx, Inc. 3.1 Revised to v3.1
09/19/2008 Xilinx, Inc. 2.8 Revised to v2.8
03/24/2008 Xilinx, Inc. 2.7 10.1 support; Revised to v2.7
10/03/2007 Xilinx, Inc. 2.6 Revised to v2.6
07/2007 Xilinx, Inc. 2.5 Revised to v2.5
04/2007 Xilinx, Inc. 2.4 Revised to v2.4 rev 1
02/2007 Xilinx, Inc. 2.4 Revised to v2.4
11/2006 Xilinx, Inc. 2.3 Revised to v2.3
09/2006 Xilinx, Inc. 2.2 Revised to v2.2
06/2006 Xilinx, Inc. 2.1 Revised to v2.1
01/2006 Xilinx, Inc. 1.1 Initial release
================================================================================
8. Legal Disclaimer
(c) Copyright 2006 - 2011 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or Xilinx had been advised of the
possibility of the same.
CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of Xilinx products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem.asy 0 → 100644
View file @ 23405448
Version 4
SymbolType BLOCK
TEXT 32 32 LEFT 4 buffermem
RECTANGLE Normal 32 32 544 1376
LINE Wide 0 80 32 80
PIN 0 80 LEFT 36
PINATTR PinName addra[11:0]
PINATTR Polarity IN
LINE Wide 0 112 32 112
PIN 0 112 LEFT 36
PINATTR PinName dina[7:0]
PINATTR Polarity IN
LINE Normal 0 144 32 144
PIN 0 144 LEFT 36
PINATTR PinName ena
PINATTR Polarity IN
LINE Wide 0 208 32 208
PIN 0 208 LEFT 36
PINATTR PinName wea[0:0]
PINATTR Polarity IN
LINE Normal 0 272 32 272
PIN 0 272 LEFT 36
PINATTR PinName clka
PINATTR Polarity IN
LINE Wide 0 432 32 432
PIN 0 432 LEFT 36
PINATTR PinName addrb[9:0]
PINATTR Polarity IN
LINE Wide 0 464 32 464
PIN 0 464 LEFT 36
PINATTR PinName dinb[31:0]
PINATTR Polarity IN
LINE Normal 0 496 32 496
PIN 0 496 LEFT 36
PINATTR PinName enb
PINATTR Polarity IN
LINE Wide 0 560 32 560
PIN 0 560 LEFT 36
PINATTR PinName web[0:0]
PINATTR Polarity IN
LINE Normal 0 624 32 624
PIN 0 624 LEFT 36
PINATTR PinName clkb
PINATTR Polarity IN
LINE Wide 576 80 544 80
PIN 576 80 RIGHT 36
PINATTR PinName douta[7:0]
PINATTR Polarity OUT
LINE Wide 576 368 544 368
PIN 576 368 RIGHT 36
PINATTR PinName doutb[31:0]
PINATTR Polarity OUT
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem.gise 0 → 100644
View file @ 23405448
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="buffermem.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="blk_mem_gen_v6_2_readme.txt" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_ASY" xil_pn:name="buffermem.asy" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="buffermem.sym" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VEO" xil_pn:name="buffermem.veo" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
</generated_project>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem.sym 0 → 100644
View file @ 23405448
<?xml version="1.0" encoding="UTF-8"?>
<symbol version="7" name="buffermem">
<symboltype>BLOCK</symboltype>
<timestamp>2012-2-28T17:6:39</timestamp>
<pin polarity="Input" x="0" y="80" name="addra[11:0]" />
<pin polarity="Input" x="0" y="112" name="dina[7:0]" />
<pin polarity="Input" x="0" y="144" name="ena" />
<pin polarity="Input" x="0" y="208" name="wea[0:0]" />
<pin polarity="Input" x="0" y="272" name="clka" />
<pin polarity="Input" x="0" y="432" name="addrb[9:0]" />
<pin polarity="Input" x="0" y="464" name="dinb[31:0]" />
<pin polarity="Input" x="0" y="496" name="enb" />
<pin polarity="Input" x="0" y="560" name="web[0:0]" />
<pin polarity="Input" x="0" y="624" name="clkb" />
<pin polarity="Output" x="576" y="80" name="douta[7:0]" />
<pin polarity="Output" x="576" y="368" name="doutb[31:0]" />
<graph>
<text style="fontsize:40;fontname:Arial" x="32" y="32">buffermem</text>
<rect width="512" x="32" y="32" height="1344" />
<line x2="32" y1="80" y2="80" style="linewidth:W" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="80" type="pin addra[11:0]" />
<line x2="32" y1="112" y2="112" style="linewidth:W" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="112" type="pin dina[7:0]" />
<line x2="32" y1="144" y2="144" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="144" type="pin ena" />
<line x2="32" y1="208" y2="208" style="linewidth:W" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="208" type="pin wea[0:0]" />
<line x2="32" y1="272" y2="272" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="272" type="pin clka" />
<line x2="32" y1="432" y2="432" style="linewidth:W" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="432" type="pin addrb[9:0]" />
<line x2="32" y1="464" y2="464" style="linewidth:W" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="464" type="pin dinb[31:0]" />
<line x2="32" y1="496" y2="496" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="496" type="pin enb" />
<line x2="32" y1="560" y2="560" style="linewidth:W" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="560" type="pin web[0:0]" />
<line x2="32" y1="624" y2="624" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="624" type="pin clkb" />
<line x2="544" y1="80" y2="80" style="linewidth:W" x1="576" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="80" type="pin douta[7:0]" />
<line x2="544" y1="368" y2="368" style="linewidth:W" x1="576" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="368" type="pin doutb[31:0]" />
</graph>
</symbol>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem.v 0 → 100644
View file @ 23405448
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2012 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file buffermem.v when simulating
// the core, buffermem. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module buffermem(
clka,
ena,
wea,
addra,
dina,
douta,
clkb,
enb,
web,
addrb,
dinb,
doutb
);
input clka;
input ena;
input [0 : 0] wea;
input [11 : 0] addra;
input [7 : 0] dina;
output [7 : 0] douta;
input clkb;
input enb;
input [0 : 0] web;
input [9 : 0] addrb;
input [31 : 0] dinb;
output [31 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V6_2 #(
.C_ADDRA_WIDTH(12),
.C_ADDRB_WIDTH(10),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("spartan6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(1),
.C_HAS_ENB(1),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(2),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(4096),
.C_READ_DEPTH_B(1024),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(32),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(4096),
.C_WRITE_DEPTH_B(1024),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(32),
.C_XDEVICEFAMILY("spartan6")
)
inst (
.CLKA(clka),
.ENA(ena),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.CLKB(clkb),
.ENB(enb),
.WEB(web),
.ADDRB(addrb),
.DINB(dinb),
.DOUTB(doutb),
.RSTA(),
.REGCEA(),
.RSTB(),
.REGCEB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem.veo 0 → 100644
View file @ 23405448
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2012 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
/*******************************************************************************
* Generated from core with identifier: xilinx.com:ip:blk_mem_gen:6.2 *
* *
* The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port *
* Block Memory and Single Port Block Memory LogiCOREs, but is not a *
* direct drop-in replacement. It should be used in all new Xilinx *
* designs. The core supports RAM and ROM functions over a wide range of *
* widths and depths. Use this core to generate block memories with *
* symmetric or asymmetric read and write port widths, as well as cores *
* which can perform simultaneous write operations to separate *
* locations, and simultaneous read operations from the same location. *
* For more information on differences in interface and feature support *
* between this core and the Dual Port Block Memory and Single Port *
* Block Memory LogiCOREs, please consult the data sheet. *
*******************************************************************************/
// Interfaces:
// AXI_SLAVE_S_AXI
// AXILite_SLAVE_S_AXI
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
buffermem your_instance_name (
.clka(clka), // input clka
.ena(ena), // input ena
.wea(wea), // input [0 : 0] wea
.addra(addra), // input [11 : 0] addra
.dina(dina), // input [7 : 0] dina
.douta(douta), // output [7 : 0] douta
.clkb(clkb), // input clkb
.enb(enb), // input enb
.web(web), // input [0 : 0] web
.addrb(addrb), // input [9 : 0] addrb
.dinb(dinb), // input [31 : 0] dinb
.doutb(doutb) // output [31 : 0] doutb
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file buffermem.v when simulating
// the core, buffermem. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem.xco 0 → 100644
View file @ 23405448
##############################################################
#
# Xilinx Core Generator version 13.2
# Date: Tue Feb 28 17:05:52 2012
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:blk_mem_gen:6.2
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc6slx45
SET devicefamily = spartan6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = csg324
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.2
# END Select
# BEGIN Parameters
CSET additional_inputs_for_power_estimation=false
CSET algorithm=Minimum_Area
CSET assume_synchronous_clk=true
CSET axi_id_width=4
CSET axi_slave_type=Memory_Slave
CSET axi_type=AXI4_Full
CSET byte_size=9
CSET coe_file=no_coe_file_loaded
CSET collision_warnings=ALL
CSET component_name=buffermem
CSET disable_collision_warnings=false
CSET disable_out_of_range_warnings=false
CSET ecc=false
CSET ecctype=No_ECC
CSET enable_a=Use_ENA_Pin
CSET enable_b=Use_ENB_Pin
CSET error_injection_type=Single_Bit_Error_Injection
CSET fill_remaining_memory_locations=false
CSET interface_type=Native
CSET load_init_file=false
CSET memory_type=True_Dual_Port_RAM
CSET operating_mode_a=WRITE_FIRST
CSET operating_mode_b=WRITE_FIRST
CSET output_reset_value_a=0
CSET output_reset_value_b=0
CSET pipeline_stages=0
CSET port_a_clock=100
CSET port_a_enable_rate=100
CSET port_a_write_rate=50
CSET port_b_clock=100
CSET port_b_enable_rate=100
CSET port_b_write_rate=50
CSET primitive=8kx2
CSET read_width_a=8
CSET read_width_b=32
CSET register_porta_input_of_softecc=false
CSET register_porta_output_of_memory_core=false
CSET register_porta_output_of_memory_primitives=false
CSET register_portb_output_of_memory_core=false
CSET register_portb_output_of_memory_primitives=false
CSET register_portb_output_of_softecc=false
CSET remaining_memory_locations=0
CSET reset_memory_latch_a=false
CSET reset_memory_latch_b=false
CSET reset_priority_a=CE
CSET reset_priority_b=CE
CSET reset_type=SYNC
CSET softecc=false
CSET use_axi_id=false
CSET use_byte_write_enable=false
CSET use_error_injection_pins=false
CSET use_regcea_pin=false
CSET use_regceb_pin=false
CSET use_rsta_pin=false
CSET use_rstb_pin=false
CSET write_depth_a=4096
CSET write_width_a=8
CSET write_width_b=32
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2011-03-11T08:24:14.000Z
# END Extra information
GENERATE
# CRC: 1fb28621
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem.xise 0 → 100644
View file @ 23405448
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="13.2" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="buffermem.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="buffermem.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="5"/>
</file>
</files>
<properties>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx45" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|buffermem" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="buffermem.ngc" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/buffermem" xil_pn:valueState="non-default"/>
<property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="non-default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_DesignName" xil_pn:value="buffermem" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-02-28T12:06:44" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="154A8C82339948B49E3C581C44A6E851" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem_flist.txt 0 → 100644
View file @ 23405448
# Output products list for <buffermem>
blk_mem_gen_ds512.pdf
blk_mem_gen_v6_2_readme.txt
buffermem.asy
buffermem.gise
buffermem.ngc
buffermem.sym
buffermem.v
buffermem.veo
buffermem.xco
buffermem.xise
buffermem_flist.txt
buffermem_ste\example_design\bmg_wrapper.vhd
buffermem_ste\example_design\buffermem_top.ucf
buffermem_ste\example_design\buffermem_top.vhd
buffermem_ste\example_design\buffermem_top.xdc
buffermem_ste\implement\implement.sh
buffermem_ste\implement\planAhead_rdn.bat
buffermem_ste\implement\planAhead_rdn.sh
buffermem_ste\implement\planAhead_rdn.tcl
buffermem_ste\implement\xst.prj
buffermem_ste\implement\xst.scr
buffermem_xmdf.tcl
summary.log
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem_ste/example_design/buffermem_top.ucf 0 → 100644
View file @ 23405448
################################################################################
#
# (c) Copyright 2002 - 2010 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
################################################################################
# Tx Core Period Constraint. This constraint can be modified, and is
# valid as long as it is met after place and route.
NET "CLKA" TNM_NET = "CLKA";
NET "CLKB" TNM_NET = "CLKB";
TIMESPEC "TS_CLKA" = PERIOD "CLKA" 25 MHZ;
TIMESPEC "TS_CLKB" = PERIOD "CLKB" 25 MHZ;
################################################################################
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem_ste/example_design/buffermem_top.vhd 0 → 100644
View file @ 23405448
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v6.2 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_wrapper.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY buffermem_top IS
PORT (
--Inputs - Port A
ENA : IN STD_LOGIC; --opt port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
ENB : IN STD_LOGIC; --opt port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END buffermem_top;
ARCHITECTURE xilinx OF buffermem_top IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT buffermem IS
PORT (
--Port A
ENA : IN STD_LOGIC; --opt port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
ENB : IN STD_LOGIC; --opt port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bufg_B : BUFG
PORT MAP (
I => CLKB,
O => CLKB_buf
);
bmg0 : buffermem
PORT MAP (
--Port A
ENA => ENA,
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf,
--Port B
ENB => ENB,
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
CLKB => CLKB_buf
);
END xilinx;
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem_ste/example_design/buffermem_top.xdc 0 → 100644
View file @ 23405448
################################################################################
#
# (c) Copyright 2002 - 2011 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
################################################################################
# Core Period Constraint. This constraint can be modified, and is
# valid as long as it is met after place and route.
create_clock -name "TS_CLKA" -period 20.0 [ get_ports CLKA ]
create_clock -name "TS_CLKB" -period 20.0 [ get_ports CLKB ]
################################################################################
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem_ste/implement/implement.sh 0 → 100644
View file @ 23405448
#!/bin/sh
# Clean up the results directory
rm -rf results
mkdir results
#Synthesize the Wrapper Files
echo 'Synthesizing XST wrapper file (core_top.vhd) with XST';
echo 'Synthesizing example design with XST';
xst -ifn xst.scr
cp buffermem_top.ngc ./results/
# Copy the netlist generated by Coregen
echo 'Copying files from the netlist directory to the results directory'
cp ../../buffermem.ngc results/
# Copy the constraints files generated by Coregen
echo 'Copying files from constraints directory to results directory'
cp ../example_design/buffermem_top.ucf results/
cd results
echo 'Running ngdbuild'
ngdbuild -p xc6slx45-csg324-2 buffermem_top
echo 'Running map'
map buffermem_top -o mapped.ncd -pr i
echo 'Running par'
par mapped.ncd routed.ncd
echo 'Running trce'
trce -e 10 routed.ncd mapped.pcf -o routed
echo 'Running design through bitgen'
bitgen -w routed
echo 'Running netgen to create gate level Verilog model'
netgen -ofmt verilog -sim -tm buffermem_top -pcf mapped.pcf -w routed.ncd routed.v
cp routed.sdf ../../production/timing/
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem_ste/implement/planAhead_rdn.bat 0 → 100644
View file @ 23405448
#!/bin/sh
rem (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
rem
rem This file contains confidential and proprietary information
rem of Xilinx, Inc. and is protected under U.S. and
rem international copyright and other intellectual property
rem laws.
rem
rem DISCLAIMER
rem This disclaimer is not a license and does not grant any
rem rights to the materials distributed herewith. Except as
rem otherwise provided in a valid license issued to you by
rem Xilinx, and to the maximum extent permitted by applicable
rem law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
rem WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
rem AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
rem BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
rem INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
rem (2) Xilinx shall not be liable (whether in contract or tort,
rem including negligence, or under any other theory of
rem liability) for any loss or damage of any kind or nature
rem related to, arising under or in connection with these
rem materials, including for any direct, or any indirect,
rem special, incidental, or consequential loss or damage
rem (including loss of data, profits, goodwill, or any type of
rem loss or damage suffered as a result of any action brought
rem by a third party) even if such damage or loss was
rem reasonably foreseeable or Xilinx had been advised of the
rem possibility of the same.
rem
rem CRITICAL APPLICATIONS
rem Xilinx products are not designed or intended to be fail-
rem safe, or for use in any application requiring fail-safe
rem performance, such as life-support or safety devices or
rem systems, Class III medical devices, nuclear facilities,
rem applications related to the deployment of airbags, or any
rem other applications that could lead to death, personal
rem injury, or severe property or environmental damage
rem (individually and collectively, "Critical
rem Applications"). Customer assumes the sole risk and
rem liability of any use of Xilinx products in Critical
rem Applications, subject only to applicable laws and
rem regulations governing limitations on product liability.
rem
rem THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
rem PART OF THIS FILE AT ALL TIMES.
rem -----------------------------------------------------------------------------
rem Script to synthesize and implement the Coregen FIFO Generator
rem -----------------------------------------------------------------------------
rmdir /S /Q results
mkdir results
cd results
copy ..\..\..\tmp\buffermem.edf .
planAhead -mode batch -source ..\planAhead_rdn.tcl
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem_ste/implement/planAhead_rdn.sh 0 → 100644
View file @ 23405448
#!/bin/sh
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#-----------------------------------------------------------------------------
# Script to synthesize and implement the Coregen FIFO Generator
#-----------------------------------------------------------------------------
rm -rf results
mkdir results
cd results
cp ../../../tmp/buffermem.edf .
planAhead -mode batch -source ../planAhead_rdn.tcl
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem_ste/implement/planAhead_rdn.tcl 0 → 100644
View file @ 23405448
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
set device xc6slx45csg324-2
set projName buffermem
set design buffermem
set projDir [file dirname [info script]]
create_project $projName $projDir/results/$projName -part $device -force
set_property design_mode RTL [current_fileset -srcset]
set top_module buffermem_top
add_files -norecurse {../../example_design/buffermem_top.vhd}
add_files -norecurse {./buffermem.edf}
import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/buffermem_top.xdc}
set_property top buffermem_top [get_property srcset [current_run]]
synth_design
opt_design
place_design
route_design
write_sdf -rename_top_module buffermem_top -file routed.sdf
write_verilog -nolib -mode sim -sdf_anno false -rename_top_module buffermem_top routed.v
report_timing -nworst 30 -path_type full -file routed.twr
report_drc -file routed.drc
#write_bitstream
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem_ste/implement/xst.scr 0 → 100644
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run
-ifmt VHDL
-ent buffermem_top
-p xc6slx45-csg324-2
-ifn xst.prj
-write_timing_constraints No
-iobuf YES
-max_fanout 100
-ofn buffermem_top
-ofmt NGC
-bus_delimiter ()
-hierarchy_separator /
-case Maintain
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem_xmdf.tcl 0 → 100644
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# The package naming convention is <core_name>_xmdf
package provide buffermem_xmdf 1.0
# This includes some utilities that support common XMDF operations
package require utilities_xmdf
# Define a namespace for this package. The name of the name space
# is <core_name>_xmdf
namespace eval ::buffermem_xmdf {
# Use this to define any statics
}
# Function called by client to rebuild the params and port arrays
# Optional when the use context does not require the param or ports
# arrays to be available.
proc ::buffermem_xmdf::xmdfInit { instance } {
# Variable containing name of library into which module is compiled
# Recommendation: <module_name>
# Required
utilities_xmdf::xmdfSetData $instance Module Attributes Name buffermem
}
# ::buffermem_xmdf::xmdfInit
# Function called by client to fill in all the xmdf* data variables
# based on the current settings of the parameters
proc ::buffermem_xmdf::xmdfApplyParams { instance } {
set fcount 0
# Array containing libraries that are assumed to exist
# Examples include unisim and xilinxcorelib
# Optional
# In this example, we assume that the unisim library will
# be available to the simulation and synthesis tool
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_ds512.pdf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v6_2_readme.txt
utilities_xmdf::xmdfSetData $instance FileSet $fcount type text
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path buffermem.asy
utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path buffermem.ngc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path buffermem.sym
utilities_xmdf::xmdfSetData $instance FileSet $fcount type symbol
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path buffermem.v
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path buffermem.veo
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path buffermem.xco
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path buffermem_ste/example_design/bmg_wrapper.vhd
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path buffermem_ste/example_design/buffermem_top.ucf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path buffermem_ste/example_design/buffermem_top.vhd
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path buffermem_ste/example_design/buffermem_top.xdc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path buffermem_ste/implement/implement.sh
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path buffermem_ste/implement/planAhead_rdn.bat
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path buffermem_ste/implement/planAhead_rdn.sh
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path buffermem_ste/implement/planAhead_rdn.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path buffermem_ste/implement/xst.prj
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path buffermem_ste/implement/xst.scr
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path buffermem_xmdf.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path summary.log
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module buffermem
incr fcount
}
# ::gen_comp_name_xmdf::xmdfApplyParams
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/coregen.cgp 0 → 100644
View file @ 23405448
SET busformat = BusFormatAngleBracketNotRipped
SET designentry = Verilog
SET device = xc6slx45
SET devicefamily = spartan6
SET flowvendor = Other
SET package = csg324
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = false
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/create_buffermem.tcl 0 → 100644
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##
## Core Generator Run Script, generator for Project Navigator create command
##
proc findRtfPath { relativePath } {
set xilenv ""
if { [info exists ::env(XILINX) ] } {
if { [info exists ::env(MYXILINX)] } {
set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]
} else {
set xilenv $::env(XILINX)
}
}
foreach path [ split $xilenv $::xilinx::path_sep ] {
set fullPath [ file join $path $relativePath ]
if { [ file exists $fullPath ] } {
return $fullPath
}
}
return ""
}
source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
set result [ run_cg_create "xilinx.com:ip:blk_mem_gen:6.2" "buffermem" "Block Memory Generator" "Block Memory Generator (xilinx.com:ip:blk_mem_gen:6.2) generated by Project Navigator" xc6slx45-2csg324 Verilog ]
if { $result == 0 } {
puts "Core Generator create command completed successfully."
} elseif { $result == 1 } {
puts "Core Generator create command failed."
} elseif { $result == 3 || $result == 4 } {
# convert 'version check' result to real return range, bypassing any messages.
set result [ expr $result - 3 ]
} else {
puts "Core Generator create cancelled."
}
exit $result
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_xmsgs/ngcbuild.xmsgs 0 → 100644
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
</messages>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_xmsgs/pn_parser.xmsgs 0 → 100644
View file @ 23405448
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated -->
<!-- by the Xilinx ISE software. Any direct editing or -->
<!-- changes made to this file may result in unpredictable -->
<!-- behavior or data corruption. It is strongly advised that -->
<!-- users do not edit the contents of this file. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
<messages>
<msg type="info" file="ProjectMgmt" num="1769" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_cg/buffermem.v\&quot; into library work</arg>
</msg>
</messages>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc_summary.html 0 → 100644
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<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>spiifc Project Status</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>spiifc.xise</TD>
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
<TD>spiifc</TD>
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
<TD>New</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD>xc6slx45-2csg324</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 13.2</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
<TD>Balanced</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
<TD>
&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
<TD>&nbsp;</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
<TD>&nbsp;&nbsp;</TD>
</TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD>Synthesis Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
</TABLE>
<br><center><b>Date Generated:</b> 02/28/2012 - 19:36:06</center>
</BODY></HTML>
\ No newline at end of file
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projnav/xps/system.mhs
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projnav/xps/system_incl.make
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