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rasky
vSPI
Commits
19c73f96
Commit
19c73f96
authored
Mar 14, 2012
by
Michael J. Lyons
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Merge branch 'xps_proj' of github.com:mjlyons/vSPI into xps_proj
parents
99e6df56
75a11566
Changes
2
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2 changed files
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71 additions
and
143 deletions
+71
-143
main.cc
projnav/xps/SDK/SDK_Workspace/demo/src/main.cc
+10
-0
user_logic.v
projnav/xps/pcores/spiifc_v1_00_a/hdl/verilog/user_logic.v
+61
-143
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projnav/xps/SDK/SDK_Workspace/demo/src/main.cc
View file @
19c73f96
...
...
@@ -140,6 +140,8 @@ int main()
void
SpiifcPioTest
()
{
int
i
=
0
;
xil_printf
(
"Testing Spiifc PIO...
\n
"
);
// PIO Write to Spiifc memmap regions
...
...
@@ -169,6 +171,14 @@ void SpiifcPioTest()
}
else
{
xil_printf
(
"[FAIL] (actual=0x%08X)
\n
"
,
*
pMisoBase
);
}
for
(
i
=
0
;
i
<
16
;
i
++
)
{
pSpiifcBase
[
i
]
=
(
i
<<
24
)
|
(
i
<<
16
)
|
(
i
<<
8
)
|
i
;
}
for
(
i
=
0
;
i
<
16
;
i
++
)
{
xil_printf
(
"Reg%d=0x%08x
\n
"
,
i
,
pSpiifcBase
[
i
]);
}
xil_printf
(
"
\n
"
);
}
...
...
projnav/xps/pcores/spiifc_v1_00_a/hdl/verilog/user_logic.v
View file @
19c73f96
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