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vSPI
Commit 19c73f96 authored by Michael J. Lyons's avatar Michael J. Lyons
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Merge branch 'xps_proj' of github.com:mjlyons/vSPI into xps_proj

parents 99e6df56 75a11566
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projnav/xps/SDK/SDK_Workspace/demo/src/main.cc
View file @ 19c73f96
......@@ -140,6 +140,8 @@ int main()
void SpiifcPioTest()
{
int i = 0;
xil_printf("Testing Spiifc PIO...\n");
// PIO Write to Spiifc memmap regions
......@@ -169,6 +171,14 @@ void SpiifcPioTest()
} else {
xil_printf("[FAIL] (actual=0x%08X)\n", *pMisoBase);
}
for (i = 0; i < 16; i++) {
pSpiifcBase[i] = (i << 24) | (i << 16) | (i << 8) | i;
}
for (i = 0; i < 16; i++) {
xil_printf("Reg%d=0x%08x\n", i, pSpiifcBase[i]);
}
xil_printf("\n");
}
......
projnav/xps/pcores/spiifc_v1_00_a/hdl/verilog/user_logic.v
View file @ 19c73f96
......@@ -154,33 +154,24 @@ output [0 : C_NUM_INTR-1] IP2Bus_IntrEvent;
wire [0 : 31] misoMem_doutb;
// Nets for user logic slave model s/w accessible register example
reg [0 : C_SLV_DWIDTH-1] slv_reg0;
reg [0 : C_SLV_DWIDTH-1] slv_reg1;
reg [0 : C_SLV_DWIDTH-1] slv_reg2;
reg [0 : C_SLV_DWIDTH-1] slv_reg3;
reg [0 : C_SLV_DWIDTH-1] slv_reg4;
reg [0 : C_SLV_DWIDTH-1] slv_reg5;
reg [0 : C_SLV_DWIDTH-1] slv_reg6;
reg [0 : C_SLV_DWIDTH-1] slv_reg7;
reg [0 : C_SLV_DWIDTH-1] slv_reg8;
reg [0 : C_SLV_DWIDTH-1] slv_reg9;
reg [0 : C_SLV_DWIDTH-1] slv_reg10;
reg [0 : C_SLV_DWIDTH-1] slv_reg11;
reg [0 : C_SLV_DWIDTH-1] slv_reg12;
reg [0 : C_SLV_DWIDTH-1] slv_reg13;
reg [0 : C_SLV_DWIDTH-1] slv_reg14;
reg [0 : C_SLV_DWIDTH-1] slv_reg15;
reg [0 : C_SLV_DWIDTH-1] slv_reg [0:15];
wire [0 : 15] slv_reg_write_sel;
wire [0 : 15] slv_reg_read_sel;
reg [0 : C_SLV_DWIDTH-1] slv_ip2bus_data;
wire slv_read_ack;
wire slv_write_ack;
integer byte_index, bit_index;
// SPI register access
wire [3 : 0] spiRegAddr;
wire [C_SLV_DWIDTH-1 : 0] spiRegWriteData;
wire spiRegWE;
reg [C_SLV_DWIDTH-1 : 0] spiRegReadData_wreg;
// --USER logic implementation added here
// memory interface logic
assign mem_enb = mem_write | mem_read /*& {C_NUM_MEM{Bus2IP_RdReq | Bus2IP_WrReq}}*/;
assign mem_enb = mem_write | mem_read;
assign mem_web = mem_write;
assign mosiMem_addrb = Bus2IP_Addr[20:29];
assign mosiMem_dinb = Bus2IP_Data;
......@@ -237,7 +228,11 @@ output [0 : C_NUM_INTR-1] IP2Bus_IntrEvent;
.txMemData(misoMem_douta),
.rcMemAddr(mosiMem_addra),
.rcMemData(mosiMem_dina),
.rcMemWE(mosiMem_wea)
.rcMemWE(mosiMem_wea),
.regAddr(spiRegAddr),
.regReadData(spiRegReadData_wreg),
.regWriteData(spiRegWriteData),
.regWriteEn(spiRegWE)
);
// ------------------------------------------------------
......@@ -265,142 +260,65 @@ output [0 : C_NUM_INTR-1] IP2Bus_IntrEvent;
slv_write_ack = Bus2IP_WrCE[0] || Bus2IP_WrCE[1] || Bus2IP_WrCE[2] || Bus2IP_WrCE[3] || Bus2IP_WrCE[4] || Bus2IP_WrCE[5] || Bus2IP_WrCE[6] || Bus2IP_WrCE[7] || Bus2IP_WrCE[8] || Bus2IP_WrCE[9] || Bus2IP_WrCE[10] || Bus2IP_WrCE[11] || Bus2IP_WrCE[12] || Bus2IP_WrCE[13] || Bus2IP_WrCE[14] || Bus2IP_WrCE[15],
slv_read_ack = Bus2IP_RdCE[0] || Bus2IP_RdCE[1] || Bus2IP_RdCE[2] || Bus2IP_RdCE[3] || Bus2IP_RdCE[4] || Bus2IP_RdCE[5] || Bus2IP_RdCE[6] || Bus2IP_RdCE[7] || Bus2IP_RdCE[8] || Bus2IP_RdCE[9] || Bus2IP_RdCE[10] || Bus2IP_RdCE[11] || Bus2IP_RdCE[12] || Bus2IP_RdCE[13] || Bus2IP_RdCE[14] || Bus2IP_RdCE[15];
// implement slave model register(s)
always @( posedge Bus2IP_Clk )
begin: SLAVE_REG_WRITE_PROC
if ( Bus2IP_Reset == 1 )
begin
slv_reg0 <= 0;
slv_reg1 <= 0;
slv_reg2 <= 0;
slv_reg3 <= 0;
slv_reg4 <= 0;
slv_reg5 <= 0;
slv_reg6 <= 0;
slv_reg7 <= 0;
slv_reg8 <= 0;
slv_reg9 <= 0;
slv_reg10 <= 0;
slv_reg11 <= 0;
slv_reg12 <= 0;
slv_reg13 <= 0;
slv_reg14 <= 0;
slv_reg15 <= 0;
genvar regIndex;
generate
for (regIndex = 0; regIndex < 16; regIndex = regIndex + 1) begin : REG_LOGIC
// Reg write logic
always @(posedge Bus2IP_Clk) begin
if (Bus2IP_Reset == 1) begin
slv_reg[regIndex] <= 0;
end else if (spiRegWE && regIndex == spiRegAddr) begin
slv_reg[regIndex] <= spiRegWriteData;
end else if (slv_reg_write_sel[regIndex]) begin
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index + 1 ) begin
if ( Bus2IP_BE[byte_index] == 1) begin
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1) begin
slv_reg[regIndex][bit_index] <= Bus2IP_Data[bit_index];
end
end
end
end
else
case ( slv_reg_write_sel )
16'b1000000000000000 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
slv_reg0[bit_index] <= Bus2IP_Data[bit_index];
16'b0100000000000000 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
slv_reg1[bit_index] <= Bus2IP_Data[bit_index];
16'b0010000000000000 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
slv_reg2[bit_index] <= Bus2IP_Data[bit_index];
16'b0001000000000000 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
slv_reg3[bit_index] <= Bus2IP_Data[bit_index];
16'b0000100000000000 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
slv_reg4[bit_index] <= Bus2IP_Data[bit_index];
16'b0000010000000000 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
slv_reg5[bit_index] <= Bus2IP_Data[bit_index];
16'b0000001000000000 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
slv_reg6[bit_index] <= Bus2IP_Data[bit_index];
16'b0000000100000000 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
slv_reg7[bit_index] <= Bus2IP_Data[bit_index];
16'b0000000010000000 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
slv_reg8[bit_index] <= Bus2IP_Data[bit_index];
16'b0000000001000000 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
slv_reg9[bit_index] <= Bus2IP_Data[bit_index];
16'b0000000000100000 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
slv_reg10[bit_index] <= Bus2IP_Data[bit_index];
16'b0000000000010000 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
slv_reg11[bit_index] <= Bus2IP_Data[bit_index];
16'b0000000000001000 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
slv_reg12[bit_index] <= Bus2IP_Data[bit_index];
16'b0000000000000100 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
slv_reg13[bit_index] <= Bus2IP_Data[bit_index];
16'b0000000000000010 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
slv_reg14[bit_index] <= Bus2IP_Data[bit_index];
16'b0000000000000001 :
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
slv_reg15[bit_index] <= Bus2IP_Data[bit_index];
default : ;
endcase
end // SLAVE_REG_WRITE_PROC
end
end
endgenerate
// implement slave model register read mux
always @( slv_reg_read_sel or slv_reg0 or slv_reg1 or slv_reg2 or slv_reg3 or slv_reg4 or slv_reg5 or slv_reg6 or slv_reg7 or slv_reg8 or slv_reg9 or slv_reg10 or slv_reg11 or slv_reg12 or slv_reg13 or slv_reg14 or slv_reg15 )
always @( slv_reg_read_sel or slv_reg[0] or slv_reg[1] or slv_reg[2]
or slv_reg[3] or slv_reg[4] or slv_reg[5] or slv_reg[6] or slv_reg[7]
or slv_reg[8] or slv_reg[9] or slv_reg[10] or slv_reg[11] or slv_reg[12]
or slv_reg[13] or slv_reg[14] or slv_reg[15] )
begin: SLAVE_REG_READ_PROC
case ( slv_reg_read_sel )
16'b1000000000000000 : slv_ip2bus_data <= slv_reg0;
16'b0100000000000000 : slv_ip2bus_data <= slv_reg1;
16'b0010000000000000 : slv_ip2bus_data <= slv_reg2;
16'b0001000000000000 : slv_ip2bus_data <= slv_reg3;
16'b0000100000000000 : slv_ip2bus_data <= slv_reg4;
16'b0000010000000000 : slv_ip2bus_data <= slv_reg5;
16'b0000001000000000 : slv_ip2bus_data <= slv_reg6;
16'b0000000100000000 : slv_ip2bus_data <= slv_reg7;
16'b0000000010000000 : slv_ip2bus_data <= slv_reg8;
16'b0000000001000000 : slv_ip2bus_data <= slv_reg9;
16'b0000000000100000 : slv_ip2bus_data <= slv_reg10;
16'b0000000000010000 : slv_ip2bus_data <= slv_reg11;
16'b0000000000001000 : slv_ip2bus_data <= slv_reg12;
16'b0000000000000100 : slv_ip2bus_data <= slv_reg13;
16'b0000000000000010 : slv_ip2bus_data <= slv_reg14;
16'b0000000000000001 : slv_ip2bus_data <= slv_reg15;
16'b1000000000000000 : slv_ip2bus_data <= slv_reg[0];
16'b0100000000000000 : slv_ip2bus_data <= slv_reg[1];
16'b0010000000000000 : slv_ip2bus_data <= slv_reg[2];
16'b0001000000000000 : slv_ip2bus_data <= slv_reg[3];
16'b0000100000000000 : slv_ip2bus_data <= slv_reg[4];
16'b0000010000000000 : slv_ip2bus_data <= slv_reg[5];
16'b0000001000000000 : slv_ip2bus_data <= slv_reg[6];
16'b0000000100000000 : slv_ip2bus_data <= slv_reg[7];
16'b0000000010000000 : slv_ip2bus_data <= slv_reg[8];
16'b0000000001000000 : slv_ip2bus_data <= slv_reg[9];
16'b0000000000100000 : slv_ip2bus_data <= slv_reg[10];
16'b0000000000010000 : slv_ip2bus_data <= slv_reg[11];
16'b0000000000001000 : slv_ip2bus_data <= slv_reg[12];
16'b0000000000000100 : slv_ip2bus_data <= slv_reg[13];
16'b0000000000000010 : slv_ip2bus_data <= slv_reg[14];
16'b0000000000000001 : slv_ip2bus_data <= slv_reg[15];
default : slv_ip2bus_data <= 0;
endcase
end // SLAVE_REG_READ_PROC
// implement spi register read mux
always @( spiRegAddr or slv_reg[0] or slv_reg[1] or slv_reg[2]
or slv_reg[3] or slv_reg[4] or slv_reg[5] or slv_reg[6] or slv_reg[7]
or slv_reg[8] or slv_reg[9] or slv_reg[10] or slv_reg[11] or slv_reg[12]
or slv_reg[13] or slv_reg[14] or slv_reg[15] ) begin
spiRegReadData_wreg <= slv_reg[spiRegAddr];
end
// ------------------------------------------------------------
// Example code to drive IP to Bus signals
// ------------------------------------------------------------
......
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