SPI connections and CPLD change to FPGA

parent be10261e
......@@ -109,10 +109,10 @@ F 3 "" H 3600 4300 60 0000 C CNN
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......@@ -400,82 +469,106 @@ Wire Wire Line
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$EndSCHEMATC
update=Mon 31 Aug 2015 03:25:24 PM CEST
update=Tue 01 Sep 2015 10:36:26 AM CEST
version=1
last_client=kicad
[cvpcb]
......@@ -45,16 +45,6 @@ LibName15=pga_sockets
LibName16=valves
[general]
version=1
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[eeschema]
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LibDir=/home/nextime/kicad/libs/nexlab;/home/nextime/kicad/libs/RPi_Hat_Template/meta
......@@ -98,3 +88,13 @@ LibName36=/home/nextime/kicad/libs/oshec/HD15_B
LibName37=/home/nextime/kicad/libs/oshec/is61c1024al
LibName38=/home/nextime/kicad/libs/thinkerforce/tinkerforge
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