Commit 99e6df56 authored by Michael J. Lyons's avatar Michael J. Lyons

Merge branch 'fastclock' into xps_proj

parents 7c087d9a 4aa6dcd1
...@@ -7,7 +7,7 @@ class SpiComm: ...@@ -7,7 +7,7 @@ class SpiComm:
_port = 0 # Change if using multiple Cheetahs _port = 0 # Change if using multiple Cheetahs
_mode = 3 # spiifc SPI mode _mode = 3 # spiifc SPI mode
_bitrate = 27900 # kbps _bitrate = 22000 # kbps
handle = None # handle to Cheetah SPI handle = None # handle to Cheetah SPI
......
...@@ -136,6 +136,16 @@ def RegLoopbackTest(): ...@@ -136,6 +136,16 @@ def RegLoopbackTest():
passCount = passCount + 1 passCount = passCount + 1
print("PASS [%d]" % (passCount)) print("PASS [%d]" % (passCount))
#
# ReadRegsTest
#
# Reads out the value of all registers
#
def ReadRegsTest():
for regId in range(16):
regVal = spi.ReadReg(regId)
print("Reg%d = 0x%08x" % (regId, regVal))
# #
# PrintCliSyntax: # PrintCliSyntax:
# #
...@@ -150,6 +160,7 @@ Valid tests (case sensitive): ...@@ -150,6 +160,7 @@ Valid tests (case sensitive):
- MultiBytePacketSend - MultiBytePacketSend
- MemLoopback - MemLoopback
- RegLoopback - RegLoopback
- ReadRegs
""" """
# #
...@@ -166,7 +177,8 @@ cliTest = sys.argv[1] ...@@ -166,7 +177,8 @@ cliTest = sys.argv[1]
testMapping = {'SingleBytePacketsSend' : [SingleBytePacketsSendTest], testMapping = {'SingleBytePacketsSend' : [SingleBytePacketsSendTest],
'MultiBytePacketSend' : [MultiBytePacketSendTest], 'MultiBytePacketSend' : [MultiBytePacketSendTest],
'MemLoopback' : [MemLoopbackTest], 'MemLoopback' : [MemLoopbackTest],
'RegLoopback' : [RegLoopbackTest]} 'RegLoopback' : [RegLoopbackTest],
'ReadRegs' : [ReadRegsTest]}
if cliTest not in testMapping: if cliTest not in testMapping:
sys.stderr.write('%s is not a valid test.\n' % (cliTest,)) sys.stderr.write('%s is not a valid test.\n' % (cliTest,))
PrintCliSyntax() PrintCliSyntax()
......
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