Adding the spiifc xps pcore skeleton to xps project

projnav/xps/__xps/ise/system.xreport

 <?xml version='1.0' encoding='UTF-8'?>
 <report-views version="2.0" >
  <header>
-  <DateModified>2012-02-28T10:59:37</DateModified>
+  <DateModified>2012-02-28T11:11:33</DateModified>
   <ModuleName>system</ModuleName>
-  <SummaryTimeStamp>2012-02-28T10:59:37</SummaryTimeStamp>
+  <SummaryTimeStamp>2012-02-28T11:11:33</SummaryTimeStamp>
   <SavedFilePath>C:/Users/mjlyons/workspace/vSPI/projnav/xps/__xps/ise/system.xreport</SavedFilePath>
   <FilterFile>filter.filter</FilterFile>
   <SavedFilterFilePath>C:/Users/mjlyons/workspace/vSPI/projnav/xps/__xps/ise</SavedFilterFilePath>

projnav/xps/__xps/system.xml

 
-<EDKSYSTEM EDKVERSION="13.2" EDWVERSION="1.2" TIMESTAMP="Tue Feb 28 10:59:38 2012">
+<EDKSYSTEM EDKVERSION="13.2" EDWVERSION="1.2" TIMESTAMP="Tue Feb 28 11:11:34 2012">
 
   <SYSTEMINFO ARCH="spartan6" DEVICE="xc6slx45" PACKAGE="csg324" PART="xc6slx45csg324-2" SOURCE="C:/Users/mjlyons/workspace/vSPI/projnav/xps/system.xmp" SPEEDGRADE="-2"/>
 

projnav/xps/drivers/spiifc_v1_00_a/data/spiifc_v2_1_0.mdd

+##############################################################################
+## Filename:          C:\Users\mjlyons\workspace\vSPI\projnav\xps/drivers/spiifc_v1_00_a/data/spiifc_v2_1_0.mdd
+## Description:       Microprocessor Driver Definition
+## Date:              Tue Feb 28 11:11:28 2012 (by Create and Import Peripheral Wizard)
+##############################################################################
+
+OPTION psf_version = 2.1.0;
+
+BEGIN DRIVER spiifc
+
+  OPTION supported_peripherals = (spiifc);
+  OPTION depends = (common_v1_00_a);
+  OPTION copyfiles = all;
+
+  BEGIN ARRAY interrupt_handler
+    PROPERTY desc = "Interrupt Handler Information";
+    PROPERTY size = 1, permit = none;
+    PARAM name = int_handler, default = SPIIFC_Intr_DefaultHandler, desc = "Name of Interrupt Handler", type = string;
+    PARAM name = int_port, default = IP2INTC_Irpt, desc = "Interrupt pin associated with the interrupt handler", permit = none;
+
+  END ARRAY
+
+END DRIVER

projnav/xps/drivers/spiifc_v1_00_a/data/spiifc_v2_1_0.tcl

+##############################################################################
+## Filename:          C:\Users\mjlyons\workspace\vSPI\projnav\xps/drivers/spiifc_v1_00_a/data/spiifc_v2_1_0.tcl
+## Description:       Microprocess Driver Command (tcl)
+## Date:              Tue Feb 28 11:11:28 2012 (by Create and Import Peripheral Wizard)
+##############################################################################
+
+#uses "xillib.tcl"
+
+proc generate {drv_handle} {
+  xdefine_include_file $drv_handle "xparameters.h" "spiifc" "NUM_INSTANCES" "DEVICE_ID" "C_BASEADDR" "C_HIGHADDR" "C_MEM0_BASEADDR" "C_MEM0_HIGHADDR" "C_MEM1_BASEADDR" "C_MEM1_HIGHADDR" 
+}

projnav/xps/drivers/spiifc_v1_00_a/src/Makefile

+##############################################################################
+## Filename:          C:\Users\mjlyons\workspace\vSPI\projnav\xps/drivers/spiifc_v1_00_a/src/Makefile
+## Description:       Microprocessor Driver Makefile
+## Date:              Tue Feb 28 11:11:28 2012 (by Create and Import Peripheral Wizard)
+##############################################################################
+
+COMPILER=
+ARCHIVER=
+CP=cp
+COMPILER_FLAGS=
+EXTRA_COMPILER_FLAGS=
+LIB=libxil.a
+
+RELEASEDIR=../../../lib
+INCLUDEDIR=../../../include
+INCLUDES=-I./. -I${INCLUDEDIR}
+
+INCLUDEFILES=*.h
+LIBSOURCES=*.c
+OUTS = *.o
+
+libs:
+	echo "Compiling spiifc"
+	$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
+	$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
+	make clean
+
+include:
+	${CP} $(INCLUDEFILES) $(INCLUDEDIR)
+
+clean:
+	rm -rf ${OUTS}

projnav/xps/drivers/spiifc_v1_00_a/src/spiifc.c

+/*****************************************************************************
+* Filename:          C:\Users\mjlyons\workspace\vSPI\projnav\xps/drivers/spiifc_v1_00_a/src/spiifc.c
+* Version:           1.00.a
+* Description:       spiifc Driver Source File
+* Date:              Tue Feb 28 11:11:28 2012 (by Create and Import Peripheral Wizard)
+*****************************************************************************/
+
+
+/***************************** Include Files *******************************/
+
+#include "spiifc.h"
+
+/************************** Function Definitions ***************************/
+
+/**
+ *
+ * Enable all possible interrupts from SPIIFC device.
+ *
+ * @param   baseaddr_p is the base address of the SPIIFC device.
+ *
+ * @return  None.
+ *
+ * @note    None.
+ *
+ */
+void SPIIFC_EnableInterrupt(void * baseaddr_p)
+{
+  Xuint32 baseaddr;
+  baseaddr = (Xuint32) baseaddr_p;
+
+  /*
+   * Enable all interrupt source from user logic.
+   */
+  SPIIFC_mWriteReg(baseaddr, SPIIFC_INTR_IPIER_OFFSET, 0x00000001);
+
+  /*
+   * Set global interrupt enable.
+   */
+  SPIIFC_mWriteReg(baseaddr, SPIIFC_INTR_DGIER_OFFSET, INTR_GIE_MASK);
+}
+
+/**
+ *
+ * Example interrupt controller handler for SPIIFC device.
+ * This is to show example of how to toggle write back ISR to clear interrupts.
+ *
+ * @param   baseaddr_p is the base address of the SPIIFC device.
+ *
+ * @return  None.
+ *
+ * @note    None.
+ *
+ */
+void SPIIFC_Intr_DefaultHandler(void * baseaddr_p)
+{
+  Xuint32 baseaddr;
+  Xuint32 IntrStatus;
+Xuint32 IpStatus;
+  baseaddr = (Xuint32) baseaddr_p;
+
+  {
+    xil_printf("User logic interrupt! \n\r");
+    IpStatus = SPIIFC_mReadReg(baseaddr, SPIIFC_INTR_IPISR_OFFSET);
+    SPIIFC_mWriteReg(baseaddr, SPIIFC_INTR_IPISR_OFFSET, IpStatus);
+  }
+
+}
+

projnav/xps/drivers/spiifc_v1_00_a/src/spiifc.h

+/*****************************************************************************
+* Filename:          C:\Users\mjlyons\workspace\vSPI\projnav\xps/drivers/spiifc_v1_00_a/src/spiifc.h
+* Version:           1.00.a
+* Description:       spiifc Driver Header File
+* Date:              Tue Feb 28 11:11:28 2012 (by Create and Import Peripheral Wizard)
+*****************************************************************************/
+
+#ifndef SPIIFC_H
+#define SPIIFC_H
+
+/***************************** Include Files *******************************/
+
+#include "xbasic_types.h"
+#include "xstatus.h"
+#include "xil_io.h"
+
+/************************** Constant Definitions ***************************/
+
+
+/**
+ * User Logic Slave Space Offsets
+ * -- SLV_REG0 : user logic slave module register 0
+ * -- SLV_REG1 : user logic slave module register 1
+ * -- SLV_REG2 : user logic slave module register 2
+ * -- SLV_REG3 : user logic slave module register 3
+ * -- SLV_REG4 : user logic slave module register 4
+ * -- SLV_REG5 : user logic slave module register 5
+ * -- SLV_REG6 : user logic slave module register 6
+ * -- SLV_REG7 : user logic slave module register 7
+ * -- SLV_REG8 : user logic slave module register 8
+ * -- SLV_REG9 : user logic slave module register 9
+ * -- SLV_REG10 : user logic slave module register 10
+ * -- SLV_REG11 : user logic slave module register 11
+ * -- SLV_REG12 : user logic slave module register 12
+ * -- SLV_REG13 : user logic slave module register 13
+ * -- SLV_REG14 : user logic slave module register 14
+ * -- SLV_REG15 : user logic slave module register 15
+ */
+#define SPIIFC_USER_SLV_SPACE_OFFSET (0x00000000)
+#define SPIIFC_SLV_REG0_OFFSET (SPIIFC_USER_SLV_SPACE_OFFSET + 0x00000000)
+#define SPIIFC_SLV_REG1_OFFSET (SPIIFC_USER_SLV_SPACE_OFFSET + 0x00000004)
+#define SPIIFC_SLV_REG2_OFFSET (SPIIFC_USER_SLV_SPACE_OFFSET + 0x00000008)
+#define SPIIFC_SLV_REG3_OFFSET (SPIIFC_USER_SLV_SPACE_OFFSET + 0x0000000C)
+#define SPIIFC_SLV_REG4_OFFSET (SPIIFC_USER_SLV_SPACE_OFFSET + 0x00000010)
+#define SPIIFC_SLV_REG5_OFFSET (SPIIFC_USER_SLV_SPACE_OFFSET + 0x00000014)
+#define SPIIFC_SLV_REG6_OFFSET (SPIIFC_USER_SLV_SPACE_OFFSET + 0x00000018)
+#define SPIIFC_SLV_REG7_OFFSET (SPIIFC_USER_SLV_SPACE_OFFSET + 0x0000001C)
+#define SPIIFC_SLV_REG8_OFFSET (SPIIFC_USER_SLV_SPACE_OFFSET + 0x00000020)
+#define SPIIFC_SLV_REG9_OFFSET (SPIIFC_USER_SLV_SPACE_OFFSET + 0x00000024)
+#define SPIIFC_SLV_REG10_OFFSET (SPIIFC_USER_SLV_SPACE_OFFSET + 0x00000028)
+#define SPIIFC_SLV_REG11_OFFSET (SPIIFC_USER_SLV_SPACE_OFFSET + 0x0000002C)
+#define SPIIFC_SLV_REG12_OFFSET (SPIIFC_USER_SLV_SPACE_OFFSET + 0x00000030)
+#define SPIIFC_SLV_REG13_OFFSET (SPIIFC_USER_SLV_SPACE_OFFSET + 0x00000034)
+#define SPIIFC_SLV_REG14_OFFSET (SPIIFC_USER_SLV_SPACE_OFFSET + 0x00000038)
+#define SPIIFC_SLV_REG15_OFFSET (SPIIFC_USER_SLV_SPACE_OFFSET + 0x0000003C)
+
+/**
+ * Interrupt Controller Space Offsets
+ * -- INTR_DGIER : device (peripheral) global interrupt enable register
+ * -- INTR_ISR   : ip (user logic) interrupt status register
+ * -- INTR_IER   : ip (user logic) interrupt enable register
+ */
+#define SPIIFC_INTR_CNTRL_SPACE_OFFSET (0x00000100)
+#define SPIIFC_INTR_DGIER_OFFSET (SPIIFC_INTR_CNTRL_SPACE_OFFSET + 0x0000001C)
+#define SPIIFC_INTR_IPISR_OFFSET (SPIIFC_INTR_CNTRL_SPACE_OFFSET + 0x00000020)
+#define SPIIFC_INTR_IPIER_OFFSET (SPIIFC_INTR_CNTRL_SPACE_OFFSET + 0x00000028)
+
+/**
+ * Interrupt Controller Masks
+ * -- INTR_TERR_MASK : transaction error
+ * -- INTR_DPTO_MASK : data phase time-out
+ * -- INTR_IPIR_MASK : ip interrupt requeset
+ * -- INTR_RFDL_MASK : read packet fifo deadlock interrupt request
+ * -- INTR_WFDL_MASK : write packet fifo deadlock interrupt request
+ * -- INTR_IID_MASK  : interrupt id
+ * -- INTR_GIE_MASK  : global interrupt enable
+ * -- INTR_NOPEND    : the DIPR has no pending interrupts
+ */
+#define INTR_TERR_MASK (0x00000001UL)
+#define INTR_DPTO_MASK (0x00000002UL)
+#define INTR_IPIR_MASK (0x00000004UL)
+#define INTR_RFDL_MASK (0x00000020UL)
+#define INTR_WFDL_MASK (0x00000040UL)
+#define INTR_IID_MASK (0x000000FFUL)
+#define INTR_GIE_MASK (0x80000000UL)
+#define INTR_NOPEND (0x80)
+
+/**************************** Type Definitions *****************************/
+
+
+/***************** Macros (Inline Functions) Definitions *******************/
+
+/**
+ *
+ * Write a value to a SPIIFC register. A 32 bit write is performed.
+ * If the component is implemented in a smaller width, only the least
+ * significant data is written.
+ *
+ * @param   BaseAddress is the base address of the SPIIFC device.
+ * @param   RegOffset is the register offset from the base to write to.
+ * @param   Data is the data written to the register.
+ *
+ * @return  None.
+ *
+ * @note
+ * C-style signature:
+ * 	void SPIIFC_mWriteReg(Xuint32 BaseAddress, unsigned RegOffset, Xuint32 Data)
+ *
+ */
+#define SPIIFC_mWriteReg(BaseAddress, RegOffset, Data) \
+ 	Xil_Out32((BaseAddress) + (RegOffset), (Xuint32)(Data))
+
+/**
+ *
+ * Read a value from a SPIIFC register. A 32 bit read is performed.
+ * If the component is implemented in a smaller width, only the least
+ * significant data is read from the register. The most significant data
+ * will be read as 0.
+ *
+ * @param   BaseAddress is the base address of the SPIIFC device.
+ * @param   RegOffset is the register offset from the base to write to.
+ *
+ * @return  Data is the data from the register.
+ *
+ * @note
+ * C-style signature:
+ * 	Xuint32 SPIIFC_mReadReg(Xuint32 BaseAddress, unsigned RegOffset)
+ *
+ */
+#define SPIIFC_mReadReg(BaseAddress, RegOffset) \
+ 	Xil_In32((BaseAddress) + (RegOffset))
+
+
+/**
+ *
+ * Write/Read 32 bit value to/from SPIIFC user logic slave registers.
+ *
+ * @param   BaseAddress is the base address of the SPIIFC device.
+ * @param   RegOffset is the offset from the slave register to write to or read from.
+ * @param   Value is the data written to the register.
+ *
+ * @return  Data is the data from the user logic slave register.
+ *
+ * @note
+ * C-style signature:
+ * 	void SPIIFC_mWriteSlaveRegn(Xuint32 BaseAddress, unsigned RegOffset, Xuint32 Value)
+ * 	Xuint32 SPIIFC_mReadSlaveRegn(Xuint32 BaseAddress, unsigned RegOffset)
+ *
+ */
+#define SPIIFC_mWriteSlaveReg0(BaseAddress, RegOffset, Value) \
+ 	Xil_Out32((BaseAddress) + (SPIIFC_SLV_REG0_OFFSET) + (RegOffset), (Xuint32)(Value))
+#define SPIIFC_mWriteSlaveReg1(BaseAddress, RegOffset, Value) \
+ 	Xil_Out32((BaseAddress) + (SPIIFC_SLV_REG1_OFFSET) + (RegOffset), (Xuint32)(Value))
+#define SPIIFC_mWriteSlaveReg2(BaseAddress, RegOffset, Value) \
+ 	Xil_Out32((BaseAddress) + (SPIIFC_SLV_REG2_OFFSET) + (RegOffset), (Xuint32)(Value))
+#define SPIIFC_mWriteSlaveReg3(BaseAddress, RegOffset, Value) \
+ 	Xil_Out32((BaseAddress) + (SPIIFC_SLV_REG3_OFFSET) + (RegOffset), (Xuint32)(Value))
+#define SPIIFC_mWriteSlaveReg4(BaseAddress, RegOffset, Value) \
+ 	Xil_Out32((BaseAddress) + (SPIIFC_SLV_REG4_OFFSET) + (RegOffset), (Xuint32)(Value))
+#define SPIIFC_mWriteSlaveReg5(BaseAddress, RegOffset, Value) \
+ 	Xil_Out32((BaseAddress) + (SPIIFC_SLV_REG5_OFFSET) + (RegOffset), (Xuint32)(Value))
+#define SPIIFC_mWriteSlaveReg6(BaseAddress, RegOffset, Value) \
+ 	Xil_Out32((BaseAddress) + (SPIIFC_SLV_REG6_OFFSET) + (RegOffset), (Xuint32)(Value))
+#define SPIIFC_mWriteSlaveReg7(BaseAddress, RegOffset, Value) \
+ 	Xil_Out32((BaseAddress) + (SPIIFC_SLV_REG7_OFFSET) + (RegOffset), (Xuint32)(Value))
+#define SPIIFC_mWriteSlaveReg8(BaseAddress, RegOffset, Value) \
+ 	Xil_Out32((BaseAddress) + (SPIIFC_SLV_REG8_OFFSET) + (RegOffset), (Xuint32)(Value))
+#define SPIIFC_mWriteSlaveReg9(BaseAddress, RegOffset, Value) \
+ 	Xil_Out32((BaseAddress) + (SPIIFC_SLV_REG9_OFFSET) + (RegOffset), (Xuint32)(Value))
+#define SPIIFC_mWriteSlaveReg10(BaseAddress, RegOffset, Value) \
+ 	Xil_Out32((BaseAddress) + (SPIIFC_SLV_REG10_OFFSET) + (RegOffset), (Xuint32)(Value))
+#define SPIIFC_mWriteSlaveReg11(BaseAddress, RegOffset, Value) \
+ 	Xil_Out32((BaseAddress) + (SPIIFC_SLV_REG11_OFFSET) + (RegOffset), (Xuint32)(Value))
+#define SPIIFC_mWriteSlaveReg12(BaseAddress, RegOffset, Value) \
+ 	Xil_Out32((BaseAddress) + (SPIIFC_SLV_REG12_OFFSET) + (RegOffset), (Xuint32)(Value))
+#define SPIIFC_mWriteSlaveReg13(BaseAddress, RegOffset, Value) \
+ 	Xil_Out32((BaseAddress) + (SPIIFC_SLV_REG13_OFFSET) + (RegOffset), (Xuint32)(Value))
+#define SPIIFC_mWriteSlaveReg14(BaseAddress, RegOffset, Value) \
+ 	Xil_Out32((BaseAddress) + (SPIIFC_SLV_REG14_OFFSET) + (RegOffset), (Xuint32)(Value))
+#define SPIIFC_mWriteSlaveReg15(BaseAddress, RegOffset, Value) \
+ 	Xil_Out32((BaseAddress) + (SPIIFC_SLV_REG15_OFFSET) + (RegOffset), (Xuint32)(Value))
+
+#define SPIIFC_mReadSlaveReg0(BaseAddress, RegOffset) \
+ 	Xil_In32((BaseAddress) + (SPIIFC_SLV_REG0_OFFSET) + (RegOffset))
+#define SPIIFC_mReadSlaveReg1(BaseAddress, RegOffset) \
+ 	Xil_In32((BaseAddress) + (SPIIFC_SLV_REG1_OFFSET) + (RegOffset))
+#define SPIIFC_mReadSlaveReg2(BaseAddress, RegOffset) \
+ 	Xil_In32((BaseAddress) + (SPIIFC_SLV_REG2_OFFSET) + (RegOffset))
+#define SPIIFC_mReadSlaveReg3(BaseAddress, RegOffset) \
+ 	Xil_In32((BaseAddress) + (SPIIFC_SLV_REG3_OFFSET) + (RegOffset))
+#define SPIIFC_mReadSlaveReg4(BaseAddress, RegOffset) \
+ 	Xil_In32((BaseAddress) + (SPIIFC_SLV_REG4_OFFSET) + (RegOffset))
+#define SPIIFC_mReadSlaveReg5(BaseAddress, RegOffset) \
+ 	Xil_In32((BaseAddress) + (SPIIFC_SLV_REG5_OFFSET) + (RegOffset))
+#define SPIIFC_mReadSlaveReg6(BaseAddress, RegOffset) \
+ 	Xil_In32((BaseAddress) + (SPIIFC_SLV_REG6_OFFSET) + (RegOffset))
+#define SPIIFC_mReadSlaveReg7(BaseAddress, RegOffset) \
+ 	Xil_In32((BaseAddress) + (SPIIFC_SLV_REG7_OFFSET) + (RegOffset))
+#define SPIIFC_mReadSlaveReg8(BaseAddress, RegOffset) \
+ 	Xil_In32((BaseAddress) + (SPIIFC_SLV_REG8_OFFSET) + (RegOffset))
+#define SPIIFC_mReadSlaveReg9(BaseAddress, RegOffset) \
+ 	Xil_In32((BaseAddress) + (SPIIFC_SLV_REG9_OFFSET) + (RegOffset))
+#define SPIIFC_mReadSlaveReg10(BaseAddress, RegOffset) \
+ 	Xil_In32((BaseAddress) + (SPIIFC_SLV_REG10_OFFSET) + (RegOffset))
+#define SPIIFC_mReadSlaveReg11(BaseAddress, RegOffset) \
+ 	Xil_In32((BaseAddress) + (SPIIFC_SLV_REG11_OFFSET) + (RegOffset))
+#define SPIIFC_mReadSlaveReg12(BaseAddress, RegOffset) \
+ 	Xil_In32((BaseAddress) + (SPIIFC_SLV_REG12_OFFSET) + (RegOffset))
+#define SPIIFC_mReadSlaveReg13(BaseAddress, RegOffset) \
+ 	Xil_In32((BaseAddress) + (SPIIFC_SLV_REG13_OFFSET) + (RegOffset))
+#define SPIIFC_mReadSlaveReg14(BaseAddress, RegOffset) \
+ 	Xil_In32((BaseAddress) + (SPIIFC_SLV_REG14_OFFSET) + (RegOffset))
+#define SPIIFC_mReadSlaveReg15(BaseAddress, RegOffset) \
+ 	Xil_In32((BaseAddress) + (SPIIFC_SLV_REG15_OFFSET) + (RegOffset))
+
+/**
+ *
+ * Write/Read 32 bit value to/from SPIIFC user logic memory (BRAM).
+ *
+ * @param   Address is the memory address of the SPIIFC device.
+ * @param   Data is the value written to user logic memory.
+ *
+ * @return  The data from the user logic memory.
+ *
+ * @note
+ * C-style signature:
+ * 	void SPIIFC_mWriteMemory(Xuint32 Address, Xuint32 Data)
+ * 	Xuint32 SPIIFC_mReadMemory(Xuint32 Address)
+ *
+ */
+#define SPIIFC_mWriteMemory(Address, Data) \
+ 	Xil_Out32(Address, (Xuint32)(Data))
+#define SPIIFC_mReadMemory(Address) \
+ 	Xil_In32(Address)
+
+/************************** Function Prototypes ****************************/
+
+
+/**
+ *
+ * Enable all possible interrupts from SPIIFC device.
+ *
+ * @param   baseaddr_p is the base address of the SPIIFC device.
+ *
+ * @return  None.
+ *
+ * @note    None.
+ *
+ */
+void SPIIFC_EnableInterrupt(void * baseaddr_p);
+
+/**
+ *
+ * Example interrupt controller handler.
+ *
+ * @param   baseaddr_p is the base address of the SPIIFC device.
+ *
+ * @return  None.
+ *
+ * @note    None.
+ *
+ */
+void SPIIFC_Intr_DefaultHandler(void * baseaddr_p);
+
+/**
+ *
+ * Run a self-test on the driver/device. Note this may be a destructive test if
+ * resets of the device are performed.
+ *
+ * If the hardware system is not built correctly, this function may never
+ * return to the caller.
+ *
+ * @param   baseaddr_p is the base address of the SPIIFC instance to be worked on.
+ *
+ * @return
+ *
+ *    - XST_SUCCESS   if all self-test code passed
+ *    - XST_FAILURE   if any self-test code failed
+ *
+ * @note    Caching must be turned off for this function to work.
+ * @note    Self test may fail if data memory and device are not on the same bus.
+ *
+ */
+XStatus SPIIFC_SelfTest(void * baseaddr_p);
+
+#endif /** SPIIFC_H */

projnav/xps/drivers/spiifc_v1_00_a/src/spiifc_selftest.c

+/*****************************************************************************
+* Filename:          C:\Users\mjlyons\workspace\vSPI\projnav\xps/drivers/spiifc_v1_00_a/src/spiifc_selftest.c
+* Version:           1.00.a
+* Description:       Contains a diagnostic self-test function for the spiifc driver
+* Date:              Tue Feb 28 11:11:28 2012 (by Create and Import Peripheral Wizard)
+*****************************************************************************/
+
+
+/***************************** Include Files *******************************/
+
+#include "spiifc.h"
+
+/************************** Constant Definitions ***************************/
+
+
+/************************** Variable Definitions ****************************/
+
+extern Xuint32 LocalBRAM; /* User logic local memory (BRAM) base address */
+
+/************************** Function Definitions ***************************/
+
+/**
+ *
+ * Run a self-test on the driver/device. Note this may be a destructive test if
+ * resets of the device are performed.
+ *
+ * If the hardware system is not built correctly, this function may never
+ * return to the caller.
+ *
+ * @param   baseaddr_p is the base address of the SPIIFC instance to be worked on.
+ *
+ * @return
+ *
+ *    - XST_SUCCESS   if all self-test code passed
+ *    - XST_FAILURE   if any self-test code failed
+ *
+ * @note    Caching must be turned off for this function to work.
+ * @note    Self test may fail if data memory and device are not on the same bus.
+ *
+ */
+XStatus SPIIFC_SelfTest(void * baseaddr_p)
+{
+  int     Index;
+  Xuint32 baseaddr;
+  Xuint8  Reg8Value;
+  Xuint16 Reg16Value;
+  Xuint32 Reg32Value;
+  Xuint32 Mem32Value;
+
+  /*
+   * Check and get the device address
+   */
+  /*
+   * Base Address maybe 0. Up to developer to uncomment line below.
+  XASSERT_NONVOID(baseaddr_p != XNULL);
+   */
+  baseaddr = (Xuint32) baseaddr_p;
+
+  xil_printf("******************************\n\r");
+  xil_printf("* User Peripheral Self Test\n\r");
+  xil_printf("******************************\n\n\r");
+
+  /*
+   * Write to user logic slave module register(s) and read back
+   */
+  xil_printf("User logic slave module test...\n\r");
+  xil_printf("   - write 1 to slave register 0 word 0\n\r");
+  SPIIFC_mWriteSlaveReg0(baseaddr, 0, 1);
+  Reg32Value = SPIIFC_mReadSlaveReg0(baseaddr, 0);
+  xil_printf("   - read %d from register 0 word 0\n\r", Reg32Value);
+  if ( Reg32Value != (Xuint32) 1 )
+  {
+    xil_printf("   - slave register 0 word 0 write/read failed\n\r");
+    return XST_FAILURE;
+  }
+  xil_printf("   - write 2 to slave register 1 word 0\n\r");
+  SPIIFC_mWriteSlaveReg1(baseaddr, 0, 2);
+  Reg32Value = SPIIFC_mReadSlaveReg1(baseaddr, 0);
+  xil_printf("   - read %d from register 1 word 0\n\r", Reg32Value);
+  if ( Reg32Value != (Xuint32) 2 )
+  {
+    xil_printf("   - slave register 1 word 0 write/read failed\n\r");
+    return XST_FAILURE;
+  }
+  xil_printf("   - write 3 to slave register 2 word 0\n\r");
+  SPIIFC_mWriteSlaveReg2(baseaddr, 0, 3);
+  Reg32Value = SPIIFC_mReadSlaveReg2(baseaddr, 0);
+  xil_printf("   - read %d from register 2 word 0\n\r", Reg32Value);
+  if ( Reg32Value != (Xuint32) 3 )
+  {
+    xil_printf("   - slave register 2 word 0 write/read failed\n\r");
+    return XST_FAILURE;
+  }
+  xil_printf("   - write 4 to slave register 3 word 0\n\r");
+  SPIIFC_mWriteSlaveReg3(baseaddr, 0, 4);
+  Reg32Value = SPIIFC_mReadSlaveReg3(baseaddr, 0);
+  xil_printf("   - read %d from register 3 word 0\n\r", Reg32Value);
+  if ( Reg32Value != (Xuint32) 4 )
+  {
+    xil_printf("   - slave register 3 word 0 write/read failed\n\r");
+    return XST_FAILURE;
+  }
+  xil_printf("   - write 5 to slave register 4 word 0\n\r");
+  SPIIFC_mWriteSlaveReg4(baseaddr, 0, 5);
+  Reg32Value = SPIIFC_mReadSlaveReg4(baseaddr, 0);
+  xil_printf("   - read %d from register 4 word 0\n\r", Reg32Value);
+  if ( Reg32Value != (Xuint32) 5 )
+  {
+    xil_printf("   - slave register 4 word 0 write/read failed\n\r");
+    return XST_FAILURE;
+  }
+  xil_printf("   - write 6 to slave register 5 word 0\n\r");
+  SPIIFC_mWriteSlaveReg5(baseaddr, 0, 6);
+  Reg32Value = SPIIFC_mReadSlaveReg5(baseaddr, 0);
+  xil_printf("   - read %d from register 5 word 0\n\r", Reg32Value);
+  if ( Reg32Value != (Xuint32) 6 )
+  {
+    xil_printf("   - slave register 5 word 0 write/read failed\n\r");
+    return XST_FAILURE;
+  }
+  xil_printf("   - write 7 to slave register 6 word 0\n\r");
+  SPIIFC_mWriteSlaveReg6(baseaddr, 0, 7);
+  Reg32Value = SPIIFC_mReadSlaveReg6(baseaddr, 0);
+  xil_printf("   - read %d from register 6 word 0\n\r", Reg32Value);
+  if ( Reg32Value != (Xuint32) 7 )
+  {
+    xil_printf("   - slave register 6 word 0 write/read failed\n\r");
+    return XST_FAILURE;
+  }
+  xil_printf("   - write 8 to slave register 7 word 0\n\r");
+  SPIIFC_mWriteSlaveReg7(baseaddr, 0, 8);
+  Reg32Value = SPIIFC_mReadSlaveReg7(baseaddr, 0);
+  xil_printf("   - read %d from register 7 word 0\n\r", Reg32Value);
+  if ( Reg32Value != (Xuint32) 8 )
+  {
+    xil_printf("   - slave register 7 word 0 write/read failed\n\r");
+    return XST_FAILURE;
+  }
+  xil_printf("   - write 9 to slave register 8 word 0\n\r");
+  SPIIFC_mWriteSlaveReg8(baseaddr, 0, 9);
+  Reg32Value = SPIIFC_mReadSlaveReg8(baseaddr, 0);
+  xil_printf("   - read %d from register 8 word 0\n\r", Reg32Value);
+  if ( Reg32Value != (Xuint32) 9 )
+  {
+    xil_printf("   - slave register 8 word 0 write/read failed\n\r");
+    return XST_FAILURE;
+  }
+  xil_printf("   - write 10 to slave register 9 word 0\n\r");
+  SPIIFC_mWriteSlaveReg9(baseaddr, 0, 10);
+  Reg32Value = SPIIFC_mReadSlaveReg9(baseaddr, 0);
+  xil_printf("   - read %d from register 9 word 0\n\r", Reg32Value);
+  if ( Reg32Value != (Xuint32) 10 )
+  {
+    xil_printf("   - slave register 9 word 0 write/read failed\n\r");
+    return XST_FAILURE;
+  }
+  xil_printf("   - write 11 to slave register 10 word 0\n\r");
+  SPIIFC_mWriteSlaveReg10(baseaddr, 0, 11);
+  Reg32Value = SPIIFC_mReadSlaveReg10(baseaddr, 0);
+  xil_printf("   - read %d from register 10 word 0\n\r", Reg32Value);
+  if ( Reg32Value != (Xuint32) 11 )
+  {
+    xil_printf("   - slave register 10 word 0 write/read failed\n\r");
+    return XST_FAILURE;
+  }
+  xil_printf("   - write 12 to slave register 11 word 0\n\r");
+  SPIIFC_mWriteSlaveReg11(baseaddr, 0, 12);
+  Reg32Value = SPIIFC_mReadSlaveReg11(baseaddr, 0);
+  xil_printf("   - read %d from register 11 word 0\n\r", Reg32Value);
+  if ( Reg32Value != (Xuint32) 12 )
+  {
+    xil_printf("   - slave register 11 word 0 write/read failed\n\r");
+    return XST_FAILURE;
+  }
+  xil_printf("   - write 13 to slave register 12 word 0\n\r");
+  SPIIFC_mWriteSlaveReg12(baseaddr, 0, 13);
+  Reg32Value = SPIIFC_mReadSlaveReg12(baseaddr, 0);
+  xil_printf("   - read %d from register 12 word 0\n\r", Reg32Value);
+  if ( Reg32Value != (Xuint32) 13 )
+  {
+    xil_printf("   - slave register 12 word 0 write/read failed\n\r");
+    return XST_FAILURE;
+  }
+  xil_printf("   - write 14 to slave register 13 word 0\n\r");
+  SPIIFC_mWriteSlaveReg13(baseaddr, 0, 14);
+  Reg32Value = SPIIFC_mReadSlaveReg13(baseaddr, 0);
+  xil_printf("   - read %d from register 13 word 0\n\r", Reg32Value);
+  if ( Reg32Value != (Xuint32) 14 )
+  {
+    xil_printf("   - slave register 13 word 0 write/read failed\n\r");
+    return XST_FAILURE;
+  }
+  xil_printf("   - write 15 to slave register 14 word 0\n\r");
+  SPIIFC_mWriteSlaveReg14(baseaddr, 0, 15);
+  Reg32Value = SPIIFC_mReadSlaveReg14(baseaddr, 0);
+  xil_printf("   - read %d from register 14 word 0\n\r", Reg32Value);
+  if ( Reg32Value != (Xuint32) 15 )
+  {
+    xil_printf("   - slave register 14 word 0 write/read failed\n\r");
+    return XST_FAILURE;
+  }
+  xil_printf("   - write 16 to slave register 15 word 0\n\r");
+  SPIIFC_mWriteSlaveReg15(baseaddr, 0, 16);
+  Reg32Value = SPIIFC_mReadSlaveReg15(baseaddr, 0);
+  xil_printf("   - read %d from register 15 word 0\n\r", Reg32Value);
+  if ( Reg32Value != (Xuint32) 16 )
+  {
+    xil_printf("   - slave register 15 word 0 write/read failed\n\r");
+    return XST_FAILURE;
+  }
+  xil_printf("   - slave register write/read passed\n\n\r");
+
+  /*
+   * Write data to user logic BRAMs and read back
+   */
+  xil_printf("User logic BRAM test...\n\r");
+  xil_printf("   - local BRAM address is 0x%08x\n\r", LocalBRAM);
+  xil_printf("   - write pattern to local BRAM and read back\n\r");
+  for ( Index = 0; Index < 256; Index++ )
+  {
+    SPIIFC_mWriteMemory(LocalBRAM+4*Index, 0xDEADBEEF);
+    Mem32Value = SPIIFC_mReadMemory(LocalBRAM+4*Index);
+    if ( Mem32Value != 0xDEADBEEF )
+    {
+      xil_printf("   - write/read BRAM failed on address 0x%08x\n\r", LocalBRAM+4*Index);
+      return XST_FAILURE;
+    }
+  }
+  xil_printf("   - write/read BRAM passed\n\n\r");
+
+  /*
+   * Enable all possible interrupts and clear interrupt status register(s)
+   */
+  xil_printf("Interrupt controller test...\n\r");
+  Reg32Value = SPIIFC_mReadReg(baseaddr, SPIIFC_INTR_IPISR_OFFSET);
+  xil_printf("   - IP (user logic) interrupt status : 0x%08x\n\r", Reg32Value);
+  xil_printf("   - clear IP (user logic) interrupt status register\n\r");
+  SPIIFC_mWriteReg(baseaddr, SPIIFC_INTR_IPISR_OFFSET, Reg32Value);
+  xil_printf("   - enable all possible interrupt(s)\n\r");
+  SPIIFC_EnableInterrupt(baseaddr_p);
+  xil_printf("   - write/read interrupt register passed\n\n\r");
+
+  return XST_SUCCESS;
+}

projnav/xps/implementation/system_summary.html

@@ -31,7 +31,11 @@
 <TR ALIGN=LEFT><TD>Platgen Log File</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
 <TR ALIGN=LEFT><TD>Simgen Log File</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
 <TR ALIGN=LEFT><TD>BitInit Log File</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/mjlyons/workspace/vSPI/projnav/xps\system.log'>System Log File</A></TD><TD>Tue Feb 28 11:00:43 2012</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/mjlyons/workspace/vSPI/projnav/xps\system.log'>System Log File</A></TD><TD>Tue Feb 28 11:11:32 2012</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+</TABLE>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>XPS Synthesis Summary (estimated values)</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=EDKSynthesisSumary"><B>[-]</B></a></TD></TR>
+<TR BGCOLOR='#FFFF99'><TD><B>Report</B></TD><TD><B>Generated</B></TD><TD><B>Flip Flops Used</B></TD><TD><B>LUTs Used</B></TD><TD><B>BRAMS Used</B></TD><TD COLSPAN='2'><B>Errors</B></TD></TR>
 </TABLE>
 
 
@@ -57,5 +61,5 @@
 </TABLE>
 
 
-<br><center><b>Date Generated:</b> 02/28/2012 - 11:00:44</center>
+<br><center><b>Date Generated:</b> 02/28/2012 - 11:11:33</center>
 </BODY></HTML>
\ No newline at end of file

projnav/xps/pcores/spiifc_v1_00_a/data/_spiifc_xst.prj

+vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/proc_common_pkg.vhd"
+vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ipif_pkg.vhd"
+vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_muxcy.vhd"
+vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_gate128.vhd"
+vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/family_support.vhd"
+vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd"
+vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter_f.vhd"
+vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/flex_addr_cntr.vhd"
+vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/addr_reg_cntr_brst_flex.vhd"
+vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plb_address_decoder.vhd"
+vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/burst_support.vhd"
+vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/wr_buffer.vhd"
+vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/be_reset_gen.vhd"
+vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plb_slave_attachment.vhd"
+vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/data_mirror_128.vhd"
+vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plbv46_slave_burst.vhd"
+vhdl interrupt_control_v2_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v2_01_a/hdl/vhdl/interrupt_control.vhd"
+verilog spiifc_v1_00_a "../hdl/verilog/user_logic.v"
+vhdl spiifc_v1_00_a "../hdl/vhdl/spiifc.vhd"

projnav/xps/pcores/spiifc_v1_00_a/data/spiifc_v2_1_0.mpd

+###################################################################
+##
+## Name     : spiifc
+## Desc     : Microprocessor Peripheral Description
+##          : Automatically generated by PsfUtility
+##
+###################################################################
+
+BEGIN spiifc
+
+## Peripheral Options
+OPTION IPTYPE = PERIPHERAL
+OPTION IMP_NETLIST = TRUE
+OPTION HDL = MIXED
+OPTION IP_GROUP = MICROBLAZE:PPC:USER
+OPTION DESC = SPIIFC
+OPTION ARCH_SUPPORT_MAP = (others=DEVELOPMENT)
+
+
+## Bus Interfaces
+BUS_INTERFACE BUS = SPLB, BUS_STD = PLBV46, BUS_TYPE = SLAVE
+
+## Generics for VHDL or Parameters for Verilog
+PARAMETER C_BASEADDR = 0xffffffff, DT = std_logic_vector, MIN_SIZE = 0x200, PAIR = C_HIGHADDR, ADDRESS = BASE, BUS = SPLB
+PARAMETER C_HIGHADDR = 0x00000000, DT = std_logic_vector, PAIR = C_BASEADDR, ADDRESS = HIGH, BUS = SPLB
+PARAMETER C_SPLB_AWIDTH = 32, DT = INTEGER, BUS = SPLB, ASSIGNMENT = CONSTANT
+PARAMETER C_SPLB_DWIDTH = 128, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128)
+PARAMETER C_SPLB_NUM_MASTERS = 8, DT = INTEGER, BUS = SPLB, RANGE = (1:16)
+PARAMETER C_SPLB_MID_WIDTH = 3, DT = INTEGER, BUS = SPLB, RANGE = (1:4)
+PARAMETER C_SPLB_NATIVE_DWIDTH = 32, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128), ASSIGNMENT = CONSTANT
+PARAMETER C_SPLB_P2P = 0, DT = INTEGER, BUS = SPLB, RANGE = (0, 1)
+PARAMETER C_SPLB_SUPPORT_BURSTS = 1, DT = INTEGER, BUS = SPLB, RANGE = (0, 1), ASSIGNMENT = CONSTANT
+PARAMETER C_SPLB_SMALLEST_MASTER = 32, DT = INTEGER, BUS = SPLB, RANGE = (32, 64, 128)
+PARAMETER C_SPLB_CLK_PERIOD_PS = 10000, DT = INTEGER, BUS = SPLB
+PARAMETER C_INCLUDE_DPHASE_TIMER = 1, DT = INTEGER, RANGE = (0, 1)
+PARAMETER C_FAMILY = virtex6, DT = STRING
+PARAMETER C_MEM0_BASEADDR = 0xffffffff, DT = std_logic_vector, PAIR = C_MEM0_HIGHADDR, ADDRESS = BASE, BUS = SPLB
+PARAMETER C_MEM0_HIGHADDR = 0x00000000, DT = std_logic_vector, PAIR = C_MEM0_BASEADDR, ADDRESS = HIGH, BUS = SPLB
+PARAMETER C_MEM1_BASEADDR = 0xffffffff, DT = std_logic_vector, PAIR = C_MEM1_HIGHADDR, ADDRESS = BASE, BUS = SPLB
+PARAMETER C_MEM1_HIGHADDR = 0x00000000, DT = std_logic_vector, PAIR = C_MEM1_BASEADDR, ADDRESS = HIGH, BUS = SPLB
+
+## Ports
+PORT SPLB_Clk = "", DIR = I, SIGIS = CLK, BUS = SPLB
+PORT SPLB_Rst = SPLB_Rst, DIR = I, SIGIS = RST, BUS = SPLB
+PORT PLB_ABus = PLB_ABus, DIR = I, VEC = [0:31], BUS = SPLB
+PORT PLB_UABus = PLB_UABus, DIR = I, VEC = [0:31], BUS = SPLB
+PORT PLB_PAValid = PLB_PAValid, DIR = I, BUS = SPLB
+PORT PLB_SAValid = PLB_SAValid, DIR = I, BUS = SPLB
+PORT PLB_rdPrim = PLB_rdPrim, DIR = I, BUS = SPLB
+PORT PLB_wrPrim = PLB_wrPrim, DIR = I, BUS = SPLB
+PORT PLB_masterID = PLB_masterID, DIR = I, VEC = [0:(C_SPLB_MID_WIDTH-1)], BUS = SPLB
+PORT PLB_abort = PLB_abort, DIR = I, BUS = SPLB
+PORT PLB_busLock = PLB_busLock, DIR = I, BUS = SPLB
+PORT PLB_RNW = PLB_RNW, DIR = I, BUS = SPLB
+PORT PLB_BE = PLB_BE, DIR = I, VEC = [0:((C_SPLB_DWIDTH/8)-1)], BUS = SPLB
+PORT PLB_MSize = PLB_MSize, DIR = I, VEC = [0:1], BUS = SPLB
+PORT PLB_size = PLB_size, DIR = I, VEC = [0:3], BUS = SPLB
+PORT PLB_type = PLB_type, DIR = I, VEC = [0:2], BUS = SPLB
+PORT PLB_lockErr = PLB_lockErr, DIR = I, BUS = SPLB
+PORT PLB_wrDBus = PLB_wrDBus, DIR = I, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB
+PORT PLB_wrBurst = PLB_wrBurst, DIR = I, BUS = SPLB
+PORT PLB_rdBurst = PLB_rdBurst, DIR = I, BUS = SPLB
+PORT PLB_wrPendReq = PLB_wrPendReq, DIR = I, BUS = SPLB
+PORT PLB_rdPendReq = PLB_rdPendReq, DIR = I, BUS = SPLB
+PORT PLB_wrPendPri = PLB_wrPendPri, DIR = I, VEC = [0:1], BUS = SPLB
+PORT PLB_rdPendPri = PLB_rdPendPri, DIR = I, VEC = [0:1], BUS = SPLB
+PORT PLB_reqPri = PLB_reqPri, DIR = I, VEC = [0:1], BUS = SPLB
+PORT PLB_TAttribute = PLB_TAttribute, DIR = I, VEC = [0:15], BUS = SPLB
+PORT Sl_addrAck = Sl_addrAck, DIR = O, BUS = SPLB
+PORT Sl_SSize = Sl_SSize, DIR = O, VEC = [0:1], BUS = SPLB
+PORT Sl_wait = Sl_wait, DIR = O, BUS = SPLB
+PORT Sl_rearbitrate = Sl_rearbitrate, DIR = O, BUS = SPLB
+PORT Sl_wrDAck = Sl_wrDAck, DIR = O, BUS = SPLB
+PORT Sl_wrComp = Sl_wrComp, DIR = O, BUS = SPLB
+PORT Sl_wrBTerm = Sl_wrBTerm, DIR = O, BUS = SPLB
+PORT Sl_rdDBus = Sl_rdDBus, DIR = O, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB
+PORT Sl_rdWdAddr = Sl_rdWdAddr, DIR = O, VEC = [0:3], BUS = SPLB
+PORT Sl_rdDAck = Sl_rdDAck, DIR = O, BUS = SPLB
+PORT Sl_rdComp = Sl_rdComp, DIR = O, BUS = SPLB
+PORT Sl_rdBTerm = Sl_rdBTerm, DIR = O, BUS = SPLB
+PORT Sl_MBusy = Sl_MBusy, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
+PORT Sl_MWrErr = Sl_MWrErr, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
+PORT Sl_MRdErr = Sl_MRdErr, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
+PORT Sl_MIRQ = Sl_MIRQ, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
+PORT IP2INTC_Irpt = "", DIR = O, SIGIS = INTERRUPT, SENSITIVITY = LEVEL_HIGH
+
+END

projnav/xps/pcores/spiifc_v1_00_a/data/spiifc_v2_1_0.pao

+##############################################################################
+## Filename:          C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/data/spiifc_v2_1_0.pao
+## Description:       Peripheral Analysis Order
+## Date:              Tue Feb 28 11:11:15 2012 (by Create and Import Peripheral Wizard)
+##############################################################################
+
+lib proc_common_v3_00_a  all 
+lib plbv46_slave_burst_v1_01_a  all 
+lib interrupt_control_v2_01_a  all 
+lib spiifc_v1_00_a user_logic verilog
+lib spiifc_v1_00_a spiifc vhdl

projnav/xps/pcores/spiifc_v1_00_a/devl/README.txt

+TABLE OF CONTENTS
+  1) Peripheral Summary
+  2) Description of Generated Files
+  3) Description of Used IPIC Signals
+  4) Description of Top Level Generics
+
+
+================================================================================
+*                             1) Peripheral Summary                            *
+================================================================================
+Peripheral Summary:
+
+  XPS project / EDK repository               : C:\Users\mjlyons\workspace\vSPI\projnav\xps
+  logical library name                       : spiifc_v1_00_a
+  top name                                   : spiifc
+  version                                    : 1.00.a
+  type                                       : PLB (v4.6) slave
+  features                                   : slave attachment
+                                               interrupt control
+                                               user s/w registers
+                                               user memory spaces
+
+Address Block for User Logic and IPIF Predefined Services
+
+  user logic slave space                     : C_BASEADDR + 0x00000000
+                                             : C_BASEADDR + 0x000000FF
+  interrupt control space                    : C_BASEADDR + 0x00000100
+                                             : C_BASEADDR + 0x000001FF
+  User logic memory space 0                  : C_MEM0_BASEADDR
+                                             : C_MEM0_HIGHADDR
+  User logic memory space 1                  : C_MEM1_BASEADDR
+                                             : C_MEM1_HIGHADDR
+
+
+================================================================================
+*                          2) Description of Generated Files                   *
+================================================================================
+- HDL source file(s)
+
+  hdl/vhdl/spiifc.vhd
+
+    This is the template file for your peripheral's top design entity. It
+    configures and instantiates the corresponding design units in the way you
+    indicated in the wizard GUI and hooks it up to the stub user logic where
+    the actual functionalites should get implemented. You are not expected to
+    modify this template file except certain marked places for adding user
+    specific generics and ports.
+
+  verilog/user_logic.v
+
+    This is the template file for the stub user logic design entity, either in
+    VHDL or Verilog, where the actual functionalities should get implemented.
+    Some sample code snippet may be provided for demonstration purpose.
+
+- XPS interface file(s)
+
+  data/spiifc_v2_1_0.mpd
+
+    This Microprocessor Peripheral Description file contains information of the
+    interface of your peripheral, so that other EDK tools can recognize your
+    peripheral.
+
+  data/spiifc_v2_1_0.pao
+
+    This Peripheral Analysis Order file defines the analysis order of all the HDL
+    source files that are used to compile your peripheral.
+
+- ISE project file(s)
+
+  devl/projnav/spiifc.ise
+
+    This is the ProjNavigator project file. It sets up the needed logical
+    libraries and dependent library files for you to help you develop your
+    peripheral using ProjNavigator.
+
+  devl/projnav/spiifc.cli
+
+    This is the TCL command line file used to generate the .ise file.
+
+- XST synthesis file(s)
+
+  devl/synthesis/spiifc_xst.scr
+
+    This is the XST synthesis script file to compile your peripheral.
+    Note: you may want to modify the device part option for your target.
+
+  devl/synthesis/spiifc_xst.prj
+
+    This is the XST synthesis project file used by the above script file to
+    compile your peripheral.
+
+- Driver source file(s)
+
+  src/spiifc.h
+
+    This is the software driver header template file, which contains address offset of
+    software addressable registers in your peripheral, as well as some common masks and
+    simple register access macros or function declaration.
+
+  src/spiifc.c
+
+    This is the software driver source template file, to define all applicable driver
+    functions.
+
+  src/spiifc_selftest.c
+
+    This is the software driver self test example file, which contain self test example
+    code to test various hardware features of your peripheral.
+
+  src/Makefile
+
+    This is the software driver makefile to compile drivers.
+
+- Driver interface file(s)
+-user needs to add these to repositories path in SDK (Xilinx Tools-->Repositories)
+
+  data/spiifc_v2_1_0.mdd
+
+    This is the Microprocessor Driver Definition file.
+
+  data/spiifc_v2_1_0.tcl
+
+    This is the Microprocessor Driver Command file.
+
+- Other misc file(s)
+
+  devl/ipwiz.opt
+
+    This is the option setting file for the wizard batch mode, which should
+    generate the same result as the wizard GUI mode.
+
+  devl/README.txt
+
+    This README file for your peripheral.
+
+  devl/ipwiz.log
+
+    This is the log file by operating on this wizard.
+
+
+================================================================================
+*                         3) Description of Used IPIC Signals                  *
+================================================================================
+For more information (usage, timing diagrams, etc.) regarding the IPIC signals
+used in the templates, please refer to the following specifications:
+proc_common_v3_00_a
+	No documentation for this library
+
+plbv46_slave_burst_v1_01_a
+	C:\Users\mjlyons\workspace\vSPI\projnav\xps\C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_slave_burst_v1_01_a\doc\plbv46_slave_burst.pdf
+
+interrupt_control_v2_01_a
+	C:\Users\mjlyons\workspace\vSPI\projnav\xps\C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\interrupt_control_v2_01_a\doc\interrupt_control.pdf
+
+Bus2IP_Clk
+    Synchronization clock provided to the user logic. All IPIC signals are 
+    synchronous to this clock. It is identical to the input <bus>_Clk signal of 
+    the peripheral. No additional buffering is provided on the clock; it is 
+    passed through as is. 
+
+Bus2IP_Reset
+    Active high reset used by the user logic. It is asserted whenever the 
+    <bus>_Rst signal asserts or whenever there is a software-programmed reset 
+    (if the soft reset block is included). 
+
+Bus2IP_Addr
+    Address bus to the user logic. It indicates the address of the requested 
+    read or write operation. It can be used for additional address decoding or 
+    as input to addressable memory devices. 
+
+Bus2IP_CS
+    Active high chip select bus. Assertion of a chip select indicates an active 
+    transaction request to the chip select's target address space. This is 
+    typically used for user logic memory space selection. 
+
+Bus2IP_RNW
+    Input signal to the user logic. It indicates the sense of a requested 
+    operation with the user logic. High is a read and low is a write. It is 
+    valid whenever at least one of the Bus2IP_CS bits is active. 
+
+Bus2IP_Data
+    Write data bus to the user logic. Write data is accepted by the user logic 
+    during a write operation by assertion of the write acknowledgement signal 
+    and the rising edge of the Bus2IP_Clk. 
+
+Bus2IP_BE
+    Byte Enable qualifiers for the requested read or write operation to the user 
+    logic. A bit in the Bus2IP_BE set to '1' indicates that the associated byte 
+    lane contains valid data. For example, if Bus2IP_BE = 0011, this indicates 
+    that byte lanes 2 and 3 contain valid data. 
+
+Bus2IP_RdCE
+    Active high chip enable bus to the user logic. These chip enables are only 
+    asserted during active read transaction requests with the target address 
+    space and in conjunction with the corresponding sub-address within the 
+    space. These are typically used for user logic readable registers selection. 
+
+Bus2IP_WrCE
+    Active high chip enable bus to the user logic. These chip enables are 
+    asserted only during active write transaction requests with the target 
+    address space and in conjunction with the corresponding sub-address within 
+    the space. Typically used for user logic writable registers selection. 
+
+Bus2IP_Burst
+    Active high signal indicating that the active read or write operation with 
+    the user logic is utilizing bursting protocol. This signal is asserted at 
+    the initiation of a burst transaction with the user logic and de-asserted at 
+    the completion of the second to last data beat of the burst data transfer. 
+
+Bus2IP_BurstLength
+    This value is an indication of the number of bytes being requested for 
+    transfer and is valid when the cycle is of burst type Bus2IP_CS is active. 
+
+Bus2IP_RdReq
+    Active high signal indicating the initiation of a read operation with the 
+    user logic. It is asserted for one Bus2IP_Clk during single data beat 
+    transactions and remains high to completion on burst read operations. 
+
+Bus2IP_WrReq
+    Active high signal indicating the initiation of a write operation with the 
+    user logic. It is asserted for one Bus2IP_Clk during single data beat 
+    transactions and remains high to completion on burst write operations. 
+
+IP2Bus_AddrAck
+    Active high signal that advances the address counter and request state 
+    during multiple data beat transfers, i.e. bursting. 
+
+IP2Bus_Data
+    Output read data bus from the user logic; data is qualified with the 
+    assertion of IP2Bus_RdAck signal and the rising edge of the Bus2IP_Clk. 
+
+IP2Bus_RdAck
+    Active high read data qualifier providing the read acknowledgement from the 
+    user logic. Read data on the IP2Bus_Data bus is deemed valid at the rising 
+    edge of the Bus2IP_Clk and IP2Bus_RdAck asserted high by the user logic. For 
+    immediate acknowledgement (such as for a register read), this signal can be 
+    tied to '1'. Wait states can be inserted in the transaction by delaying the 
+    assertion of the acknowledgement. 
+
+IP2Bus_WrAck
+    Active high write data qualifier providing the write acknowledgement from 
+    the user logic. Write data on the Bus2IP_Data bus is deemed accepted by the 
+    user logic at the rising edge of the Bus2IP_Clk and IP2Bus_WrAck asserted 
+    high by the user logic. For immediate acknowledgement (such as for a 
+    register write), this signal can be tied to '1'. Wait states can be inserted 
+    in the transaction by delaying the assertion of the acknowledgement. 
+
+IP2Bus_Error
+    Active high signal indicating the user logic has encountered an error with 
+    the requested operation. It is asserted in conjunction with the read/write 
+    acknowledgement signal(s). 
+
+IP2Bus_IntrEvent
+    An output from the user logic to the IPIF that consists of interrupt event 
+    signals to be detected and latched inside the IPIF. 
+
+================================================================================
+*                     4) Description of Top Level Generics                     *
+================================================================================
+C_BASEADDR/C_HIGHADDR
+    These two generics are used to define the memory mapped address space for
+    the peripheral registers, including Soft Reset register, Interrupt Source
+    Controller registers, Read/Write FIFO control/data registers, user logic
+    software accessible registers and etc., but excluding those user logic
+    memory spaces if ever existed. When instantiation, the address space
+    size determined by these two generics must be a power of 2 (e.g. 2^k =
+    C_HIGHADDR - C_BASEADDR + 1), a factor of C_BASEADDR and larger than the
+    minimum size as indicated in the template.
+
+C_SPLB_AWIDTH
+    This is the slave interface address bus width for Processor Local Bus
+    version 4.6 (PLBv46). Value can be assigned automatically by EDK
+    tooling during system creation.
+
+C_SPLB_DWIDTH
+    This is the slave interface data bus width for Processor Local Bus
+    version 4.6 (PLBv46). Value can be assigned automatically by EDK
+    tooling during system creation.
+
+C_SPLB_NUM_MASTERS
+    This indicates to the slave interface the number of PLBv46 masters
+    present. Value can be assigned automatically by EDK tooling during
+    system creation.
+
+C_SPLB_MID_WIDTH
+    This indicates to the slave interface the number of bits required
+    for the PLB_masterID input bus. It is an integer value equal to
+    log2(C_SPLB_NUM_MASTERS). Value will be assigned automatically by
+    EDK tooling during system creation.
+
+C_SPLB_NATIVE_DWIDTH
+    This indicates to the slave interface the native bit width of the
+    internal data bus of the peripheral. Some peripheral will require
+    the value of this parameter to be fixed, while others might have
+    selectable native data widths.
+
+C_SPLB_P2P
+    This indicates to the slave interface when it is exclusively attached
+    to a PLBv46 bus via a Point to Point interconnect scheme. In this
+    scenario, the slave interface may be able to reduce resource utilization
+    by eliminating address decode function and modifying interface behavior
+    to allow for a reduction in latency.
+
+C_SPLB_SUPPORT_BURSTS
+    This indicates to the associated PLBv46 bus that this slave interface
+    support burst transfers to improve performance.
+
+C_SPLB_SMALLEST_MASTER
+    This indicates the smallest native data width of any master on the
+    corresponding PLBv46 bus that may access the slave interface. It allows
+    optimizations within the slave interface logic if narrower masters don't
+    have to be supported for that application.
+
+C_SPLB_CLK_PERIOD_PS
+    This is the period of the PLBv46 bus clock (in picoseconds) for the
+    corresponding PLBv46 slave interface attachment. It has been defined
+    for use by peripheral that needs to know the bus clock rate to improve
+    certain functions such as internal timers.
+
+C_INCLUDE_DPHASE_TIMER
+    This indicates if the data phase timer is used or not. The value of
+    0 will exclude the timer.  The value of 1 includes the timer.
+    If C_INCLUDE_DPHASE_TIMER = 1 and after 128 SPLB_Clk cycles, as
+    measured from the assertion of Sl_AddrAck, the User IP does not
+    respond with either an IP2Bus_RdAck or IP2Bus_WrAck the 
+    plbv46_slave_single will de-assert the User IP cycle request
+    signals, Bus2IP_CS and Bus2IP_RdCE or Bus2IP_WrCE, and will assert
+    Sl_rdDAck with Sl_rdDBus=zero for a read cycle or Sl_wrDAck for
+    a write cycle. This will gracefully terminate the cycle. Note 
+    that the requesting master will have no knowledge that the data
+    phase of the PLB request was terminated in this manner.
+
+C_FAMILY
+    This is to set the target FPGA architecture, s.t. virtex6, etc.
+
+C_MEMn_BASEADDR/C_MEMn_HIGHADDR (n = 0, 1, 2, etc.)
+    These two generics are used to define the memory mapped address space for
+    user logic memory space n, which are typically used in peripherals like
+    memory controllers, bridges, that need to access memory blocks other
+    than local register space. When instantiation, the address space size
+    determined by these two generics should be a power of 2 (e.g. 2^k =
+    C_MEMn_HIGHADDR - C_MEMn_BASEADDR + 1) and a factor of C_MEMn_BASEADDR.
+
+================================================================================
+*          5) Location to documentation of dependent libraries                 *
+*                                                                              *
+*   In general, the documentation is located under:                            *
+*   $XILINX_EDK/hw/XilinxProcessorIPLib/pcores/$libName/doc                    *
+*                                                                              *
+================================================================================
+proc_common_v3_00_a
+	No documentation for this library
+
+plbv46_slave_burst_v1_01_a
+	C:\Users\mjlyons\workspace\vSPI\projnav\xps\C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_slave_burst_v1_01_a\doc\plbv46_slave_burst.pdf
+
+interrupt_control_v2_01_a
+	C:\Users\mjlyons\workspace\vSPI\projnav\xps\C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\interrupt_control_v2_01_a\doc\interrupt_control.pdf
+

projnav/xps/pcores/spiifc_v1_00_a/devl/create.cip

+CipWiz::SetVersion "13.2";
+CipWiz::SetFlow "CREATE";
+CipWiz::SetParameter "ProjectDir" "C:\Users\mjlyons\workspace\vSPI\projnav\xps";
+CipWiz::SetParameter "IpName" "spiifc";
+CipWiz::SetParameter "IpVersion" "1.00.a";
+CipWiz::SetParameter "HdlLanguage" "2";
+CipWiz::SetParameter "BusType" "64";
+CipWiz::SetParameter "IncludeIseFile" "TRUE";
+CipWiz::SetParameter "IncludeXpsFile" "TRUE";
+CipWiz::SetParameter "IncludeSoftwareDriverFile" "TRUE";
+CipWiz::SetParameter "IncludeBFMSimulationFile" "FALSE";
+CipWiz::SetParameter "IncludeSlaveAttachmentSupport" "TRUE";
+CipWiz::SetParameter "IncludeMasterAttachmentSupport" "FALSE";
+CipWiz::SetParameter "IncludeMirResetRegister" "FALSE";
+CipWiz::SetParameter "IncludeFifoSupport" "FALSE";
+CipWiz::SetParameter "IncludeInterruptSupport" "TRUE";
+CipWiz::SetParameter "IncludeDMASupport" "FALSE";
+CipWiz::SetParameter "IncludeBurstSupport" "FALSE";
+CipWiz::SetParameter "IncludeUserRegisterSupport" "TRUE";
+CipWiz::SetParameter "IncludeUserMasterSupport" "FALSE";
+CipWiz::SetParameter "IncludeUserMemorySupport" "TRUE";
+CipWiz::SetParameter "UseSlaveBurst" "TRUE";
+CipWiz::SetParameter "UseMasterBurst" "FALSE";
+CipWiz::SetParameter "UseReadFifo" "FALSE";
+CipWiz::SetParameter "UseWriteFifo" "FALSE";
+CipWiz::SetParameter "UseReadFifoPacketMode" "FALSE";
+CipWiz::SetParameter "UseWriteFifoPacketMode" "FALSE";
+CipWiz::SetParameter "UseReadFifoVacancyCalculation" "FALSE";
+CipWiz::SetParameter "UseWriteFifoVacancyCalculation" "FALSE";
+CipWiz::SetParameter "WriteFifoDataWidth" "0";
+CipWiz::SetParameter "WriteFifoDepth" "0";
+CipWiz::SetParameter "ReadFifoDataWidth" "0";
+CipWiz::SetParameter "ReadFifoDepth" "0";
+CipWiz::SetParameter "UseDeviceISC" "FALSE";
+CipWiz::SetParameter "UseDevicePriorityEncoder" "FALSE";
+CipWiz::SetParameter "NumberOfInterrupt" "1";
+CipWiz::SetParameter "TypeOfInterrupt" "1";
+CipWiz::SetParameter "TypeOfDMA" "0";
+CipWiz::SetParameter "UseFastTransferProtocol" "FALSE";
+CipWiz::SetParameter "BurstMaxSize" "0";
+CipWiz::SetParameter "BurstPageSize" "0";
+CipWiz::SetParameter "IncludeDPhaseTimer" "TRUE";
+CipWiz::SetParameter "SlaveSideNativeDataWidth" "32";
+CipWiz::SetParameter "SlaveBurstWriteBufferDepth" "16";
+CipWiz::SetParameter "MasterSideNativeDataWidth" "0";
+CipWiz::SetParameter "AXIMasterMaxBurstSize" "0";
+CipWiz::SetParameter "AXIMasterWidthOfPort" "0";
+CipWiz::SetParameter "AXIMasterAddrPipelineDepth" "0";
+CipWiz::SetParameter "NumberOfUserRegister" "16";
+CipWiz::SetParameter "UserRegisterDataWidth" "0";
+CipWiz::SetParameter "WriteMode" "0";
+CipWiz::SetParameter "HasInputFSL" "0";
+CipWiz::SetParameter "HasOutputFSL" "0";
+CipWiz::SetParameter "TotalInputData" "0";
+CipWiz::SetParameter "TotalOutputData" "0";
+CipWiz::SetParameter "NumOfInputArgs" "0";
+CipWiz::SetParameter "NumOfOutputArgs" "0";
+CipWiz::SetParameter "NumberOfUserMemoryBank" "2";
+CipWiz::SetParameter "UserMemoryBankDataWidth" "0";
+CipWiz::SetParameter "IpicSelectedPortNames" "Bus2IP_Clk|Bus2IP_Reset|Bus2IP_Addr|Bus2IP_CS|Bus2IP_RNW|Bus2IP_Data|Bus2IP_BE|Bus2IP_RdCE|Bus2IP_WrCE|Bus2IP_Burst|Bus2IP_BurstLength|Bus2IP_RdReq|Bus2IP_WrReq|IP2Bus_AddrAck|IP2Bus_Data|IP2Bus_RdAck|IP2Bus_WrAck|IP2Bus_Error|IP2Bus_IntrEvent|";
+CipWiz::SetParameter "UserLogicModuleName" "0";
+CipWiz::SetParameter "TypeOfUserLogicSource" "user_logic";

projnav/xps/pcores/spiifc_v1_00_a/devl/ipwiz.log

+
+----------------------------------------------------------------------------
+--                            Design Analysis                             --
+----------------------------------------------------------------------------
+Analyze pcore spiifc ...
+
+
+----------------------------------------------------------------------------
+--                            Design Analysis                             --
+----------------------------------------------------------------------------
+Analyze pcore spiifc ...
+
+
+----------------------------------------------------------------------------
+--                            Design Analysis                             --
+----------------------------------------------------------------------------
+Analyze pcore spiifc ...
+
+
+----------------------------------------------------------------------------
+--                            File Generation                             --
+----------------------------------------------------------------------------
+Creating HDL source directory ...
+Generating top peripheral VHDL template ...
+Generating stub user logic Verilog template ...
+HDL templates successfully generated ...
+Creating data directory ...
+Generating XPS inteface files ...
+WARNING:HDLParsers:3497 - Ignoring Verilog File
+   "C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/data/../hd
+   l/verilog/user_logic.v"
+Compiling vhdl file
+"C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
+l/vhdl/family_support.vhd" in Library proc_common_v3_00_a.
+Package <family_support> compiled.
+Package body <family_support> compiled.
+Compiling vhdl file
+"C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
+l/vhdl/or_muxcy.vhd" in Library proc_common_v3_00_a.
+Entity <or_muxcy> compiled.
+Entity <or_muxcy> (Architecture <implementation>) compiled.
+Compiling vhdl file
+"C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
+l/vhdl/proc_common_pkg.vhd" in Library proc_common_v3_00_a.
+Package <proc_common_pkg> compiled.
+Package body <proc_common_pkg> compiled.
+Compiling vhdl file
+"C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
+l/vhdl/ipif_pkg.vhd" in Library proc_common_v3_00_a.
+Package <ipif_pkg> compiled.
+Package body <ipif_pkg> compiled.
+Compiling vhdl file
+"C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
+l/vhdl/or_gate128.vhd" in Library proc_common_v3_00_a.
+Entity <or_gate128> compiled.
+Entity <or_gate128> (Architecture <imp>) compiled.
+Compiling vhdl file
+"C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
+l/vhdl/pselect_f.vhd" in Library proc_common_v3_00_a.
+Entity <pselect_f> compiled.
+Entity <pselect_f> (Architecture <imp>) compiled.
+Compiling vhdl file
+"C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hd
+l/vhdl/counter_f.vhd" in Library proc_common_v3_00_a.
+Entity <counter_f> compiled.
+Entity <counter_f> (Architecture <imp>) compiled.
+Compiling vhdl file
+"C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_
+01_a/hdl/vhdl/flex_addr_cntr.vhd" in Library plbv46_slave_burst_v1_01_a.
+Entity <flex_addr_cntr> compiled.
+Entity <flex_addr_cntr> (Architecture <implementation>) compiled.
+Compiling vhdl file
+"C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_
+01_a/hdl/vhdl/be_reset_gen.vhd" in Library plbv46_slave_burst_v1_01_a.
+Entity <be_reset_gen> compiled.
+Entity <be_reset_gen> (Architecture <implementation>) compiled.
+Compiling vhdl file
+"C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_
+01_a/hdl/vhdl/plb_address_decoder.vhd" in Library plbv46_slave_burst_v1_01_a.
+Entity <plb_address_decoder> compiled.
+Entity <plb_address_decoder> (Architecture <IMP>) compiled.
+Compiling vhdl file
+"C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_
+01_a/hdl/vhdl/wr_buffer.vhd" in Library plbv46_slave_burst_v1_01_a.
+Entity <wr_buffer> compiled.
+Entity <wr_buffer> (Architecture <imp>) compiled.
+Compiling vhdl file
+"C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_
+01_a/hdl/vhdl/burst_support.vhd" in Library plbv46_slave_burst_v1_01_a.
+Entity <burst_support> compiled.
+Entity <burst_support> (Architecture <implementation>) compiled.
+Compiling vhdl file
+"C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_
+01_a/hdl/vhdl/addr_reg_cntr_brst_flex.vhd" in Library
+plbv46_slave_burst_v1_01_a.
+Entity <addr_reg_cntr_brst_flex> compiled.
+Entity <addr_reg_cntr_brst_flex> (Architecture <implementation>) compiled.
+Compiling vhdl file
+"C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_
+01_a/hdl/vhdl/plb_slave_attachment.vhd" in Library plbv46_slave_burst_v1_01_a.
+Entity <plb_slave_attachment> compiled.
+Entity <plb_slave_attachment> (Architecture <implementation>) compiled.
+Compiling vhdl file
+"C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_
+01_a/hdl/vhdl/data_mirror_128.vhd" in Library plbv46_slave_burst_v1_01_a.
+Entity <data_mirror_128> compiled.
+Entity <data_mirror_128> (Architecture <implementation>) compiled.
+Compiling vhdl file
+"C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v2_0
+1_a/hdl/vhdl/interrupt_control.vhd" in Library interrupt_control_v2_01_a.
+Entity <interrupt_control> compiled.
+Entity <interrupt_control> (Architecture <implementation>) compiled.
+Compiling vhdl file
+"C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_
+01_a/hdl/vhdl/plbv46_slave_burst.vhd" in Library plbv46_slave_burst_v1_01_a.
+Entity <plbv46_slave_burst> compiled.
+Entity <plbv46_slave_burst> (Architecture <implementation>) compiled.
+Compiling vhdl file
+"C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/data/../hdl/v
+hdl/spiifc.vhd" in Library spiifc_v1_00_a.
+Entity <spiifc> compiled.
+Entity <spiifc> (Architecture <IMP>) compiled.
+
+
+Analyzing HDL attributes ...
+Entity name = spiifc
+INFO:EDK:1607 - IPTYPE set to value : PERIPHERAL
+INFO:EDK:1511 - IMP_NETLIST set to value : TRUE
+INFO:EDK:1486 - HDL set to value : VHDL
+WARNING:EDK:3588 - Unable to delete temporary XST project file
+   C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\data\_spiif
+   c_xst.prj : 13
+XPS interface files successfully generated ...
+Creating development directory ...
+Generating command option file ...
+Generating readme file ...
+Development misc files successfully generated ...
+Creating projnav directory ...
+Generating ProjNav support files ...
+ProjNav support files successfully generated ...
+Creating synthesis directory ...
+Generating XST synthesis support files ...
+XST synthesis support files successfully generated ...
+No BFM simulation files will be generated at this time ...
+Creating software driver data directory ...
+Generating software driver XPS interface (mdd/tcl) files ...
+Software driver data definition file (.mdd) successfully generated ...
+Software driver data generation file (.tcl) successfully generated ...
+Creating software driver src directory ...
+Generating software driver template files ...
+Software driver compile file (Makefile) successfully generated ...
+output user slave register(s) offset to software driver header ...
+output interrupt control register(s) offset to software driver header ...
+Software driver header file (.h) successfully generated ...
+Software driver source file (.c) successfully generated ...
+Software driver SelfTest file (.c) successfully generated ...
+Software driver template files successfully generated ...
+
+----------------------------------------------------------------------------
+--                              Final Report                              --
+----------------------------------------------------------------------------
+Thank you for using Create and Import Peripheral Wizard! Please find your
+peripheral hardware templates under
+C:\Users\mjlyons\workspace\vSPI\projnav\xps/pcores/spiifc_v1_00_a and peripheral
+software templates under
+C:\Users\mjlyons\workspace\vSPI\projnav\xps/drivers/spiifc_v1_00_a respectively.
+
+Peripheral Summary:
+
+  top name       : spiifc
+  version        : 1.00.a
+  type           : PLB (v4.6) slave
+  features       : slave attachment
+                   interrupt control
+                   user s/w registers
+                   user memory spaces
+
+Address Block Summary:
+
+  user logic slv : C_BASEADDR + 0x00000000
+                 : C_BASEADDR + 0x000000FF
+  interrupt      : C_BASEADDR + 0x00000100
+                 : C_BASEADDR + 0x000001FF
+  user memory 0  : C_MEM0_BASEADDR
+                 : C_MEM0_HIGHADDR
+  user memory 1  : C_MEM1_BASEADDR
+                 : C_MEM1_HIGHADDR
+
+File Summary
+
+  - HDL source -
+  C:\Users\mjlyons\workspace\vSPI\projnav\xps/pcores/spiifc_v1_00_a/hdl
+  top entity     : vhdl/spiifc.vhd
+  user logic     : verilog/user_logic.v
+
+  - XPS interface -
+  C:\Users\mjlyons\workspace\vSPI\projnav\xps/pcores/spiifc_v1_00_a/data
+  mpd            : spiifc_v2_1_0.mpd
+  pao            : spiifc_v2_1_0.pao
+
+  - ISE project -
+  C:\Users\mjlyons\workspace\vSPI\projnav\xps/pcores/spiifc_v1_00_a/devl/projnav
+  ise project    : spiifc.xise
+  tcl script     : spiifc.tcl
+
+
+  - XST synthesis -
+C:\Users\mjlyons\workspace\vSPI\projnav\xps/pcores/spiifc_v1_00_a/devl/synthesis
+  xst script     : spiifc_xst.scr
+  xst project    : spiifc_xst.prj
+
+  - Misc file -
+  C:\Users\mjlyons\workspace\vSPI\projnav\xps/pcores/spiifc_v1_00_a/devl
+  help           : README.txt
+  option         : ipwiz.opt
+  log            : ipwiz.log
+
+  - Driver source -
+  C:\Users\mjlyons\workspace\vSPI\projnav\xps/drivers/spiifc_v1_00_a/src
+  makefile       : Makefile
+  header         : spiifc.h
+  source         : spiifc.c
+  selftest       : spiifc_selftest.c
+
+  - Driver interface -
+  C:\Users\mjlyons\workspace\vSPI\projnav\xps/drivers/spiifc_v1_00_a/data
+  mdd            : spiifc_v2_1_0.mdd
+  tcl            : spiifc_v2_1_0.tcl
+
+

projnav/xps/pcores/spiifc_v1_00_a/devl/ipwiz.opt

+-batch 
+-create spiifc 
+-ver 1.00.a 
+-dir "C:\Users\mjlyons\workspace\vSPI\projnav\xps" 
+-lang verilog 
+-bus plbv46 s 
+-burst s 32 
+-isc 1 
+-intrn 1 1 
+-reg 16 
+-mem 2 
+-wrbuf 16 
+-xps 
+-ise 
+-driver 

projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/_xmsgs/pn_parser.xmsgs

+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated   -->
+<!--     by the Xilinx ISE software.  Any direct editing or        -->
+<!--     changes made to this file may result in unpredictable     -->
+<!--     behavior or data corruption.  It is strongly advised that -->
+<!--     users do not edit the contents of this file.              -->
+<!--                                                               -->
+<!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.    -->
+
+<messages>
+<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v2_01_a/hdl/vhdl/interrupt_control.vhd&quot; into library interrupt_control_v2_01_a</arg>
+</msg>
+
+</messages>
+

projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc.gise

+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <!--                                                          -->
+
+  <!--             For tool use only. Do not edit.              -->
+
+  <!--                                                          -->
+
+  <!-- ProjectNavigator created generated project file.         -->
+
+  <!-- For use in tracking generated file and other information -->
+
+  <!-- allowing preservation of process status.                 -->
+
+  <!--                                                          -->
+
+  <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
+
+  <version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
+
+  <sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="spiifc.xise"/>
+
+  <files xmlns="http://www.xilinx.com/XMLSchema"/>
+
+  <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+
+</generated_project>

projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc.tcl

+project new C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc.xise;
+project set family spartan6;
+project set device xc6slx45;
+project set package csg324;
+project set speed -2;
+project set top_level_module_type HDL;
+project set synthesis_tool "XST (VHDL/Verilog)";
+lib_vhdl new spiifc_v1_00_a;
+xfile add C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/hdl/vhdl/spiifc.vhd;
+xfile add C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/hdl/verilog/user_logic.v;
+lib_vhdl new proc_common_v3_00_a;
+xfile add C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/proc_common_pkg.vhd -lib_vhdl proc_common_v3_00_a;
+xfile add C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ipif_pkg.vhd -lib_vhdl proc_common_v3_00_a;
+xfile add C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_muxcy.vhd -lib_vhdl proc_common_v3_00_a;
+xfile add C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_gate128.vhd -lib_vhdl proc_common_v3_00_a;
+xfile add C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/family_support.vhd -lib_vhdl proc_common_v3_00_a;
+xfile add C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd -lib_vhdl proc_common_v3_00_a;
+xfile add C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter_f.vhd -lib_vhdl proc_common_v3_00_a;
+lib_vhdl new plbv46_slave_burst_v1_01_a;
+xfile add C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/flex_addr_cntr.vhd -lib_vhdl plbv46_slave_burst_v1_01_a;
+xfile add C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/addr_reg_cntr_brst_flex.vhd -lib_vhdl plbv46_slave_burst_v1_01_a;
+xfile add C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plb_address_decoder.vhd -lib_vhdl plbv46_slave_burst_v1_01_a;
+xfile add C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/burst_support.vhd -lib_vhdl plbv46_slave_burst_v1_01_a;
+xfile add C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/wr_buffer.vhd -lib_vhdl plbv46_slave_burst_v1_01_a;
+xfile add C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/be_reset_gen.vhd -lib_vhdl plbv46_slave_burst_v1_01_a;
+xfile add C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plb_slave_attachment.vhd -lib_vhdl plbv46_slave_burst_v1_01_a;
+xfile add C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/data_mirror_128.vhd -lib_vhdl plbv46_slave_burst_v1_01_a;
+xfile add C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plbv46_slave_burst.vhd -lib_vhdl plbv46_slave_burst_v1_01_a;
+lib_vhdl new interrupt_control_v2_01_a;
+xfile add C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v2_01_a/hdl/vhdl/interrupt_control.vhd -lib_vhdl interrupt_control_v2_01_a;
+project close;

projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc.xise

+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
+
+  <header>
+    <!-- ISE source project file created by Project Navigator.             -->
+    <!--                                                                   -->
+    <!-- This file contains project source information including a list of -->
+    <!-- project source files, project and process properties.  This file, -->
+    <!-- along with the project source files, is sufficient to open and    -->
+    <!-- implement in ISE Project Navigator.                               -->
+    <!--                                                                   -->
+    <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved. -->
+  </header>
+
+  <version xil_pn:ise_version="13.2" xil_pn:schema_version="2"/>
+
+  <files>
+    <file xil_pn:name="../../hdl/vhdl/spiifc.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+    </file>
+    <file xil_pn:name="../../hdl/verilog/user_logic.v" xil_pn:type="FILE_VERILOG">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
+    </file>
+    <file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/proc_common_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
+      <library xil_pn:name="proc_common_v3_00_a"/>
+    </file>
+    <file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ipif_pkg.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
+      <library xil_pn:name="proc_common_v3_00_a"/>
+    </file>
+    <file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_muxcy.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
+      <library xil_pn:name="proc_common_v3_00_a"/>
+    </file>
+    <file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_gate128.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
+      <library xil_pn:name="proc_common_v3_00_a"/>
+    </file>
+    <file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/family_support.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
+      <library xil_pn:name="proc_common_v3_00_a"/>
+    </file>
+    <file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
+      <library xil_pn:name="proc_common_v3_00_a"/>
+    </file>
+    <file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter_f.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
+      <library xil_pn:name="proc_common_v3_00_a"/>
+    </file>
+    <file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/flex_addr_cntr.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
+      <library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
+    </file>
+    <file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/addr_reg_cntr_brst_flex.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
+      <library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
+    </file>
+    <file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plb_address_decoder.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
+      <library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
+    </file>
+    <file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/burst_support.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
+      <library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
+    </file>
+    <file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/wr_buffer.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
+      <library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
+    </file>
+    <file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/be_reset_gen.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
+      <library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
+    </file>
+    <file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plb_slave_attachment.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
+      <library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
+    </file>
+    <file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/data_mirror_128.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
+      <library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
+    </file>
+    <file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plbv46_slave_burst.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
+      <library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
+    </file>
+    <file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v2_01_a/hdl/vhdl/interrupt_control.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
+      <library xil_pn:name="interrupt_control_v2_01_a"/>
+    </file>
+  </files>
+
+  <properties>
+    <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
+    <property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Auto Implementation Top" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
+    <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
+    <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/>
+    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/>
+    <property xil_pn:name="Clock Enable" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Collapsing Input Limit (4-40)" xil_pn:value="32" xil_pn:valueState="default"/>
+    <property xil_pn:name="Collapsing Pterm Limit (3-56)" xil_pn:value="28" xil_pn:valueState="default"/>
+    <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile CPLD Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Compile uni9000 (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
+    <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Default Powerup Value of Registers" xil_pn:value="Low" xil_pn:valueState="default"/>
+    <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
+    <property xil_pn:name="Device" xil_pn:value="xc6slx45" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-2" xil_pn:valueState="default"/>
+    <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
+    <property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
+    <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
+    <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
+    <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Function Block Input Limit (4-40)" xil_pn:value="38" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
+    <property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Post-Fit Power Data" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Post-Fit Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
+    <property xil_pn:name="HDL Equations Style" xil_pn:value="Source" xil_pn:valueState="default"/>
+    <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
+    <property xil_pn:name="I/O Voltage Standard" xil_pn:value="LVCMOS18" xil_pn:valueState="default"/>
+    <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Implementation Template" xil_pn:value="Optimize Density" xil_pn:valueState="default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|spiifc|IMP" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="../../hdl/vhdl/spiifc.vhd" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/spiifc" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Input and tristate I/O Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
+    <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
+    <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Keep Hierarchy CPLD" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Logic Optimization" xil_pn:value="Density" xil_pn:valueState="default"/>
+    <property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
+    <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
+    <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
+    <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Programming Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Fit" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Timing Report Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output File Name" xil_pn:value="spiifc" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output Slew Rate" xil_pn:value="Fast" xil_pn:valueState="default"/>
+    <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
+    <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="spiifc_map.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="spiifc_timesim.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="spiifc_synthesis.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="spiifc_translate.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
+    <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
+    <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
+    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
+    <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
+    <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
+    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
+    <property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
+    <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
+    <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
+    <property xil_pn:name="Timing Report Format" xil_pn:value="Summary" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
+    <property xil_pn:name="Unused I/O Pad Termination Mode" xil_pn:value="Keeper" xil_pn:valueState="default"/>
+    <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Data Gate" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Direct Input for Input Registers" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Timing Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
+    <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
+    <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
+    <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
+    <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
+    <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
+    <!--                                                                                  -->
+    <!-- The following properties are for internal use only. These should not be modified.-->
+    <!--                                                                                  -->
+    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_DesignName" xil_pn:value="spiifc" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-02-28T11:11:25" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="8CCD92A1D6E74DAC823A444842F84F30" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
+  </properties>
+
+  <bindings/>
+
+  <libraries>
+    <library xil_pn:name="interrupt_control_v2_01_a"/>
+    <library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
+    <library xil_pn:name="proc_common_v3_00_a"/>
+    <library xil_pn:name="spiifc_v1_00_a"/>
+  </libraries>
+
+  <autoManagedFiles>
+    <!-- The following files are identified by `include statements in verilog -->
+    <!-- source files and are automatically managed by Project Navigator.     -->
+    <!--                                                                      -->
+    <!-- Do not hand-edit this section, as it will be overwritten when the    -->
+    <!-- project is analyzed based on files automatically identified as       -->
+    <!-- include files.                                                       -->
+  </autoManagedFiles>
+
+</project>

projnav/xps/pcores/spiifc_v1_00_a/devl/synthesis/spiifc_xst.prj

+vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/proc_common_pkg.vhd"
+vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ipif_pkg.vhd"
+vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_muxcy.vhd"
+vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_gate128.vhd"
+vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/family_support.vhd"
+vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd"
+vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter_f.vhd"
+vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/flex_addr_cntr.vhd"
+vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/addr_reg_cntr_brst_flex.vhd"
+vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plb_address_decoder.vhd"
+vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/burst_support.vhd"
+vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/wr_buffer.vhd"
+vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/be_reset_gen.vhd"
+vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plb_slave_attachment.vhd"
+vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/data_mirror_128.vhd"
+vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plbv46_slave_burst.vhd"
+vhdl interrupt_control_v2_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v2_01_a/hdl/vhdl/interrupt_control.vhd"
+verilog spiifc_v1_00_a "../../hdl/verilog/user_logic.v"
+vhdl spiifc_v1_00_a "../../hdl/vhdl/spiifc.vhd"

projnav/xps/pcores/spiifc_v1_00_a/devl/synthesis/spiifc_xst.scr

+run
+-opt_level 2
+-opt_mode speed
+-ifmt mixed
+-ifn "C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\synthesis\spiifc_xst.prj"
+-top spiifc
+-p virtex6
+-ofn "C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\synthesis\spiifc_xst.ngc"
+-iobuf NO
+-rtlview YES
+-hierarchy_separator /
+-work_lib spiifc_v1_00_a

projnav/xps/pcores/spiifc_v1_00_a/hdl/verilog/user_logic.v

+//----------------------------------------------------------------------------
+// user_logic.vhd - module
+//----------------------------------------------------------------------------
+//
+// ***************************************************************************
+// ** Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.            **
+// **                                                                       **
+// ** Xilinx, Inc.                                                          **
+// ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"         **
+// ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND       **
+// ** SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE,        **
+// ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,        **
+// ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION           **
+// ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,     **
+// ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE      **
+// ** FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY              **
+// ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE               **
+// ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR        **
+// ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF       **
+// ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS       **
+// ** FOR A PARTICULAR PURPOSE.                                             **
+// **                                                                       **
+// ***************************************************************************
+//
+//----------------------------------------------------------------------------
+// Filename:          user_logic.vhd
+// Version:           1.00.a
+// Description:       User logic module.
+// Date:              Tue Feb 28 11:11:15 2012 (by Create and Import Peripheral Wizard)
+// Verilog Standard:  Verilog-2001
+//----------------------------------------------------------------------------
+// Naming Conventions:
+//   active low signals:                    "*_n"
+//   clock signals:                         "clk", "clk_div#", "clk_#x"
+//   reset signals:                         "rst", "rst_n"
+//   generics:                              "C_*"
+//   user defined types:                    "*_TYPE"
+//   state machine next state:              "*_ns"
+//   state machine current state:           "*_cs"
+//   combinatorial signals:                 "*_com"
+//   pipelined or register delay signals:   "*_d#"
+//   counter signals:                       "*cnt*"
+//   clock enable signals:                  "*_ce"
+//   internal version of output port:       "*_i"
+//   device pins:                           "*_pin"
+//   ports:                                 "- Names begin with Uppercase"
+//   processes:                             "*_PROCESS"
+//   component instantiations:              "<ENTITY_>I_<#|FUNC>"
+//----------------------------------------------------------------------------
+
+module user_logic
+(
+  // -- ADD USER PORTS BELOW THIS LINE ---------------
+  // --USER ports added here 
+  // -- ADD USER PORTS ABOVE THIS LINE ---------------
+
+  // -- DO NOT EDIT BELOW THIS LINE ------------------
+  // -- Bus protocol ports, do not add to or delete 
+  Bus2IP_Clk,                     // Bus to IP clock
+  Bus2IP_Reset,                   // Bus to IP reset
+  Bus2IP_Addr,                    // Bus to IP address bus
+  Bus2IP_CS,                      // Bus to IP chip select for user logic memory selection
+  Bus2IP_RNW,                     // Bus to IP read/not write
+  Bus2IP_Data,                    // Bus to IP data bus
+  Bus2IP_BE,                      // Bus to IP byte enables
+  Bus2IP_RdCE,                    // Bus to IP read chip enable
+  Bus2IP_WrCE,                    // Bus to IP write chip enable
+  Bus2IP_Burst,                   // Bus to IP burst-mode qualifier
+  Bus2IP_BurstLength,             // Bus to IP burst length
+  Bus2IP_RdReq,                   // Bus to IP read request
+  Bus2IP_WrReq,                   // Bus to IP write request
+  IP2Bus_AddrAck,                 // IP to Bus address acknowledgement
+  IP2Bus_Data,                    // IP to Bus data bus
+  IP2Bus_RdAck,                   // IP to Bus read transfer acknowledgement
+  IP2Bus_WrAck,                   // IP to Bus write transfer acknowledgement
+  IP2Bus_Error,                   // IP to Bus error response
+  IP2Bus_IntrEvent                // IP to Bus interrupt event
+  // -- DO NOT EDIT ABOVE THIS LINE ------------------
+); // user_logic
+
+// -- ADD USER PARAMETERS BELOW THIS LINE ------------
+// --USER parameters added here 
+// -- ADD USER PARAMETERS ABOVE THIS LINE ------------
+
+// -- DO NOT EDIT BELOW THIS LINE --------------------
+// -- Bus protocol parameters, do not add to or delete
+parameter C_SLV_AWIDTH                   = 32;
+parameter C_SLV_DWIDTH                   = 32;
+parameter C_NUM_REG                      = 16;
+parameter C_NUM_MEM                      = 2;
+parameter C_NUM_INTR                     = 1;
+// -- DO NOT EDIT ABOVE THIS LINE --------------------
+
+// -- ADD USER PORTS BELOW THIS LINE -----------------
+// --USER ports added here 
+// -- ADD USER PORTS ABOVE THIS LINE -----------------
+
+// -- DO NOT EDIT BELOW THIS LINE --------------------
+// -- Bus protocol ports, do not add to or delete
+input                                     Bus2IP_Clk;
+input                                     Bus2IP_Reset;
+input      [0 : C_SLV_AWIDTH-1]           Bus2IP_Addr;
+input      [0 : C_NUM_MEM-1]              Bus2IP_CS;
+input                                     Bus2IP_RNW;
+input      [0 : C_SLV_DWIDTH-1]           Bus2IP_Data;
+input      [0 : C_SLV_DWIDTH/8-1]         Bus2IP_BE;
+input      [0 : C_NUM_REG-1]              Bus2IP_RdCE;
+input      [0 : C_NUM_REG-1]              Bus2IP_WrCE;
+input                                     Bus2IP_Burst;
+input      [0 : 8]                        Bus2IP_BurstLength;
+input                                     Bus2IP_RdReq;
+input                                     Bus2IP_WrReq;
+output                                    IP2Bus_AddrAck;
+output     [0 : C_SLV_DWIDTH-1]           IP2Bus_Data;
+output                                    IP2Bus_RdAck;
+output                                    IP2Bus_WrAck;
+output                                    IP2Bus_Error;
+output     [0 : C_NUM_INTR-1]             IP2Bus_IntrEvent;
+// -- DO NOT EDIT ABOVE THIS LINE --------------------
+
+//----------------------------------------------------------------------------
+// Implementation
+//----------------------------------------------------------------------------
+
+  // --USER nets declarations added here, as needed for user logic
+
+  // Nets for user logic slave model s/w accessible register example
+  reg        [0 : C_SLV_DWIDTH-1]           slv_reg0;
+  reg        [0 : C_SLV_DWIDTH-1]           slv_reg1;
+  reg        [0 : C_SLV_DWIDTH-1]           slv_reg2;
+  reg        [0 : C_SLV_DWIDTH-1]           slv_reg3;
+  reg        [0 : C_SLV_DWIDTH-1]           slv_reg4;
+  reg        [0 : C_SLV_DWIDTH-1]           slv_reg5;
+  reg        [0 : C_SLV_DWIDTH-1]           slv_reg6;
+  reg        [0 : C_SLV_DWIDTH-1]           slv_reg7;
+  reg        [0 : C_SLV_DWIDTH-1]           slv_reg8;
+  reg        [0 : C_SLV_DWIDTH-1]           slv_reg9;
+  reg        [0 : C_SLV_DWIDTH-1]           slv_reg10;
+  reg        [0 : C_SLV_DWIDTH-1]           slv_reg11;
+  reg        [0 : C_SLV_DWIDTH-1]           slv_reg12;
+  reg        [0 : C_SLV_DWIDTH-1]           slv_reg13;
+  reg        [0 : C_SLV_DWIDTH-1]           slv_reg14;
+  reg        [0 : C_SLV_DWIDTH-1]           slv_reg15;
+  wire       [0 : 15]                       slv_reg_write_sel;
+  wire       [0 : 15]                       slv_reg_read_sel;
+  reg        [0 : C_SLV_DWIDTH-1]           slv_ip2bus_data;
+  wire                                      slv_read_ack;
+  wire                                      slv_write_ack;
+  integer                                   byte_index, bit_index;
+
+  // --USER logic implementation added here
+
+  // ------------------------------------------------------
+  // Example code to read/write user logic slave model s/w accessible registers
+  // 
+  // Note:
+  // The example code presented here is to show you one way of reading/writing
+  // software accessible registers implemented in the user logic slave model.
+  // Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
+  // to one software accessible register by the top level template. For example,
+  // if you have four 32 bit software accessible registers in the user logic,
+  // you are basically operating on the following memory mapped registers:
+  // 
+  //    Bus2IP_WrCE/Bus2IP_RdCE   Memory Mapped Register
+  //                     "1000"   C_BASEADDR + 0x0
+  //                     "0100"   C_BASEADDR + 0x4
+  //                     "0010"   C_BASEADDR + 0x8
+  //                     "0001"   C_BASEADDR + 0xC
+  // 
+  // ------------------------------------------------------
+
+  assign
+    slv_reg_write_sel = Bus2IP_WrCE[0:15],
+    slv_reg_read_sel  = Bus2IP_RdCE[0:15],
+    slv_write_ack     = Bus2IP_WrCE[0] || Bus2IP_WrCE[1] || Bus2IP_WrCE[2] || Bus2IP_WrCE[3] || Bus2IP_WrCE[4] || Bus2IP_WrCE[5] || Bus2IP_WrCE[6] || Bus2IP_WrCE[7] || Bus2IP_WrCE[8] || Bus2IP_WrCE[9] || Bus2IP_WrCE[10] || Bus2IP_WrCE[11] || Bus2IP_WrCE[12] || Bus2IP_WrCE[13] || Bus2IP_WrCE[14] || Bus2IP_WrCE[15],
+    slv_read_ack      = Bus2IP_RdCE[0] || Bus2IP_RdCE[1] || Bus2IP_RdCE[2] || Bus2IP_RdCE[3] || Bus2IP_RdCE[4] || Bus2IP_RdCE[5] || Bus2IP_RdCE[6] || Bus2IP_RdCE[7] || Bus2IP_RdCE[8] || Bus2IP_RdCE[9] || Bus2IP_RdCE[10] || Bus2IP_RdCE[11] || Bus2IP_RdCE[12] || Bus2IP_RdCE[13] || Bus2IP_RdCE[14] || Bus2IP_RdCE[15];
+
+  // implement slave model register(s)
+  always @( posedge Bus2IP_Clk )
+    begin: SLAVE_REG_WRITE_PROC
+
+      if ( Bus2IP_Reset == 1 )
+        begin
+          slv_reg0 <= 0;
+          slv_reg1 <= 0;
+          slv_reg2 <= 0;
+          slv_reg3 <= 0;
+          slv_reg4 <= 0;
+          slv_reg5 <= 0;
+          slv_reg6 <= 0;
+          slv_reg7 <= 0;
+          slv_reg8 <= 0;
+          slv_reg9 <= 0;
+          slv_reg10 <= 0;
+          slv_reg11 <= 0;
+          slv_reg12 <= 0;
+          slv_reg13 <= 0;
+          slv_reg14 <= 0;
+          slv_reg15 <= 0;
+        end
+      else
+        case ( slv_reg_write_sel )
+          16'b1000000000000000 :
+            for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
+              if ( Bus2IP_BE[byte_index] == 1 )
+                for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
+                  slv_reg0[bit_index] <= Bus2IP_Data[bit_index];
+          16'b0100000000000000 :
+            for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
+              if ( Bus2IP_BE[byte_index] == 1 )
+                for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
+                  slv_reg1[bit_index] <= Bus2IP_Data[bit_index];
+          16'b0010000000000000 :
+            for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
+              if ( Bus2IP_BE[byte_index] == 1 )
+                for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
+                  slv_reg2[bit_index] <= Bus2IP_Data[bit_index];
+          16'b0001000000000000 :
+            for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
+              if ( Bus2IP_BE[byte_index] == 1 )
+                for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
+                  slv_reg3[bit_index] <= Bus2IP_Data[bit_index];
+          16'b0000100000000000 :
+            for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
+              if ( Bus2IP_BE[byte_index] == 1 )
+                for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
+                  slv_reg4[bit_index] <= Bus2IP_Data[bit_index];
+          16'b0000010000000000 :
+            for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
+              if ( Bus2IP_BE[byte_index] == 1 )
+                for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
+                  slv_reg5[bit_index] <= Bus2IP_Data[bit_index];
+          16'b0000001000000000 :
+            for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
+              if ( Bus2IP_BE[byte_index] == 1 )
+                for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
+                  slv_reg6[bit_index] <= Bus2IP_Data[bit_index];
+          16'b0000000100000000 :
+            for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
+              if ( Bus2IP_BE[byte_index] == 1 )
+                for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
+                  slv_reg7[bit_index] <= Bus2IP_Data[bit_index];
+          16'b0000000010000000 :
+            for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
+              if ( Bus2IP_BE[byte_index] == 1 )
+                for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
+                  slv_reg8[bit_index] <= Bus2IP_Data[bit_index];
+          16'b0000000001000000 :
+            for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
+              if ( Bus2IP_BE[byte_index] == 1 )
+                for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
+                  slv_reg9[bit_index] <= Bus2IP_Data[bit_index];
+          16'b0000000000100000 :
+            for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
+              if ( Bus2IP_BE[byte_index] == 1 )
+                for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
+                  slv_reg10[bit_index] <= Bus2IP_Data[bit_index];
+          16'b0000000000010000 :
+            for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
+              if ( Bus2IP_BE[byte_index] == 1 )
+                for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
+                  slv_reg11[bit_index] <= Bus2IP_Data[bit_index];
+          16'b0000000000001000 :
+            for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
+              if ( Bus2IP_BE[byte_index] == 1 )
+                for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
+                  slv_reg12[bit_index] <= Bus2IP_Data[bit_index];
+          16'b0000000000000100 :
+            for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
+              if ( Bus2IP_BE[byte_index] == 1 )
+                for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
+                  slv_reg13[bit_index] <= Bus2IP_Data[bit_index];
+          16'b0000000000000010 :
+            for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
+              if ( Bus2IP_BE[byte_index] == 1 )
+                for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
+                  slv_reg14[bit_index] <= Bus2IP_Data[bit_index];
+          16'b0000000000000001 :
+            for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index+1 )
+              if ( Bus2IP_BE[byte_index] == 1 )
+                for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
+                  slv_reg15[bit_index] <= Bus2IP_Data[bit_index];
+          default : ;
+        endcase
+
+    end // SLAVE_REG_WRITE_PROC
+
+  // implement slave model register read mux
+  always @( slv_reg_read_sel or slv_reg0 or slv_reg1 or slv_reg2 or slv_reg3 or slv_reg4 or slv_reg5 or slv_reg6 or slv_reg7 or slv_reg8 or slv_reg9 or slv_reg10 or slv_reg11 or slv_reg12 or slv_reg13 or slv_reg14 or slv_reg15 )
+    begin: SLAVE_REG_READ_PROC
+
+      case ( slv_reg_read_sel )
+        16'b1000000000000000 : slv_ip2bus_data <= slv_reg0;
+        16'b0100000000000000 : slv_ip2bus_data <= slv_reg1;
+        16'b0010000000000000 : slv_ip2bus_data <= slv_reg2;
+        16'b0001000000000000 : slv_ip2bus_data <= slv_reg3;
+        16'b0000100000000000 : slv_ip2bus_data <= slv_reg4;
+        16'b0000010000000000 : slv_ip2bus_data <= slv_reg5;
+        16'b0000001000000000 : slv_ip2bus_data <= slv_reg6;
+        16'b0000000100000000 : slv_ip2bus_data <= slv_reg7;
+        16'b0000000010000000 : slv_ip2bus_data <= slv_reg8;
+        16'b0000000001000000 : slv_ip2bus_data <= slv_reg9;
+        16'b0000000000100000 : slv_ip2bus_data <= slv_reg10;
+        16'b0000000000010000 : slv_ip2bus_data <= slv_reg11;
+        16'b0000000000001000 : slv_ip2bus_data <= slv_reg12;
+        16'b0000000000000100 : slv_ip2bus_data <= slv_reg13;
+        16'b0000000000000010 : slv_ip2bus_data <= slv_reg14;
+        16'b0000000000000001 : slv_ip2bus_data <= slv_reg15;
+        default : slv_ip2bus_data <= 0;
+      endcase
+
+    end // SLAVE_REG_READ_PROC
+
+  // ------------------------------------------------------------
+  // Example code to drive IP to Bus signals
+  // ------------------------------------------------------------
+
+  assign IP2Bus_AddrAck = slv_write_ack || slv_read_ack;
+  assign IP2Bus_Data    = slv_ip2bus_data;
+  assign IP2Bus_WrAck   = slv_write_ack;
+  assign IP2Bus_RdAck   = slv_read_ack;
+  assign IP2Bus_Error   = 0;
+
+endmodule

projnav/xps/pcores/spiifc_v1_00_a/hdl/vhdl/spiifc.vhd

+------------------------------------------------------------------------------
+-- spiifc.vhd - entity/architecture pair
+------------------------------------------------------------------------------
+-- IMPORTANT:
+-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
+--
+-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
+--
+-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
+-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
+-- OF THE USER_LOGIC ENTITY.
+------------------------------------------------------------------------------
+--
+-- ***************************************************************************
+-- ** Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.            **
+-- **                                                                       **
+-- ** Xilinx, Inc.                                                          **
+-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"         **
+-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND       **
+-- ** SOLUTIONS FOR XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE,        **
+-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,        **
+-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION           **
+-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,     **
+-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE      **
+-- ** FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY              **
+-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE               **
+-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR        **
+-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF       **
+-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS       **
+-- ** FOR A PARTICULAR PURPOSE.                                             **
+-- **                                                                       **
+-- ***************************************************************************
+--
+------------------------------------------------------------------------------
+-- Filename:          spiifc.vhd
+-- Version:           1.00.a
+-- Description:       Top level design, instantiates library components and user logic.
+-- Date:              Tue Feb 28 11:11:15 2012 (by Create and Import Peripheral Wizard)
+-- VHDL Standard:     VHDL'93
+------------------------------------------------------------------------------
+-- Naming Conventions:
+--   active low signals:                    "*_n"
+--   clock signals:                         "clk", "clk_div#", "clk_#x"
+--   reset signals:                         "rst", "rst_n"
+--   generics:                              "C_*"
+--   user defined types:                    "*_TYPE"
+--   state machine next state:              "*_ns"
+--   state machine current state:           "*_cs"
+--   combinatorial signals:                 "*_com"
+--   pipelined or register delay signals:   "*_d#"
+--   counter signals:                       "*cnt*"
+--   clock enable signals:                  "*_ce"
+--   internal version of output port:       "*_i"
+--   device pins:                           "*_pin"
+--   ports:                                 "- Names begin with Uppercase"
+--   processes:                             "*_PROCESS"
+--   component instantiations:              "<ENTITY_>I_<#|FUNC>"
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+
+library proc_common_v3_00_a;
+use proc_common_v3_00_a.proc_common_pkg.all;
+use proc_common_v3_00_a.ipif_pkg.all;
+
+library interrupt_control_v2_01_a;
+use interrupt_control_v2_01_a.interrupt_control;
+
+library plbv46_slave_burst_v1_01_a;
+use plbv46_slave_burst_v1_01_a.plbv46_slave_burst;
+
+------------------------------------------------------------------------------
+-- Entity section
+------------------------------------------------------------------------------
+-- Definition of Generics:
+--   C_BASEADDR                   -- PLBv46 slave: base address
+--   C_HIGHADDR                   -- PLBv46 slave: high address
+--   C_SPLB_AWIDTH                -- PLBv46 slave: address bus width
+--   C_SPLB_DWIDTH                -- PLBv46 slave: data bus width
+--   C_SPLB_NUM_MASTERS           -- PLBv46 slave: Number of masters
+--   C_SPLB_MID_WIDTH             -- PLBv46 slave: master ID bus width
+--   C_SPLB_NATIVE_DWIDTH         -- PLBv46 slave: internal native data bus width
+--   C_SPLB_P2P                   -- PLBv46 slave: point to point interconnect scheme
+--   C_SPLB_SUPPORT_BURSTS        -- PLBv46 slave: support bursts
+--   C_SPLB_SMALLEST_MASTER       -- PLBv46 slave: width of the smallest master
+--   C_SPLB_CLK_PERIOD_PS         -- PLBv46 slave: bus clock in picoseconds
+--   C_INCLUDE_DPHASE_TIMER       -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
+--   C_FAMILY                     -- Xilinx FPGA family
+--   C_MEM0_BASEADDR              -- User memory space 0 base address
+--   C_MEM0_HIGHADDR              -- User memory space 0 high address
+--   C_MEM1_BASEADDR              -- User memory space 1 base address
+--   C_MEM1_HIGHADDR              -- User memory space 1 high address
+--
+-- Definition of Ports:
+--   SPLB_Clk                     -- PLB main bus clock
+--   SPLB_Rst                     -- PLB main bus reset
+--   PLB_ABus                     -- PLB address bus
+--   PLB_UABus                    -- PLB upper address bus
+--   PLB_PAValid                  -- PLB primary address valid indicator
+--   PLB_SAValid                  -- PLB secondary address valid indicator
+--   PLB_rdPrim                   -- PLB secondary to primary read request indicator
+--   PLB_wrPrim                   -- PLB secondary to primary write request indicator
+--   PLB_masterID                 -- PLB current master identifier
+--   PLB_abort                    -- PLB abort request indicator
+--   PLB_busLock                  -- PLB bus lock
+--   PLB_RNW                      -- PLB read/not write
+--   PLB_BE                       -- PLB byte enables
+--   PLB_MSize                    -- PLB master data bus size
+--   PLB_size                     -- PLB transfer size
+--   PLB_type                     -- PLB transfer type
+--   PLB_lockErr                  -- PLB lock error indicator
+--   PLB_wrDBus                   -- PLB write data bus
+--   PLB_wrBurst                  -- PLB burst write transfer indicator
+--   PLB_rdBurst                  -- PLB burst read transfer indicator
+--   PLB_wrPendReq                -- PLB write pending bus request indicator
+--   PLB_rdPendReq                -- PLB read pending bus request indicator
+--   PLB_wrPendPri                -- PLB write pending request priority
+--   PLB_rdPendPri                -- PLB read pending request priority
+--   PLB_reqPri                   -- PLB current request priority
+--   PLB_TAttribute               -- PLB transfer attribute
+--   Sl_addrAck                   -- Slave address acknowledge
+--   Sl_SSize                     -- Slave data bus size
+--   Sl_wait                      -- Slave wait indicator
+--   Sl_rearbitrate               -- Slave re-arbitrate bus indicator
+--   Sl_wrDAck                    -- Slave write data acknowledge
+--   Sl_wrComp                    -- Slave write transfer complete indicator
+--   Sl_wrBTerm                   -- Slave terminate write burst transfer
+--   Sl_rdDBus                    -- Slave read data bus
+--   Sl_rdWdAddr                  -- Slave read word address
+--   Sl_rdDAck                    -- Slave read data acknowledge
+--   Sl_rdComp                    -- Slave read transfer complete indicator
+--   Sl_rdBTerm                   -- Slave terminate read burst transfer
+--   Sl_MBusy                     -- Slave busy indicator
+--   Sl_MWrErr                    -- Slave write error indicator
+--   Sl_MRdErr                    -- Slave read error indicator
+--   Sl_MIRQ                      -- Slave interrupt indicator
+--   IP2INTC_Irpt                 -- Interrupt output to processor
+------------------------------------------------------------------------------
+
+entity spiifc is
+  generic
+  (
+    -- ADD USER GENERICS BELOW THIS LINE ---------------
+    --USER generics added here
+    -- ADD USER GENERICS ABOVE THIS LINE ---------------
+
+    -- DO NOT EDIT BELOW THIS LINE ---------------------
+    -- Bus protocol parameters, do not add to or delete
+    C_BASEADDR                     : std_logic_vector     := X"FFFFFFFF";
+    C_HIGHADDR                     : std_logic_vector     := X"00000000";
+    C_SPLB_AWIDTH                  : integer              := 32;
+    C_SPLB_DWIDTH                  : integer              := 128;
+    C_SPLB_NUM_MASTERS             : integer              := 8;
+    C_SPLB_MID_WIDTH               : integer              := 3;
+    C_SPLB_NATIVE_DWIDTH           : integer              := 32;
+    C_SPLB_P2P                     : integer              := 0;
+    C_SPLB_SUPPORT_BURSTS          : integer              := 1;
+    C_SPLB_SMALLEST_MASTER         : integer              := 32;
+    C_SPLB_CLK_PERIOD_PS           : integer              := 10000;
+    C_INCLUDE_DPHASE_TIMER         : integer              := 1;
+    C_FAMILY                       : string               := "virtex6";
+    C_MEM0_BASEADDR                : std_logic_vector     := X"FFFFFFFF";
+    C_MEM0_HIGHADDR                : std_logic_vector     := X"00000000";
+    C_MEM1_BASEADDR                : std_logic_vector     := X"FFFFFFFF";
+    C_MEM1_HIGHADDR                : std_logic_vector     := X"00000000"
+    -- DO NOT EDIT ABOVE THIS LINE ---------------------
+  );
+  port
+  (
+    -- ADD USER PORTS BELOW THIS LINE ------------------
+    --USER ports added here
+    -- ADD USER PORTS ABOVE THIS LINE ------------------
+
+    -- DO NOT EDIT BELOW THIS LINE ---------------------
+    -- Bus protocol ports, do not add to or delete
+    SPLB_Clk                       : in  std_logic;
+    SPLB_Rst                       : in  std_logic;
+    PLB_ABus                       : in  std_logic_vector(0 to 31);
+    PLB_UABus                      : in  std_logic_vector(0 to 31);
+    PLB_PAValid                    : in  std_logic;
+    PLB_SAValid                    : in  std_logic;
+    PLB_rdPrim                     : in  std_logic;
+    PLB_wrPrim                     : in  std_logic;
+    PLB_masterID                   : in  std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
+    PLB_abort                      : in  std_logic;
+    PLB_busLock                    : in  std_logic;
+    PLB_RNW                        : in  std_logic;
+    PLB_BE                         : in  std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
+    PLB_MSize                      : in  std_logic_vector(0 to 1);
+    PLB_size                       : in  std_logic_vector(0 to 3);
+    PLB_type                       : in  std_logic_vector(0 to 2);
+    PLB_lockErr                    : in  std_logic;
+    PLB_wrDBus                     : in  std_logic_vector(0 to C_SPLB_DWIDTH-1);
+    PLB_wrBurst                    : in  std_logic;
+    PLB_rdBurst                    : in  std_logic;
+    PLB_wrPendReq                  : in  std_logic;
+    PLB_rdPendReq                  : in  std_logic;
+    PLB_wrPendPri                  : in  std_logic_vector(0 to 1);
+    PLB_rdPendPri                  : in  std_logic_vector(0 to 1);
+    PLB_reqPri                     : in  std_logic_vector(0 to 1);
+    PLB_TAttribute                 : in  std_logic_vector(0 to 15);
+    Sl_addrAck                     : out std_logic;
+    Sl_SSize                       : out std_logic_vector(0 to 1);
+    Sl_wait                        : out std_logic;
+    Sl_rearbitrate                 : out std_logic;
+    Sl_wrDAck                      : out std_logic;
+    Sl_wrComp                      : out std_logic;
+    Sl_wrBTerm                     : out std_logic;
+    Sl_rdDBus                      : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
+    Sl_rdWdAddr                    : out std_logic_vector(0 to 3);
+    Sl_rdDAck                      : out std_logic;
+    Sl_rdComp                      : out std_logic;
+    Sl_rdBTerm                     : out std_logic;
+    Sl_MBusy                       : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
+    Sl_MWrErr                      : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
+    Sl_MRdErr                      : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
+    Sl_MIRQ                        : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
+    IP2INTC_Irpt                   : out std_logic
+    -- DO NOT EDIT ABOVE THIS LINE ---------------------
+  );
+
+  attribute MAX_FANOUT : string;
+  attribute SIGIS : string;
+
+  attribute SIGIS of SPLB_Clk      : signal is "CLK";
+  attribute SIGIS of SPLB_Rst      : signal is "RST";
+  attribute SIGIS of IP2INTC_Irpt  : signal is "INTR_LEVEL_HIGH";
+
+end entity spiifc;
+
+------------------------------------------------------------------------------
+-- Architecture section
+------------------------------------------------------------------------------
+
+architecture IMP of spiifc is
+
+  ------------------------------------------
+  -- Array of base/high address pairs for each address range
+  ------------------------------------------
+  constant ZERO_ADDR_PAD                  : std_logic_vector(0 to 31) := (others => '0');
+  constant USER_SLV_BASEADDR              : std_logic_vector     := C_BASEADDR or X"00000000";
+  constant USER_SLV_HIGHADDR              : std_logic_vector     := C_BASEADDR or X"000000FF";
+  constant INTR_BASEADDR                  : std_logic_vector     := C_BASEADDR or X"00000100";
+  constant INTR_HIGHADDR                  : std_logic_vector     := C_BASEADDR or X"000001FF";
+
+  constant IPIF_ARD_ADDR_RANGE_ARRAY      : SLV64_ARRAY_TYPE     := 
+    (
+      ZERO_ADDR_PAD & USER_SLV_BASEADDR,  -- user logic slave space base address
+      ZERO_ADDR_PAD & USER_SLV_HIGHADDR,  -- user logic slave space high address
+      ZERO_ADDR_PAD & INTR_BASEADDR,      -- interrupt control space base address
+      ZERO_ADDR_PAD & INTR_HIGHADDR,      -- interrupt control space high address
+      ZERO_ADDR_PAD & C_MEM0_BASEADDR,    -- user logic memory space 0 base address
+      ZERO_ADDR_PAD & C_MEM0_HIGHADDR,    -- user logic memory space 0 high address
+      ZERO_ADDR_PAD & C_MEM1_BASEADDR,    -- user logic memory space 1 base address
+      ZERO_ADDR_PAD & C_MEM1_HIGHADDR     -- user logic memory space 1 high address
+    );
+
+  ------------------------------------------
+  -- Array of desired number of chip enables for each address range
+  ------------------------------------------
+  constant USER_SLV_NUM_REG               : integer              := 16;
+  constant USER_NUM_REG                   : integer              := USER_SLV_NUM_REG;
+  constant INTR_NUM_CE                    : integer              := 16;
+  constant USER_NUM_MEM                   : integer              := 2;
+
+  constant IPIF_ARD_NUM_CE_ARRAY          : INTEGER_ARRAY_TYPE   := 
+    (
+      0  => pad_power2(USER_SLV_NUM_REG), -- number of ce for user logic slave space
+      1  => INTR_NUM_CE,                  -- number of ce for interrupt control space
+      2  => 1,                            -- number of ce for user logic memory space 0 (always 1 chip enable)
+      3  => 1                             -- number of ce for user logic memory space 1 (always 1 chip enable)
+    );
+
+  ------------------------------------------
+  -- Cache line addressing mode (for cacheline read operations)
+  -- 0 = target word first on reads
+  -- 1 = line word first on reads
+  ------------------------------------------
+  constant IPIF_CACHLINE_ADDR_MODE        : integer              := 0;
+
+  ------------------------------------------
+  -- Number of storage locations for the write buffer
+  -- Valid depths are 0, 16, 32, or 64
+  -- 0 = no write buffer implemented
+  ------------------------------------------
+  constant IPIF_WR_BUFFER_DEPTH           : integer              := 16;
+
+  ------------------------------------------
+  -- The type out of the Bus2IP_BurstLength signal
+  -- 0 = length is in actual byte number
+  -- 1 = length is in data beats - 1
+  ------------------------------------------
+  constant IPIF_BURSTLENGTH_TYPE          : integer              := 0;
+
+  ------------------------------------------
+  -- Width of the slave data bus (32, 64, or 128)
+  ------------------------------------------
+  constant USER_SLV_DWIDTH                : integer              := C_SPLB_NATIVE_DWIDTH;
+
+  constant IPIF_SLV_DWIDTH                : integer              := C_SPLB_NATIVE_DWIDTH;
+
+  ------------------------------------------
+  -- Number of device level interrupts
+  ------------------------------------------
+  constant INTR_NUM_IPIF_IRPT_SRC         : integer              := 4;
+
+  ------------------------------------------
+  -- Capture mode for each IP interrupt (generated by user logic)
+  -- 1 = pass through (non-inverting)
+  -- 2 = pass through (inverting)
+  -- 3 = registered level (non-inverting)
+  -- 4 = registered level (inverting)
+  -- 5 = positive edge detect
+  -- 6 = negative edge detect
+  ------------------------------------------
+  constant USER_NUM_INTR                  : integer              := 1;
+  constant USER_INTR_CAPTURE_MODE         : integer              := 1;
+
+  constant INTR_IP_INTR_MODE_ARRAY        : INTEGER_ARRAY_TYPE   := 
+    (
+      0  => USER_INTR_CAPTURE_MODE 
+    );
+
+  ------------------------------------------
+  -- Device priority encoder feature inclusion/omission
+  -- true  = include priority encoder
+  -- false = omit priority encoder
+  ------------------------------------------
+  constant INTR_INCLUDE_DEV_PENCODER      : boolean              := false;
+
+  ------------------------------------------
+  -- Device ISC feature inclusion/omission
+  -- true  = include device ISC
+  -- false = omit device ISC
+  ------------------------------------------
+  constant INTR_INCLUDE_DEV_ISC           : boolean              := false;
+
+  ------------------------------------------
+  -- Width of the slave address bus (32 only)
+  ------------------------------------------
+  constant USER_SLV_AWIDTH                : integer              := C_SPLB_AWIDTH;
+
+  ------------------------------------------
+  -- Index for CS/CE
+  ------------------------------------------
+  constant USER_SLV_CS_INDEX              : integer              := 0;
+  constant USER_SLV_CE_INDEX              : integer              := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
+  constant INTR_CS_INDEX                  : integer              := 1;
+  constant INTR_CE_INDEX                  : integer              := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, INTR_CS_INDEX);
+  constant USER_MEM0_CS_INDEX             : integer              := 2;
+  constant USER_CS_INDEX                  : integer              := USER_MEM0_CS_INDEX;
+
+  constant USER_CE_INDEX                  : integer              := USER_SLV_CE_INDEX;
+
+  ------------------------------------------
+  -- IP Interconnect (IPIC) signal declarations
+  ------------------------------------------
+  signal ipif_Bus2IP_Clk                : std_logic;
+  signal ipif_Bus2IP_Reset              : std_logic;
+  signal ipif_IP2Bus_Data               : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
+  signal ipif_IP2Bus_WrAck              : std_logic;
+  signal ipif_IP2Bus_RdAck              : std_logic;
+  signal ipif_IP2Bus_AddrAck            : std_logic;
+  signal ipif_IP2Bus_Error              : std_logic;
+  signal ipif_Bus2IP_Addr               : std_logic_vector(0 to C_SPLB_AWIDTH-1);
+  signal ipif_Bus2IP_Data               : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
+  signal ipif_Bus2IP_RNW                : std_logic;
+  signal ipif_Bus2IP_BE                 : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
+  signal ipif_Bus2IP_Burst              : std_logic;
+  signal ipif_Bus2IP_BurstLength        : std_logic_vector(0 to log2(16*(C_SPLB_DWIDTH/8)));
+  signal ipif_Bus2IP_WrReq              : std_logic;
+  signal ipif_Bus2IP_RdReq              : std_logic;
+  signal ipif_Bus2IP_CS                 : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
+  signal ipif_Bus2IP_RdCE               : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
+  signal ipif_Bus2IP_WrCE               : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
+  signal intr_IPIF_Reg_Interrupts       : std_logic_vector(0 to 1);
+  signal intr_IPIF_Lvl_Interrupts       : std_logic_vector(0 to INTR_NUM_IPIF_IRPT_SRC-1);
+  signal intr_IP2Bus_Data               : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
+  signal intr_IP2Bus_WrAck              : std_logic;
+  signal intr_IP2Bus_RdAck              : std_logic;
+  signal intr_IP2Bus_Error              : std_logic;
+  signal user_Bus2IP_RdCE               : std_logic_vector(0 to USER_NUM_REG-1);
+  signal user_Bus2IP_WrCE               : std_logic_vector(0 to USER_NUM_REG-1);
+  signal user_Bus2IP_BurstLength        : std_logic_vector(0 to 8)   := (others => '0');
+  signal user_IP2Bus_AddrAck            : std_logic;
+  signal user_IP2Bus_Data               : std_logic_vector(0 to USER_SLV_DWIDTH-1);
+  signal user_IP2Bus_RdAck              : std_logic;
+  signal user_IP2Bus_WrAck              : std_logic;
+  signal user_IP2Bus_Error              : std_logic;
+  signal user_IP2Bus_IntrEvent          : std_logic_vector(0 to USER_NUM_INTR-1);
+
+  ------------------------------------------
+  -- Component declaration for verilog user logic
+  ------------------------------------------
+  component user_logic is
+    generic
+    (
+      -- ADD USER GENERICS BELOW THIS LINE ---------------
+      --USER generics added here
+      -- ADD USER GENERICS ABOVE THIS LINE ---------------
+
+      -- DO NOT EDIT BELOW THIS LINE ---------------------
+      -- Bus protocol parameters, do not add to or delete
+      C_SLV_AWIDTH                   : integer              := 32;
+      C_SLV_DWIDTH                   : integer              := 32;
+      C_NUM_REG                      : integer              := 16;
+      C_NUM_MEM                      : integer              := 2;
+      C_NUM_INTR                     : integer              := 1
+      -- DO NOT EDIT ABOVE THIS LINE ---------------------
+    );
+    port
+    (
+      -- ADD USER PORTS BELOW THIS LINE ------------------
+      --USER ports added here
+      -- ADD USER PORTS ABOVE THIS LINE ------------------
+
+      -- DO NOT EDIT BELOW THIS LINE ---------------------
+      -- Bus protocol ports, do not add to or delete
+      Bus2IP_Clk                     : in  std_logic;
+      Bus2IP_Reset                   : in  std_logic;
+      Bus2IP_Addr                    : in  std_logic_vector(0 to C_SLV_AWIDTH-1);
+      Bus2IP_CS                      : in  std_logic_vector(0 to C_NUM_MEM-1);
+      Bus2IP_RNW                     : in  std_logic;
+      Bus2IP_Data                    : in  std_logic_vector(0 to C_SLV_DWIDTH-1);
+      Bus2IP_BE                      : in  std_logic_vector(0 to C_SLV_DWIDTH/8-1);
+      Bus2IP_RdCE                    : in  std_logic_vector(0 to C_NUM_REG-1);
+      Bus2IP_WrCE                    : in  std_logic_vector(0 to C_NUM_REG-1);
+      Bus2IP_Burst                   : in  std_logic;
+      Bus2IP_BurstLength             : in  std_logic_vector(0 to 8);
+      Bus2IP_RdReq                   : in  std_logic;
+      Bus2IP_WrReq                   : in  std_logic;
+      IP2Bus_AddrAck                 : out std_logic;
+      IP2Bus_Data                    : out std_logic_vector(0 to C_SLV_DWIDTH-1);
+      IP2Bus_RdAck                   : out std_logic;
+      IP2Bus_WrAck                   : out std_logic;
+      IP2Bus_Error                   : out std_logic;
+      IP2Bus_IntrEvent               : out std_logic_vector(0 to C_NUM_INTR-1)
+      -- DO NOT EDIT ABOVE THIS LINE ---------------------
+    );
+  end component user_logic;
+
+begin
+
+  ------------------------------------------
+  -- instantiate plbv46_slave_burst
+  ------------------------------------------
+  PLBV46_SLAVE_BURST_I : entity plbv46_slave_burst_v1_01_a.plbv46_slave_burst
+    generic map
+    (
+      C_ARD_ADDR_RANGE_ARRAY         => IPIF_ARD_ADDR_RANGE_ARRAY,
+      C_ARD_NUM_CE_ARRAY             => IPIF_ARD_NUM_CE_ARRAY,
+      C_SPLB_P2P                     => C_SPLB_P2P,
+      C_CACHLINE_ADDR_MODE           => IPIF_CACHLINE_ADDR_MODE,
+      C_WR_BUFFER_DEPTH              => IPIF_WR_BUFFER_DEPTH,
+      C_BURSTLENGTH_TYPE             => IPIF_BURSTLENGTH_TYPE,
+      C_SPLB_MID_WIDTH               => C_SPLB_MID_WIDTH,
+      C_SPLB_NUM_MASTERS             => C_SPLB_NUM_MASTERS,
+      C_SPLB_SMALLEST_MASTER         => C_SPLB_SMALLEST_MASTER,
+      C_SPLB_AWIDTH                  => C_SPLB_AWIDTH,
+      C_SPLB_DWIDTH                  => C_SPLB_DWIDTH,
+      C_SIPIF_DWIDTH                 => IPIF_SLV_DWIDTH,
+      C_INCLUDE_DPHASE_TIMER         => C_INCLUDE_DPHASE_TIMER,
+      C_FAMILY                       => C_FAMILY
+    )
+    port map
+    (
+      SPLB_Clk                       => SPLB_Clk,
+      SPLB_Rst                       => SPLB_Rst,
+      PLB_ABus                       => PLB_ABus,
+      PLB_UABus                      => PLB_UABus,
+      PLB_PAValid                    => PLB_PAValid,
+      PLB_SAValid                    => PLB_SAValid,
+      PLB_rdPrim                     => PLB_rdPrim,
+      PLB_wrPrim                     => PLB_wrPrim,
+      PLB_masterID                   => PLB_masterID,
+      PLB_abort                      => PLB_abort,
+      PLB_busLock                    => PLB_busLock,
+      PLB_RNW                        => PLB_RNW,
+      PLB_BE                         => PLB_BE,
+      PLB_MSize                      => PLB_MSize,
+      PLB_size                       => PLB_size,
+      PLB_type                       => PLB_type,
+      PLB_lockErr                    => PLB_lockErr,
+      PLB_wrDBus                     => PLB_wrDBus,
+      PLB_wrBurst                    => PLB_wrBurst,
+      PLB_rdBurst                    => PLB_rdBurst,
+      PLB_wrPendReq                  => PLB_wrPendReq,
+      PLB_rdPendReq                  => PLB_rdPendReq,
+      PLB_wrPendPri                  => PLB_wrPendPri,
+      PLB_rdPendPri                  => PLB_rdPendPri,
+      PLB_reqPri                     => PLB_reqPri,
+      PLB_TAttribute                 => PLB_TAttribute,
+      Sl_addrAck                     => Sl_addrAck,
+      Sl_SSize                       => Sl_SSize,
+      Sl_wait                        => Sl_wait,
+      Sl_rearbitrate                 => Sl_rearbitrate,
+      Sl_wrDAck                      => Sl_wrDAck,
+      Sl_wrComp                      => Sl_wrComp,
+      Sl_wrBTerm                     => Sl_wrBTerm,
+      Sl_rdDBus                      => Sl_rdDBus,
+      Sl_rdWdAddr                    => Sl_rdWdAddr,
+      Sl_rdDAck                      => Sl_rdDAck,
+      Sl_rdComp                      => Sl_rdComp,
+      Sl_rdBTerm                     => Sl_rdBTerm,
+      Sl_MBusy                       => Sl_MBusy,
+      Sl_MWrErr                      => Sl_MWrErr,
+      Sl_MRdErr                      => Sl_MRdErr,
+      Sl_MIRQ                        => Sl_MIRQ,
+      Bus2IP_Clk                     => ipif_Bus2IP_Clk,
+      Bus2IP_Reset                   => ipif_Bus2IP_Reset,
+      IP2Bus_Data                    => ipif_IP2Bus_Data,
+      IP2Bus_WrAck                   => ipif_IP2Bus_WrAck,
+      IP2Bus_RdAck                   => ipif_IP2Bus_RdAck,
+      IP2Bus_AddrAck                 => ipif_IP2Bus_AddrAck,
+      IP2Bus_Error                   => ipif_IP2Bus_Error,
+      Bus2IP_Addr                    => ipif_Bus2IP_Addr,
+      Bus2IP_Data                    => ipif_Bus2IP_Data,
+      Bus2IP_RNW                     => ipif_Bus2IP_RNW,
+      Bus2IP_BE                      => ipif_Bus2IP_BE,
+      Bus2IP_Burst                   => ipif_Bus2IP_Burst,
+      Bus2IP_BurstLength             => ipif_Bus2IP_BurstLength,
+      Bus2IP_WrReq                   => ipif_Bus2IP_WrReq,
+      Bus2IP_RdReq                   => ipif_Bus2IP_RdReq,
+      Bus2IP_CS                      => ipif_Bus2IP_CS,
+      Bus2IP_RdCE                    => ipif_Bus2IP_RdCE,
+      Bus2IP_WrCE                    => ipif_Bus2IP_WrCE
+    );
+
+  ------------------------------------------
+  -- instantiate interrupt_control
+  ------------------------------------------
+  INTERRUPT_CONTROL_I : entity interrupt_control_v2_01_a.interrupt_control
+    generic map
+    (
+      C_NUM_CE                       => INTR_NUM_CE,
+      C_NUM_IPIF_IRPT_SRC            => INTR_NUM_IPIF_IRPT_SRC,
+      C_IP_INTR_MODE_ARRAY           => INTR_IP_INTR_MODE_ARRAY,
+      C_INCLUDE_DEV_PENCODER         => INTR_INCLUDE_DEV_PENCODER,
+      C_INCLUDE_DEV_ISC              => INTR_INCLUDE_DEV_ISC,
+      C_IPIF_DWIDTH                  => IPIF_SLV_DWIDTH
+    )
+    port map
+    (
+      Bus2IP_Clk                     => ipif_Bus2IP_Clk,
+      Bus2IP_Reset                   => ipif_Bus2IP_Reset,
+      Bus2IP_Data                    => ipif_Bus2IP_Data,
+      Bus2IP_BE                      => ipif_Bus2IP_BE,
+      Interrupt_RdCE                 => ipif_Bus2IP_RdCE(INTR_CE_INDEX to INTR_CE_INDEX+INTR_NUM_CE-1),
+      Interrupt_WrCE                 => ipif_Bus2IP_WrCE(INTR_CE_INDEX to INTR_CE_INDEX+INTR_NUM_CE-1),
+      IPIF_Reg_Interrupts            => intr_IPIF_Reg_Interrupts,
+      IPIF_Lvl_Interrupts            => intr_IPIF_Lvl_Interrupts,
+      IP2Bus_IntrEvent               => user_IP2Bus_IntrEvent,
+      Intr2Bus_DevIntr               => IP2INTC_Irpt,
+      Intr2Bus_DBus                  => intr_IP2Bus_Data,
+      Intr2Bus_WrAck                 => intr_IP2Bus_WrAck,
+      Intr2Bus_RdAck                 => intr_IP2Bus_RdAck,
+      Intr2Bus_Error                 => intr_IP2Bus_Error,
+      Intr2Bus_Retry                 => open,
+      Intr2Bus_ToutSup               => open
+    );
+
+  -- feed registered and level-pass-through interrupts into Device ISC if exists, otherwise ignored
+  intr_IPIF_Reg_Interrupts(0) <= '0';
+  intr_IPIF_Reg_Interrupts(1) <= '0';
+  intr_IPIF_Lvl_Interrupts(0) <= '0';
+  intr_IPIF_Lvl_Interrupts(1) <= '0';
+  intr_IPIF_Lvl_Interrupts(2) <= '0';
+  intr_IPIF_Lvl_Interrupts(3) <= '0';
+
+  ------------------------------------------
+  -- instantiate User Logic
+  ------------------------------------------
+  USER_LOGIC_I : component user_logic
+    generic map
+    (
+      -- MAP USER GENERICS BELOW THIS LINE ---------------
+      --USER generics mapped here
+      -- MAP USER GENERICS ABOVE THIS LINE ---------------
+
+      C_SLV_AWIDTH                   => USER_SLV_AWIDTH,
+      C_SLV_DWIDTH                   => USER_SLV_DWIDTH,
+      C_NUM_REG                      => USER_NUM_REG,
+      C_NUM_MEM                      => USER_NUM_MEM,
+      C_NUM_INTR                     => USER_NUM_INTR
+    )
+    port map
+    (
+      -- MAP USER PORTS BELOW THIS LINE ------------------
+      --USER ports mapped here
+      -- MAP USER PORTS ABOVE THIS LINE ------------------
+
+      Bus2IP_Clk                     => ipif_Bus2IP_Clk,
+      Bus2IP_Reset                   => ipif_Bus2IP_Reset,
+      Bus2IP_Addr                    => ipif_Bus2IP_Addr,
+      Bus2IP_CS                      => ipif_Bus2IP_CS(USER_CS_INDEX to USER_CS_INDEX+USER_NUM_MEM-1),
+      Bus2IP_RNW                     => ipif_Bus2IP_RNW,
+      Bus2IP_Data                    => ipif_Bus2IP_Data,
+      Bus2IP_BE                      => ipif_Bus2IP_BE,
+      Bus2IP_RdCE                    => user_Bus2IP_RdCE,
+      Bus2IP_WrCE                    => user_Bus2IP_WrCE,
+      Bus2IP_Burst                   => ipif_Bus2IP_Burst,
+      Bus2IP_BurstLength             => user_Bus2IP_BurstLength,
+      Bus2IP_RdReq                   => ipif_Bus2IP_RdReq,
+      Bus2IP_WrReq                   => ipif_Bus2IP_WrReq,
+      IP2Bus_AddrAck                 => user_IP2Bus_AddrAck,
+      IP2Bus_Data                    => user_IP2Bus_Data,
+      IP2Bus_RdAck                   => user_IP2Bus_RdAck,
+      IP2Bus_WrAck                   => user_IP2Bus_WrAck,
+      IP2Bus_Error                   => user_IP2Bus_Error,
+      IP2Bus_IntrEvent               => user_IP2Bus_IntrEvent
+    );
+
+  ------------------------------------------
+  -- connect internal signals
+  ------------------------------------------
+  IP2BUS_DATA_MUX_PROC : process( ipif_Bus2IP_CS, user_IP2Bus_Data, intr_IP2Bus_Data ) is
+  begin
+
+    case ipif_Bus2IP_CS is
+      when "1000" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
+      when "0100" => ipif_IP2Bus_Data <= intr_IP2Bus_Data;
+      when "0010" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
+      when "0001" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
+      when others => ipif_IP2Bus_Data <= (others => '0');
+    end case;
+
+  end process IP2BUS_DATA_MUX_PROC;
+
+  ipif_IP2Bus_AddrAck <= ipif_Bus2IP_Burst and user_IP2Bus_AddrAck;
+  ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck or intr_IP2Bus_WrAck;
+  ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck or intr_IP2Bus_RdAck;
+  ipif_IP2Bus_Error <= user_IP2Bus_Error or intr_IP2Bus_Error;
+
+  user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
+  user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
+
+  user_Bus2IP_BurstLength(8-log2(16*(C_SPLB_DWIDTH/8)) to 8) <= ipif_Bus2IP_BurstLength;
+
+end IMP;

projnav/xps/system.log

@@ -47,3 +47,17 @@ Done writing filter settings to:
 	C:\Users\mjlyons\workspace\vSPI\projnav\xps\etc\system.filters
 Done writing Tab View settings to:
 	C:\Users\mjlyons\workspace\vSPI\projnav\xps\etc\system.gui
+Xilinx Platform Studio (XPS)
+Xilinx EDK 13.2 Build EDK_O.61xd
+Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
+
+Writing filter settings....
+Done writing filter settings to:
+	C:\Users\mjlyons\workspace\vSPI\projnav\xps\etc\system.filters
+Done writing Tab View settings to:
+	C:\Users\mjlyons\workspace\vSPI\projnav\xps\etc\system.gui
+Writing filter settings....
+Done writing filter settings to:
+	C:\Users\mjlyons\workspace\vSPI\projnav\xps\etc\system.filters
+Done writing Tab View settings to:
+	C:\Users\mjlyons\workspace\vSPI\projnav\xps\etc\system.gui