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grabor
Commit 68fbc2fb authored by Upi Tamminen's avatar Upi Tamminen
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Some verilog renames

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verilog/cpldtest1.qpf deleted 100644 → 0
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2011 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 32-bit
# Version 11.1 Build 259 01/25/2012 Service Pack 2.11 SJ Web Edition
# Date created = 12:28:47 January 21, 2013
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "11.1"
DATE = "12:28:47 January 21, 2013"
# Revisions
PROJECT_REVISION = "grabor"
verilog/cpldtest1.qsf deleted 100644 → 0
View file @ 45999dcd
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2011 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 32-bit
# Version 11.1 Build 259 01/25/2012 Service Pack 2.11 SJ Web Edition
# Date created = 12:28:47 January 21, 2013
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# grabor_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "MAX II"
set_global_assignment -name DEVICE EPM240T100C5
set_global_assignment -name TOP_LEVEL_ENTITY grabor
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "11.1 SP2.11"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:28:47 JANUARY 21, 2013"
set_global_assignment -name LAST_QUARTUS_VERSION "11.1 SP2.11"
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
set_global_assignment -name POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR 3.3V
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_location_assignment PIN_73 -to LED
set_location_assignment PIN_64 -to clk
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
set_location_assignment PIN_55 -to PIXEL[7]
set_location_assignment PIN_54 -to PIXEL[6]
set_location_assignment PIN_53 -to PIXEL[5]
set_location_assignment PIN_52 -to PIXEL[4]
set_location_assignment PIN_51 -to PIXEL[3]
set_location_assignment PIN_50 -to PIXEL[2]
set_location_assignment PIN_49 -to PIXEL[1]
set_location_assignment PIN_48 -to PIXEL[0]
set_location_assignment PIN_66 -to HSYNC
set_location_assignment PIN_67 -to VSYNC
set_location_assignment PIN_84 -to SRAM_IO[5]
set_location_assignment PIN_85 -to SRAM_IO[4]
set_location_assignment PIN_86 -to SRAM_ADDR[14]
set_location_assignment PIN_87 -to SRAM_ADDR[13]
set_location_assignment PIN_88 -to SRAM_ADDR[12]
set_location_assignment PIN_89 -to SRAM_ADDR[11]
set_location_assignment PIN_90 -to SRAM_ADDR[10]
set_location_assignment PIN_91 -to SRAM_IO[6]
set_location_assignment PIN_92 -to SRAM_IO[7]
set_location_assignment PIN_95 -to SRAM_OE
set_location_assignment PIN_96 -to SRAM_ADDR[15]
set_location_assignment PIN_97 -to SRAM_ADDR[16]
set_location_assignment PIN_98 -to SRAM_ADDR[17]
set_location_assignment PIN_99 -to SRAM_ADDR[18]
set_location_assignment PIN_100 -to SRAM_ADDR[0]
set_location_assignment PIN_1 -to SRAM_ADDR[1]
set_location_assignment PIN_4 -to SRAM_ADDR[4]
set_location_assignment PIN_3 -to SRAM_ADDR[3]
set_location_assignment PIN_2 -to SRAM_ADDR[2]
set_location_assignment PIN_5 -to SRAM_CE
set_location_assignment PIN_15 -to SRAM_IO[3]
set_location_assignment PIN_8 -to SRAM_IO[2]
set_location_assignment PIN_7 -to SRAM_IO[1]
set_location_assignment PIN_6 -to SRAM_IO[0]
set_location_assignment PIN_16 -to SRAM_WE
set_location_assignment PIN_17 -to SRAM_ADDR[9]
set_location_assignment PIN_18 -to SRAM_ADDR[8]
set_location_assignment PIN_19 -to SRAM_ADDR[7]
set_location_assignment PIN_20 -to SRAM_ADDR[6]
set_location_assignment PIN_21 -to SRAM_ADDR[5]
set_location_assignment PIN_37 -to PIXELOUT[7]
set_location_assignment PIN_36 -to PIXELOUT[6]
set_location_assignment PIN_35 -to PIXELOUT[5]
set_location_assignment PIN_34 -to PIXELOUT[4]
set_location_assignment PIN_33 -to PIXELOUT[3]
set_location_assignment PIN_28 -to PIXELOUT[2]
set_location_assignment PIN_27 -to PIXELOUT[1]
set_location_assignment PIN_26 -to PIXELOUT[0]
set_location_assignment PIN_40 -to SAVE
set_location_assignment PIN_41 -to XFR
set_location_assignment PIN_42 -to OUTCLK
set_global_assignment -name CDF_FILE Chain1.cdf
verilog/cpldtest1.v deleted 100644 → 0
View file @ 45999dcd
/* Copyright (C) 2013 Upi Tamminen
* See the COPYRIGHT file for more information */
module grabor(clk,
SRAM_ADDR, SRAM_IO, SRAM_OE, SRAM_CE, SRAM_WE,
SAVE, XFR, OUTCLK,
HSYNC, VSYNC, PIXEL,
PIXELOUT, LED);
input clk;
output LED;
input HSYNC;
input VSYNC;
input [7:0] PIXEL;
output reg [7:0] PIXELOUT; // DMA output to MCU
input SAVE;
input XFR;
output reg OUTCLK;
/* SRAM definitions */
output SRAM_OE;
output SRAM_CE;
output SRAM_WE;
inout SRAM_IO;
output SRAM_ADDR;
reg [18:0] SRAM_ADDR;
reg [7:0] SRAM_IO;
/* main blink turn on */
blinker Blinker(clk, LED);
/* SRAM controller */
reg [7:0] sram_q;
reg [18:0] sram_address;
reg [7:0] sram_d;
reg sram_wren;
sramctrl SRAMCtrl(clk, sram_wren, sram_d, sram_q, sram_address,
SRAM_WE, SRAM_CE, SRAM_OE, SRAM_IO, SRAM_ADDR);
/* fun */
reg [15:0] active_line;
reg [15:0] active_column;
reg [15:0] num_columns; // keep the total number of columns here
reg [15:0] num_rows; // keep the total number of rows here
reg can_save;
reg saving;
reg save_done;
reg [2:0] VSYNCr;
always @(posedge clk) VSYNCr <= {VSYNCr[1:0], VSYNC};
wire VSYNC_risingedge = (VSYNCr[2:1] == 2'b01);
wire VSYNC_fallingedge = (VSYNCr[2:1] == 2'b10);
wire VSYNC_active = ~VSYNCr[1];
reg [2:0] HSYNCr;
always @(posedge clk) HSYNCr <= {HSYNCr[1:0], HSYNC};
wire HSYNC_risingedge = (HSYNCr[2:1] == 2'b01);
wire HSYNC_fallingedge = (HSYNCr[2:1] == 2'b10);
wire HSYNC_active = ~HSYNCr[1];
/* save pin goes high = save */
reg [2:0] SAVEr;
always @(posedge clk) SAVEr <= {SAVEr[1:0], SAVE};
wire SAVE_risingedge = (SAVEr[2:1] == 2'b01);
/* xfr pin goes high = start clocking out data */
reg [2:0] XFRr;
always @(posedge clk) XFRr <= {XFRr[1:0], XFR};
wire XFR_risingedge = (XFRr[2:1] == 2'b01);
reg [13:0] pulse; /* temp test for pulses */
reg pulseflip;
reg [4:0] pulsediv;
always @(posedge clk) begin
/* DMA transfer to MCU */
pulsediv <= pulsediv + 1;
if (pulsediv == 2'b00000) begin
if (pulseflip) begin
if (pulse > 0 && pulse <= 2048) begin
PIXELOUT <= sram_q;
//PIXELOUT <= 8'b11111111;
OUTCLK <= 1'b1;
pulse <= pulse + 1;
sram_address <= sram_address + 1;
end else begin
OUTCLK <= 1'b0;
end
pulseflip = 0;
end else begin
OUTCLK <= 1'b0;
pulseflip = 1;
end
end
if (~HSYNC_active) begin
active_column = active_column + 1;
if (saving) begin
sram_address <= sram_address + 1;
sram_d <= PIXEL;
//sram_d <= 8'b00000010;
//sram_d = color_toggle == 1 ? 8'b11100000 : 8'b00011100;
sram_wren <= 1;
end
end
/* line begins */
if (HSYNC_risingedge) begin
active_line <= active_line + 1;
active_column <= 0;
/* line ends */
end else if (HSYNC_fallingedge) begin
num_columns <= active_column;
end
/* frame begins */
if (VSYNC_risingedge) begin
active_line <= 0;
if (can_save && !saving) begin
can_save <= 0;
saving <= 1;
sram_address <= 0;
sram_wren <= 0;
end
/* frame ends */
end else if (VSYNC_fallingedge) begin
num_rows <= active_line;
if (saving) begin
save_done <= 1;
sram_address <= 0;
saving <= 0;
sram_wren <= 0;
end
end
if (SAVE_risingedge) begin
saving <= 0;
can_save <= 1;
end
if (XFR_risingedge) begin
pulse <= 1'b1;
end
end
endmodule
/* vim: set sw=4 et: */
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