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RPi_Hat_Template
Commit 8e6d07cd authored by Dave Vandenbout's avatar Dave Vandenbout
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README.md 0 → 100644
View file @ 8e6d07cd
% RPi B+ Hat
Raspberry Pi B+ Hat
============================
Expansion Board
----------------------------
This is a project template for a
[Raspberry Pi B+ Hat](https://github.com/raspberrypi/hats).
This base project includes a PCB edge defined according to
[this specification](https://github.com/raspberrypi/hats/blob/master/hat-board-mechanical.pdf).
Both a thru-hole and a surface mount connector are provided, along with a different
PCB edge for each. Just keep the PCB edge and connector type that you're using for your design
and delete the others.
The board outline looks like this:
<img src="brd.png" style="width:100%">
(c)2015 XESS Corp.
RPi_GPIO.sch 0 → 100644
View file @ 8e6d07cd
EESchema Schematic File Version 2
LIBS:power
LIBS:device
LIBS:transistors
LIBS:conn
LIBS:linear
LIBS:regul
LIBS:74xx
LIBS:cmos4000
LIBS:adc-dac
LIBS:memory
LIBS:xilinx
LIBS:special
LIBS:microcontrollers
LIBS:dsp
LIBS:microchip
LIBS:analog_switches
LIBS:motorola
LIBS:texas
LIBS:intel
LIBS:audio
LIBS:interface
LIBS:digital-audio
LIBS:philips
LIBS:display
LIBS:cypress
LIBS:siliconi
LIBS:opto
LIBS:atmel
LIBS:contrib
LIBS:valves
LIBS:xess
LIBS:RPi_Hat-cache
EELAYER 25 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 2 2
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Comp
L RPi_GPIO J1
U 1 1 5515D39E
P 2750 2700
F 0 "J1" H 3500 2950 60 0000 C CNN
F 1 "RPi_GPIO" H 3500 2850 60 0000 C CNN
F 2 "XESS:Samtec_HLE-120-02-XXX-DV-BE-XX-XX" H 2750 2700 60 0001 C CNN
F 3 "" H 2750 2700 60 0000 C CNN
1 2750 2700
1 0 0 -1
$EndComp
$Comp
L RPi_GPIO J2
U 1 1 5516AE26
P 7500 2700
F 0 "J2" H 8250 2950 60 0000 C CNN
F 1 "RPi_GPIO" H 8250 2850 60 0000 C CNN
F 2 "Pin_Headers:Pin_Header_Straight_2x20" H 7500 2700 60 0001 C CNN
F 3 "" H 7500 2700 60 0000 C CNN
1 7500 2700
1 0 0 -1
$EndComp
Text Notes 2950 5000 0 60 Italic 0
Surface Mount Connector
Text Notes 7800 5000 0 60 Italic 0
Thru-Hole Connector
$EndSCHEMATC
RPi_Hat-cache.lib 0 → 100644
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EESchema-LIBRARY Version 2.3
#encoding utf-8
#
# RPi_GPIO
#
DEF RPi_GPIO J 0 40 Y Y 1 F N
F0 "J" 750 250 60 H V C CNN
F1 "RPi_GPIO" 750 150 60 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
S 0 100 1500 -2000 0 1 0 N
X 3.3V 1 -200 0 200 R 50 50 1 1 W I
X 5V 2 1700 0 200 L 50 50 1 1 W I
X GPIO02_SDA1_I2C 3 -200 -100 200 R 50 50 1 1 B I
X 5V 4 1700 -100 200 L 50 50 1 1 W I
X GPIO03_SCL1_I2C 5 -200 -200 200 R 50 50 1 1 B I
X GND 6 1700 -200 200 L 50 50 1 1 W I
X GPIO04_GCLK 7 -200 -300 200 R 50 50 1 1 B I
X GPIO14_TXD0 8 1700 -300 200 L 50 50 1 1 B I
X GND 9 -200 -400 200 R 50 50 1 1 W I
X GPIO15_RXD0 10 1700 -400 200 L 50 50 1 1 B I
X GND 20 1700 -900 200 L 50 50 1 1 W I
X GND 30 1700 -1400 200 L 50 50 1 1 W I
X GPIO21 40 1700 -1900 200 L 50 50 1 1 B I
X GPIO17 11 -200 -500 200 R 50 50 1 1 B I
X GPIO09_SPI_MISO 21 -200 -1000 200 R 50 50 1 1 B I
X GPIO06 31 -200 -1500 200 R 50 50 1 1 B I
X GPIO18 12 1700 -500 200 L 50 50 1 1 B I
X GPIO25 22 1700 -1000 200 L 50 50 1 1 B I
X GPIO12 32 1700 -1500 200 L 50 50 1 1 B I
X GPIO27 13 -200 -600 200 R 50 50 1 1 B I
X GPIO11_SPI_CLK 23 -200 -1100 200 R 50 50 1 1 B I
X GPIO13 33 -200 -1600 200 R 50 50 1 1 B I
X GND 14 1700 -600 200 L 50 50 1 1 W I
X GPIO08_SPI_CE0_N 24 1700 -1100 200 L 50 50 1 1 B I
X GND 34 1700 -1600 200 L 50 50 1 1 W I
X GPIO22 15 -200 -700 200 R 50 50 1 1 B I
X GND 25 -200 -1200 200 R 50 50 1 1 W I
X GPIO19 35 -200 -1700 200 R 50 50 1 1 B I
X GPIO23 16 1700 -700 200 L 50 50 1 1 B I
X GPIO07_SPI_CE1_N 26 1700 -1200 200 L 50 50 1 1 B I
X GPIO16 36 1700 -1700 200 L 50 50 1 1 B I
X 3.3V 17 -200 -800 200 R 50 50 1 1 W I
X ID_SD 27 -200 -1300 200 R 50 50 1 1 B I
X GPIO26 37 -200 -1800 200 R 50 50 1 1 B I
X GPIO24 18 1700 -800 200 L 50 50 1 1 B I
X ID_SC 28 1700 -1300 200 L 50 50 1 1 B I
X GPIO20 38 1700 -1800 200 L 50 50 1 1 B I
X GPIO10_SPI_MOSI 19 -200 -900 200 R 50 50 1 1 B I
X GPIO05 29 -200 -1400 200 R 50 50 1 1 B I
X GND 39 -200 -1900 200 R 50 50 1 1 W I
ENDDRAW
ENDDEF
#
#End Library
RPi_Hat.cmp 0 → 100644
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Cmp-Mod V01 Created by Cvpcb (2015-03-15 BZR 5517)-product date = 03/28/2015 9:36:24 AM
BeginCmp
TimeStamp = /5515D395/5515D39E;
Reference = J1;
ValeurCmp = RPi_GPIO;
IdModule = XESS:Samtec_HLE-120-02-XXX-DV-BE-XX-XX;
EndCmp
BeginCmp
TimeStamp = /5515D395/5516AE26;
Reference = J2;
ValeurCmp = RPi_GPIO;
IdModule = Pin_Headers:Pin_Header_Straight_2x20;
EndCmp
EndListe
RPi_Hat.kicad_pcb 0 → 100644
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RPi_Hat.net 0 → 100644
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(export (version D)
(design
(source C:/xesscorp/PRODUCTS/RPi_Hat/pcb/stickit_hat.sch)
(date "03/28/2015 9:35:50 AM")
(tool "Eeschema (2015-03-15 BZR 5517)-product")
(sheet (number 1) (name /) (tstamps /)
(title_block
(title)
(company)
(rev)
(date)
(source stickit_hat.sch)
(comment (number 1) (value ""))
(comment (number 2) (value ""))
(comment (number 3) (value ""))
(comment (number 4) (value ""))))
(sheet (number 2) (name /RPi_GPIO/) (tstamps /5515D395/)
(title_block
(title)
(company)
(rev)
(date)
(source RPi_GPIO.sch)
(comment (number 1) (value ""))
(comment (number 2) (value ""))
(comment (number 3) (value ""))
(comment (number 4) (value "")))))
(components
(comp (ref J1)
(value RPi_GPIO)
(footprint XESS:Samtec_HLE-120-02-XXX-DV-BE-XX-XX)
(libsource (lib xess) (part RPi_GPIO))
(sheetpath (names /RPi_GPIO/) (tstamps /5515D395/))
(tstamp 5515D39E))
(comp (ref J2)
(value RPi_GPIO)
(footprint XESS:Samtec_HLE-120-02-XXX-DV-BE-XX-XX)
(libsource (lib xess) (part RPi_GPIO))
(sheetpath (names /RPi_GPIO/) (tstamps /5515D395/))
(tstamp 5516AE26)))
(libparts
(libpart (lib xess) (part RPi_GPIO)
(fields
(field (name Reference) J)
(field (name Value) RPi_GPIO))
(pins
(pin (num 1) (name 3.3V) (type power_in))
(pin (num 2) (name 5V) (type power_in))
(pin (num 3) (name GPIO02_SDA1_I2C) (type BiDi))
(pin (num 4) (name 5V) (type power_in))
(pin (num 5) (name GPIO03_SCL1_I2C) (type BiDi))
(pin (num 6) (name GND) (type power_in))
(pin (num 7) (name GPIO04_GCLK) (type BiDi))
(pin (num 8) (name GPIO14_TXD0) (type BiDi))
(pin (num 9) (name GND) (type power_in))
(pin (num 10) (name GPIO15_RXD0) (type BiDi))
(pin (num 11) (name GPIO17) (type BiDi))
(pin (num 12) (name GPIO18) (type BiDi))
(pin (num 13) (name GPIO27) (type BiDi))
(pin (num 14) (name GND) (type power_in))
(pin (num 15) (name GPIO22) (type BiDi))
(pin (num 16) (name GPIO23) (type BiDi))
(pin (num 17) (name 3.3V) (type power_in))
(pin (num 18) (name GPIO24) (type BiDi))
(pin (num 19) (name GPIO10_SPI_MOSI) (type BiDi))
(pin (num 20) (name GND) (type power_in))
(pin (num 21) (name GPIO09_SPI_MISO) (type BiDi))
(pin (num 22) (name GPIO25) (type BiDi))
(pin (num 23) (name GPIO11_SPI_CLK) (type BiDi))
(pin (num 24) (name GPIO08_SPI_CE0_N) (type BiDi))
(pin (num 25) (name GND) (type power_in))
(pin (num 26) (name GPIO07_SPI_CE1_N) (type BiDi))
(pin (num 27) (name ID_SD) (type BiDi))
(pin (num 28) (name ID_SC) (type BiDi))
(pin (num 29) (name GPIO05) (type BiDi))
(pin (num 30) (name GND) (type power_in))
(pin (num 31) (name GPIO06) (type BiDi))
(pin (num 32) (name GPIO12) (type BiDi))
(pin (num 33) (name GPIO13) (type BiDi))
(pin (num 34) (name GND) (type power_in))
(pin (num 35) (name GPIO19) (type BiDi))
(pin (num 36) (name GPIO16) (type BiDi))
(pin (num 37) (name GPIO26) (type BiDi))
(pin (num 38) (name GPIO20) (type BiDi))
(pin (num 39) (name GND) (type power_in))
(pin (num 40) (name GPIO21) (type BiDi)))))
(libraries
(library (logical xess)
(uri C:\xesscorp\KiCad\libraries\xess.lib)))
(nets
(net (code 1) (name "Net-(J2-Pad20)")
(node (ref J2) (pin 20)))
(net (code 2) (name "Net-(J2-Pad13)")
(node (ref J2) (pin 13)))
(net (code 3) (name "Net-(J2-Pad32)")
(node (ref J2) (pin 32)))
(net (code 4) (name "Net-(J2-Pad22)")
(node (ref J2) (pin 22)))
(net (code 5) (name "Net-(J2-Pad12)")
(node (ref J2) (pin 12)))
(net (code 6) (name "Net-(J2-Pad31)")
(node (ref J2) (pin 31)))
(net (code 7) (name "Net-(J2-Pad21)")
(node (ref J2) (pin 21)))
(net (code 8) (name "Net-(J2-Pad11)")
(node (ref J2) (pin 11)))
(net (code 9) (name "Net-(J2-Pad40)")
(node (ref J2) (pin 40)))
(net (code 10) (name "Net-(J2-Pad30)")
(node (ref J2) (pin 30)))
(net (code 11) (name "Net-(J2-Pad23)")
(node (ref J2) (pin 23)))
(net (code 12) (name "Net-(J2-Pad10)")
(node (ref J2) (pin 10)))
(net (code 13) (name "Net-(J2-Pad9)")
(node (ref J2) (pin 9)))
(net (code 14) (name "Net-(J2-Pad8)")
(node (ref J2) (pin 8)))
(net (code 15) (name "Net-(J2-Pad7)")
(node (ref J2) (pin 7)))
(net (code 16) (name "Net-(J2-Pad6)")
(node (ref J2) (pin 6)))
(net (code 17) (name "Net-(J2-Pad5)")
(node (ref J2) (pin 5)))
(net (code 18) (name "Net-(J2-Pad4)")
(node (ref J2) (pin 4)))
(net (code 19) (name "Net-(J2-Pad3)")
(node (ref J2) (pin 3)))
(net (code 20) (name "Net-(J2-Pad2)")
(node (ref J2) (pin 2)))
(net (code 21) (name "Net-(J2-Pad36)")
(node (ref J2) (pin 36)))
(net (code 22) (name "Net-(J2-Pad39)")
(node (ref J2) (pin 39)))
(net (code 23) (name "Net-(J2-Pad29)")
(node (ref J2) (pin 29)))
(net (code 24) (name "Net-(J2-Pad19)")
(node (ref J2) (pin 19)))
(net (code 25) (name "Net-(J2-Pad38)")
(node (ref J2) (pin 38)))
(net (code 26) (name "Net-(J2-Pad28)")
(node (ref J2) (pin 28)))
(net (code 27) (name "Net-(J2-Pad18)")
(node (ref J2) (pin 18)))
(net (code 28) (name "Net-(J2-Pad37)")
(node (ref J2) (pin 37)))
(net (code 29) (name "Net-(J2-Pad27)")
(node (ref J2) (pin 27)))
(net (code 30) (name "Net-(J2-Pad17)")
(node (ref J2) (pin 17)))
(net (code 31) (name "Net-(J2-Pad1)")
(node (ref J2) (pin 1)))
(net (code 32) (name "Net-(J2-Pad26)")
(node (ref J2) (pin 26)))
(net (code 33) (name "Net-(J2-Pad16)")
(node (ref J2) (pin 16)))
(net (code 34) (name "Net-(J2-Pad35)")
(node (ref J2) (pin 35)))
(net (code 35) (name "Net-(J2-Pad25)")
(node (ref J2) (pin 25)))
(net (code 36) (name "Net-(J2-Pad15)")
(node (ref J2) (pin 15)))
(net (code 37) (name "Net-(J2-Pad34)")
(node (ref J2) (pin 34)))
(net (code 38) (name "Net-(J2-Pad24)")
(node (ref J2) (pin 24)))
(net (code 39) (name "Net-(J2-Pad14)")
(node (ref J2) (pin 14)))
(net (code 40) (name "Net-(J2-Pad33)")
(node (ref J2) (pin 33)))
(net (code 41) (name "Net-(J1-Pad20)")
(node (ref J1) (pin 20)))
(net (code 42) (name "Net-(J1-Pad13)")
(node (ref J1) (pin 13)))
(net (code 43) (name "Net-(J1-Pad32)")
(node (ref J1) (pin 32)))
(net (code 44) (name "Net-(J1-Pad22)")
(node (ref J1) (pin 22)))
(net (code 45) (name "Net-(J1-Pad12)")
(node (ref J1) (pin 12)))
(net (code 46) (name "Net-(J1-Pad31)")
(node (ref J1) (pin 31)))
(net (code 47) (name "Net-(J1-Pad21)")
(node (ref J1) (pin 21)))
(net (code 48) (name "Net-(J1-Pad11)")
(node (ref J1) (pin 11)))
(net (code 49) (name "Net-(J1-Pad40)")
(node (ref J1) (pin 40)))
(net (code 50) (name "Net-(J1-Pad30)")
(node (ref J1) (pin 30)))
(net (code 51) (name "Net-(J1-Pad23)")
(node (ref J1) (pin 23)))
(net (code 52) (name "Net-(J1-Pad10)")
(node (ref J1) (pin 10)))
(net (code 53) (name "Net-(J1-Pad9)")
(node (ref J1) (pin 9)))
(net (code 54) (name "Net-(J1-Pad8)")
(node (ref J1) (pin 8)))
(net (code 55) (name "Net-(J1-Pad7)")
(node (ref J1) (pin 7)))
(net (code 56) (name "Net-(J1-Pad6)")
(node (ref J1) (pin 6)))
(net (code 57) (name "Net-(J1-Pad5)")
(node (ref J1) (pin 5)))
(net (code 58) (name "Net-(J1-Pad4)")
(node (ref J1) (pin 4)))
(net (code 59) (name "Net-(J1-Pad3)")
(node (ref J1) (pin 3)))
(net (code 60) (name "Net-(J1-Pad2)")
(node (ref J1) (pin 2)))
(net (code 61) (name "Net-(J1-Pad36)")
(node (ref J1) (pin 36)))
(net (code 62) (name "Net-(J1-Pad39)")
(node (ref J1) (pin 39)))
(net (code 63) (name "Net-(J1-Pad29)")
(node (ref J1) (pin 29)))
(net (code 64) (name "Net-(J1-Pad19)")
(node (ref J1) (pin 19)))
(net (code 65) (name "Net-(J1-Pad38)")
(node (ref J1) (pin 38)))
(net (code 66) (name "Net-(J1-Pad28)")
(node (ref J1) (pin 28)))
(net (code 67) (name "Net-(J1-Pad18)")
(node (ref J1) (pin 18)))
(net (code 68) (name "Net-(J1-Pad37)")
(node (ref J1) (pin 37)))
(net (code 69) (name "Net-(J1-Pad27)")
(node (ref J1) (pin 27)))
(net (code 70) (name "Net-(J1-Pad17)")
(node (ref J1) (pin 17)))
(net (code 71) (name "Net-(J1-Pad1)")
(node (ref J1) (pin 1)))
(net (code 72) (name "Net-(J1-Pad26)")
(node (ref J1) (pin 26)))
(net (code 73) (name "Net-(J1-Pad16)")
(node (ref J1) (pin 16)))
(net (code 74) (name "Net-(J1-Pad35)")
(node (ref J1) (pin 35)))
(net (code 75) (name "Net-(J1-Pad25)")
(node (ref J1) (pin 25)))
(net (code 76) (name "Net-(J1-Pad15)")
(node (ref J1) (pin 15)))
(net (code 77) (name "Net-(J1-Pad34)")
(node (ref J1) (pin 34)))
(net (code 78) (name "Net-(J1-Pad24)")
(node (ref J1) (pin 24)))
(net (code 79) (name "Net-(J1-Pad14)")
(node (ref J1) (pin 14)))
(net (code 80) (name "Net-(J1-Pad33)")
(node (ref J1) (pin 33)))))
\ No newline at end of file
RPi_Hat.pro 0 → 100644
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update=03/28/2015 11:09:15 AM
version=1
last_client=kicad
[cvpcb]
version=1
NetIExt=net
[pcbnew]
version=1
PageLayoutDescrFile=C:/xesscorp/KiCad/page_layouts/title_block_only.kicad_wks
LastNetListRead=
UseCmpFile=1
PadDrill=0.6
PadDrillOvalY=0.6
PadSizeH=1.5
PadSizeV=1.5
PcbTextSizeV=1.5
PcbTextSizeH=1.5
PcbTextThickness=0.3
ModuleTextSizeV=1
ModuleTextSizeH=1
ModuleTextSizeThickness=0.15
SolderMaskClearance=0
SolderMaskMinWidth=0
DrawSegmentWidth=0.2
BoardOutlineThickness=0.09999999999999999
ModuleOutlineThickness=0.15
[eeschema]
version=1
LibDir=C:/xesscorp/KiCad/libraries
[eeschema/libraries]
LibName1=power
LibName2=device
LibName3=transistors
LibName4=conn
LibName5=linear
LibName6=regul
LibName7=74xx
LibName8=cmos4000
LibName9=adc-dac
LibName10=memory
LibName11=xilinx
LibName12=special
LibName13=microcontrollers
LibName14=dsp
LibName15=microchip
LibName16=analog_switches
LibName17=motorola
LibName18=texas
LibName19=intel
LibName20=audio
LibName21=interface
LibName22=digital-audio
LibName23=philips
LibName24=display
LibName25=cypress
LibName26=siliconi
LibName27=opto
LibName28=atmel
LibName29=contrib
LibName30=valves
LibName31=xess
[general]
version=1
RPi_Hat.sch 0 → 100644
View file @ 8e6d07cd
EESchema Schematic File Version 2
LIBS:power
LIBS:device
LIBS:transistors
LIBS:conn
LIBS:linear
LIBS:regul
LIBS:74xx
LIBS:cmos4000
LIBS:adc-dac
LIBS:memory
LIBS:xilinx
LIBS:special
LIBS:microcontrollers
LIBS:dsp
LIBS:microchip
LIBS:analog_switches
LIBS:motorola
LIBS:texas
LIBS:intel
LIBS:audio
LIBS:interface
LIBS:digital-audio
LIBS:philips
LIBS:display
LIBS:cypress
LIBS:siliconi
LIBS:opto
LIBS:atmel
LIBS:contrib
LIBS:valves
LIBS:xess
LIBS:RPi_Hat-cache
EELAYER 25 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 1 2
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Sheet
S 1400 1400 1000 1000
U 5515D395
F0 "RPi_GPIO" 60
F1 "RPi_GPIO.sch" 60
$EndSheet
$EndSCHEMATC
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<!DOCTYPE html PUBLIC "-//W3C//DTD XHTML 1.0 Transitional//EN" "http://www.w3.org/TR/xhtml1/DTD/xhtml1-transitional.dtd">
<html xmlns="http://www.w3.org/1999/xhtml">
<head>
<meta http-equiv="Content-Type" content="text/html; charset=utf-8" />
<meta http-equiv="Content-Style-Type" content="text/css" />
<meta name="generator" content="pandoc" />
<title>RPi B+ Hat</title>
<style type="text/css">code{white-space: pre;}</style>
</head>
<body>
<div id="header">
<h1 class="title">RPi B+ Hat</h1>
</div>
<h1 id="raspberry-pi-b-hat">Raspberry Pi B+ Hat</h1>
<h2 id="expansion-board">Expansion Board</h2>
<p>This is a project template for a <a href="https://github.com/raspberrypi/hats">Raspberry Pi B+ Hat</a>.</p>
<p>This base project includes a PCB edge defined according to <a href="https://github.com/raspberrypi/hats/blob/master/hat-board-mechanical.pdf">this specification</a>. Both a thru-hole and a surface mount connector are provided, along with a different PCB edge for each. Just keep the PCB edge and connector type that you're using for your design and delete the others.</p>
<p>The board outline looks like this:</p>
<p><img src="brd.png" style="width:100%"></p>
<p>(c)2015 XESS Corp.</p>
</body>
</html>
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