Commit b837e1f6 authored by Michael J. Lyons's avatar Michael J. Lyons

Adding test script to rewrite all sixteen spi registers

parent 19c73f96
...@@ -146,6 +146,19 @@ def ReadRegsTest(): ...@@ -146,6 +146,19 @@ def ReadRegsTest():
regVal = spi.ReadReg(regId) regVal = spi.ReadReg(regId)
print("Reg%d = 0x%08x" % (regId, regVal)) print("Reg%d = 0x%08x" % (regId, regVal))
#
# WriteRegsTest
#
# Writes a test pattern to the spi registers
#
def WriteRegsTest():
for regId in range(16):
regVal = 255 - regId
regVal = (regVal * 256) + regVal
regVal = (regVal * 256 * 256) + regVal
print("Reg%d = 0x%08x" % (regId, regVal))
spi.WriteReg(regId=regId, value=regVal)
# #
# PrintCliSyntax: # PrintCliSyntax:
# #
...@@ -161,6 +174,7 @@ Valid tests (case sensitive): ...@@ -161,6 +174,7 @@ Valid tests (case sensitive):
- MemLoopback - MemLoopback
- RegLoopback - RegLoopback
- ReadRegs - ReadRegs
- WriteRegsTest
""" """
# #
...@@ -178,7 +192,8 @@ testMapping = {'SingleBytePacketsSend' : [SingleBytePacketsSendTest], ...@@ -178,7 +192,8 @@ testMapping = {'SingleBytePacketsSend' : [SingleBytePacketsSendTest],
'MultiBytePacketSend' : [MultiBytePacketSendTest], 'MultiBytePacketSend' : [MultiBytePacketSendTest],
'MemLoopback' : [MemLoopbackTest], 'MemLoopback' : [MemLoopbackTest],
'RegLoopback' : [RegLoopbackTest], 'RegLoopback' : [RegLoopbackTest],
'ReadRegs' : [ReadRegsTest]} 'ReadRegs' : [ReadRegsTest],
'WriteRegs' : [WriteRegsTest]}
if cliTest not in testMapping: if cliTest not in testMapping:
sys.stderr.write('%s is not a valid test.\n' % (cliTest,)) sys.stderr.write('%s is not a valid test.\n' % (cliTest,))
PrintCliSyntax() PrintCliSyntax()
......
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