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Commit a64d58e7 authored by Mike Lyons's avatar Mike Lyons
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Merging xps_proj into master branch

parents 7d13bfe3 46a3a306
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projnav/ucf/atlys/spiloop.ucf 0 → 100644
View file @ a64d58e7
Net Reset LOC=N4 | IOSTANDARD=LVCMOS18;
Net SysClk LOC=L15 | IOSTANDARD=LVCMOS33;
# SPI Port
Net spi_miso LOC=U16 | IOSTANDARD=LVCMOS33;
Net spi_mosi LOC=U15 | IOSTANDARD=LVCMOS33;
Net spi_clk LOC=R10 | IOSTANDARD=LVCMOS33;
Net spi_ss LOC=M11 | IOSTANDARD=LVCMOS33;
# LEDs
Net leds<0> LOC=U18 | IOSTANDARD=LVCMOS33;
Net leds<1> LOC=M14 | IOSTANDARD=LVCMOS33;
Net leds<2> LOC=N14 | IOSTANDARD=LVCMOS33;
Net leds<3> LOC=L14 | IOSTANDARD=LVCMOS33;
Net leds<4> LOC=M13 | IOSTANDARD=LVCMOS33;
Net leds<5> LOC=D4 | IOSTANDARD=LVCMOS33;
Net leds<6> LOC=P16 | IOSTANDARD=LVCMOS33;
Net leds<7> LOC=N12 | IOSTANDARD=LVCMOS33;
projnav/ucf/atlys/spiwrap.ucf 0 → 100644
View file @ a64d58e7
Net Reset LOC=N4 | IOSTANDARD=LVCMOS18;
Net SysClk LOC=L15 | IOSTANDARD=LVCMOS33;
# SPI Port
Net spi_miso LOC=U16 | IOSTANDARD=LVCMOS33;
Net spi_mosi LOC=U15 | IOSTANDARD=LVCMOS33;
Net spi_clk LOC=R10 | IOSTANDARD=LVCMOS33;
Net spi_ss LOC=M11 | IOSTANDARD=LVCMOS33;
# LEDs
Net leds<0> LOC=U18 | IOSTANDARD=LVCMOS33;
Net leds<1> LOC=M14 | IOSTANDARD=LVCMOS33;
Net leds<2> LOC=N14 | IOSTANDARD=LVCMOS33;
Net leds<3> LOC=L14 | IOSTANDARD=LVCMOS33;
Net leds<4> LOC=M13 | IOSTANDARD=LVCMOS33;
Net leds<5> LOC=D4 | IOSTANDARD=LVCMOS33;
Net leds<6> LOC=P16 | IOSTANDARD=LVCMOS33;
Net leds<7> LOC=N12 | IOSTANDARD=LVCMOS33;
projnav/xps/.gitignore 0 → 100644
View file @ a64d58e7
system.log
psf2Edward.log
projnav/xps/SDK/SDK_Export/hw/system.xml 0 → 100644
View file @ a64d58e7
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projnav/xps/SDK/SDK_Export/hw/system_bd.bmm 0 → 100644
View file @ a64d58e7
// BMM LOC annotation file.
//
// Release 13.2 - Data2MEM O.61xd, build 2.2 May 20, 2011
// Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
///////////////////////////////////////////////////////////////////////////////
//
// Processor 'microblaze_0', ID 100, memory map.
//
///////////////////////////////////////////////////////////////////////////////
ADDRESS_MAP microblaze_0 MICROBLAZE 100
///////////////////////////////////////////////////////////////////////////////
//
// Processor 'microblaze_0' address space 'lmb_bram_combined' 0x00000000:0x0000FFFF (64 KBytes).
//
///////////////////////////////////////////////////////////////////////////////
ADDRESS_SPACE lmb_bram_combined RAMB16 [0x00000000:0x0000FFFF]
BUS_BLOCK
lmb_bram/lmb_bram/ramb16bwer_0 [31:31] INPUT = lmb_bram_combined_0.mem PLACED = X3Y24;
lmb_bram/lmb_bram/ramb16bwer_1 [30:30] INPUT = lmb_bram_combined_1.mem PLACED = X2Y26;
lmb_bram/lmb_bram/ramb16bwer_2 [29:29] INPUT = lmb_bram_combined_2.mem PLACED = X3Y26;
lmb_bram/lmb_bram/ramb16bwer_3 [28:28] INPUT = lmb_bram_combined_3.mem PLACED = X3Y22;
lmb_bram/lmb_bram/ramb16bwer_4 [27:27] INPUT = lmb_bram_combined_4.mem PLACED = X3Y30;
lmb_bram/lmb_bram/ramb16bwer_5 [26:26] INPUT = lmb_bram_combined_5.mem PLACED = X2Y28;
lmb_bram/lmb_bram/ramb16bwer_6 [25:25] INPUT = lmb_bram_combined_6.mem PLACED = X2Y30;
lmb_bram/lmb_bram/ramb16bwer_7 [24:24] INPUT = lmb_bram_combined_7.mem PLACED = X3Y32;
lmb_bram/lmb_bram/ramb16bwer_8 [23:23] INPUT = lmb_bram_combined_8.mem PLACED = X1Y34;
lmb_bram/lmb_bram/ramb16bwer_9 [22:22] INPUT = lmb_bram_combined_9.mem PLACED = X2Y52;
lmb_bram/lmb_bram/ramb16bwer_10 [21:21] INPUT = lmb_bram_combined_10.mem PLACED = X2Y50;
lmb_bram/lmb_bram/ramb16bwer_11 [20:20] INPUT = lmb_bram_combined_11.mem PLACED = X2Y48;
lmb_bram/lmb_bram/ramb16bwer_12 [19:19] INPUT = lmb_bram_combined_12.mem PLACED = X2Y46;
lmb_bram/lmb_bram/ramb16bwer_13 [18:18] INPUT = lmb_bram_combined_13.mem PLACED = X2Y32;
lmb_bram/lmb_bram/ramb16bwer_14 [17:17] INPUT = lmb_bram_combined_14.mem PLACED = X1Y30;
lmb_bram/lmb_bram/ramb16bwer_15 [16:16] INPUT = lmb_bram_combined_15.mem PLACED = X1Y32;
lmb_bram/lmb_bram/ramb16bwer_16 [15:15] INPUT = lmb_bram_combined_16.mem PLACED = X2Y18;
lmb_bram/lmb_bram/ramb16bwer_17 [14:14] INPUT = lmb_bram_combined_17.mem PLACED = X2Y20;
lmb_bram/lmb_bram/ramb16bwer_18 [13:13] INPUT = lmb_bram_combined_18.mem PLACED = X2Y14;
lmb_bram/lmb_bram/ramb16bwer_19 [12:12] INPUT = lmb_bram_combined_19.mem PLACED = X2Y16;
lmb_bram/lmb_bram/ramb16bwer_20 [11:11] INPUT = lmb_bram_combined_20.mem PLACED = X2Y44;
lmb_bram/lmb_bram/ramb16bwer_21 [10:10] INPUT = lmb_bram_combined_21.mem PLACED = X2Y42;
lmb_bram/lmb_bram/ramb16bwer_22 [9:9] INPUT = lmb_bram_combined_22.mem PLACED = X2Y38;
lmb_bram/lmb_bram/ramb16bwer_23 [8:8] INPUT = lmb_bram_combined_23.mem PLACED = X2Y40;
lmb_bram/lmb_bram/ramb16bwer_24 [7:7] INPUT = lmb_bram_combined_24.mem PLACED = X2Y24;
lmb_bram/lmb_bram/ramb16bwer_25 [6:6] INPUT = lmb_bram_combined_25.mem PLACED = X1Y28;
lmb_bram/lmb_bram/ramb16bwer_26 [5:5] INPUT = lmb_bram_combined_26.mem PLACED = X2Y22;
lmb_bram/lmb_bram/ramb16bwer_27 [4:4] INPUT = lmb_bram_combined_27.mem PLACED = X3Y28;
lmb_bram/lmb_bram/ramb16bwer_28 [3:3] INPUT = lmb_bram_combined_28.mem PLACED = X3Y34;
lmb_bram/lmb_bram/ramb16bwer_29 [2:2] INPUT = lmb_bram_combined_29.mem PLACED = X3Y36;
lmb_bram/lmb_bram/ramb16bwer_30 [1:1] INPUT = lmb_bram_combined_30.mem PLACED = X2Y34;
lmb_bram/lmb_bram/ramb16bwer_31 [0:0] INPUT = lmb_bram_combined_31.mem PLACED = X2Y36;
END_BUS_BLOCK;
END_ADDRESS_SPACE;
END_ADDRESS_MAP;
projnav/xps/SDK/SDK_Workspace/demo/.cproject 0 → 100644
View file @ a64d58e7
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<scannerConfigBuildInfo instanceId="xilinx.gnu.mb.exe.release.1874379234;xilinx.gnu.mb.exe.release.1874379234.;xilinx.gnu.mb.c.toolchain.compiler.release.1098713828;xilinx.gnu.compiler.input.794413244">
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</storageModule>
</cproject>
projnav/xps/SDK/SDK_Workspace/demo/.project 0 → 100644
View file @ a64d58e7
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>demo</name>
<comment></comment>
<projects>
<project>standalone_bsp_0</project>
<project>demobsp</project>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
<arguments>
<dictionary>
<key>?name?</key>
<value></value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.append_environment</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.autoBuildTarget</key>
<value>all</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.buildArguments</key>
<value></value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.buildCommand</key>
<value>make</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.buildLocation</key>
<value>${workspace_loc:/demo/Debug}</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.cleanBuildTarget</key>
<value>clean</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.contents</key>
<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
<value>true</value>
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<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.enableFullBuild</key>
<value>true</value>
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<dictionary>
<key>org.eclipse.cdt.make.core.fullBuildTarget</key>
<value>all</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.stopOnError</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
<value>true</value>
</dictionary>
</arguments>
</buildCommand>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
<triggers>full,incremental,</triggers>
<arguments>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>org.eclipse.cdt.core.cnature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
<nature>org.eclipse.cdt.core.ccnature</nature>
</natures>
</projectDescription>
projnav/xps/SDK/SDK_Workspace/demo/Debug/makefile 0 → 100644
View file @ a64d58e7
################################################################################
# Automatically-generated file. Do not edit!
################################################################################
-include ../makefile.init
RM := rm -rf
# All of the sources participating in the build are defined here
-include sources.mk
-include subdir.mk
-include src/subdir.mk
-include objects.mk
ifneq ($(MAKECMDGOALS),clean)
ifneq ($(strip $(C_DEPS)),)
-include $(C_DEPS)
endif
ifneq ($(strip $(CC_DEPS)),)
-include $(CC_DEPS)
endif
ifneq ($(strip $(CPP_DEPS)),)
-include $(CPP_DEPS)
endif
ifneq ($(strip $(CXX_DEPS)),)
-include $(CXX_DEPS)
endif
ifneq ($(strip $(C_UPPER_DEPS)),)
-include $(C_UPPER_DEPS)
endif
ifneq ($(strip $(S_UPPER_DEPS)),)
-include $(S_UPPER_DEPS)
endif
endif
-include ../makefile.defs
# Add inputs and outputs from these tool invocations to the build variables
ELFSIZE += \
demo.elf.size \
ELFCHECK += \
demo.elf.elfcheck \
# All Target
all: demo.elf secondary-outputs
# Tool invocations
demo.elf: $(OBJS) $(USER_OBJS)
@echo Building target: $@
@echo Invoking: MicroBlaze g++ linker
mb-g++ -L../../standalone_bsp_0/microblaze_0/lib -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.20.a -mno-xl-soft-mul -o"demo.elf" $(OBJS) $(USER_OBJS) $(LIBS)
@echo Finished building target: $@
@echo ' '
demo.elf.size: demo.elf
@echo Invoking: MicroBlaze Print Size
mb-size demo.elf |tee "demo.elf.size"
@echo Finished building: $@
@echo ' '
demo.elf.elfcheck: demo.elf
@echo Invoking: Xilinx ELF Check
elfcheck demo.elf -hw ../../xps_hw_platform/system.xml -pe microblaze_0 |tee "demo.elf.elfcheck"
@echo Finished building: $@
@echo ' '
# Other Targets
clean:
-$(RM) $(OBJS)$(C_DEPS)$(CC_DEPS)$(CPP_DEPS)$(EXECUTABLES)$(ELFSIZE)$(CXX_DEPS)$(C_UPPER_DEPS)$(ELFCHECK)$(S_UPPER_DEPS) demo.elf
-@echo ' '
secondary-outputs: $(ELFSIZE) $(ELFCHECK)
.PHONY: all clean dependents
.SECONDARY:
-include ../makefile.targets
projnav/xps/SDK/SDK_Workspace/demo/Debug/objects.mk 0 → 100644
View file @ a64d58e7
################################################################################
# Automatically-generated file. Do not edit!
################################################################################
USER_OBJS :=
LIBS :=
projnav/xps/SDK/SDK_Workspace/demo/Debug/sources.mk 0 → 100644
View file @ a64d58e7
################################################################################
# Automatically-generated file. Do not edit!
################################################################################
O_SRCS :=
CPP_SRCS :=
C_UPPER_SRCS :=
C_SRCS :=
LD_SRCS :=
S_UPPER_SRCS :=
S_SRCS :=
OBJ_SRCS :=
CXX_SRCS :=
CC_SRCS :=
OBJS :=
C_DEPS :=
CC_DEPS :=
CPP_DEPS :=
EXECUTABLES :=
ELFSIZE :=
CXX_DEPS :=
C_UPPER_DEPS :=
ELFCHECK :=
S_UPPER_DEPS :=
# Every subdirectory with source files must be described here
SUBDIRS := \
src \
projnav/xps/SDK/SDK_Workspace/demo/Debug/src/subdir.mk 0 → 100644
View file @ a64d58e7
################################################################################
# Automatically-generated file. Do not edit!
################################################################################
# Add inputs and outputs from these tool invocations to the build variables
CC_SRCS += \
../src/main.cc
OBJS += \
./src/main.o
CC_DEPS += \
./src/main.d
# Each subdirectory must supply rules for building sources it contributes
src/%.o: ../src/%.cc
@echo Building file: $<
@echo Invoking: MicroBlaze g++ compiler
mb-g++ -Wall -O0 -g3 -c -fmessage-length=0 -I../../standalone_bsp_0/microblaze_0/include -mxl-barrel-shift -mxl-pattern-compare -mcpu=v8.20.a -mno-xl-soft-mul -MMD -MP -MF"$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -o"$@" "$<"
@echo Finished building: $<
@echo ' '
projnav/xps/SDK/SDK_Workspace/demo/src/main.cc 0 → 100644
View file @ a64d58e7
/*
* Empty C++ Application
*/
#include <stdio.h>
#include "xil_types.h"
#include "xparameters.h"
#include "xdmacentral.h"
#define DMA_DEVICE_ID XPAR_DMACENTRAL_0_DEVICE_ID
#define DMA_BUFFER_BYTE_SIZE 4096
static XDmaCentral Dma;
u32 * pSpiifcBase = (u32 *)0x85000000;
u32 * pMosiBase = (u32 *)0x85010000;
u32 * pMisoBase = (u32 *)0x85011000;
//
// Initializes DMA controller
//
int InitDma();
//
// Copies a block of data between two burst-mode enabled memory regions. Uses
// XPS Central DMA controller. Function spins while waiting for copy to complete.
//
int DmaCopy(void * pSrc, void * pDest, size_t byteCount);
//
// Writes to the three memmap regions in the Spiifc peripheral
// (regs, mosi/miso buffers). Verifies the writes stuck using a read.
//
void SpiifcPioTest();
//
// DMA copies from mosi to miso buffers and verifies result using PIO.
//
void SpiifcDmaTest();
//
// InitDma - Initializes DMA controller
//
int InitDma()
{
XDmaCentral_Config *pDmaCfg;
int status;
// Configure DMA controller
pDmaCfg = XDmaCentral_LookupConfig(DMA_DEVICE_ID);
if (NULL == pDmaCfg) { return XST_FAILURE; }
status = XDmaCentral_CfgInitialize(&Dma, pDmaCfg, pDmaCfg->BaseAddress);
if (XST_SUCCESS != status) { return status; }
// Reset DMAC
XDmaCentral_Reset(&Dma);
// Setup DMAC control register to increment src & dest addr
XDmaCentral_SetControl(
&Dma,
XDMC_DMACR_SOURCE_INCR_MASK | XDMC_DMACR_DEST_INCR_MASK);
// DMAC does not raise interrupts (when transfer completes)
XDmaCentral_InterruptEnableSet(&Dma, 0);
return XST_SUCCESS;
}
int DmaCopy(void * pSrc, void * pDest, size_t byteCount)
{
u32 regValue;
XDmaCentral_Transfer(&Dma, pSrc, pDest, byteCount);
do { // Wait for DMA transfer to complete
regValue = XDmaCentral_GetStatus(&Dma);
} while ((regValue & XDMC_DMASR_BUSY_MASK) == XDMC_DMASR_BUSY_MASK);
if (regValue & XDMC_DMASR_BUS_ERROR_MASK) {
xil_printf("DMA_BUS_ERROR\n");
return XST_FAILURE;
}
return XST_SUCCESS;
}
int main()
{
int status, i;
// Initialize system
if (XST_SUCCESS != (status = InitDma())) {
xil_printf("[FAIL] InitDma() failed. Exiting.\n");
return status;
}
// Perform Programmed IO tests
SpiifcPioTest();
// Test DMA
SpiifcDmaTest();
// Spiifc loopback: anything sent to spiifc is sent back
while (1) {
// //
// // Print values of all SPI registers
// //
// for (i = 0; i < 16; i++) {
// xil_printf("Reg%d=0x%08x\n", i, pSpiifcBase[i]);
// }
// Wait for M->S transfer to complete
//xil_printf("Waiting for M->S transfer to complete..\n");
while(0 == (pSpiifcBase[0] & 0x1)) { ; }
pSpiifcBase[0] &= (~0x1); // Handling MOSI transfer completion
// Initiating DMA transfer
//xil_printf("DMA MOSI buffer to MISO buffer\n");
DmaCopy(pMosiBase, pMisoBase, 4096);
// DMA done, set flag for master
//xil_printf("DMA completed\n");
pSpiifcBase[0] |= 0x2;
}
/*
int i = 0;
for (i = 0; i < 40000000; i++) { ; }
for (i = 0; i < 1024; i++) {
xil_printf("pMOSI[i] = 0x%08X\n", pMosiBase[i]);
}
*/
}
void SpiifcPioTest()
{
int i = 0;
xil_printf("Testing Spiifc PIO...\n");
// PIO Write to Spiifc memmap regions
pSpiifcBase[0] = 0x87654321;
pMosiBase[0] = 0x12345678;
pMisoBase[0] = 0xFEEDFACE;
pMisoBase[1] = 0xBEEFBABE;
pMisoBase[2] = 0xBEEFBEEF;
xil_printf("Reg0 @ 0x%08X: verifying PIO... ", pSpiifcBase);
if (0x87654321 == *pSpiifcBase) {
xil_printf("[PASS]\n");
} else {
xil_printf("[FAIL] (actual=0x%08X)\n", *pSpiifcBase);
}
xil_printf("MOSI @ 0x%08X: verifying PIO... ", pMosiBase);
if (0x12345678 == *pMosiBase) {
xil_printf("[PASS]\n");
} else {
xil_printf("[FAIL] (actual=0x%08X)\n", *pMosiBase);
}
xil_printf("MISO @ 0x%08X: verifying PIO... ", pMisoBase);
if (0xFEEDFACE == *pMisoBase) {
xil_printf("[PASS]\n");
} else {
xil_printf("[FAIL] (actual=0x%08X)\n", *pMisoBase);
}
for (i = 0; i < 16; i++) {
pSpiifcBase[i] = (i << 24) | (i << 16) | (i << 8) | i;
}
for (i = 0; i < 16; i++) {
xil_printf("Reg%d=0x%08x\n", i, pSpiifcBase[i]);
}
xil_printf("\n");
}
void SpiifcDmaTest()
{
int status;
u32 i;
// Pattern DMA memory buffer
for(i = 0; i < DMA_BUFFER_BYTE_SIZE/4; i++) {
pMosiBase[i] = ((i*4+3) & 0xFF) << 24 |
((i*4+2) & 0xFF) << 16 |
((i*4+1) & 0xFF) << 8 |
((i*4+0) & 0xFF);
//pMosiBase[i] = 0xAABBCCDD;
//xil_printf("0x%08X\n", pMosiBase[i]);
}
// DMA buffer to Spiifc.MISO buffer
if (XST_SUCCESS != (status =
DmaCopy(pMosiBase, pMisoBase, DMA_BUFFER_BYTE_SIZE))) {
xil_printf("[FAIL] DmaCopy() failed. Exiting.\n");
}
// Check DMAC copied Spiifc.MOSI --> Spiifc.MISO buffer
u32 expectedDmaWord = 0;
int failWords = 0;
for (i = 0; i < (DMA_BUFFER_BYTE_SIZE/4); i++) {
expectedDmaWord = ((i*4+3) & 0xFF) << 24 |
((i*4+2) & 0xFF) << 16 |
((i*4+1) & 0xFF) << 8 |
((i*4+0) & 0xFF) << 0;
if (pMisoBase[i] != expectedDmaWord) {
xil_printf(
"[FAIL] DMA mem word [i]: expected=0x%08X, actual=0x%08X\n",
expectedDmaWord, pMisoBase[i]);
}
}
if (0 == failWords) {
xil_printf("[PASS] DMA transfer from MOSI to MISO memory\n");
}
}
projnav/xps/SDK/SDK_Workspace/standalone_bsp_0/.cproject 0 → 100644
View file @ a64d58e7
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<?fileVersion 4.0.0?>
<cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
<storageModule moduleId="org.eclipse.cdt.core.settings">
<cconfiguration id="org.eclipse.cdt.core.default.config.1065451617">
<storageModule buildSystemId="org.eclipse.cdt.core.defaultConfigDataProvider" id="org.eclipse.cdt.core.default.config.1065451617" moduleId="org.eclipse.cdt.core.settings" name="Configuration">
<externalSettings/>
<extensions/>
</storageModule>
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
</cconfiguration>
</storageModule>
</cproject>
projnav/xps/SDK/SDK_Workspace/standalone_bsp_0/.project 0 → 100644
View file @ a64d58e7
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>standalone_bsp_0</name>
<comment></comment>
<projects>
<project>xps_hw_platform</project>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.cdt.make.core.makeBuilder</name>
<triggers>clean,full,incremental,</triggers>
<arguments>
<dictionary>
<key>org.eclipse.cdt.core.errorOutputParser</key>
<value>org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.VCErrorParser;org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.MakeErrorParser;</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.append_environment</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.build.arguments</key>
<value></value>
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<dictionary>
<key>org.eclipse.cdt.make.core.build.command</key>
<value>make</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.build.target.auto</key>
<value>all</value>
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<dictionary>
<key>org.eclipse.cdt.make.core.build.target.clean</key>
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<dictionary>
<key>org.eclipse.cdt.make.core.build.target.inc</key>
<value>all</value>
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<dictionary>
<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
<value>false</value>
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<dictionary>
<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
<value>true</value>
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<key>org.eclipse.cdt.make.core.enableFullBuild</key>
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<key>org.eclipse.cdt.make.core.enabledIncrementalBuild</key>
<value>true</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.environment</key>
<value></value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.stopOnError</key>
<value>false</value>
</dictionary>
<dictionary>
<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
<value>true</value>
</dictionary>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>com.xilinx.sdk.sw.SwProjectNature</nature>
<nature>org.eclipse.cdt.core.cnature</nature>
<nature>org.eclipse.cdt.make.core.makeNature</nature>
</natures>
</projectDescription>
projnav/xps/SDK/SDK_Workspace/standalone_bsp_0/.sdkproject 0 → 100644
View file @ a64d58e7
THIRPARTY=false
PROCESSOR=microblaze_0
MSS_FILE=system.mss
projnav/xps/SDK/SDK_Workspace/standalone_bsp_0/Makefile 0 → 100644
View file @ a64d58e7
# Makefile generated by Xilinx SDK.
-include libgen.options
LIBRARIES = ${PROCESSOR}/lib/libxil.a
MSS = system.mss
all: libs
@echo 'Finished building libraries'
libs: $(LIBRARIES)
$(LIBRARIES): $(MSS)
libgen -hw ${HWSPEC}\
${REPOSITORIES}\
-pe ${PROCESSOR} \
-log libgen.log \
$(MSS)
clean:
rm -rf ${PROCESSOR}
projnav/xps/SDK/SDK_Workspace/standalone_bsp_0/libgen.log 0 → 100644
View file @ a64d58e7
Release 13.2 - libgen Xilinx EDK 13.2 Build EDK_O.61xd
(nt64)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
Command Line: libgen -hw ../xps_hw_platform/system.xml -pe microblaze_0 -log
libgen.log system.mss
Staging source files.
Running DRCs.
Running generate.
Running post_generate.
Running include - 'make -s include "COMPILER=mb-gcc" "ARCHIVER=mb-ar"
"COMPILER_FLAGS=-mno-xl-soft-mul -mxl-barrel-shift -mxl-pattern-compare
-mcpu=v8.20.a -O2 -c" "EXTRA_COMPILER_FLAGS=-g"'.
Running libs - 'make -s libs "COMPILER=mb-gcc" "ARCHIVER=mb-ar"
"COMPILER_FLAGS=-mno-xl-soft-mul -mxl-barrel-shift -mxl-pattern-compare
-mcpu=v8.20.a -O2 -c" "EXTRA_COMPILER_FLAGS=-g"'.
Running execs_generate.
projnav/xps/SDK/SDK_Workspace/standalone_bsp_0/libgen.options 0 → 100644
View file @ a64d58e7
PROCESSOR=microblaze_0
REPOSITORIES=
HWSPEC=../xps_hw_platform/system.xml
projnav/xps/SDK/SDK_Workspace/standalone_bsp_0/system.mss 0 → 100644
View file @ a64d58e7
PARAMETER VERSION = 2.2.0
BEGIN OS
PARAMETER OS_NAME = standalone
PARAMETER OS_VER = 3.01.a
PARAMETER PROC_INSTANCE = microblaze_0
PARAMETER STDIN = mdm_0
PARAMETER STDOUT = mdm_0
END
BEGIN PROCESSOR
PARAMETER DRIVER_NAME = cpu
PARAMETER DRIVER_VER = 1.13.a
PARAMETER HW_INSTANCE = microblaze_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = gpio
PARAMETER DRIVER_VER = 3.00.a
PARAMETER HW_INSTANCE = DIP_Switches_8Bits
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = gpio
PARAMETER DRIVER_VER = 3.00.a
PARAMETER HW_INSTANCE = LEDs_8Bits
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = gpio
PARAMETER DRIVER_VER = 3.00.a
PARAMETER HW_INSTANCE = Push_Buttons_5Bits
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = bram
PARAMETER DRIVER_VER = 3.00.a
PARAMETER HW_INSTANCE = dlmb_cntlr
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = bram
PARAMETER DRIVER_VER = 3.00.a
PARAMETER HW_INSTANCE = ilmb_cntlr
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = uartlite
PARAMETER DRIVER_VER = 2.00.a
PARAMETER HW_INSTANCE = mdm_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = generic
PARAMETER DRIVER_VER = 1.00.a
PARAMETER HW_INSTANCE = spiifc_0
END
BEGIN DRIVER
PARAMETER DRIVER_NAME = dmacentral
PARAMETER DRIVER_VER = 2.00.a
PARAMETER HW_INSTANCE = xps_central_dma_0
END
projnav/xps/SDK/SDK_Workspace/xps_hw_platform/.project 0 → 100644
View file @ a64d58e7
<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>xps_hw_platform</name>
<comment></comment>
<projects>
</projects>
<buildSpec>
</buildSpec>
<natures>
<nature>com.xilinx.sdk.hw.HwProject</nature>
</natures>
</projectDescription>
projnav/xps/SDK/SDK_Workspace/xps_hw_platform/system.xml 0 → 100644
View file @ a64d58e7
This source diff could not be displayed because it is too large. You can view the blob instead.
projnav/xps/SDK/SDK_Workspace/xps_hw_platform/system_bd.bmm 0 → 100644
View file @ a64d58e7
// BMM LOC annotation file.
//
// Release 13.2 - Data2MEM O.61xd, build 2.2 May 20, 2011
// Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
///////////////////////////////////////////////////////////////////////////////
//
// Processor 'microblaze_0', ID 100, memory map.
//
///////////////////////////////////////////////////////////////////////////////
ADDRESS_MAP microblaze_0 MICROBLAZE 100
///////////////////////////////////////////////////////////////////////////////
//
// Processor 'microblaze_0' address space 'lmb_bram_combined' 0x00000000:0x0000FFFF (64 KBytes).
//
///////////////////////////////////////////////////////////////////////////////
ADDRESS_SPACE lmb_bram_combined RAMB16 [0x00000000:0x0000FFFF]
BUS_BLOCK
lmb_bram/lmb_bram/ramb16bwer_0 [31:31] INPUT = lmb_bram_combined_0.mem PLACED = X3Y24;
lmb_bram/lmb_bram/ramb16bwer_1 [30:30] INPUT = lmb_bram_combined_1.mem PLACED = X2Y26;
lmb_bram/lmb_bram/ramb16bwer_2 [29:29] INPUT = lmb_bram_combined_2.mem PLACED = X3Y26;
lmb_bram/lmb_bram/ramb16bwer_3 [28:28] INPUT = lmb_bram_combined_3.mem PLACED = X3Y22;
lmb_bram/lmb_bram/ramb16bwer_4 [27:27] INPUT = lmb_bram_combined_4.mem PLACED = X3Y30;
lmb_bram/lmb_bram/ramb16bwer_5 [26:26] INPUT = lmb_bram_combined_5.mem PLACED = X2Y28;
lmb_bram/lmb_bram/ramb16bwer_6 [25:25] INPUT = lmb_bram_combined_6.mem PLACED = X2Y30;
lmb_bram/lmb_bram/ramb16bwer_7 [24:24] INPUT = lmb_bram_combined_7.mem PLACED = X3Y32;
lmb_bram/lmb_bram/ramb16bwer_8 [23:23] INPUT = lmb_bram_combined_8.mem PLACED = X1Y34;
lmb_bram/lmb_bram/ramb16bwer_9 [22:22] INPUT = lmb_bram_combined_9.mem PLACED = X2Y52;
lmb_bram/lmb_bram/ramb16bwer_10 [21:21] INPUT = lmb_bram_combined_10.mem PLACED = X2Y50;
lmb_bram/lmb_bram/ramb16bwer_11 [20:20] INPUT = lmb_bram_combined_11.mem PLACED = X2Y48;
lmb_bram/lmb_bram/ramb16bwer_12 [19:19] INPUT = lmb_bram_combined_12.mem PLACED = X2Y46;
lmb_bram/lmb_bram/ramb16bwer_13 [18:18] INPUT = lmb_bram_combined_13.mem PLACED = X2Y32;
lmb_bram/lmb_bram/ramb16bwer_14 [17:17] INPUT = lmb_bram_combined_14.mem PLACED = X1Y30;
lmb_bram/lmb_bram/ramb16bwer_15 [16:16] INPUT = lmb_bram_combined_15.mem PLACED = X1Y32;
lmb_bram/lmb_bram/ramb16bwer_16 [15:15] INPUT = lmb_bram_combined_16.mem PLACED = X2Y18;
lmb_bram/lmb_bram/ramb16bwer_17 [14:14] INPUT = lmb_bram_combined_17.mem PLACED = X2Y20;
lmb_bram/lmb_bram/ramb16bwer_18 [13:13] INPUT = lmb_bram_combined_18.mem PLACED = X2Y14;
lmb_bram/lmb_bram/ramb16bwer_19 [12:12] INPUT = lmb_bram_combined_19.mem PLACED = X2Y16;
lmb_bram/lmb_bram/ramb16bwer_20 [11:11] INPUT = lmb_bram_combined_20.mem PLACED = X2Y44;
lmb_bram/lmb_bram/ramb16bwer_21 [10:10] INPUT = lmb_bram_combined_21.mem PLACED = X2Y42;
lmb_bram/lmb_bram/ramb16bwer_22 [9:9] INPUT = lmb_bram_combined_22.mem PLACED = X2Y38;
lmb_bram/lmb_bram/ramb16bwer_23 [8:8] INPUT = lmb_bram_combined_23.mem PLACED = X2Y40;
lmb_bram/lmb_bram/ramb16bwer_24 [7:7] INPUT = lmb_bram_combined_24.mem PLACED = X2Y24;
lmb_bram/lmb_bram/ramb16bwer_25 [6:6] INPUT = lmb_bram_combined_25.mem PLACED = X1Y28;
lmb_bram/lmb_bram/ramb16bwer_26 [5:5] INPUT = lmb_bram_combined_26.mem PLACED = X2Y22;
lmb_bram/lmb_bram/ramb16bwer_27 [4:4] INPUT = lmb_bram_combined_27.mem PLACED = X3Y28;
lmb_bram/lmb_bram/ramb16bwer_28 [3:3] INPUT = lmb_bram_combined_28.mem PLACED = X3Y34;
lmb_bram/lmb_bram/ramb16bwer_29 [2:2] INPUT = lmb_bram_combined_29.mem PLACED = X3Y36;
lmb_bram/lmb_bram/ramb16bwer_30 [1:1] INPUT = lmb_bram_combined_30.mem PLACED = X2Y34;
lmb_bram/lmb_bram/ramb16bwer_31 [0:0] INPUT = lmb_bram_combined_31.mem PLACED = X2Y36;
END_BUS_BLOCK;
END_ADDRESS_SPACE;
END_ADDRESS_MAP;
projnav/xps/__xps/edw2xtl_sav_globals.xsl 0 → 100644
View file @ a64d58e7
<?xml version="1.0" standalone="no"?>
<!DOCTYPE stylesheet [
<!ENTITY UPPERCASE "ABCDEFGHIJKLMNOPQRSTUVWXYZ">
<!ENTITY LOWERCASE "abcdefghijklmnopqrstuvwxyz">
<!ENTITY UPPER2LOWER " '&UPPERCASE;' , '&LOWERCASE;' ">
<!ENTITY LOWER2UPPER " '&LOWERCASE;' , '&UPPERCASE;' ">
<!ENTITY ALPHALOWER "ABCDEFxX0123456789">
<!ENTITY HEXUPPER "ABCDEFxX0123456789">
<!ENTITY HEXLOWER "abcdefxX0123456789">
<!ENTITY HEXU2L " '&HEXLOWER;' , '&HEXUPPER;' ">
<!ENTITY ALLMODS "MODULE[(@INSTANCE)]">
<!ENTITY BUSMODS "MODULE[(@MODCLASS ='BUS')]">
<!ENTITY CPUMODS "MODULE[(@MODCLASS ='PROCESSOR')]">
<!ENTITY MODIOFS "MODULE/IOINTERFACES/IOINTERFACE">
<!ENTITY ALLIOFS "&MODIOFS;[(not(@IS_VALID) or (@IS_VALID = 'TRUE'))]">
<!ENTITY MODBIFS "MODULE/BUSINTERFACES/BUSINTERFACE">
<!ENTITY ALLBIFS "&MODBIFS;[(not(@IS_VALID) or (@IS_VALID = 'TRUE'))]">
<!ENTITY MSTBIFS "&MODBIFS;[(not(@IS_VALID) or (@IS_VALID = 'TRUE')) and (@TYPE = 'MASTER')]">
<!ENTITY SLVBIFS "&MODBIFS;[(not(@IS_VALID) or (@IS_VALID = 'TRUE')) and (@TYPE = 'SLAVE')]">
<!ENTITY MOSBIFS "&MODBIFS;[(not(@IS_VALID) or (@IS_VALID = 'TRUE')) and ((@TYPE = 'MASTER') or (@TYPE = 'SLAVE'))]">
<!ENTITY P2PBIFS "&MODBIFS;[(not(@IS_VALID) or (@IS_VALID = 'TRUE')) and ((@TYPE = 'TARGET') or (@TYPE = 'INITIATOR'))]">
<!ENTITY MODPORTS "MODULE/PORTS/PORT">
<!ENTITY ALLPORTS "&MODPORTS;[ (not(@IS_VALID) or (@IS_VALID = 'TRUE'))]">
<!ENTITY NDFPORTS "&MODPORTS;[((not(@IS_VALID) or (@IS_VALID = 'TRUE')) and (not(@BUS) and not(@IOS)))]">
<!ENTITY DEFPORTS "&MODPORTS;[((not(@IS_VALID) or (@IS_VALID = 'TRUE')) and ((@BUS) or (@IOS)))]">
]>
<xsl:stylesheet version="1.0"
xmlns:xsl="http://www.w3.org/1999/XSL/Transform"
xmlns:exsl="http://exslt.org/common"
xmlns:dyn="http://exslt.org/dynamic"
xmlns:math="http://exslt.org/math"
xmlns:xlink="http://www.w3.org/1999/xlink"
extension-element-prefixes="math dyn exsl xlink">
<xsl:variable name="G_ROOT" select="/"/>
<!--
======================================================
EDK SYSTEM (EDWARD) Globals.
======================================================
-->
<xsl:variable name="G_SYS_EVAL">
<xsl:choose>
<xsl:when test="not($P_SYSTEM_XML = '__UNDEF__')"><xsl:text>document($P_SYSTEM_XML)</xsl:text></xsl:when>
<xsl:otherwise><xsl:text>/</xsl:text></xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:variable name="G_SYS_DOC" select="dyn:evaluate($G_SYS_EVAL)"/>
<xsl:variable name="G_SYS" select="$G_SYS_DOC/EDKSYSTEM"/>
<xsl:variable name="G_SYS_TIMESTAMP" select="$G_SYS/@TIMESTAMP"/>
<xsl:variable name="G_SYS_EDKVERSION" select="$G_SYS/@EDKVERSION"/>
<xsl:variable name="G_SYS_INFO" select="$G_SYS/SYSTEMINFO"/>
<xsl:variable name="G_SYS_INFO_PKG" select="$G_SYS_INFO/@PACKAGE"/>
<xsl:variable name="G_SYS_INFO_DEV" select="$G_SYS_INFO/@DEVICE"/>
<xsl:variable name="G_SYS_INFO_ARCH" select="$G_SYS_INFO/@ARCH"/>
<xsl:variable name="G_SYS_INFO_SPEED" select="$G_SYS_INFO/@SPEEDGRADE"/>
<xsl:variable name="G_SYS_MODS" select="$G_SYS/MODULES"/>
<xsl:variable name="G_SYS_EXPS" select="$G_SYS/EXTERNALPORTS"/>
<xsl:variable name="COL_FOCUSED_MASTER" select="'AAAAFF'"/>
<xsl:variable name="COL_BG_OUTOF_FOCUS_CONNECTIONS" select="'AA7711'"/>
<!-- INDEX KEYS FOR FAST ACCESS -->
<xsl:key name="G_MAP_MODULES" match="&ALLMODS;" use="@INSTANCE"/>
<xsl:key name="G_MAP_PROCESSORS" match="&CPUMODS;" use="@INSTANCE"/>
<xsl:key name="G_MAP_BUSSES" match="&BUSMODS;" use="@INSTANCE"/>
<xsl:key name="G_MAP_BUSSES" match="&BUSMODS;" use="@BUSSTD"/>
<xsl:key name="G_MAP_BUSSES" match="&BUSMODS;" use="@BUSSTD_PSF"/>
<xsl:key name="G_MAP_ALL_IOFS" match="&ALLIOFS;" use="../../@INSTANCE"/>
<xsl:key name="G_MAP_ALL_BIFS" match="&ALLBIFS;" use="../../@INSTANCE"/>
<xsl:key name="G_MAP_ALL_BIFS_BY_BUS" match="&ALLBIFS;" use="@BUSNAME"/>
<!--
-->
<xsl:key name="G_MAP_MST_BIFS" match="&MSTBIFS;" use="@BUSNAME"/>
<xsl:key name="G_MAP_SLV_BIFS" match="&SLVBIFS;" use="@BUSNAME"/>
<xsl:key name="G_MAP_MOS_BIFS" match="&MOSBIFS;" use="@BUSNAME"/>
<xsl:key name="G_MAP_P2P_BIFS" match="&P2PBIFS;" use="@BUSNAME"/>
<xsl:key name="G_MAP_P2P_BIFS" match="&P2PBIFS;" use="@BUSSTD"/>
<xsl:key name="G_MAP_P2P_BIFS" match="&P2PBIFS;" use="@BUSSTD_PSF"/>
<xsl:key name="G_MAP_ALL_PORTS" match="&ALLPORTS;" use="../../@INSTANCE"/>
<xsl:key name="G_MAP_DEF_PORTS" match="&DEFPORTS;" use="../../@INSTANCE"/> <!-- Default ports -->
<xsl:key name="G_MAP_NDF_PORTS" match="&NDFPORTS;" use="../../@INSTANCE"/> <!-- Non Default ports -->
<!--
<xsl:key name="G_MAP_MASTER_BIFS" match="&MSTBIFS;" use="@BUSNAME"/>
<xsl:key name="G_MAP_MASTER_BIFS" match="MODULE[not(@MODCLASS ='BUS')]/BUSINTERFACES/BUSINTERFACE[(not(@IS_VALID) or (@IS_VALID = 'TRUE')) and (@TYPE = 'MASTER')]" use="../../@INSTANCE.@NAME"/>
<xsl:key name="G_MAP_BUSSES_BY_INSTANCE" match="MODULE[(@MODCLASS ='BUS')]" use="@INSTANCE"/>
<xsl:key name="G_MAP_XB_BUSSES" match="MODULE[(@MODCASS ='BUS')and (@IS_CROSSBAR)]" use="@INSTANCE"/>
-->
<!--
======================================================
Groups.xml (BLOCKS) Globals
======================================================
-->
<xsl:variable name="G_GRP_EVAL">
<xsl:choose>
<xsl:when test="not($P_GROUPS_XML = '__UNDEF__')"><xsl:text>document($P_GROUPS_XML)</xsl:text></xsl:when>
<xsl:otherwise><xsl:text>/</xsl:text></xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:variable name="G_GRPS_DOC" select="dyn:evaluate($G_GRP_EVAL)"/>
<xsl:variable name="G_GROUPS" select="$G_GRPS_DOC/BLOCKS"/>
<xsl:variable name="G_NUM_OF_PROCS" select="count($G_SYS/MODULES/MODULE[(@MODCLASS = 'PROCESSOR')])"/>
<xsl:variable name="G_NUM_OF_PROCS_W_ADDRS" select="count($G_SYS/MODULES/MODULE[(@MODCLASS = 'PROCESSOR') and MEMORYMAP/MEMRANGE[((not(@IS_VALID) or (@IS_VALID = 'TRUE')) and ACCESSROUTE) ]])"/>
<xsl:variable name="G_FOCUSED_SCOPE">
<xsl:choose>
<!-- FOCUSING ON SPECIFIC SELECTIONS-->
<xsl:when test="$G_ROOT/SAV/SELECTION">
</xsl:when>
<!-- FOCUSING ON PROCESSOR -->
<xsl:when test="$G_ROOT/SAV/MASTER">
<xsl:if test="$G_DEBUG = 'TRUE'"><xsl:message>FOCUSED MASTERS SPECIFIED</xsl:message></xsl:if>
<xsl:for-each select="$G_ROOT/SAV/MASTER">
<xsl:variable name="m_inst_" select="@INSTANCE"/>
<xsl:variable name="m_mod_" select="$G_SYS_MODS/MODULE[(@INSTANCE = $m_inst_)]"/>
<xsl:for-each select="$m_mod_/BUSINTERFACES/BUSINTERFACE[(not(@IS_VALID) or (@IS_VALID = 'TRUE')) and not(@BUSNAME = '__NOC__') and ((@TYPE = 'MASTER') or (@TYPE = 'SLAVE') or (@TYPE = 'INITIATOR') or (@TYPE = 'TARGET'))]">
<xsl:if test="$G_DEBUG = 'TRUE'"><xsl:message> FOCUSED MASTER BIF <xsl:value-of select="$m_inst_"/>.<xsl:value-of select="@NAME"/> = <xsl:value-of select="@BUSNAME"/></xsl:message></xsl:if>
<xsl:variable name="b_bus_" select="@BUSNAME"/>
<BUS NAME="{@BUSNAME}" BUSSTD="{@BUSSTD}"/>
<xsl:for-each select="$G_SYS_MODS/MODULE[(not(@INSTANCE = $m_inst_) and (@MODCLASS = 'BUS_BRIDGE'))]/BUSINTERFACES/BUSINTERFACE[(not(@IS_VALID) or (@IS_VALID = 'TRUE')) and (@TYPE = 'SLAVE') and (@BUSNAME = $b_bus_)]">
<xsl:variable name="b_inst_" select="../../@INSTANCE"/>
<xsl:choose>
<xsl:when test="MASTERS/MASTER">
<xsl:for-each select="MASTERS/MASTER">
<xsl:variable name="sm_inst_" select="@INSTANCE"/>
<xsl:if test="count($G_ROOT/SAV/MASTER[(@INSTANCE = $sm_inst_)]) &gt; 0">
<xsl:if test="$G_DEBUG = 'TRUE'"><xsl:message> FOCUSED PERIPHERAL BRIDGE <xsl:value-of select="$b_inst_"/></xsl:message></xsl:if>
<PERIPHERAL NAME="{$b_inst_}"/>
</xsl:if>
</xsl:for-each>
</xsl:when>
<xsl:otherwise>
<xsl:if test="$G_DEBUG = 'TRUE'"><xsl:message> FOCUSED PERIPHERAL BRIDGE <xsl:value-of select="$b_inst_"/></xsl:message></xsl:if>
<PERIPHERAL NAME="{$b_inst_}"/>
</xsl:otherwise>
</xsl:choose>
</xsl:for-each>
</xsl:for-each>
<xsl:for-each select="$m_mod_/PERIPHERALS/PERIPHERAL">
<xsl:variable name="p_id_" select="@INSTANCE"/>
<xsl:variable name="p_mod_" select="$G_SYS_MODS/MODULE[@INSTANCE = $p_id_]"/>
<PERIPHERAL NAME="{@INSTANCE}"/>
<xsl:variable name="p_mr_cnt_" select="count($m_mod_/MEMORYMAP/MEMRANGE[(@INSTANCE = $p_id_)])"/>
<xsl:if test="$G_DEBUG = 'TRUE'"><xsl:message> FOCUSED PERIPHERAL <xsl:value-of select="$p_id_"/> has <xsl:value-of select="$p_mr_cnt_"/> memory ranges</xsl:message></xsl:if>
<xsl:for-each select="$m_mod_/MEMORYMAP/MEMRANGE[(@INSTANCE = $p_id_)]/ACCESSROUTE/ROUTEPNT">
<xsl:variable name="b_id_" select="@INSTANCE"/>
<xsl:for-each select="$G_SYS_MODS/MODULE[((@INSTANCE = $b_id_) and (@MODCLASS = 'BUS'))]">
<xsl:if test="$G_DEBUG = 'TRUE'"><xsl:message> FOCUSED PERIPHERAL BUS <xsl:value-of select="@INSTANCE"/></xsl:message></xsl:if>
<BUS NAME="{@INSTANCE}" BUSSTD="{@BUSSTD}"/>
</xsl:for-each>
</xsl:for-each>
</xsl:for-each>
</xsl:for-each>
</xsl:when>
<!-- FOCUSING ON BUS -->
<xsl:when test="$G_ROOT/SAV/BUS">
<xsl:if test="$G_DEBUG = 'TRUE'"><xsl:message>FOCUSED BUSSES SPECIFIED</xsl:message></xsl:if>
<xsl:for-each select="$G_ROOT/SAV/BUS">
<xsl:variable name="m_inst_" select="@INSTANCE"/>
<xsl:variable name="m_mod_" select="$G_SYS_MODS/MODULE[(@INSTANCE = $m_inst_)]"/>
<xsl:variable name="m_bstd_" select="$m_mod_/@BUSSTD"/>
<BUS NAME="{$m_inst_}" BUSSTD="{$m_bstd_}"/>
<xsl:if test="$G_DEBUG = 'TRUE'"><xsl:message> FOCUSED BUS <xsl:value-of select="$m_inst_"/> <xsl:value-of select="$m_bstd_"/></xsl:message></xsl:if>
</xsl:for-each>
</xsl:when>
</xsl:choose>
</xsl:variable>
<xsl:variable name="G_HAVE_XB_BUSSES">
<xsl:choose>
<xsl:when test="(count($G_SYS_MODS/MODULE[((@MODCLASS = 'BUS') and (@IS_CROSSBAR = 'TRUE'))]) &gt; 0)">TRUE</xsl:when>
<xsl:otherwise>FALSE</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:template name="F_ModClass_To_IpClassification">
<xsl:param name="iModClass" select="'NONE'"/>
<xsl:param name="iBusStd" select="'NONE'"/>
<xsl:choose>
<xsl:when test="$iModClass = 'BUS'"><xsl:value-of select="$iBusStd"/> Bus</xsl:when>
<xsl:when test="$iModClass = 'DEBUG'">Debug</xsl:when>
<xsl:when test="$iModClass = 'MEMORY'">Memory</xsl:when>
<xsl:when test="$iModClass = 'MEMORY_CNTLR'">Memory Controller</xsl:when>
<xsl:when test="$iModClass = 'INTERRUPT_CNTLR'">Interrupt Controller</xsl:when>
<xsl:when test="$iModClass = 'PERIPHERAL'">Peripheral</xsl:when>
<xsl:when test="$iModClass = 'PROCESSOR'">Processor</xsl:when>
<xsl:when test="$iModClass = 'BUS_BRIDGE'">Bus Bridge</xsl:when>
<xsl:otherwise><xsl:value-of select="$iModClass"/></xsl:otherwise>
</xsl:choose>
</xsl:template>
<xsl:template name="F_Connection_To_AXI_SLAVE">
<xsl:param name="iNameParam" select="''"/>
<xsl:param name="iModuleRefParam" select="''"/>
<xsl:variable name="FilName" select="$iModuleRefParam/PARAMETERS/PARAMETER[@NAME=concat('C_', $iNameParam, '_MASTERS')]/@VALUE"/>
<!-- <xsl:message>FIL NAME WAS <xsl:value-of select="$FilName"/></xsl:message> -->
<xsl:value-of select="$FilName"/>
</xsl:template>
<xsl:template name="F_IS_Interface_External">
<xsl:param name="iInstRef"/> <!-- Instance reference -->
<xsl:param name="iIntfRef"/> <!-- Interface reference -->
<xsl:variable name="intfName_" select="$iIntfRef/@NAME"/>
<xsl:variable name="instName_" select="$iInstRef/@INSTANCE"/>
<!-- <xsl:message>NAME 1 <xsl:value-of select="$expName1_"/></xsl:message>-->
<!-- <xsl:message>NAME 2 <xsl:value-of select="$expName2_"/></xsl:message>-->
<!--
<xsl:variable name="expName1_" select="concat($instName_,'_',$intfName_,'_',@PHYSICAL,'_pin')"/>
<xsl:variable name="expName2_" select="concat($instName_,'_',@PHYSICAL,'_pin')"/>
-->
<!-- Store the number of physical ports connected externals in a variable -->
<xsl:variable name="connected_externals_">
<xsl:for-each select="$iIntfRef/PORTMAPS/PORTMAP">
<xsl:variable name="portName_" select="@PHYSICAL"/>
<xsl:if test="$iInstRef/PORTS/PORT[(@NAME = $portName_)]">
<xsl:variable name="portNet_" select="$iInstRef/PORTS/PORT[(@NAME = $portName_)]/@SIGNAME"/>
<xsl:if test="$G_SYS_EXPS/PORT[(@SIGNAME = $portNet_)]">
<EXTP NAME="{@PHYSICAL}"/>
</xsl:if>
</xsl:if>
</xsl:for-each>
</xsl:variable>
<!--
<xsl:message><xsl:value-of select="$instName_"/>.<xsl:value-of select="$intfName_"/> has <xsl:value-of select="count(exsl:node-set($connected_externals_)/EXTP)"/> connected externals.</xsl:message>
-->
<xsl:choose>
<xsl:when test="(count(exsl:node-set($connected_externals_)/EXTP) &gt; 0)">TRUE</xsl:when>
<xsl:otherwise>FALSE</xsl:otherwise>
</xsl:choose>
</xsl:template>
</xsl:stylesheet>
projnav/xps/__xps/edw2xtl_sav_view.xsl 0 → 100644
View file @ a64d58e7
<?xml version="1.0" standalone="no"?>
<!DOCTYPE stylesheet [
<!ENTITY UPPERCASE "ABCDEFGHIJKLMNOPQRSTUVWXYZ">
<!ENTITY LOWERCASE "abcdefghijklmnopqrstuvwxyz">
<!ENTITY UPPER2LOWER " '&UPPERCASE;' , '&LOWERCASE;' ">
<!ENTITY LOWER2UPPER " '&LOWERCASE;' , '&UPPERCASE;' ">
<!ENTITY ALPHALOWER "ABCDEFxX0123456789">
<!ENTITY HEXUPPER "ABCDEFxX0123456789">
<!ENTITY HEXLOWER "abcdefxX0123456789">
<!ENTITY HEXU2L " '&HEXLOWER;' , '&HEXUPPER;' ">
]>
<xsl:stylesheet version="1.0"
xmlns:xsl="http://www.w3.org/1999/XSL/Transform"
xmlns:exsl="http://exslt.org/common"
xmlns:dyn="http://exslt.org/dynamic"
xmlns:math="http://exslt.org/math"
xmlns:xlink="http://www.w3.org/1999/xlink"
extension-element-prefixes="math exsl dyn xlink">
<xsl:include href="edw2xtl_sav_globals.xsl"/>
<xsl:include href="edw2xtl_sav_view_addr.xsl"/>
<xsl:include href="edw2xtl_sav_view_busif.xsl"/>
<xsl:include href="edw2xtl_sav_view_port.xsl"/>
<xsl:include href="edw2xtl_sav_view_groups.xsl"/>
<xsl:output method="xml" version="1.0" encoding="UTF-8" indent="yes"/>
<xsl:param name="P_SYSTEM_XML" select= "'__UNDEF__'"/>
<xsl:param name="P_GROUPS_XML" select= "'__UNDEF__'"/>
<xsl:param name="G_DEBUG" select="'FALSE'"/>
<xsl:param name="G_ADD_CHOICES" select="'TRUE'"/>
<!--
<xsl:param name="P_VIEW" select="'__UNDEF__'"/>
<xsl:param name="P_MODE" select="'__UNDEF__'"/>
<xsl:param name="P_SCOPE" select="'__UNDEF__'"/>
-->
<!-- MAIN TEMPLATE -->
<xsl:template match="SAV[@VIEW]">
<xsl:if test="$G_DEBUG='TRUE'">
<xsl:message>SAV VIEW <xsl:value-of select="@VIEW"/></xsl:message>
<xsl:message>SAV MODE <xsl:value-of select="@MODE"/></xsl:message>
<xsl:message>SAV SCOPE <xsl:value-of select="@SCOPE"/></xsl:message>
</xsl:if>
<xsl:choose>
<xsl:when test="not(@VIEW = 'PORT') and not(@VIEW = 'BUSINTERFACE') and not(@VIEW = 'ADDRESS')">
<xsl:message>EDW2SAV XTELLER ERROR: UNDEFINED VIEW <xsl:value-of select="@VIEW"/></xsl:message>
</xsl:when>
<xsl:when test="(@MODE and not(@MODE = 'FLAT') and not(@MODE = 'TREE') and not(@MODE = 'GROUPS'))">
<xsl:message>EDW2SAV XTELLER ERROR: UNDEFINED MODE <xsl:value-of select="@MODE"/></xsl:message>
</xsl:when>
<xsl:when test="(@SCOPE and not(@SCOPE = 'FULL') and not(@SCOPE= 'FOCUS'))">
<xsl:message>EDW2SAV XTELLER ERROR: UNDEFINED SCOPE <xsl:value-of select="@SCOPE"/></xsl:message>
</xsl:when>
<xsl:when test="$P_SYSTEM_XML ='__UNDEF__'">
<xsl:message>EDW2SAV XTELLER ERROR: SYSTEM XML UNDEFINED</xsl:message>
</xsl:when>
<xsl:when test="not($G_SYS)" >
<xsl:message>EDW2SAV XTELLER ERROR: EDKSYSTEM MISSING in SYSTEM XML <xsl:value-of select="$P_SYSTEM_XML"/></xsl:message>
</xsl:when>
<xsl:when test="($P_GROUPS_XML ='__UNDEF__') and (@MODE = 'GROUPS')" >
<xsl:message>EDW2SAV XTELLER ERROR: GROUP XML UNDEFINED for FOCUS</xsl:message>
</xsl:when>
<xsl:when test="($P_GROUPS_XML ='__UNDEF__') and (@SCOPE = 'FOCUS') and (@VIEW = 'BUSINTERFACE')" >
<xsl:message>EDW2SAV XTELLER ERROR: GROUP XML UNDEFINED for SCOPE</xsl:message>
</xsl:when>
<xsl:otherwise>
<xsl:if test="$G_DEBUG='TRUE'">
<xsl:message>SYSTEM XML <xsl:value-of select="$P_SYSTEM_XML"/></xsl:message>
<xsl:message>GROUPS XML <xsl:value-of select="$P_GROUPS_XML"/></xsl:message>
</xsl:if>
<xsl:variable name="use_mode_">
<xsl:choose>
<xsl:when test="@MODE = 'GROUPS'">TREE</xsl:when>
<xsl:otherwise><xsl:value-of select="@MODE"/></xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:variable name="num_procs_focused_on_" select="count(MASTER)"/>
<xsl:variable name="num_buses_focused_on_" select="count(BUS)"/>
<xsl:element name="SET">
<xsl:attribute name="CLASS">PROJECT</xsl:attribute>
<xsl:attribute name="VIEW_ID"><xsl:value-of select="@VIEW"/></xsl:attribute>
<xsl:attribute name="DISPLAYMODE"><xsl:value-of select="$use_mode_"/></xsl:attribute>
<xsl:choose>
<!-- ADDRESS TAB VIEW -->
<xsl:when test="(@VIEW = 'ADDRESS')">
<xsl:call-template name="WRITE_VIEW_ADDRESS"/>
</xsl:when>
<!-- BIF TAB VIEWS -->
<xsl:when test="((@VIEW ='BUSINTERFACE') and (@SCOPE = 'FOCUS') and ($num_procs_focused_on_ &gt; 0))">
<xsl:call-template name="WRITE_VIEW_BIF_FOCUS_ON_PROCS"/>
</xsl:when>
<!-- BIF TAB VIEWS -->
<xsl:when test="((@VIEW ='BUSINTERFACE') and (@SCOPE = 'FOCUS') and ($num_buses_focused_on_ &gt; 0))">
<xsl:call-template name="WRITE_VIEW_BIF_FOCUS_ON_BUSES"/>
</xsl:when>
<xsl:when test="((@VIEW ='BUSINTERFACE') and (@MODE = 'TREE') and not(@SCOPE))">
<xsl:call-template name="WRITE_VIEW_BIF_TREE"/>
</xsl:when>
<xsl:when test="((@VIEW = 'BUSINTERFACE') and (@MODE = 'FLAT') and not(@SCOPE))">
<xsl:call-template name="WRITE_VIEW_BIF_FLAT"/>
</xsl:when>
<xsl:when test="((@VIEW = 'BUSINTERFACE') and (@MODE = 'GROUPS'))">
<xsl:call-template name="WRITE_VIEW_BIF_GROUPS">
<xsl:with-param name="iModules" select="$G_BLOCKS"/>
</xsl:call-template>
</xsl:when>
<!-- PORT TAB VIEWS -->
<xsl:when test="((@VIEW ='PORT') and (@SCOPE = 'FOCUS'))">
<xsl:call-template name="WRITE_VIEW_PORT_FOCUSED"/>
</xsl:when>
<!-- Generate XTeller panel data for Ports using hierarchy -->
<xsl:when test="((@VIEW = 'PORT') and (@MODE = 'TREE'))">
<xsl:call-template name="WRITE_VIEW_PORT_TREE"/>
</xsl:when>
<!-- Generate XTeller panel data for Ports without hierarchy, (flat view) -->
<xsl:when test="((@VIEW='PORT') and (@MODE = 'FLAT'))">
<xsl:call-template name="WRITE_VIEW_PORT_FLAT"/>
</xsl:when>
<xsl:otherwise>
<xsl:message>ERROR during SAV XTeller generation with panel <xsl:value-of select="@VIEW"/> and display mode <xsl:value-of select="@MODE"/></xsl:message>
</xsl:otherwise>
</xsl:choose>
</xsl:element>
</xsl:otherwise>
</xsl:choose>
</xsl:template>
<xsl:template match="EDKSYSTEM">
<!--
<xsl:message>EDW VERSION <xsl:value-of select="$G_EDWVER"/></xsl:message>
<xsl:message>VIEW <xsl:value-of select="$VIEW"/></xsl:message>
<xsl:message>MODE <xsl:value-of select="$MODE"/></xsl:message>
-->
<xsl:variable name="by_interface_">
<xsl:choose>
<!--
Show interfaces or not
-->
<xsl:when test="(($SHOW_BUSIF ='TRUE') or ($SHOW_IOIF ='TRUE'))">TRUE</xsl:when>
<xsl:otherwise>FALSE</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<!--
<xsl:message>VIEW <xsl:value-of select="$VIEW"/></xsl:message>
<xsl:message>MODE <xsl:value-of select="$MODE"/></xsl:message>
<xsl:message>BY INTERFACE <xsl:value-of select="$by_interface_"/></xsl:message>
-->
<xsl:variable name="displayMode_">
<xsl:choose>
<!--
Hard code view to view for address panel,
always show view in what was formerly
multiprocessor view. See below.
<xsl:when test="(($G_NUM_OF_PROCS &gt; 1) and ($VIEW='ADDRESS'))">TREE</xsl:when>
<xsl:when test="(($G_NUM_OF_PROCS &lt;= 1) and ($VIEW='ADDRESS'))">FLAT</xsl:when>
-->
<xsl:when test="($VIEW='ADDRESS')">TREE</xsl:when>
<xsl:otherwise><xsl:value-of select="$MODE"/></xsl:otherwise>
</xsl:choose>
</xsl:variable>
<SET CLASS="PROJECT" VIEW= "{$VIEW}" MODE="{$displayMode_}">
<xsl:choose>
<!-- Generate XTeller panel data for Bus Interfaces using hierarchy -->
<xsl:when test="(($VIEW='BUSINTERFACE') and (not($MODE) or ($MODE = 'TREE')))">
<xsl:call-template name="WRITE_VIEW_BIF_TREE"/>
</xsl:when>
<!-- Generate XTeller panel data for Bus Interfaces without hierarchy, (flat view) -->
<xsl:when test="(($VIEW='BUSINTERFACE') and ($MODE = 'FLAT'))">
<xsl:call-template name="WRITE_VIEW_BIF_FLAT"/>
</xsl:when>
<!-- Generate XTeller panel data for Ports using hierarchy -->
<xsl:when test="(($VIEW='PORT') and (not($MODE) or ($MODE = 'TREE')))">
<xsl:call-template name="WRITE_VIEW_PORT_TREE"/>
</xsl:when>
<!-- Generate XTeller panel data for Ports without hierarchy, (flat view) -->
<xsl:when test="(($VIEW='PORT') and ($MODE = 'FLAT'))">
<xsl:call-template name="WRITE_VIEW_PORT_FLAT"/>
</xsl:when>
<!--
Hard code display of the address panel to always the the same.
No more tree or flat mode, always show address panel
in what was formerly the multiprocessor view.
-->
<xsl:when test="($VIEW='ADDRESS')">
<xsl:call-template name="WRITE_VIEW_ADDRESS"/>
</xsl:when>
<xsl:otherwise>
<xsl:message>ERROR during SAV XTeller generation with panel <xsl:value-of select="$VIEW"/> and display mode <xsl:value-of select="$MODE"/></xsl:message>
</xsl:otherwise>
</xsl:choose>
</SET>
</xsl:template>
</xsl:stylesheet>
projnav/xps/__xps/edw2xtl_sav_view_addr.xsl 0 → 100644
View file @ a64d58e7
<?xml version="1.0" standalone="no"?>
<!DOCTYPE stylesheet [
<!ENTITY UPPERCASE "ABCDEFGHIJKLMNOPQRSTUVWXYZ">
<!ENTITY LOWERCASE "abcdefghijklmnopqrstuvwxyz">
<!ENTITY UPPER2LOWER " '&UPPERCASE;' , '&LOWERCASE;' ">
<!ENTITY LOWER2UPPER " '&LOWERCASE;' , '&UPPERCASE;' ">
<!ENTITY ALPHALOWER "ABCDEFxX0123456789">
<!ENTITY HEXUPPER "ABCDEFxX0123456789">
<!ENTITY HEXLOWER "abcdefxX0123456789">
<!ENTITY HEXU2L " '&HEXLOWER;' , '&HEXUPPER;' ">
]>
<xsl:stylesheet version="1.0"
xmlns:xsl="http://www.w3.org/1999/XSL/Transform"
xmlns:exsl="http://exslt.org/common"
xmlns:dyn="http://exslt.org/dynamic"
xmlns:math="http://exslt.org/math"
xmlns:xlink="http://www.w3.org/1999/xlink"
extension-element-prefixes="exsl dyn math xlink">
<xsl:output method="xml" version="1.0" encoding="UTF-8" indent="yes"/>
<!--
================================================================================
Generate XTeller for ADDRESSES
================================================================================
-->
<xsl:template name="WRITE_VIEW_ADDRESS">
<xsl:for-each select="$G_SYS_MODS/MODULE[((@MODCLASS = 'PROCESSOR') and (MEMORYMAP/MEMRANGE[((not(@IS_VALID) or (@IS_VALID = 'TRUE')) and ACCESSROUTE)]))]">
<xsl:sort data-type="number" select="@ROW_INDEX" order="ascending"/>
<xsl:variable name="procInst_" select="@INSTANCE"/>
<xsl:variable name="procMod_" select="self::node()"/>
<xsl:variable name="procModType" select="@MODTYPE"/>
<xsl:variable name="procModClass_" select="@MODCLASS"/>
<xsl:variable name="procInstHdrVal_"><xsl:value-of select="$procInst_"/>'s Address Map</xsl:variable>
<xsl:variable name="procInstRowIdx_" select="position() - 1"/>
<!-- <SET ID="{$procInst_}" CLASS="MODULE" ROW_INDEX="{$procInstRowIdx_}"> -->
<xsl:element name="SET">
<xsl:attribute name="ID"><xsl:value-of select="$procInst_"/></xsl:attribute>
<xsl:attribute name="CLASS">MODULE</xsl:attribute>
<xsl:attribute name="ROW_INDEX"><xsl:value-of select="$procInstRowIdx_"/></xsl:attribute>
<!-- <VARIABLE VIEWTYPE="STATIC" VIEWDISP="Instance" NAME="INSTANCE" VALUE="{$procInstHdrVal_}"/> -->
<xsl:element name="VARIABLE">
<xsl:attribute name="NAME">INSTANCE</xsl:attribute>
<xsl:attribute name="VALUE"><xsl:value-of select="$procInstHdrVal_"/></xsl:attribute>
<xsl:attribute name="VIEWDISP">Instance</xsl:attribute>
<xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
</xsl:element>
<xsl:for-each select="$procMod_/MEMORYMAP/MEMRANGE[((not(@IS_VALID) or (@IS_VALID = 'TRUE')) and (ACCESSROUTE or (@MEMTYPE = 'BRIDGE')))]">
<xsl:sort data-type="number" select="@BASEDECIMAL" order="ascending"/>
<xsl:variable name="addr_id_"><xsl:value-of select="@BASENAME"/>:<xsl:value-of select="@HIGHNAME"/></xsl:variable>
<xsl:variable name="baseName_" select="@BASENAME"/>
<xsl:variable name="highName_" select="@HIGHNAME"/>
<!--
<xsl:if test="$G_DEBUG='TRUE'">
<xsl:message>ADDRESS ID <xsl:value-of select="$addr_id_"/></xsl:message>
</xsl:if>
-->
<xsl:variable name="set_id_">
<xsl:if test="(@INSTANCE)">
<xsl:value-of select="$procInst_"/>.<xsl:value-of select="@INSTANCE"/>:<xsl:value-of select="$addr_id_"/>
</xsl:if>
<xsl:if test="not(@INSTANCE)">
<xsl:value-of select="$procInst_"/>:<xsl:value-of select="$addr_id_"/>
</xsl:if>
</xsl:variable>
<xsl:variable name="procAddrRowIdx_" select="position() - 1"/>
<SET ID="{$set_id_}" CLASS="ADDRESS" ROW_INDEX="{$procAddrRowIdx_}">
<xsl:if test="(@INSTANCE)">
<xsl:variable name="periInst_" select="@INSTANCE"/>
<xsl:variable name="periMod_" select="key('G_MAP_MODULES', $periInst_)"/>
<!--
<xsl:variable name="subInstance_" select="$G_SYS_MODS/MODULE[(@INSTANCE = $instance_)]"/>
<xsl:message>Count memrange slaves <xsl:value-of select="count($modMemMapSlvs_)"/> </xsl:message>
<xsl:message>Count mod valid bifs <xsl:value-of select="count($modValidBifs_)"/> </xsl:message>
-->
<xsl:variable name="periModType_" select="$periMod_/@MODTYPE"/>
<xsl:variable name="periViewIcon_" select="$periMod_/LICENSEINFO/@ICON_NAME"/>
<xsl:variable name="periHwVersion_" select="$periMod_/@HWVERSION"/>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="Instance" NAME="INSTANCE" VALUE="{$periInst_}"/>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Type" NAME="MODTYPE" VALUE="{$periModType_}" VIEWICON="{$periViewIcon_}"/>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Version" NAME="HWVERSION" VALUE="{$periHwVersion_}"/>
</xsl:if>
<xsl:if test="not(@INSTANCE)">
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="Instance" NAME="INSTANCE" VALUE="{$procInst_}"/>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Type" NAME="MODTYPE" VALUE="{$procModType}" VIEWICON="{$procMod_/LICENSEINFO/@ICON_NAME}"/>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Version" NAME="HWVERSION" VALUE="{$procHwVersion_}"/>
</xsl:if>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="Address Type" NAME="MEMTYPE" VALUE="{@MEMTYPE}"/>
<xsl:variable name="instName_">
<xsl:choose>
<xsl:when test="@INSTANCE"><xsl:value-of select="@INSTANCE"/></xsl:when>
<xsl:otherwise>Connected<xsl:value-of select="$procInst_"/></xsl:otherwise>
</xsl:choose>
</xsl:variable>
<!--
<xsl:message>INST : <xsl:value-of select="$set_id_"/></xsl:message>
-->
<xsl:variable name="is_locked_">
<xsl:if test="@IS_LOCKED = 'TRUE'">TRUE</xsl:if>
<xsl:if test="not(@IS_LOCKED) or not(@IS_LOCKED = 'TRUE')">FALSE</xsl:if>
</xsl:variable>
<xsl:variable name="baseAddrViewType_">
<xsl:choose>
<xsl:when test="$is_locked_='TRUE'">STATIC</xsl:when>
<xsl:otherwise>TEXTBOX</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:if test="(@SIZEABRV and not(@SIZEABRV = 'U'))">
<xsl:variable name="baseAddr_"><xsl:value-of select="translate(@BASEVALUE,&HEXU2L;)"/></xsl:variable>
<xsl:variable name="highAddr_"><xsl:value-of select="translate(@HIGHVALUE,&HEXU2L;)"/></xsl:variable>
<VARIABLE VIEWTYPE="{$baseAddrViewType_}" VIEWDISP="Base Address" NAME="BASEVALUE" VALUE="{$baseAddr_}"/>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="High Address" NAME="HIGHVALUE" VALUE="{$highAddr_}"/>
<xsl:if test="not(@MEMTYPE) or not(@MEMTYPE = 'BRIDGE')">
<VARIABLE VIEWTYPE="CHECKBOX" VIEWDISP="Lock" NAME="IS_LOCKED" VALUE="{$is_locked_}"/>
</xsl:if>
<xsl:if test="@MEMTYPE and (@MEMTYPE = 'BRIDGE') and not(@BRIDGE_TO)">
<VARIABLE VIEWTYPE="CHECKBOX" VIEWDISP="Lock" NAME="IS_LOCKED" VALUE="{$is_locked_}"/>
</xsl:if>
</xsl:if>
<xsl:if test="(@SIZEABRV and (@SIZEABRV = 'U'))">
<VARIABLE VIEWTYPE="TEXTBOX" VIEWDISP="Base Address" NAME="BASEVALUE" VALUE=""/>
</xsl:if>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="Base Name" NAME="BASENAME" VALUE="{@BASENAME}"/>
<xsl:variable name="sizeViewType_">
<xsl:choose>
<xsl:when test="(@SIZEABRV and (@SIZEABRV = 'U'))">DROPDOWN</xsl:when>
<xsl:when test="$is_locked_='TRUE'">STATIC</xsl:when>
<xsl:otherwise>DROPDOWN</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<VARIABLE VIEWTYPE="{$sizeViewType_}" VIEWDISP="Size" NAME="SIZEABRV" VALUE="{@SIZEABRV}"/>
<xsl:variable name="periInst_" select="@INSTANCE"/>
<xsl:variable name="periMod_" select="key('G_MAP_MODULES', $periInst_)"/>
<xsl:variable name="periModClass_" select="$periMod_/@MODCLASS"/>
<xsl:variable name="periValidBifs_" select="key('G_MAP_ALL_BIFS', $periInst_)[not(@BUSNAME = '__NOC__')]"/>
<xsl:variable name="periMemMapSlvs_" select="$periMod_/MEMORYMAP/MEMRANGE[(@BASENAME = $baseName_) and (@HIGHNAME = $highName_)]/SLAVES/SLAVE"/>
<xsl:variable name="periMemMapBifs_">
<xsl:for-each select="$periMemMapSlvs_">
<xsl:variable name="periSlvBifName_" select="@BUSINTERFACE"/>
<xsl:if test="$periValidBifs_[(@NAME = $periSlvBifName_)]">
<xsl:variable name="periBif_" select="$periValidBifs_[(@NAME = $periSlvBifName_)]"/>
<xsl:variable name="periBifName_" select="$periBif_/@NAME"/>
<xsl:variable name="periBifBus_" select="$periBif_/@BUSNAME"/>
<!--
<xsl:message> Slv Bif <xsl:value-of select="$periBifName_"/> = <xsl:value-of select="$periBifBus_"/></xsl:message>
-->
<MMBIF NAME="{$periBifName_}" BUS="{$periBifBus_}"/>
</xsl:if>
</xsl:for-each>
</xsl:variable>
<xsl:variable name="num_of_periMemMapBifs_" select="count(exsl:node-set($periMemMapBifs_)/MMBIF)"/>
<!--
<xsl:message> Total num of slv bifs <xsl:value-of select="$num_of_periMemMapBifs_"/> </xsl:message>
<xsl:message> </xsl:message>
-->
<xsl:variable name="valid_bifNames_">
<xsl:for-each select="exsl:node-set($periMemMapBifs_)/MMBIF">
<xsl:variable name="bifName_" select="@NAME"/>
<xsl:if test="position() &gt; 1">:</xsl:if><xsl:value-of select="$bifName_"/>
</xsl:for-each>
</xsl:variable>
<xsl:variable name="valid_busNames_">
<xsl:for-each select="exsl:node-set($periMemMapBifs_)/MMBIF">
<xsl:variable name="busName_" select="@BUS"/>
<xsl:if test="position() &gt; 1">:</xsl:if><xsl:value-of select="$busName_"/>
</xsl:for-each>
</xsl:variable>
<!--
<xsl:message> Mod Bif <xsl:value-of select="$bifName_"/> : <xsl:value-of select="position()"/></xsl:message>
<xsl:message> Mod Bif <xsl:value-of select="$bifName_"/> : <xsl:value-of select="position()"/></xsl:message>
<xsl:message>Slv Bif <xsl:value-of select="$bifName_"/> : <xsl:value-of select="position()"/></xsl:message>
<xsl:variable name="modBifs_" select="$modInst_/BUSINTERFACES"/>
<xsl:if test="$periValidBifs_[(@NAME = $bifName_)]">
<xsl:variable name="busName_" select="$periValidBifs_[(@NAME = $bifName_)]/@BUSNAME"/>
<xsl:message>Mod Bif <xsl:value-of select="$bifName_"/> : <xsl:value-of select="position()"/></xsl:message>
<xsl:if test="position() &gt; 1">:</xsl:if><xsl:value-of select="$bifName_"/>
</xsl:if>
-->
<!--
<xsl:message>Module Instances <xsl:value-of select="$instName_"/> </xsl:message>
<xsl:message>Base Name <xsl:value-of select="$baseName_"/> </xsl:message>
<xsl:message>High Name <xsl:value-of select="$highName_"/> </xsl:message>
<xsl:message>Valid bif names <xsl:value-of select="$valid_bifNames_"/> </xsl:message>
<xsl:message>Valid bif names <xsl:value-of select="$valid_bifNames_"/> </xsl:message>
<xsl:message>Valid bus names <xsl:value-of select="$valid_busNames_"/> </xsl:message>
-->
<xsl:variable name="var_bifNames_">
<xsl:choose>
<xsl:when test="string-length($valid_bifNames_) &lt; 1">
<xsl:choose>
<xsl:when test="$periModClass_ = 'BUS'">Not Applicable</xsl:when>
<xsl:otherwise>Not Connected</xsl:otherwise>
</xsl:choose>
</xsl:when>
<xsl:otherwise><xsl:value-of select="$valid_bifNames_"/></xsl:otherwise>
</xsl:choose>
</xsl:variable>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="Bus Interface(s)" NAME="BIFNAMES" VALUE="{$var_bifNames_}"/>
<xsl:if test="(($num_of_periMemMapBifs_ &gt; 0) and (string-length($valid_busNames_) &gt; 0))">
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="Bus Name" NAME="BUSNAME" VALUE="{$valid_busNames_}"/>
</xsl:if>
</SET> <!-- End of one processor memory range row -->
</xsl:for-each> <!-- end of processor memory ranges loop -->
</xsl:element><!-- End of Processor memory map set -->
</xsl:for-each> <!-- end of processor module address space loop -->
<!--
Add branch for valid address that are not part of a processor's
memory map. Usually modules that have just been added, but have
not been connected to a bus yet.
-->
<xsl:variable name="nonProcAddresses_">
<!-- Add a dummy non proc as a place holder. Otherwise the exsl:node-set test
Below complains if the variable is completely empty
-->
<NONPROCADDRESS INSTANCE="__DUMMY__" BASENAME="__DUMMY__" HIGHNAME="__DUMMY__" BASEDECIMAL="__DUMMY__"/>
<xsl:for-each select="$G_SYS_MODS/MODULE[(not(@MODCLASS = 'PROCESSOR') and (MEMORYMAP/MEMRANGE[((not(@IS_VALID) or (@IS_VALID = 'TRUE')) and ACCESSROUTE)]))]">
<xsl:variable name="nonProcInst_" select="@INSTANCE"/>
<xsl:for-each select="MEMORYMAP/MEMRANGE[(not(@IS_VALID) or (@IS_VALID = 'TRUE'))]">
<xsl:variable name="highName_" select="@HIGHNAME"/>
<xsl:variable name="baseName_" select="@BASENAME"/>
<xsl:variable name="baseDecimal_" select="@BASEDECIMAL"/>
<xsl:if test="not($G_SYS_MODS/MODULE[(@MODCLASS = 'PROCESSOR')]/MEMORYMAP/MEMRANGE[((@INSTANCE = $nonProcInst_) and (@BASENAME = $baseName_) and (@HIGHNAME = $highName_))])">
<NONPROCADDRESS INSTANCE="{$nonProcInst_}" BASENAME="{$baseName_}" HIGHNAME="{$highName_}" BASEDECIMAL="{$baseDecimal_}"/>
</xsl:if>
</xsl:for-each>
</xsl:for-each>
</xsl:variable>
<!-- Add unmapped addresses -->
<xsl:variable name="hasUnMappedAddress">
<xsl:for-each select="$G_SYS_MODS/MODULE[(not(@MODCLASS = 'PROCESSOR') and (MEMORYMAP/MEMRANGE[(not(@IS_VALID) or (@IS_VALID = 'TRUE'))]))]">
<xsl:variable name="nonProcInst_" select="@INSTANCE"/>
<xsl:for-each select="MEMORYMAP/MEMRANGE[(not(@IS_VALID) or (@IS_VALID = 'TRUE'))]">
<xsl:variable name="highName_" select="@HIGHNAME"/>
<xsl:variable name="baseName_" select="@BASENAME"/>
<xsl:variable name="baseDecimal_" select="@BASEDECIMAL"/>
<xsl:if test="not($G_SYS_MODS/MODULE[(@MODCLASS = 'PROCESSOR')]/MEMORYMAP/MEMRANGE[((@INSTANCE = $nonProcInst_) and (@BASENAME = $baseName_) and (@HIGHNAME = $highName_))])"><xsl:value-of select="$nonProcInst_"/></xsl:if>
</xsl:for-each>
</xsl:for-each>
</xsl:variable>
<xsl:if test="string-length($hasUnMappedAddress) &gt; 1">
<SET ID="Unmapped Addresses" CLASS="MODULE" ROW_INDEX="{$G_NUM_OF_PROCS_W_ADDRS}">
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="Instance" NAME="INSTANCE" VALUE="Unmapped Addresses"/>
<xsl:for-each select="$G_SYS_MODS/MODULE[(not(@MODCLASS = 'PROCESSOR') and (MEMORYMAP/MEMRANGE[(not(@IS_VALID) or (@IS_VALID = 'TRUE'))]))]/MEMORYMAP/MEMRANGE[(not(@IS_VALID) or (@IS_VALID = 'TRUE'))]">
<xsl:variable name="nonProcMod_" select="../.."/>
<xsl:variable name="nonProcMMap_" select="$nonProcMod_/MEMORYMAP"/>
<xsl:variable name="instance_" select="$nonProcMod_/@INSTANCE"/>
<xsl:variable name="row_index_" select="position()"/>
<xsl:variable name="instName_" select="$nonProcMod_/@INSTANCE"/>
<xsl:variable name="highName_" select="@HIGHNAME"/>
<xsl:variable name="baseName_" select="@BASENAME"/>
<xsl:variable name="baseDecimal_" select="@BASEDECIMAL"/>
<xsl:for-each select="$nonProcMMap_/MEMRANGE[((@BASENAME = $baseName_) and (@HIGHNAME = $highName_))]">
<xsl:if test="not($G_SYS_MODS/MODULE[(@MODCLASS = 'PROCESSOR')]/MEMORYMAP/MEMRANGE[((@INSTANCE = $instName_) and (@BASENAME = $baseName_) and (@HIGHNAME = $highName_))])">
<xsl:variable name="addr_id_"><xsl:value-of select="$baseName_"/>:<xsl:value-of select="$highName_"/></xsl:variable>
<xsl:variable name="set_id_"><xsl:value-of select="$instName_"/>:<xsl:value-of select="$addr_id_"/></xsl:variable>
<xsl:variable name="inst_modtype_" select="$nonProcMod_/@MODTYPE"/>
<xsl:variable name="inst_viewicon_" select="$nonProcMod_/LICENSEINFO/@ICON_NAME"/>
<xsl:variable name="inst_modclass_" select="$nonProcMod_/@MODCLASS"/>
<xsl:variable name="inst_hwversion_" select="$nonProcMod_/@HWVERSION"/>
<SET ID="{$set_id_}" CLASS="ADDRESS">
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="Instance" NAME="INSTANCE" VALUE="{$instance_}"/>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Type" NAME="MODTYPE" VALUE="{$inst_modtype_}" VIEWICON="{$inst_viewicon_}"/>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Version" NAME="HWVERSION" VALUE="{$inst_hwversion_}"/>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="Address Type" NAME="MEMTYPE" VALUE="{@MEMTYPE}"/>
<xsl:variable name="is_locked_">
<xsl:if test="@IS_LOCKED = 'TRUE'">TRUE</xsl:if>
<xsl:if test="not(@IS_LOCKED) or not(@IS_LOCKED = 'TRUE')">FALSE</xsl:if>
</xsl:variable>
<xsl:variable name="baseAddrViewType_">
<xsl:choose>
<xsl:when test="$is_locked_='TRUE'">STATIC</xsl:when>
<xsl:otherwise>TEXTBOX</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:if test="(@SIZEABRV and not(@SIZEABRV = 'U'))">
<xsl:variable name="baseAddr_"><xsl:value-of select="translate(@BASEVALUE,&HEXU2L;)"/></xsl:variable>
<xsl:variable name="highAddr_"><xsl:value-of select="translate(@HIGHVALUE,&HEXU2L;)"/></xsl:variable>
<VARIABLE VIEWTYPE="{$baseAddrViewType_}" VIEWDISP="Base Address" NAME="BASEVALUE" VALUE="{$baseAddr_}"/>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="High Address" NAME="HIGHVALUE" VALUE="{$highAddr_}"/>
<xsl:if test="not(@MEMTYPE) or not(@MEMTYPE = 'BRIDGE')">
<VARIABLE VIEWTYPE="CHECKBOX" VIEWDISP="Lock" NAME="IS_LOCKED" VALUE="{$is_locked_}"/>
</xsl:if>
<xsl:if test="@MEMTYPE and (@MEMTYPE = 'BRIDGE') and not(@BRIDGE_TO)">
<VARIABLE VIEWTYPE="CHECKBOX" VIEWDISP="Lock" NAME="IS_LOCKED" VALUE="{$is_locked_}"/>
</xsl:if>
</xsl:if>
<xsl:if test="(@SIZEABRV and (@SIZEABRV = 'U'))">
<VARIABLE VIEWTYPE="TEXTBOX" VIEWDISP="Base Address" NAME="BASEVALUE" VALUE=""/>
</xsl:if>
<!--
Lock, DCache and ICache removed in 11.1
<xsl:if test="(@IS_CACHEABLE = 'TRUE')">
<xsl:variable name="is_dcached_">
<xsl:if test="(@IS_DCACHED = 'TRUE')">TRUE</xsl:if>
<xsl:if test="(not(@IS_DCACHED) or not(@IS_DCACHED = 'TRUE'))">FALSE</xsl:if>
</xsl:variable>
<xsl:variable name="is_icached_">
<xsl:if test="(@IS_ICACHED = 'TRUE')">TRUE</xsl:if>
<xsl:if test="(not(@IS_ICACHED) or not(@IS_ICACHED = 'TRUE'))">FALSE</xsl:if>
</xsl:variable>
<VARIABLE VIEWTYPE="CHECKBOX" VIEWDISP="DCache" NAME="IS_DCACHED" VALUE="{$is_dcached_}"/>
<VARIABLE VIEWTYPE="CHECKBOX" VIEWDISP="ICache" NAME="IS_ICACHED" VALUE="{$is_icached_}"/>
</xsl:if>
-->
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="Base Name" NAME="BASENAME" VALUE="{@BASENAME}"/>
<xsl:variable name="sizeViewType_">
<xsl:choose>
<xsl:when test="(@SIZEABRV and (@SIZEABRV = 'U'))">DROPDOWN</xsl:when>
<xsl:when test="$is_locked_='TRUE'">STATIC</xsl:when>
<xsl:otherwise>DROPDOWN</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<VARIABLE VIEWTYPE="{$sizeViewType_}" VIEWDISP="Size" NAME="SIZEABRV" VALUE="{@SIZEABRV}"/>
<xsl:variable name="valid_bifNames_">
<xsl:choose>
<xsl:when test="$nonProcMMap_/MEMRANGE[(@BASENAME = $baseName_) and (@HIGHNAME = $highName_)]/SLAVES">
<xsl:for-each select="$nonProcMMap_/MEMRANGE[(@BASENAME = $baseName_) and (@HIGHNAME = $highName_)]/SLAVES/SLAVE">
<xsl:variable name="bifName_" select="@BUSINTERFACE"/>
<!-- <xsl:message>Bif Name <xsl:value-of select="$bifName_"/> </xsl:message> -->
<xsl:variable name="modBifs_" select="$nonProcMod_/BUSINTERFACES"/>
<xsl:if test="$modBifs_/BUSINTERFACE[((@NAME = $bifName_) and not(@IS_VALID = 'FALSE') and not(@BUSNAME = '__NOC__'))]">
<xsl:variable name="busName_" select="$modBifs_/BUSINTERFACE[((@NAME = $bifName_) and not(@IS_VALID = 'FALSE') and not(@BUSNAME = '__NOC__'))]/@BUSNAME"/>
<xsl:if test="position() &gt; 1">:</xsl:if><xsl:value-of select="@BUSINTERFACE"/>
</xsl:if>
</xsl:for-each>
</xsl:when>
<xsl:otherwise>
<xsl:for-each select="$nonProcMMap_/MEMRANGE[(@BASENAME = $baseName_) and (@HIGHNAME = $highName_)]/SLVINTERFACES/BUSINTERFACE">
<xsl:variable name="bifName_" select="@NAME"/>
<xsl:variable name="modBifs_" select="$nonProcMod_"/>
<xsl:if test="$modBifs_/BUSINTERFACE[((@NAME = $bifName_) and not(@IS_VALID = 'FALSE') and not(@BUSNAME = '__NOC__'))]">
<xsl:variable name="busName_" select="$modBifs_/BUSINTERFACE[((@NAME = $bifName_) and not(@IS_VALID = 'FALSE') and not(@BUSNAME = '__NOC__'))]/@BUSNAME"/>
<xsl:if test="position() &gt; 1">:</xsl:if><xsl:value-of select="@NAME"/>
</xsl:if>
</xsl:for-each>
</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:variable name="def_bifNames_">
<xsl:choose>
<xsl:when test="(string-length($valid_bifNames_) &lt; 1) or ((string-length($valid_bifNames_) = 1) and ($valid_bifNames_ = ':'))">Not Connected</xsl:when>
<xsl:when test="starts-with($valid_bifNames_,':')"><xsl:value-of select="substring-after($valid_bifNames_,':')"/></xsl:when>
<xsl:otherwise><xsl:value-of select="$valid_bifNames_"/></xsl:otherwise>
</xsl:choose>
</xsl:variable>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="Bus Interface(s)" NAME="BIFNAMES" VALUE="{$def_bifNames_}"/>
<xsl:choose>
<xsl:when test="$nonProcMMap_/MEMRANGE[(@BASENAME = $baseName_) and (@HIGHNAME = $highName_)]/SLAVES">
<xsl:for-each select="$nonProcMMap_/MEMRANGE[(@BASENAME = $baseName_) and (@HIGHNAME = $highName_)]/SLAVES/SLAVE">
<xsl:variable name="slvBifName_" select="@BUSINTERFACE"/>
<xsl:variable name="modBifs_" select="$nonProcMod_/BUSINTERFACES"/>
<xsl:if test="count($modBifs_/BUSINTERFACE[((@NAME = $slvBifName_) and not(@IS_VALID = 'FALSE') and not(@BUSNAME = '__NOC__'))]) = 1">
<xsl:variable name="slvBusName_" select="$modBifs_/BUSINTERFACE[((@NAME = $slvBifName_) and not(@IS_VALID = 'FALSE') and not(@BUSNAME = '__NOC__'))]/@BUSNAME"/>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="Bus Name" NAME="BUSNAME" VALUE="{$slvBusName_}"/>
</xsl:if>
</xsl:for-each>
</xsl:when>
<xsl:otherwise>
<xsl:for-each select="$nonProcMMap_/MEMRANGE[(@BASENAME = $baseName_) and (@HIGHNAME = $highName_)]/SLVINTERFACES/BUSINTERFACE">
<xsl:variable name="slvBifName_" select="@NAME"/>
<xsl:variable name="modBifs_" select="$nonProcMod_"/>
<xsl:if test="count($modBifs_/BUSINTERFACE[((@NAME = $slvBifName_) and not(@IS_VALID = 'FALSE') and not(@BUSNAME = '__NOC__'))]) = 1">
<xsl:variable name="slvBusName_" select="$modBifs_/BUSINTERFACE[((@NAME = $slvBifName_) and not(@IS_VALID = 'FALSE') and not(@BUSNAME = '__NOC__'))]/@BUSNAME"/>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="Bus Name" NAME="BUSNAME" VALUE="{$slvBusName_}"/>
</xsl:if>
</xsl:for-each>
</xsl:otherwise>
</xsl:choose>
</SET> <!-- End of one non processor memory range row -->
</xsl:if>
</xsl:for-each> <!-- end of non processor memory ranges loop -->
</xsl:for-each> <!-- end of NONPROCADDRESS loop -->
</SET> <!-- End of non processor tree branch -->
</xsl:if> <!-- End of test to see if we have and non processor mapped address -->
</xsl:template>
<xsl:template name="__WRITE_VIEW_ADDRESS__">
<!--
-->
<xsl:for-each select="$G_SYS_MODS/MODULE[((@MODCLASS = 'PROCESSOR') and (MEMORYMAP/MEMRANGE[((not(@IS_VALID) or (@IS_VALID = 'TRUE')) and ACCESSROUTE)]))]">
<xsl:sort data-type="number" select="@ROW_INDEX" order="ascending"/>
<xsl:variable name="procInst_" select="@INSTANCE"/>
<xsl:variable name="modClass_" select="@MODCLASS"/>
<xsl:variable name="procInstHdrVal_"><xsl:value-of select="$procInst_"/>'s Address Map</xsl:variable>
<xsl:variable name="procInstRowIdx_" select="position() - 1"/>
<xsl:variable name="modInstance_" select="self::node()"/>
<SET ID="{$procInst_}" CLASS="MODULE" ROW_INDEX="{$procInstRowIdx_}">
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="Instance" NAME="INSTANCE" VALUE="{$procInstHdrVal_}"/>
<xsl:for-each select="$modInstance_/MEMORYMAP/MEMRANGE[((not(@IS_VALID) or (@IS_VALID = 'TRUE')) and (ACCESSROUTE or (@MEMTYPE = 'BRIDGE')))]">
<xsl:sort data-type="number" select="@BASEDECIMAL" order="ascending"/>
<xsl:variable name="addr_id_"><xsl:value-of select="@BASENAME"/>:<xsl:value-of select="@HIGHNAME"/></xsl:variable>
<xsl:variable name="baseName_" select="@BASENAME"/>
<xsl:variable name="highName_" select="@HIGHNAME"/>
<xsl:if test="$G_DEBUG='TRUE'">
<xsl:message>ADDRESS ID <xsl:value-of select="$addr_id_"/></xsl:message>
</xsl:if>
<xsl:variable name="set_id_">
<xsl:if test="(@INSTANCE)">
<xsl:value-of select="$procInst_"/>.<xsl:value-of select="@INSTANCE"/>:<xsl:value-of select="$addr_id_"/>
</xsl:if>
<xsl:if test="not(@INSTANCE)">
<xsl:value-of select="$procInst_"/>:<xsl:value-of select="$addr_id_"/>
</xsl:if>
</xsl:variable>
<xsl:variable name="procAddrRowIdx_" select="position() - 1"/>
<SET ID="{$set_id_}" CLASS="ADDRESS" ROW_INDEX="{$procAddrRowIdx_}">
<xsl:if test="(@INSTANCE)">
<xsl:variable name="instance_" select="@INSTANCE"/>
<xsl:variable name="subInstance_" select="$G_SYS_MODS/MODULE[(@INSTANCE = $instance_)]"/>
<xsl:variable name="inst_modtype_" select="$subInstance_/@MODTYPE"/>
<xsl:variable name="inst_viewicon_" select="$subInstance_/LICENSEINFO/@ICON_NAME"/>
<xsl:variable name="inst_hwversion_" select="$subInstance_/@HWVERSION"/>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="Instance" NAME="INSTANCE" VALUE="{$instance_}"/>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Type" NAME="MODTYPE" VALUE="{$inst_modtype_}" VIEWICON="{$inst_viewicon_}"/>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Version" NAME="HWVERSION" VALUE="{$inst_hwversion_}"/>
</xsl:if>
<xsl:if test="not(@INSTANCE)">
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="Instance" NAME="INSTANCE" VALUE="{$modInstance_/@INSTANCE}"/>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Type" NAME="MODTYPE" VALUE="{$modInstance_/@MODTYPE}" VIEWICON="{$modInstance_/LICENSEINFO/@ICON_NAME}"/>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Version" NAME="HWVERSION" VALUE="{$modInstance_/@HWVERSION}"/>
</xsl:if>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="Address Type" NAME="MEMTYPE" VALUE="{@MEMTYPE}"/>
<xsl:variable name="instName_">
<xsl:choose>
<xsl:when test="@INSTANCE"><xsl:value-of select="@INSTANCE"/></xsl:when>
<xsl:otherwise>Connected<xsl:value-of select="$modInstance_/@INSTANCE"/></xsl:otherwise>
</xsl:choose>
</xsl:variable>
<!--
<xsl:message>INST : <xsl:value-of select="$set_id_"/></xsl:message>
-->
<xsl:variable name="is_locked_">
<xsl:if test="@IS_LOCKED = 'TRUE'">TRUE</xsl:if>
<xsl:if test="not(@IS_LOCKED) or not(@IS_LOCKED = 'TRUE')">FALSE</xsl:if>
</xsl:variable>
<xsl:variable name="baseAddrViewType_">
<xsl:choose>
<xsl:when test="$is_locked_='TRUE'">STATIC</xsl:when>
<xsl:otherwise>TEXTBOX</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:if test="(@SIZEABRV and not(@SIZEABRV = 'U'))">
<xsl:variable name="baseAddr_"><xsl:value-of select="translate(@BASEVALUE,&HEXU2L;)"/></xsl:variable>
<xsl:variable name="highAddr_"><xsl:value-of select="translate(@HIGHVALUE,&HEXU2L;)"/></xsl:variable>
<VARIABLE VIEWTYPE="{$baseAddrViewType_}" VIEWDISP="Base Address" NAME="BASEVALUE" VALUE="{$baseAddr_}"/>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="High Address" NAME="HIGHVALUE" VALUE="{$highAddr_}"/>
<xsl:if test="not(@MEMTYPE) or not(@MEMTYPE = 'BRIDGE')">
<VARIABLE VIEWTYPE="CHECKBOX" VIEWDISP="Lock" NAME="IS_LOCKED" VALUE="{$is_locked_}"/>
</xsl:if>
<xsl:if test="@MEMTYPE and (@MEMTYPE = 'BRIDGE') and not(@BRIDGE_TO)">
<VARIABLE VIEWTYPE="CHECKBOX" VIEWDISP="Lock" NAME="IS_LOCKED" VALUE="{$is_locked_}"/>
</xsl:if>
</xsl:if>
<xsl:if test="(@SIZEABRV and (@SIZEABRV = 'U'))">
<VARIABLE VIEWTYPE="TEXTBOX" VIEWDISP="Base Address" NAME="BASEVALUE" VALUE=""/>
</xsl:if>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="Base Name" NAME="BASENAME" VALUE="{@BASENAME}"/>
<xsl:variable name="sizeViewType_">
<xsl:choose>
<xsl:when test="(@SIZEABRV and (@SIZEABRV = 'U'))">DROPDOWN</xsl:when>
<xsl:when test="$is_locked_='TRUE'">STATIC</xsl:when>
<xsl:otherwise>DROPDOWN</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<VARIABLE VIEWTYPE="{$sizeViewType_}" VIEWDISP="Size" NAME="SIZEABRV" VALUE="{@SIZEABRV}"/>
<xsl:variable name="modInst_" select="$G_SYS_MODS/MODULE[(@INSTANCE = $instName_)]"/>
<xsl:variable name="modMemMap_" select="$modInst_/MEMORYMAP"/>
<xsl:variable name="valid_bifNames_">
<xsl:choose>
<xsl:when test="$modMemMap_/MEMRANGE[(@BASENAME = $baseName_) and (@HIGHNAME = $highName_)]/SLAVES">
<xsl:for-each select="$modMemMap_/MEMRANGE[(@BASENAME = $baseName_) and (@HIGHNAME = $highName_)]/SLAVES/SLAVE">
<xsl:variable name="bifName_" select="@BUSINTERFACE"/>
<!-- <xsl:message>Bif Name <xsl:value-of select="$bifName_"/> </xsl:message> -->
<xsl:variable name="modBifs_" select="$modInst_/BUSINTERFACES"/>
<xsl:if test="$modBifs_/BUSINTERFACE[((@NAME = $bifName_) and not(@IS_VALID = 'FALSE') and not(@BUSNAME = '__NOC__'))]">
<xsl:variable name="busName_" select="$modBifs_/BUSINTERFACE[((@NAME = $bifName_) and not(@IS_VALID = 'FALSE') and not(@BUSNAME = '__NOC__'))]/@BUSNAME"/>
<xsl:if test="position() &gt; 1">:</xsl:if><xsl:value-of select="@BUSINTERFACE"/>
</xsl:if>
</xsl:for-each>
</xsl:when>
<xsl:otherwise>
<xsl:for-each select="$modMemMap_/MEMRANGE[(@BASENAME = $baseName_) and (@HIGHNAME = $highName_)]/SLVINTERFACES/BUSINTERFACE">
<xsl:variable name="bifName_" select="@NAME"/>
<xsl:variable name="modBifs_" select="$modInst_"/>
<xsl:if test="$modBifs_/BUSINTERFACE[((@NAME = $bifName_) and not(@IS_VALID = 'FALSE') and not(@BUSNAME = '__NOC__'))]">
<xsl:variable name="busName_" select="$modBifs_/BUSINTERFACE[((@NAME = $bifName_) and not(@IS_VALID = 'FALSE') and not(@BUSNAME = '__NOC__'))]/@BUSNAME"/>
<xsl:if test="position() &gt; 1">:</xsl:if><xsl:value-of select="@NAME"/>
</xsl:if>
</xsl:for-each>
</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<!--
<xsl:message>Module Instances <xsl:value-of select="$instName_"/> </xsl:message>
<xsl:message>Base Name <xsl:value-of select="$baseName_"/> </xsl:message>
<xsl:message>High Name <xsl:value-of select="$highName_"/> </xsl:message>
<xsl:message>Valid bif names <xsl:value-of select="$valid_bifNames_"/> </xsl:message>
-->
<xsl:variable name="def_bifNames_">
<xsl:choose>
<xsl:when test="string-length($valid_bifNames_) &lt; 1">
<xsl:choose>
<xsl:when test="$modClass_ = 'BUS'">Not Applicable</xsl:when>
<xsl:otherwise>Not Connected</xsl:otherwise>
</xsl:choose>
</xsl:when>
<xsl:when test="starts-with($valid_bifNames_,':')"><xsl:value-of select="substring-after($valid_bifNames_,':')"/></xsl:when>
<xsl:otherwise><xsl:value-of select="$valid_bifNames_"/></xsl:otherwise>
</xsl:choose>
</xsl:variable>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="Bus Interface(s)" NAME="BIFNAMES" VALUE="{$def_bifNames_}"/>
<xsl:choose>
<xsl:when test="$modMemMap_/MEMRANGE[(@BASENAME = $baseName_) and (@HIGHNAME = $highName_)]/SLAVES">
<xsl:for-each select="$modMemMap_/MEMRANGE[(@BASENAME = $baseName_) and (@HIGHNAME = $highName_)]/SLAVES/SLAVE">
<xsl:variable name="bifName_" select="@BUSINTERFACE"/>
<xsl:variable name="modBifs_" select="$modInst_/BUSINTERFACES"/>
<xsl:if test="$modBifs_/BUSINTERFACE[((@NAME = $bifName_) and not(@IS_VALID = 'FALSE') and not(@BUSNAME = '__NOC__'))]">
<xsl:variable name="busName_" select="$modBifs_/BUSINTERFACE[((@NAME = $bifName_) and not(@IS_VALID = 'FALSE') and not(@BUSNAME = '__NOC__'))]/@BUSNAME"/>
<xsl:variable name="numBifs_" select="count($modBifs_/BUSINTERFACE[((@NAME = $bifName_) and not(@IS_VALID = 'FALSE') and not(@BUSNAME = '__NOC__'))])"/>
<xsl:if test="((position() = 1) or ($numBifs_ = 1))">
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="Bus Name" NAME="BUSNAME" VALUE="{$busName_}"/>
</xsl:if>
</xsl:if>
</xsl:for-each>
</xsl:when>
<xsl:otherwise>
<xsl:for-each select="$modMemMap_/MEMRANGE[(@BASENAME = $baseName_) and (@HIGHNAME = $highName_)]/SLVINTERFACES/BUSINTERFACE">
<xsl:variable name="bifName_" select="@NAME"/>
<xsl:variable name="modBifs_" select="$modInst_"/>
<xsl:if test="$modBifs_/BUSINTERFACE[((@NAME = $bifName_) and not(@IS_VALID = 'FALSE') and not(@BUSNAME = '__NOC__'))]">
<xsl:variable name="busName_" select="$modBifs_/BUSINTERFACE[((@NAME = $bifName_) and not(@IS_VALID = 'FALSE') and not(@BUSNAME = '__NOC__'))]/@BUSNAME"/>
<xsl:variable name="numBifs_" select="count($modBifs_/BUSINTERFACE[((@NAME = $bifName_) and not(@IS_VALID = 'FALSE') and not(@BUSNAME = '__NOC__'))])"/>
<xsl:if test="((position() = 1) or ($numBifs_ = 1))">
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="Bus Name" NAME="BUSNAME" VALUE="{$busName_}"/>
</xsl:if>
</xsl:if>
</xsl:for-each>
</xsl:otherwise>
</xsl:choose>
<!--
-->
</SET> <!-- End of one processor memory range row -->
</xsl:for-each> <!-- end of processor memory ranges loop -->
</SET>
</xsl:for-each> <!-- end of processor module address space loop -->
<!--
Add branch for valid address that are not part of a processor's
memory map. Usually modules that have just been added, but have
not been connected to a bus yet.
-->
<xsl:variable name="nonProcAddresses_">
<!-- Add a dummy non proc as a place holder. Otherwise the exsl:node-set test
Below complains if the variable is completely empty
-->
<NONPROCADDRESS INSTANCE="__DUMMY__" BASENAME="__DUMMY__" HIGHNAME="__DUMMY__" BASEDECIMAL="__DUMMY__"/>
<xsl:for-each select="$G_SYS_MODS/MODULE[(not(@MODCLASS = 'PROCESSOR') and (MEMORYMAP/MEMRANGE[((not(@IS_VALID) or (@IS_VALID = 'TRUE')) and ACCESSROUTE)]))]">
<xsl:variable name="nonProcInst_" select="@INSTANCE"/>
<xsl:for-each select="MEMORYMAP/MEMRANGE[(not(@IS_VALID) or (@IS_VALID = 'TRUE'))]">
<xsl:variable name="highName_" select="@HIGHNAME"/>
<xsl:variable name="baseName_" select="@BASENAME"/>
<xsl:variable name="baseDecimal_" select="@BASEDECIMAL"/>
<xsl:if test="not($G_SYS_MODS/MODULE[(@MODCLASS = 'PROCESSOR')]/MEMORYMAP/MEMRANGE[((@INSTANCE = $nonProcInst_) and (@BASENAME = $baseName_) and (@HIGHNAME = $highName_))])">
<NONPROCADDRESS INSTANCE="{$nonProcInst_}" BASENAME="{$baseName_}" HIGHNAME="{$highName_}" BASEDECIMAL="{$baseDecimal_}"/>
</xsl:if>
</xsl:for-each>
</xsl:for-each>
</xsl:variable>
<!-- Add unmapped addresses -->
<xsl:variable name="hasUnMappedAddress">
<xsl:for-each select="$G_SYS_MODS/MODULE[(not(@MODCLASS = 'PROCESSOR') and (MEMORYMAP/MEMRANGE[(not(@IS_VALID) or (@IS_VALID = 'TRUE'))]))]">
<xsl:variable name="nonProcInst_" select="@INSTANCE"/>
<xsl:for-each select="MEMORYMAP/MEMRANGE[(not(@IS_VALID) or (@IS_VALID = 'TRUE'))]">
<xsl:variable name="highName_" select="@HIGHNAME"/>
<xsl:variable name="baseName_" select="@BASENAME"/>
<xsl:variable name="baseDecimal_" select="@BASEDECIMAL"/>
<xsl:if test="not($G_SYS_MODS/MODULE[(@MODCLASS = 'PROCESSOR')]/MEMORYMAP/MEMRANGE[((@INSTANCE = $nonProcInst_) and (@BASENAME = $baseName_) and (@HIGHNAME = $highName_))])"><xsl:value-of select="$nonProcInst_"/></xsl:if>
</xsl:for-each>
</xsl:for-each>
</xsl:variable>
<xsl:if test="string-length($hasUnMappedAddress) &gt; 1">
<SET ID="Unmapped Addresses" CLASS="MODULE" ROW_INDEX="{$G_NUM_OF_PROCS_W_ADDRS}">
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="Instance" NAME="INSTANCE" VALUE="Unmapped Addresses"/>
<xsl:for-each select="$G_SYS_MODS/MODULE[(not(@MODCLASS = 'PROCESSOR') and (MEMORYMAP/MEMRANGE[(not(@IS_VALID) or (@IS_VALID = 'TRUE'))]))]/MEMORYMAP/MEMRANGE[(not(@IS_VALID) or (@IS_VALID = 'TRUE'))]">
<xsl:variable name="nonProcMod_" select="../.."/>
<xsl:variable name="nonProcMMap_" select="$nonProcMod_/MEMORYMAP"/>
<xsl:variable name="instance_" select="$nonProcMod_/@INSTANCE"/>
<xsl:variable name="row_index_" select="position()"/>
<xsl:variable name="instName_" select="$nonProcMod_/@INSTANCE"/>
<xsl:variable name="highName_" select="@HIGHNAME"/>
<xsl:variable name="baseName_" select="@BASENAME"/>
<xsl:variable name="baseDecimal_" select="@BASEDECIMAL"/>
<xsl:for-each select="$nonProcMMap_/MEMRANGE[((@BASENAME = $baseName_) and (@HIGHNAME = $highName_))]">
<xsl:if test="not($G_SYS_MODS/MODULE[(@MODCLASS = 'PROCESSOR')]/MEMORYMAP/MEMRANGE[((@INSTANCE = $instName_) and (@BASENAME = $baseName_) and (@HIGHNAME = $highName_))])">
<xsl:variable name="addr_id_"><xsl:value-of select="$baseName_"/>:<xsl:value-of select="$highName_"/></xsl:variable>
<xsl:variable name="set_id_"><xsl:value-of select="$instName_"/>:<xsl:value-of select="$addr_id_"/></xsl:variable>
<xsl:variable name="inst_modtype_" select="$nonProcMod_/@MODTYPE"/>
<xsl:variable name="inst_viewicon_" select="$nonProcMod_/LICENSEINFO/@ICON_NAME"/>
<xsl:variable name="inst_modclass_" select="$nonProcMod_/@MODCLASS"/>
<xsl:variable name="inst_hwversion_" select="$nonProcMod_/@HWVERSION"/>
<SET ID="{$set_id_}" CLASS="ADDRESS">
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="Instance" NAME="INSTANCE" VALUE="{$instance_}"/>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Type" NAME="MODTYPE" VALUE="{$inst_modtype_}" VIEWICON="{$inst_viewicon_}"/>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Version" NAME="HWVERSION" VALUE="{$inst_hwversion_}"/>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="Address Type" NAME="MEMTYPE" VALUE="{@MEMTYPE}"/>
<xsl:variable name="is_locked_">
<xsl:if test="@IS_LOCKED = 'TRUE'">TRUE</xsl:if>
<xsl:if test="not(@IS_LOCKED) or not(@IS_LOCKED = 'TRUE')">FALSE</xsl:if>
</xsl:variable>
<xsl:variable name="baseAddrViewType_">
<xsl:choose>
<xsl:when test="$is_locked_='TRUE'">STATIC</xsl:when>
<xsl:otherwise>TEXTBOX</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:if test="(@SIZEABRV and not(@SIZEABRV = 'U'))">
<xsl:variable name="baseAddr_"><xsl:value-of select="translate(@BASEVALUE,&HEXU2L;)"/></xsl:variable>
<xsl:variable name="highAddr_"><xsl:value-of select="translate(@HIGHVALUE,&HEXU2L;)"/></xsl:variable>
<VARIABLE VIEWTYPE="{$baseAddrViewType_}" VIEWDISP="Base Address" NAME="BASEVALUE" VALUE="{$baseAddr_}"/>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="High Address" NAME="HIGHVALUE" VALUE="{$highAddr_}"/>
<xsl:if test="not(@MEMTYPE) or not(@MEMTYPE = 'BRIDGE')">
<VARIABLE VIEWTYPE="CHECKBOX" VIEWDISP="Lock" NAME="IS_LOCKED" VALUE="{$is_locked_}"/>
</xsl:if>
<xsl:if test="@MEMTYPE and (@MEMTYPE = 'BRIDGE') and not(@BRIDGE_TO)">
<VARIABLE VIEWTYPE="CHECKBOX" VIEWDISP="Lock" NAME="IS_LOCKED" VALUE="{$is_locked_}"/>
</xsl:if>
</xsl:if>
<xsl:if test="(@SIZEABRV and (@SIZEABRV = 'U'))">
<VARIABLE VIEWTYPE="TEXTBOX" VIEWDISP="Base Address" NAME="BASEVALUE" VALUE=""/>
</xsl:if>
<!--
Lock, DCache and ICache removed in 11.1
<xsl:if test="(@IS_CACHEABLE = 'TRUE')">
<xsl:variable name="is_dcached_">
<xsl:if test="(@IS_DCACHED = 'TRUE')">TRUE</xsl:if>
<xsl:if test="(not(@IS_DCACHED) or not(@IS_DCACHED = 'TRUE'))">FALSE</xsl:if>
</xsl:variable>
<xsl:variable name="is_icached_">
<xsl:if test="(@IS_ICACHED = 'TRUE')">TRUE</xsl:if>
<xsl:if test="(not(@IS_ICACHED) or not(@IS_ICACHED = 'TRUE'))">FALSE</xsl:if>
</xsl:variable>
<VARIABLE VIEWTYPE="CHECKBOX" VIEWDISP="DCache" NAME="IS_DCACHED" VALUE="{$is_dcached_}"/>
<VARIABLE VIEWTYPE="CHECKBOX" VIEWDISP="ICache" NAME="IS_ICACHED" VALUE="{$is_icached_}"/>
</xsl:if>
-->
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="Base Name" NAME="BASENAME" VALUE="{@BASENAME}"/>
<xsl:variable name="sizeViewType_">
<xsl:choose>
<xsl:when test="(@SIZEABRV and (@SIZEABRV = 'U'))">DROPDOWN</xsl:when>
<xsl:when test="$is_locked_='TRUE'">STATIC</xsl:when>
<xsl:otherwise>DROPDOWN</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<VARIABLE VIEWTYPE="{$sizeViewType_}" VIEWDISP="Size" NAME="SIZEABRV" VALUE="{@SIZEABRV}"/>
<xsl:variable name="valid_bifNames_">
<xsl:choose>
<xsl:when test="$nonProcMMap_/MEMRANGE[(@BASENAME = $baseName_) and (@HIGHNAME = $highName_)]/SLAVES">
<xsl:for-each select="$nonProcMMap_/MEMRANGE[(@BASENAME = $baseName_) and (@HIGHNAME = $highName_)]/SLAVES/SLAVE">
<xsl:variable name="bifName_" select="@BUSINTERFACE"/>
<!-- <xsl:message>Bif Name <xsl:value-of select="$bifName_"/> </xsl:message> -->
<xsl:variable name="modBifs_" select="$nonProcMod_/BUSINTERFACES"/>
<xsl:if test="$modBifs_/BUSINTERFACE[((@NAME = $bifName_) and not(@IS_VALID = 'FALSE') and not(@BUSNAME = '__NOC__'))]">
<xsl:variable name="busName_" select="$modBifs_/BUSINTERFACE[((@NAME = $bifName_) and not(@IS_VALID = 'FALSE') and not(@BUSNAME = '__NOC__'))]/@BUSNAME"/>
<xsl:if test="position() &gt; 1">:</xsl:if><xsl:value-of select="@BUSINTERFACE"/>
</xsl:if>
</xsl:for-each>
</xsl:when>
<xsl:otherwise>
<xsl:for-each select="$nonProcMMap_/MEMRANGE[(@BASENAME = $baseName_) and (@HIGHNAME = $highName_)]/SLVINTERFACES/BUSINTERFACE">
<xsl:variable name="bifName_" select="@NAME"/>
<xsl:variable name="modBifs_" select="$nonProcMod_"/>
<xsl:if test="$modBifs_/BUSINTERFACE[((@NAME = $bifName_) and not(@IS_VALID = 'FALSE') and not(@BUSNAME = '__NOC__'))]">
<xsl:variable name="busName_" select="$modBifs_/BUSINTERFACE[((@NAME = $bifName_) and not(@IS_VALID = 'FALSE') and not(@BUSNAME = '__NOC__'))]/@BUSNAME"/>
<xsl:if test="position() &gt; 1">:</xsl:if><xsl:value-of select="@NAME"/>
</xsl:if>
</xsl:for-each>
</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:variable name="def_bifNames_">
<xsl:choose>
<xsl:when test="(string-length($valid_bifNames_) &lt; 1) or ((string-length($valid_bifNames_) = 1) and ($valid_bifNames_ = ':'))">Not Connected</xsl:when>
<xsl:when test="starts-with($valid_bifNames_,':')"><xsl:value-of select="substring-after($valid_bifNames_,':')"/></xsl:when>
<xsl:otherwise><xsl:value-of select="$valid_bifNames_"/></xsl:otherwise>
</xsl:choose>
</xsl:variable>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="Bus Interface(s)" NAME="BIFNAMES" VALUE="{$def_bifNames_}"/>
<xsl:choose>
<xsl:when test="$nonProcMMap_/MEMRANGE[(@BASENAME = $baseName_) and (@HIGHNAME = $highName_)]/SLAVES">
<xsl:for-each select="$nonProcMMap_/MEMRANGE[(@BASENAME = $baseName_) and (@HIGHNAME = $highName_)]/SLAVES/SLAVE">
<xsl:variable name="slvBifName_" select="@BUSINTERFACE"/>
<xsl:variable name="modBifs_" select="$nonProcMod_/BUSINTERFACES"/>
<xsl:if test="count($modBifs_/BUSINTERFACE[((@NAME = $slvBifName_) and not(@IS_VALID = 'FALSE') and not(@BUSNAME = '__NOC__'))]) = 1">
<xsl:variable name="slvBusName_" select="$modBifs_/BUSINTERFACE[((@NAME = $slvBifName_) and not(@IS_VALID = 'FALSE') and not(@BUSNAME = '__NOC__'))]/@BUSNAME"/>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="Bus Name" NAME="BUSNAME" VALUE="{$slvBusName_}"/>
</xsl:if>
</xsl:for-each>
</xsl:when>
<xsl:otherwise>
<xsl:for-each select="$nonProcMMap_/MEMRANGE[(@BASENAME = $baseName_) and (@HIGHNAME = $highName_)]/SLVINTERFACES/BUSINTERFACE">
<xsl:variable name="slvBifName_" select="@NAME"/>
<xsl:variable name="modBifs_" select="$nonProcMod_"/>
<xsl:if test="count($modBifs_/BUSINTERFACE[((@NAME = $slvBifName_) and not(@IS_VALID = 'FALSE') and not(@BUSNAME = '__NOC__'))]) = 1">
<xsl:variable name="slvBusName_" select="$modBifs_/BUSINTERFACE[((@NAME = $slvBifName_) and not(@IS_VALID = 'FALSE') and not(@BUSNAME = '__NOC__'))]/@BUSNAME"/>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="Bus Name" NAME="BUSNAME" VALUE="{$slvBusName_}"/>
</xsl:if>
</xsl:for-each>
</xsl:otherwise>
</xsl:choose>
</SET> <!-- End of one non processor memory range row -->
</xsl:if>
</xsl:for-each> <!-- end of non processor memory ranges loop -->
</xsl:for-each> <!-- end of NONPROCADDRESS loop -->
</SET> <!-- End of non processor tree branch -->
</xsl:if> <!-- End of test to see if we have and non processor mapped address -->
</xsl:template>
</xsl:stylesheet>
projnav/xps/__xps/edw2xtl_sav_view_busif.xsl 0 → 100644
View file @ a64d58e7
<?xml version="1.0" standalone="no"?>
<!DOCTYPE stylesheet [
<!ENTITY UPPERCASE "ABCDEFGHIJKLMNOPQRSTUVWXYZ">
<!ENTITY LOWERCASE "abcdefghijklmnopqrstuvwxyz">
<!ENTITY UPPER2LOWER " '&UPPERCASE;' , '&LOWERCASE;' ">
<!ENTITY LOWER2UPPER " '&LOWERCASE;' , '&UPPERCASE;' ">
<!ENTITY ALPHALOWER "ABCDEFxX0123456789">
<!ENTITY HEXUPPER "ABCDEFxX0123456789">
<!ENTITY HEXLOWER "abcdefxX0123456789">
<!ENTITY HEXU2L " '&HEXLOWER;' , '&HEXUPPER;' ">
]>
<xsl:stylesheet version="1.0"
xmlns:xsl="http://www.w3.org/1999/XSL/Transform"
xmlns:exsl="http://exslt.org/common"
xmlns:dyn="http://exslt.org/dynamic"
xmlns:math="http://exslt.org/math"
xmlns:xlink="http://www.w3.org/1999/xlink"
extension-element-prefixes="exsl dyn math xlink">
<!--
================================================================================
Generate XTeller for BIFS
================================================================================
-->
<xsl:template name="WRITE_VIEW_BIF_TREE">
<xsl:for-each select="$G_SYS_MODS/MODULE">
<xsl:variable name="modRef_" select="self::node()"/>
<xsl:variable name="m_inst_" select="$modRef_/@INSTANCE"/>
<xsl:element name="SET">
<xsl:attribute name="ID"><xsl:value-of select="@INSTANCE"/></xsl:attribute>
<xsl:attribute name="CLASS">MODULE</xsl:attribute>
<xsl:choose>
<xsl:when test="$modRef_/@POTENTIAL_INDEX">
<xsl:attribute name="POTENTIAL_INDEX"><xsl:value-of select="$modRef_/@POTENTIAL_INDEX"/></xsl:attribute>
</xsl:when>
<xsl:when test="$modRef_/@CONNECTED_INDEX">
<xsl:attribute name="CONNECTED_INDEX"><xsl:value-of select="$modRef_/@CONNECTED_INDEX"/></xsl:attribute>
</xsl:when>
</xsl:choose>
<!--
CR452579
Can only modify INSTANCE name in Hierarchal view.
-->
<VARIABLE VIEWTYPE="TEXTBOX" VIEWDISP="Name" NAME="INSTANCE" VALUE="{@INSTANCE}"/>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Type" NAME="MODTYPE" VALUE="{@MODTYPE}" VIEWICON="{LICENSEINFO/@ICON_NAME}"/>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Version" NAME="HWVERSION" VALUE="{@HWVERSION}"/>
<xsl:variable name="ipClassification_">
<xsl:call-template name="F_ModClass_To_IpClassification">
<xsl:with-param name="iModClass" select="@MODCLASS"/>
<xsl:with-param name="iBusStd" select="@BUSSTD"/>
</xsl:call-template>
</xsl:variable>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Classification" NAME="IPCLASS" VALUE="{$ipClassification_}"/>
<!-- Write Bus Interfaces here -->
<xsl:for-each select="$G_SYS_MODS"> <!-- To put things in the right scope for the keys below -->
<xsl:variable name="m_bifs_all_" select="key('G_MAP_ALL_BIFS', $m_inst_)"/>
<xsl:for-each select="$m_bifs_all_">
<xsl:sort data-type="number" select="@MPD_INDEX" order="ascending"/>
<xsl:call-template name="WRITE_VIEW_BIF_TREE_SET">
<xsl:with-param name="iModRef" select="$modRef_"/>
<xsl:with-param name="iBifRef" select="self::node()"/>
</xsl:call-template>
</xsl:for-each> <!-- End of bus interface loop -->
</xsl:for-each>
</xsl:element>
</xsl:for-each> <!-- End module loop -->
</xsl:template>
<xsl:template name="WRITE_VIEW_BIF_TREE_SET">
<xsl:param name="iModRef" select="'__NONE__'"/>
<xsl:param name="iBifRef" select="'__NONE__'"/>
<xsl:param name="iBifCol" select="'__NONE__'"/>
<xsl:element name="SET">
<xsl:if test="not($iBifCol = '__NONE__')">
<xsl:attribute name="RGB_FG"><xsl:value-of select="$iBifCol"/></xsl:attribute>
</xsl:if>
<xsl:attribute name="ID"><xsl:value-of select="$iBifRef/@NAME"/></xsl:attribute>
<xsl:attribute name="CLASS">BUSINTERFACE</xsl:attribute>
<xsl:if test="($iBifRef/@TYPE = 'MONITOR')">
<xsl:choose>
<xsl:when test="($iBifRef/@IS_P2P)">
<xsl:attribute name="IS_P2P_MONITOR">TRUE</xsl:attribute>
</xsl:when>
<xsl:otherwise>
<xsl:attribute name="IS_SHARED_MONITOR">TRUE</xsl:attribute>
</xsl:otherwise>
</xsl:choose>
</xsl:if>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="NAME" NAME="NAME" VALUE="{$iBifRef/@NAME}"/>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="Type" NAME="TYPE" VALUE="{$iBifRef/@TYPE}"/>
<xsl:element name="VARIABLE">
<xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
<xsl:attribute name="VIEWDISP">Bus Standard</xsl:attribute>
<xsl:attribute name="NAME">BUSSTD</xsl:attribute>
<xsl:choose>
<xsl:when test="($iBifRef/@BUSSTD_PSF)">
<xsl:attribute name="VALUE"><xsl:value-of select="$iBifRef/@BUSSTD_PSF"/></xsl:attribute>
</xsl:when>
<xsl:when test="($iBifRef/@BUSSTD)">
<xsl:attribute name="VALUE"><xsl:value-of select="$iBifRef/@BUSSTD"/></xsl:attribute>
</xsl:when>
<xsl:when test="($iBifRef/@BUS_STD)">
<xsl:attribute name="VALUE"><xsl:value-of select="$iBifRef/@BUS_STD"/></xsl:attribute>
</xsl:when>
<xsl:otherwise>
<xsl:attribute name="VALUE">USER</xsl:attribute>
</xsl:otherwise>
</xsl:choose>
</xsl:element>
<xsl:choose>
<xsl:when test="($iBifRef/@TYPE = 'INITIATOR')">
<xsl:element name="VARIABLE">
<xsl:attribute name="VIEWTYPE">TEXTBOX</xsl:attribute>
<xsl:attribute name="VIEWDISP">Bus Name</xsl:attribute>
<xsl:attribute name="NAME">BUSNAME</xsl:attribute>
<xsl:choose>
<xsl:when test="(($iBifRef/@BUSNAME = '__NOC__') or ($iBifRef/@BUSNAME = '') or not($iBifRef/@BUSNAME))">
<xsl:variable name="def_noc_name_"><xsl:value-of select="$iModRef/@INSTANCE"/>_<xsl:value-of select="$iBifRef/@NAME"/></xsl:variable>
<xsl:attribute name="VALUE"><xsl:value-of select="$def_noc_name_"/></xsl:attribute>
</xsl:when>
<xsl:otherwise>
<xsl:attribute name="VALUE"><xsl:value-of select="$iBifRef/@BUSNAME"/></xsl:attribute>
</xsl:otherwise>
</xsl:choose>
<xsl:if test="$G_ADD_CHOICES = 'TRUE'">
<xsl:call-template name="WRITE_VIEW_BIF_BUSNAME_CHOICES">
<xsl:with-param name="iModRef" select="$iModRef"/>
<xsl:with-param name="iBifRef" select="$iBifRef"/>
</xsl:call-template>
</xsl:if>
</xsl:element>
</xsl:when>
<xsl:otherwise>
<xsl:choose>
<xsl:when test="(($iBifRef/@BUSNAME = '__NOC__') or ($iBifRef/@BUSNAME = '') or not($iBifRef/@BUSNAME))">
<xsl:element name="VARIABLE">
<xsl:choose>
<xsl:when test="(($iBifRef/@BUSSTD = 'AXI') and ($iBifRef/@TYPE = 'SLAVE') and ($G_HAVE_XB_BUSSES = 'TRUE'))">
<xsl:attribute name="VIEWTYPE">BUTTON</xsl:attribute>
</xsl:when>
<xsl:otherwise>
<xsl:attribute name="VIEWTYPE">DROPDOWN</xsl:attribute>
</xsl:otherwise>
</xsl:choose>
<xsl:attribute name="VIEWDISP">Bus Name</xsl:attribute>
<xsl:attribute name="NAME">BUSNAME</xsl:attribute>
<xsl:attribute name="VALUE">No Connection</xsl:attribute>
<xsl:if test="$G_ADD_CHOICES = 'TRUE'">
<xsl:call-template name="WRITE_VIEW_BIF_BUSNAME_CHOICES">
<xsl:with-param name="iModRef" select="$iModRef"/>
<xsl:with-param name="iBifRef" select="$iBifRef"/>
</xsl:call-template>
</xsl:if>
</xsl:element>
</xsl:when>
<xsl:otherwise>
<xsl:choose>
<xsl:when test="(($iBifRef/@TYPE = 'MONITOR') and ($iBifRef/MONITORS/MONITOR))">
<xsl:variable name="monitorBif_" select="$iBifRef/MONITORS/MONITOR"/>
<xsl:variable name="p2pMonConn_" select="concat($monitorBif_/@INSTANCE,'.',$monitorBif_/@BUSINTERFACE)"/>
<xsl:element name="VARIABLE">
<xsl:attribute name="VIEWTYPE">DROPDOWN</xsl:attribute>
<xsl:attribute name="VIEWDISP">Bus Name</xsl:attribute>
<xsl:attribute name="NAME">BUSNAME</xsl:attribute>
<xsl:attribute name="VALUE"><xsl:value-of select="$p2pMonConn_"/></xsl:attribute>
<xsl:if test="$G_ADD_CHOICES = 'TRUE'">
<xsl:call-template name="WRITE_VIEW_BIF_BUSNAME_CHOICES">
<xsl:with-param name="iModRef" select="$iModRef"/>
<xsl:with-param name="iBifRef" select="$iBifRef"/>
</xsl:call-template>
</xsl:if>
</xsl:element>
</xsl:when>
<xsl:when test="($iBifRef/@TYPE = 'SLAVE')">
<xsl:element name="VARIABLE">
<xsl:choose>
<xsl:when test="(($iBifRef/@BUSSTD = 'AXI') and ($G_HAVE_XB_BUSSES ='TRUE'))">
<xsl:attribute name="VIEWTYPE">BUTTON</xsl:attribute>
</xsl:when>
<xsl:otherwise>
<xsl:attribute name="VIEWTYPE">DROPDOWN</xsl:attribute>
</xsl:otherwise>
</xsl:choose>
<xsl:attribute name="NAME">BUSNAME</xsl:attribute>
<xsl:attribute name="VIEWDISP">Bus Name</xsl:attribute>
<xsl:choose>
<xsl:when test="$iBifRef/MASTERS/MASTER">
<xsl:variable name="mastersList_"><xsl:for-each select="$iBifRef/MASTERS/MASTER"><xsl:if test="position() &gt; 1"> &amp; </xsl:if><xsl:value-of select="concat(@INSTANCE,'.',@BUSINTERFACE)"/></xsl:for-each></xsl:variable>
<xsl:variable name="mastersConn_" select="concat($iBifRef/@BUSNAME,':',$mastersList_)"/>
<xsl:attribute name="VALUE"><xsl:value-of select="$mastersConn_"/></xsl:attribute>
</xsl:when>
<xsl:otherwise>
<xsl:attribute name="VALUE"><xsl:value-of select="$iBifRef/@BUSNAME"/></xsl:attribute>
</xsl:otherwise>
</xsl:choose>
<xsl:if test="$G_ADD_CHOICES = 'TRUE'">
<xsl:call-template name="WRITE_VIEW_BIF_BUSNAME_CHOICES">
<xsl:with-param name="iModRef" select="$iModRef"/>
<xsl:with-param name="iBifRef" select="$iBifRef"/>
</xsl:call-template>
</xsl:if>
</xsl:element>
</xsl:when>
<xsl:otherwise>
<xsl:element name="VARIABLE">
<xsl:attribute name="VIEWTYPE">DROPDOWN</xsl:attribute>
<xsl:attribute name="VIEWDISP">Bus Name</xsl:attribute>
<xsl:attribute name="NAME">BUSNAME</xsl:attribute>
<xsl:attribute name="VALUE"><xsl:value-of select="$iBifRef/@BUSNAME"/></xsl:attribute>
<xsl:if test="$G_ADD_CHOICES = 'TRUE'">
<xsl:call-template name="WRITE_VIEW_BIF_BUSNAME_CHOICES">
<xsl:with-param name="iModRef" select="$iModRef"/>
<xsl:with-param name="iBifRef" select="$iBifRef"/>
</xsl:call-template>
</xsl:if>
</xsl:element>
</xsl:otherwise>
</xsl:choose>
</xsl:otherwise>
</xsl:choose>
</xsl:otherwise>
</xsl:choose>
</xsl:element>
</xsl:template>
<xsl:template name="WRITE_VIEW_BIF_FLAT">
<xsl:for-each select="$G_SYS_MODS/MODULE">
<xsl:sort data-type="number" select="@ROW_INDEX" order="ascending"/>
<xsl:variable name="moduleRef_" select="self::node()"/>
<xsl:variable name="busifsRef_">
<xsl:choose>
<xsl:when test="self::node()/BUSINTERFACES"><xsl:text>$moduleRef_/BUSINTERFACES</xsl:text></xsl:when>
<xsl:otherwise><xsl:text>$moduleRef_</xsl:text></xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:for-each select="dyn:evaluate($busifsRef_)/BUSINTERFACE[(not(@IS_VALID) or (@IS_VALID = 'TRUE'))]">
<xsl:sort data-type="number" select="@MPD_INDEX" order="ascending"/>
<xsl:call-template name="WRITE_VIEW_BIF_FLAT_SET">
<xsl:with-param name="iModRef" select="$moduleRef_"/>
<xsl:with-param name="iBifRef" select="self::node()"/>
</xsl:call-template>
</xsl:for-each> <!-- End of Bus Interface Loop -->
</xsl:for-each> <!-- End of Module loop -->
</xsl:template>
<xsl:template name="WRITE_VIEW_BIF_FLAT_SET">
<xsl:param name="iModRef" select="'__NONE__'"/>
<xsl:param name="iBifRef" select="'__NONE__'"/>
<xsl:param name="iBifCol" select="'__NONE__'"/>
<xsl:element name="SET">
<xsl:if test="not($iBifCol = '__NONE__')">
<xsl:attribute name="RGB_FG"><xsl:value-of select="$iBifCol"/></xsl:attribute>
</xsl:if>
<!--
<xsl:attribute name="ID"><xsl:value-of select="$iModRef/@INSTANCE"/>.<xsl:value-of select="$iBifRef/@NAME"/></xsl:attribute>
-->
<xsl:attribute name="ID"><xsl:value-of select="$iBifRef/@NAME"/></xsl:attribute>
<xsl:attribute name="CLASS">BUSINTERFACE</xsl:attribute>
<xsl:if test="($iBifRef/@TYPE = 'MONITOR')">
<xsl:choose>
<xsl:when test="($iBifRef/@IS_P2P)">
<xsl:attribute name="IS_P2P_MONITOR">TRUE</xsl:attribute>
</xsl:when>
<xsl:otherwise>
<xsl:attribute name="IS_SHARED_MONITOR">TRUE</xsl:attribute>
</xsl:otherwise>
</xsl:choose>
</xsl:if>
<!-- CR452579 Can only modify INSTANCE name in Hierarchal view. -->
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="Instance" NAME="INSTANCE" VALUE="{$iModRef/@INSTANCE}"/>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="Bus Interface" NAME="NAME" VALUE="{$iBifRef/@NAME}"/>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Type" NAME="MODTYPE" VALUE="{$iModRef/@MODTYPE}" VIEWICON="{$iModRef/LICENSEINFO/@ICON_NAME}"/>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Version" NAME="HWVERSION" VALUE="{$iModRef/@HWVERSION}"/>
<xsl:variable name="ipClassification_">
<xsl:call-template name="F_ModClass_To_IpClassification">
<xsl:with-param name="iModClass" select="$iModRef/@MODCLASS"/>
<xsl:with-param name="iBusStd" select="$iBifRef/@BUSSTD"/>
</xsl:call-template>
</xsl:variable>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Classification" NAME="IPCLASS" VALUE="{$ipClassification_}"/>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="Type" NAME="TYPE" VALUE="{$iBifRef/@TYPE}"/>
<xsl:element name="VARIABLE">
<xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
<xsl:attribute name="VIEWDISP">Bus Standard</xsl:attribute>
<xsl:attribute name="NAME">BUSSTD</xsl:attribute>
<xsl:choose>
<xsl:when test="($iBifRef/@BUS_STD)">
<xsl:attribute name="VALUE"><xsl:value-of select="$iBifRef/@BUS_STD"/></xsl:attribute>
</xsl:when>
<xsl:when test="($iBifRef/@BUSSTD)">
<xsl:attribute name="VALUE"><xsl:value-of select="$iBifRef/@BUSSTD"/></xsl:attribute>
</xsl:when>
<xsl:otherwise>
<xsl:attribute name="VALUE">USER</xsl:attribute>
</xsl:otherwise>
</xsl:choose>
</xsl:element>
<xsl:choose>
<xsl:when test="$iBifRef/@TYPE = 'INITIATOR'">
<xsl:element name="VARIABLE">
<xsl:attribute name="VIEWTYPE">TEXTBOX</xsl:attribute>
<xsl:attribute name="VIEWDISP">Bus Name</xsl:attribute>
<xsl:attribute name="NAME">BUSNAME</xsl:attribute>
<xsl:choose>
<xsl:when test="(($iBifRef/@BUSNAME = '__NOC__') or ($iBifRef/@BUSNAME = '') or not($iBifRef/@BUSNAME))">
<xsl:variable name="def_noc_name_"><xsl:value-of select="$iModRef/@INSTANCE"/>_<xsl:value-of select="$iBifRef/@NAME"/></xsl:variable>
<xsl:attribute name="VALUE"><xsl:value-of select="$def_noc_name_"/></xsl:attribute>
</xsl:when>
<xsl:otherwise>
<xsl:attribute name="VALUE"><xsl:value-of select="$iBifRef/@BUSNAME"/></xsl:attribute>
</xsl:otherwise>
</xsl:choose>
<xsl:if test="$G_ADD_CHOICES = 'TRUE'">
<xsl:call-template name="WRITE_VIEW_BIF_BUSNAME_CHOICES">
<xsl:with-param name="iModRef" select="$iModRef"/>
<xsl:with-param name="iBifRef" select="$iBifRef"/>
</xsl:call-template>
</xsl:if>
</xsl:element>
</xsl:when>
<xsl:otherwise>
<xsl:choose>
<xsl:when test="(($iBifRef/@BUSNAME = '__NOC__') or ($iBifRef/@BUSNAME = '') or not($iBifRef/@BUSNAME))">
<xsl:element name="VARIABLE">
<xsl:choose>
<xsl:when test="(($iBifRef/@BUSSTD = 'AXI') and ($iBifRef/@TYPE = 'SLAVE') and ($G_HAVE_XB_BUSSES = 'TRUE'))">
<xsl:attribute name="VIEWTYPE">BUTTON</xsl:attribute>
</xsl:when>
<xsl:otherwise>
<xsl:attribute name="VIEWTYPE">DROPDOWN</xsl:attribute>
</xsl:otherwise>
</xsl:choose>
<xsl:attribute name="VIEWDISP">Bus Name</xsl:attribute>
<xsl:attribute name="NAME">BUSNAME</xsl:attribute>
<xsl:attribute name="VALUE">No Connection</xsl:attribute>
<xsl:if test="$G_ADD_CHOICES = 'TRUE'">
<xsl:call-template name="WRITE_VIEW_BIF_BUSNAME_CHOICES">
<xsl:with-param name="iModRef" select="$iModRef"/>
<xsl:with-param name="iBifRef" select="$iBifRef"/>
</xsl:call-template>
</xsl:if>
</xsl:element>
</xsl:when>
<xsl:otherwise>
<xsl:choose>
<xsl:when test="(($iBifRef/@TYPE = 'MONITOR') and ($iBifRef/MONITORS/MONITOR))">
<xsl:variable name="monitorBif_" select="$iBifRef/MONITORS/MONITOR"/>
<xsl:variable name="p2pMonConn_" select="concat($monitorBif_/@INSTANCE,'.',$monitorBif_/@BUSINTERFACE)"/>
<!--
<VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Bus Name" NAME="BUSNAME" VALUE="{$p2pMonConn_}"/>
-->
<xsl:element name="VARIABLE">
<xsl:attribute name="VIEWTYPE">DROPDOWN</xsl:attribute>
<xsl:attribute name="VIEWDISP">Bus Name</xsl:attribute>
<xsl:attribute name="NAME">BUSNAME</xsl:attribute>
<xsl:attribute name="VALUE"><xsl:value-of select="$p2pMonConn_"/></xsl:attribute>
<xsl:if test="$G_ADD_CHOICES = 'TRUE'">
<xsl:call-template name="WRITE_VIEW_BIF_BUSNAME_CHOICES">
<xsl:with-param name="iModRef" select="$iModRef"/>
<xsl:with-param name="iBifRef" select="$iBifRef"/>
</xsl:call-template>
</xsl:if>
</xsl:element>
</xsl:when>
<xsl:when test="($iBifRef/@TYPE = 'SLAVE')">
<xsl:element name="VARIABLE">
<xsl:choose>
<xsl:when test="$iBifRef/@BUSSTD = 'AXI' and $G_HAVE_XB_BUSSES ='TRUE'">
<xsl:attribute name="VIEWTYPE">BUTTON</xsl:attribute>
</xsl:when>
<xsl:otherwise>
<xsl:attribute name="VIEWTYPE">DROPDOWN</xsl:attribute>
</xsl:otherwise>
</xsl:choose>
<xsl:attribute name="NAME">BUSNAME</xsl:attribute>
<xsl:attribute name="VIEWDISP">Bus Name</xsl:attribute>
<xsl:choose>
<xsl:when test="$iBifRef/MASTERS/MASTER">
<xsl:variable name="mastersList_"><xsl:for-each select="$iBifRef/MASTERS/MASTER"><xsl:if test="position() &gt; 1"> &amp; </xsl:if><xsl:value-of select="concat(@INSTANCE,'.',@BUSINTERFACE)"/></xsl:for-each></xsl:variable>
<xsl:variable name="mastersConn_" select="concat($iBifRef/@BUSNAME,':',$mastersList_)"/>
<xsl:attribute name="VALUE"><xsl:value-of select="$mastersConn_"/></xsl:attribute>
</xsl:when>
<xsl:otherwise>
<xsl:attribute name="VALUE"><xsl:value-of select="$iBifRef/@BUSNAME"/></xsl:attribute>
</xsl:otherwise>
</xsl:choose>
<xsl:if test="$G_ADD_CHOICES = 'TRUE'">
<xsl:call-template name="WRITE_VIEW_BIF_BUSNAME_CHOICES">
<xsl:with-param name="iModRef" select="$iModRef"/>
<xsl:with-param name="iBifRef" select="$iBifRef"/>
</xsl:call-template>
</xsl:if>
</xsl:element>
</xsl:when>
<xsl:otherwise>
<!--
<VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Bus Name" NAME="BUSNAME" VALUE="{$iBifRef/@BUSNAME}"/>
-->
<xsl:element name="VARIABLE">
<xsl:attribute name="VIEWTYPE">DROPDOWN</xsl:attribute>
<xsl:attribute name="VIEWDISP">Bus Name</xsl:attribute>
<xsl:attribute name="NAME">BUSNAME</xsl:attribute>
<xsl:attribute name="VALUE"><xsl:value-of select="$iBifRef/@BUSNAME"/></xsl:attribute>
<xsl:if test="$G_ADD_CHOICES = 'TRUE'">
<xsl:call-template name="WRITE_VIEW_BIF_BUSNAME_CHOICES">
<xsl:with-param name="iModRef" select="$iModRef"/>
<xsl:with-param name="iBifRef" select="$iBifRef"/>
</xsl:call-template>
</xsl:if>
</xsl:element>
</xsl:otherwise>
</xsl:choose>
</xsl:otherwise>
</xsl:choose>
</xsl:otherwise>
</xsl:choose>
</xsl:element>
</xsl:template>
<xsl:template name="WRITE_VIEW_BIF_BUSNAME_CHOICES">
<xsl:param name="iModRef" select="None"/>
<xsl:param name="iBifRef" select="None"/>
<xsl:variable name="b_bus_" select="$iBifRef/@BUSNAME"/>
<xsl:variable name="b_name_" select="$iBifRef/@NAME"/>
<xsl:variable name="b_type_" select="$iBifRef/@TYPE"/>
<xsl:variable name="b_bstd_" select="$iBifRef/@BUSSTD"/>
<xsl:variable name="b_bstd_psf_" select="$iBifRef/@BUSSTD_PSF"/>
<xsl:variable name="b_protocol_" select="$iBifRef/@PROTOCOL"/>
<xsl:element name="CHOICES">
<xsl:choose>
<xsl:when test="($b_type_ = 'INITIATOR')">
<xsl:variable name="initiator_busName_">
<xsl:choose>
<xsl:when test="($b_bus_ = '__NOC__')"><xsl:value-of select="concat($iModRef/@INSTANCE,'_',$b_name_)"/></xsl:when>
<xsl:otherwise><xsl:value-of select="$b_bus_"/></xsl:otherwise>
</xsl:choose>
</xsl:variable>
<CHOICE NAME="{$initiator_busName_}"/>
</xsl:when>
<xsl:when test="(($b_type_ = 'MASTER') or ($b_type_ = 'SLAVE') or ($b_type_ = 'MASTER_SLAVE'))">
<CHOICE NAME="No Connection"/>
<xsl:for-each select="$G_SYS_MODS"> <!-- To set correct scope for KEY functions below -->
<xsl:if test="not(($b_bstd_ = 'AXI') and ($b_type_ = 'SLAVE'))">
<CHOICE NAME="New Connection"/>
</xsl:if>
<xsl:for-each select="key('G_MAP_BUSSES',$b_bstd_)">
<xsl:variable name="busName_" select="@INSTANCE"/>
<xsl:choose>
<!-- CR#590473 This was setting wrong choices filled up-->
<!--xsl:when test="(($b_type_ = 'SLAVE') and (@IS_CROSSBAR) and $iBifRef/@PROTOCOL)">
<xsl:for-each select="key('G_MAP_MST_BIFS',$busName_)[(not(@PROTOCOL) or (@PROTOCOL = $b_protocol_) or (@PROTOCOL = 'GENERIC'))]">
<xsl:variable name="bifName_" select="@NAME"/>
<xsl:variable name="insName_" select="../../@INSTANCE"/>
<xsl:variable name="xb_slave_busName_" select="concat($busName_,':',$insName_,'.',$bifName_)"/>
<CHOICE NAME="{$xb_slave_busName_}"/>
</xsl:for-each>
</xsl:when-->
<xsl:when test="($b_type_ = 'SLAVE') and (@IS_CROSSBAR)">
<xsl:for-each select="key('G_MAP_MST_BIFS',$busName_)">
<xsl:variable name="bifName_" select="@NAME"/>
<xsl:variable name="insName_" select="../../@INSTANCE"/>
<xsl:variable name="xb_slave_busName_" select="concat($busName_,':',$insName_,'.',$bifName_)"/>
<CHOICE NAME="{$xb_slave_busName_}"/>
</xsl:for-each>
</xsl:when>
<xsl:otherwise>
<CHOICE NAME="{$busName_}"/>
</xsl:otherwise>
</xsl:choose>
</xsl:for-each>
</xsl:for-each>
</xsl:when>
<xsl:when test="($b_type_ = 'TARGET')">
<CHOICE NAME="No Connection"/>
<xsl:for-each select="$G_SYS_MODS"> <!-- To set correct scope for KEY functions below -->
<xsl:variable name="use_bstd_">
<xsl:choose>
<xsl:when test="(($b_bstd_ = 'AXIS') or ($b_bstd_ = 'XIL'))">
<xsl:value-of select="$b_bstd_psf_"/>
</xsl:when>
<xsl:otherwise>
<xsl:value-of select="$b_bstd_"/>
</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:choose>
<xsl:when test="$iBifRef/@PROTOCOL">
<xsl:for-each select="key('G_MAP_P2P_BIFS',$use_bstd_)[(@TYPE = 'INITIATOR') and (not(@PROTOCOL) or (@PROTOCOL = $b_protocol_) or (@PROTOCOL = 'GENERIC'))]">
<xsl:variable name="busName_" select="@BUSNAME"/>
<xsl:choose>
<xsl:when test="($busName_ = '__NOC__')">
<xsl:variable name="bifName_" select="@NAME"/>
<xsl:variable name="insName_" select="../../@INSTANCE"/>
<xsl:variable name="initiator_busName_" select="concat($insName_,'_',$bifName_)"/>
<CHOICE NAME="{$initiator_busName_}"/>
</xsl:when>
<xsl:otherwise>
<CHOICE NAME="{$busName_}"/>
</xsl:otherwise>
</xsl:choose>
</xsl:for-each>
</xsl:when>
<xsl:otherwise>
<xsl:for-each select="key('G_MAP_P2P_BIFS',$use_bstd_)[(@TYPE = 'INITIATOR')]">
<xsl:variable name="busName_" select="@BUSNAME"/>
<xsl:choose>
<xsl:when test="($busName_ = '__NOC__')">
<xsl:variable name="bifName_" select="@NAME"/>
<xsl:variable name="insName_" select="../../@INSTANCE"/>
<xsl:variable name="initiator_busName_" select="concat($insName_,'_',$bifName_)"/>
<CHOICE NAME="{$initiator_busName_}"/>
</xsl:when>
<xsl:otherwise>
<CHOICE NAME="{$busName_}"/>
</xsl:otherwise>
</xsl:choose>
</xsl:for-each>
</xsl:otherwise>
</xsl:choose>
</xsl:for-each>
</xsl:when>
<xsl:when test="($b_type_ = 'MONITOR')">
<CHOICE NAME="No Connection"/>
<xsl:for-each select="$G_SYS_MODS"> <!-- To set correct scope for KEY functions below -->
<xsl:choose>
<xsl:when test="($iBifRef/@IS_P2P = 'TRUE')">
<xsl:for-each select="$G_SYS_MODS"> <!-- To set correct scope for KEY functions below -->
<xsl:variable name="use_bstd_">
<xsl:choose>
<xsl:when test="(($b_bstd_ = 'AXIS') or ($b_bstd_ = 'XIL'))">
<xsl:value-of select="$b_bstd_psf_"/>
</xsl:when>
<xsl:otherwise>
<xsl:value-of select="$b_bstd_"/>
</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<!-- <xsl:message>monitor p2p <xsl:value-of select="count(key('G_MAP_P2P_BIFS',$use_bstd_)[(@TYPE = 'INITIATOR')])"/> </xsl:message> -->
<xsl:for-each select="key('G_MAP_P2P_BIFS',$use_bstd_)[(@TYPE = 'INITIATOR')]">
<xsl:variable name="busName_" select="@BUSNAME"/>
<xsl:choose>
<xsl:when test="($busName_ = '__NOC__')">
<xsl:variable name="bifName_" select="@NAME"/>
<xsl:variable name="insName_" select="../../@INSTANCE"/>
<xsl:variable name="initiator_busName_" select="concat($insName_,'_',$bifName_)"/>
<CHOICE NAME="{$initiator_busName_}"/>
</xsl:when>
<xsl:otherwise>
<CHOICE NAME="{$busName_}"/>
</xsl:otherwise>
</xsl:choose>
</xsl:for-each>
</xsl:for-each>
</xsl:when>
<xsl:otherwise>
<xsl:for-each select="key('G_MAP_BUSSES',$b_bstd_)">
<xsl:variable name="busName_" select="@INSTANCE"/>
<xsl:choose>
<xsl:when test="(@IS_CROSSBAR or ($b_bstd_ = 'AXI'))">
<xsl:for-each select="key('G_MAP_MOS_BIFS',$busName_)">
<xsl:variable name="bifName_" select="@NAME"/>
<xsl:variable name="insName_" select="../../@INSTANCE"/>
<!--
<xsl:variable name="xb_moni_busName_" select="concat($busName_,':',$insName_,'.',$bifName_)"/>
-->
<xsl:variable name="xb_moni_busName_" select="concat($insName_,'.',$bifName_)"/>
<CHOICE NAME="{$xb_moni_busName_}"/>
</xsl:for-each>
</xsl:when>
<xsl:otherwise>
<CHOICE NAME="{$busName_}"/>
</xsl:otherwise>
</xsl:choose>
</xsl:for-each>
</xsl:otherwise>
</xsl:choose>
</xsl:for-each>
</xsl:when>
</xsl:choose>
</xsl:element>
</xsl:template>
</xsl:stylesheet>
projnav/xps/__xps/edw2xtl_sav_view_groups.xsl 0 → 100644
View file @ a64d58e7
<!DOCTYPE stylesheet [
<!ENTITY ALPUPRS "ABCDEFGHIJKLMNOPQRSTUVWXYZ">
<!ENTITY ALPLWRS "abcdefghijklmnopqrstuvwxyz">
<!ENTITY UPR2LWS " '&ALPUPRS;' , '&ALPLWRS;' ">
<!ENTITY HEXUPPER "ABCDEFxx0123456789">
<!ENTITY HEXLOWER "abcdefxX0123456789">
<!ENTITY HEXU2L " '&HEXLOWER;' , '&HEXUPPER;' ">
<!ENTITY DIV2SLSH " 'div' , '&#047;' ">
<!ENTITY NOT_ELM_CONN "not(name() = 'PARAMETER') and not(name() = 'PORT') and not(name() = 'BUSINTERFACE')">
<!ENTITY NOT_BEF_CONN "not(name() = 'DOCUMENT') and not(name() = 'DOCUMENTATION') and not(name() = 'DESCRIPTION') and not(name() = 'LICENSEINFO')">
<!ENTITY NOT_AFT_CONN "not(name() = 'MEMORYMP') and not(name() = 'PERIPHERALS') and not(name() = 'INTERRUPTINFO')">
]>
<!-- ==============================================================
This XSL file converts BLOCK xml to SAV XTeller
============================================================== -->
<xsl:stylesheet
version="1.0"
xmlns:xsl="http://www.w3.org/1999/XSL/Transform"
xmlns:exsl="http://exslt.org/common"
xmlns:dyn="http://exslt.org/dynamic"
xmlns:math="http://exslt.org/math"
xmlns:xlink="http://www.w3.org/1999/xlink"
extension-element-prefixes="math exsl dyn xlink">
<xsl:output method="xml"
version="1.0"
indent="yes"
encoding="UTF-8"/>
<!--
===================================================
THE MAIN TEMPLATE FOR PORT VIEW SELECTED FOCUS
===================================================
-->
<xsl:template name="WRITE_VIEW_PORT_FOCUSED">
<xsl:choose>
<xsl:when test="$G_ROOT/SAV/@MODE = 'TREE'">
<xsl:call-template name="WRITE_VIEW_EXTP_TREE_SET"/>
</xsl:when>
<xsl:when test="$G_ROOT/SAV/@MODE = 'FLAT'">
<xsl:call-template name="WRITE_VIEW_EXTP_FLAT_SET"/>
</xsl:when>
</xsl:choose>
<xsl:apply-templates select="$G_SYS_MODS/MODULE" mode="_port_view_focusing_on_selected"/>
</xsl:template>
<!--
====================================================
THE MAIN TEMPLATE FOR BIF VIEW BUS FOCUS
====================================================
-->
<xsl:template name="WRITE_VIEW_BIF_FOCUS_ON_BUSES">
<xsl:if test="$G_DEBUG = 'TRUE'"><xsl:message>Focusing on busses</xsl:message></xsl:if>
<!--
<xsl:call-template name="WRITE_VIEW_BIF_FOCUSED_CONNECTED_MODULES">
<xsl:with-param name="iModules" select="$G_GROUPS"/>
</xsl:call-template>
-->
<xsl:apply-templates select="$G_SYS_MODS/MODULE" mode="_bif_view_focusing_on_buses"/>
<xsl:if test="$G_ROOT/SAV/@MODE = 'TREE'"> <!-- The separator -->
<xsl:element name="SET">
<xsl:attribute name="ID">MODULES WITH POTENTIAL CONNECTIONS TO FOCUSED BUS</xsl:attribute>
<xsl:attribute name="CLASS">SEPARATOR</xsl:attribute>
<xsl:element name="VARIABLE">
<xsl:attribute name="VIEWDISP">Name</xsl:attribute>
<xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
<xsl:attribute name="NAME">Name</xsl:attribute>
<xsl:attribute name="VALUE">POTENTIAL MODULES BELOW HERE</xsl:attribute>
</xsl:element>
<xsl:element name="VARIABLE">
<xsl:attribute name="VIEWDISP">IP Type</xsl:attribute>
<xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
<xsl:attribute name="NAME">MODTYPE</xsl:attribute>
<xsl:attribute name="VALUE"></xsl:attribute>
</xsl:element>
<xsl:element name="VARIABLE">
<xsl:attribute name="VIEWDISP">IP Version</xsl:attribute>
<xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
<xsl:attribute name="NAME">HWVERSION</xsl:attribute>
<xsl:attribute name="VALUE"></xsl:attribute>
</xsl:element>
<xsl:element name="VARIABLE">
<xsl:attribute name="VIEWDISP">IP Classification</xsl:attribute>
<xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
<xsl:attribute name="NAME">IPCLASS</xsl:attribute>
<xsl:attribute name="VALUE"></xsl:attribute>
</xsl:element>
<xsl:element name="VARIABLE">
<xsl:attribute name="VIEWDISP">Bus Name</xsl:attribute>
<xsl:attribute name="VIEWTYPE"></xsl:attribute>
<xsl:attribute name="NAME">BUSNAME</xsl:attribute>
<xsl:attribute name="VALUE"></xsl:attribute>
</xsl:element>
<xsl:element name="VARIABLE">
<xsl:attribute name="VIEWDISP">Type</xsl:attribute>
<xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
<xsl:attribute name="NAME">TYPE</xsl:attribute>
<xsl:attribute name="VALUE"></xsl:attribute>
</xsl:element>
<xsl:element name="VARIABLE">
<xsl:attribute name="VIEWDISP">Bus Standard</xsl:attribute>
<xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
<xsl:attribute name="NAME">BUSSTD</xsl:attribute>
<xsl:attribute name="VALUE"></xsl:attribute>
</xsl:element>
</xsl:element>
</xsl:if>
</xsl:template>
<!--
====================================================
THE MAIN TEMPLATE FOR BIF VIEW PROCESSOR FOCUS
====================================================
-->
<xsl:template name="WRITE_VIEW_BIF_FOCUS_ON_PROCS">
<xsl:call-template name="WRITE_VIEW_BIF_FOCUSED_CONNECTED_MODULES">
<xsl:with-param name="iModules" select="$G_GROUPS"/>
</xsl:call-template>
<xsl:if test="$G_ROOT/SAV/@MODE = 'TREE'"> <!-- The separator -->
<xsl:element name="SET">
<xsl:attribute name="ID">MODULES WITH POTENTIAL CONNECTIONS TO THIS SUBSYSTEM</xsl:attribute>
<xsl:attribute name="CLASS">SEPARATOR</xsl:attribute>
<xsl:element name="VARIABLE">
<xsl:attribute name="VIEWDISP">Name</xsl:attribute>
<xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
<xsl:attribute name="NAME">Name</xsl:attribute>
<xsl:attribute name="VALUE">POTENTIAL MODULES BELOW HERE</xsl:attribute>
</xsl:element>
<xsl:element name="VARIABLE">
<xsl:attribute name="VIEWDISP">IP Type</xsl:attribute>
<xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
<xsl:attribute name="NAME">MODTYPE</xsl:attribute>
<xsl:attribute name="VALUE"></xsl:attribute>
</xsl:element>
<xsl:element name="VARIABLE">
<xsl:attribute name="VIEWDISP">IP Version</xsl:attribute>
<xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
<xsl:attribute name="NAME">HWVERSION</xsl:attribute>
<xsl:attribute name="VALUE"></xsl:attribute>
</xsl:element>
<xsl:element name="VARIABLE">
<xsl:attribute name="VIEWDISP">IP Classification</xsl:attribute>
<xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
<xsl:attribute name="NAME">IPCLASS</xsl:attribute>
<xsl:attribute name="VALUE"></xsl:attribute>
</xsl:element>
<xsl:element name="VARIABLE">
<xsl:attribute name="VIEWDISP">Bus Name</xsl:attribute>
<xsl:attribute name="VIEWTYPE"></xsl:attribute>
<xsl:attribute name="NAME">BUSNAME</xsl:attribute>
<xsl:attribute name="VALUE"></xsl:attribute>
</xsl:element>
<xsl:element name="VARIABLE">
<xsl:attribute name="VIEWDISP">Type</xsl:attribute>
<xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
<xsl:attribute name="NAME">TYPE</xsl:attribute>
<xsl:attribute name="VALUE"></xsl:attribute>
</xsl:element>
<xsl:element name="VARIABLE">
<xsl:attribute name="VIEWDISP">Bus Standard</xsl:attribute>
<xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
<xsl:attribute name="NAME">BUSSTD</xsl:attribute>
<xsl:attribute name="VALUE"></xsl:attribute>
</xsl:element>
</xsl:element>
</xsl:if>
</xsl:template>
<!--
===============================================
COPY TRANSFORMS FOR FOCUSING IN BIF VIEW
===============================================
-->
<!-- Root copy template for connected -->
<xsl:template match="node() | @*" mode="_bif_view_focusing_on_connected">
<xsl:copy>
<xsl:apply-templates select="@* | node()" mode="_bif_view_focusing_on_connected"/>
</xsl:copy>
</xsl:template>
<!-- Root copy template for potentials -->
<xsl:template match="node() | @*" mode="_bif_view_focusing_on_potentials">
<xsl:copy>
<xsl:apply-templates select="@* | node()" mode="_bif_view_focusing_on_potentials"/>
</xsl:copy>
</xsl:template>
<xsl:template name="WRITE_VIEW_BIF_FOCUSED_CONNECTED_MODULES"> <!-- Recursive !! -->
<xsl:param name="iModules"/>
<xsl:for-each select="$iModules/BLOCK[@ID and not(BLOCK) and not(@C)]">
<xsl:variable name="m_id_" select="@ID"/>
<xsl:if test="(count(exsl:node-set($G_FOCUSED_SCOPE)/BUS[@NAME = $m_id_]) &gt; 0)">
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message>PLACING BUS <xsl:value-of select="@ID"/></xsl:message></xsl:if>
<xsl:variable name="m_module_" select="$G_SYS_MODS/MODULE[@INSTANCE = $m_id_]"/>
<xsl:apply-templates select="$m_module_" mode="_bif_view_focusing_on_connected"/>
</xsl:if>
</xsl:for-each>
<xsl:for-each select="$iModules/BLOCK[@ID and BLOCK]">
<xsl:choose>
<!-- An actual module that needs to be written -->
<xsl:when test="not(starts-with(@ID,'__')) and BLOCK[@C] and (not(BLOCK/BLOCK) or BLOCK/BLOCK[@CP])">
<xsl:variable name="m_id_" select="@ID"/>
<xsl:variable name="m_module_" select="$G_SYS_MODS/MODULE[@INSTANCE = $m_id_]"/>
<xsl:apply-templates select="$m_module_" mode="_bif_view_focusing_on_connected"/>
</xsl:when>
<xsl:when test="starts-with(@ID,'__GROUP_PROCESSOR__.') or starts-with(@ID,'__GROUP_MASTER__.')">
<!--
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message>MASTER GROUP <xsl:value-of select="@ID"/></xsl:message></xsl:if>
-->
<xsl:variable name="master_id_">
<xsl:choose>
<xsl:when test="starts-with(@ID,'__GROUP_MASTER__.')"><xsl:value-of select="substring-after(@ID,'__GROUP_MASTER__.')"/> </xsl:when>
<xsl:when test="starts-with(@ID,'__GROUP_PROCESSOR__.')"><xsl:value-of select="substring-after(@ID,'__GROUP_PROCESSOR__.')"/> </xsl:when>
</xsl:choose>
</xsl:variable>
<xsl:variable name="num_focused_on_" select="count($G_ROOT/SAV/MASTER[(@INSTANCE = $master_id_)])"/>
<xsl:choose>
<xsl:when test="$num_focused_on_ &gt; 0">
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message>CONNECTED MASTER GROUP <xsl:value-of select="$master_id_"/></xsl:message></xsl:if>
<xsl:call-template name="WRITE_VIEW_BIF_FOCUSED_CONNECTED_MODULES">
<xsl:with-param name="iModules" select="self::node()"/>
</xsl:call-template>
</xsl:when>
<xsl:otherwise>
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message>POTENTIAL MASTER GROUP <xsl:value-of select="$master_id_"/></xsl:message></xsl:if>
<xsl:call-template name="WRITE_VIEW_BIF_FOCUSED_POTENTIAL_MODULES">
<xsl:with-param name="iModules" select="self::node()"/>
</xsl:call-template>
</xsl:otherwise>
</xsl:choose>
</xsl:when>
<xsl:when test="starts-with(@ID,'__GROUP_SHARED__')">
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message>SHARED GROUP <xsl:value-of select="@ID"/></xsl:message></xsl:if>
<xsl:variable name="p_id_" select="substring-after(@ID,'__GROUP_SHARED__')"/>
<xsl:variable name="num_focused_on_" select="count($G_ROOT/SAV/MASTER[contains($p_id_,@INSTANCE)])"/>
<xsl:choose>
<xsl:when test="$num_focused_on_ &gt; 0">
<xsl:call-template name="WRITE_VIEW_BIF_FOCUSED_CONNECTED_MODULES">
<xsl:with-param name="iModules" select="self::node()"/>
</xsl:call-template>
</xsl:when>
<xsl:otherwise>
<xsl:call-template name="WRITE_VIEW_BIF_FOCUSED_POTENTIAL_MODULES">
<xsl:with-param name="iModules" select="self::node()"/>
</xsl:call-template>
</xsl:otherwise>
</xsl:choose>
</xsl:when>
<xsl:when test="starts-with(@ID,'__GROUP_MEMORY__')">
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message> MEMORY GROUP <xsl:value-of select="@ID"/></xsl:message></xsl:if>
<xsl:variable name="m_id_" select="substring-after(@ID,'__GROUP_MEMORY__')"/>
<xsl:call-template name="WRITE_VIEW_BIF_FOCUSED_CONNECTED_MODULES">
<xsl:with-param name="iModules" select="self::node()"/>
</xsl:call-template>
</xsl:when>
<xsl:when test="starts-with(@ID,'__GROUP_PERIPHERAL__')">
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message>PERIPHERAL GROUP <xsl:value-of select="@ID"/></xsl:message></xsl:if>
<xsl:call-template name="WRITE_VIEW_BIF_FOCUSED_CONNECTED_MODULES">
<xsl:with-param name="iModules" select="self::node()"/>
</xsl:call-template>
</xsl:when>
<xsl:when test="starts-with(@ID,'__GROUP_SLAVES__')">
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message>SLAVE GROUP <xsl:value-of select="@ID"/></xsl:message></xsl:if>
<xsl:call-template name="WRITE_VIEW_BIF_FOCUSED_CONNECTED_MODULES">
<xsl:with-param name="iModules" select="self::node()"/>
</xsl:call-template>
</xsl:when>
<xsl:when test="(starts-with(@ID,'__GROUP_IP__') and not($G_ROOT/SAV/@VIEW = 'BUSINTERFACE'))">
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message>IP GROUP<xsl:value-of select="@ID"/></xsl:message></xsl:if>
<xsl:call-template name="WRITE_VIEW_BIF_FOCUSED_CONNECTED_MODULES">
<xsl:with-param name="iModules" select="self::node()"/>
</xsl:call-template>
</xsl:when>
<xsl:when test="starts-with(@ID,'__GROUP_FLOATING__')">
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message>FLOATING GROUP <xsl:value-of select="@ID"/></xsl:message></xsl:if>
<xsl:call-template name="WRITE_VIEW_BIF_FOCUSED_POTENTIAL_MODULES">
<xsl:with-param name="iModules" select="self::node()"/>
</xsl:call-template>
</xsl:when>
<xsl:otherwise>
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message> IGNORING <xsl:value-of select="@ID"/></xsl:message></xsl:if>
</xsl:otherwise>
</xsl:choose>
</xsl:for-each>
</xsl:template>
<!--
===============================================
TRANSFORMS FOR FOCUSED POTENTIAL MODULES
===============================================
-->
<xsl:template name="WRITE_VIEW_BIF_FOCUSED_POTENTIAL_MODULES"> <!-- Recursive !! -->
<xsl:param name="iModules"/>
<!-- BUS -->
<xsl:for-each select="$iModules/BLOCK[@ID and not(BLOCK) and not(@C)]">
<xsl:variable name="m_id_" select="@ID"/>
<xsl:if test="(count(exsl:node-set($G_FOCUSED_SCOPE)/BUS[@NAME = $m_id_]) &gt; 0)">
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message>PLACING BUS <xsl:value-of select="@ID"/></xsl:message></xsl:if>
<xsl:variable name="m_module_" select="$G_SYS_MODS/MODULE[@INSTANCE = $m_id_]"/>
<xsl:apply-templates select="$m_module_" mode="_bif_view_focusing_on_connected"/>
</xsl:if>
</xsl:for-each>
<!-- GROUP -->
<xsl:for-each select="$iModules/BLOCK[@ID and BLOCK]">
<xsl:choose>
<xsl:when test="not(starts-with(@ID,'__')) and BLOCK[@C] and (not(BLOCK/BLOCK) or BLOCK/BLOCK[@CP])">
<xsl:variable name="m_id_" select="@ID"/>
<xsl:variable name="m_module_" select="$G_SYS_MODS/MODULE[@INSTANCE = $m_id_]"/>
<xsl:variable name="m_class_" select="$m_module_/@MODCLASS"/>
<xsl:choose>
<xsl:when test ="not($m_class_ = 'PROCESSOR')">
<xsl:variable name="potential_bifs_">
<xsl:for-each select="$m_module_/BUSINTERFACES/BUSINTERFACE[(not(@IS_VALID) or (@IS_VALID = 'TRUE'))]">
<xsl:variable name="b_std_" select="@BUSSTD"/>
<xsl:variable name="b_bus_" select="@BUSNAME"/>
<xsl:if test="count(exsl:node-set($G_FOCUSED_SCOPE)/BUS[@NAME = $b_bus_]) &gt; 0"><CONNECTED/></xsl:if>
<xsl:if test="count(exsl:node-set($G_FOCUSED_SCOPE)/BUS[@BUSSTD = $b_std_]) &gt; 0"><POTENTIAL/></xsl:if>
</xsl:for-each>
</xsl:variable>
<xsl:variable name="num_potential_" select="count(exsl:node-set($potential_bifs_)/POTENTIAL)"/>
<xsl:variable name="num_connected_" select="count(exsl:node-set($potential_bifs_)/CONNECTED)"/>
<xsl:if test=" ($num_potential_ &gt; 0)">
<xsl:apply-templates select="$m_module_" mode="_bif_view_focusing_on_potentials"/>
</xsl:if>
</xsl:when>
<xsl:when test="count(exsl:node-set($G_FOCUSED_SCOPE)/PERIPHERAL[(@NAME = $m_id_)]) &gt; 0">
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message> PERI PROCESSOR <xsl:value-of select="$m_id_"/></xsl:message></xsl:if>
<xsl:apply-templates select="$m_module_" mode="_bif_view_focusing_on_potentials"/>
</xsl:when>
</xsl:choose>
</xsl:when>
<xsl:when test="starts-with(@ID,'__GROUP_MEMORY__')">
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message>PLACING MEMORY <xsl:value-of select="@ID"/></xsl:message></xsl:if>
<xsl:variable name="m_id_" select="substring-after(@ID,'__GROUP_MEMORY__')"/>
<xsl:call-template name="WRITE_VIEW_BIF_FOCUSED_POTENTIAL_MODULES">
<xsl:with-param name="iModules" select="self::node()"/>
</xsl:call-template>
</xsl:when>
<xsl:when test="starts-with(@ID,'__GROUP_PERIPHERAL__')">
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message>PLACING POTENTIAL GROUP OF PERIPHERALS <xsl:value-of select="@ID"/></xsl:message></xsl:if>
<xsl:call-template name="WRITE_VIEW_BIF_FOCUSED_POTENTIAL_MODULES">
<xsl:with-param name="iModules" select="self::node()"/>
</xsl:call-template>
</xsl:when>
<xsl:when test="starts-with(@ID,'__GROUP_SLAVES__')">
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message>PLACING POTENTIAL GROUP OF SLAVES <xsl:value-of select="@ID"/></xsl:message></xsl:if>
<xsl:call-template name="WRITE_VIEW_BIF_FOCUSED_POTENTIAL_MODULES">
<xsl:with-param name="iModules" select="self::node()"/>
</xsl:call-template>
</xsl:when>
<xsl:otherwise>
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message> IGNORING <xsl:value-of select="@ID"/></xsl:message></xsl:if>
</xsl:otherwise>
</xsl:choose>
</xsl:for-each>
</xsl:template>
<!--
+++++++++++++++++++++++++++++++++++++++++++++++++++++
MODULE TEMPLATES
+++++++++++++++++++++++++++++++++++++++++++++++++++++
-->
<!--
===================================================
THE MODULE TEMPLATE FOR PORT VIEW SELECTED FOCUS
===================================================
-->
<xsl:template match="MODULE" mode="_port_view_focusing_on_selected">
<xsl:variable name="m_inst_" select="@INSTANCE"/>
<xsl:if test="count($G_ROOT/SAV/SELECTED[(@INSTANCE = $m_inst_)]) &gt; 0">
<xsl:choose>
<xsl:when test="$G_ROOT/SAV/@MODE = 'TREE'">
<xsl:call-template name="WRITE_VIEW_PORT_TREE_SET">
<xsl:with-param name="iModRef" select="self::node()"/>
</xsl:call-template>
</xsl:when>
<xsl:when test="$G_ROOT/SAV/@MODE = 'FLAT'">
<xsl:call-template name="WRITE_VIEW_PORT_FLAT_SET">
<xsl:with-param name="iModRef" select="self::node()"/>
</xsl:call-template>
</xsl:when>
</xsl:choose>
</xsl:if>
</xsl:template>
<!--
===================================================
THE MODULE TEMPLATE FOR BIF VIEW BUS FOCUS
===================================================
-->
<xsl:template match="MODULE" mode="_bif_view_focusing_on_buses">
<xsl:variable name="m_instance_" select="@INSTANCE"/>
<xsl:variable name="m_modclass_" select="@MODCLASS"/>
<xsl:variable name="is_focused_bus_" select="count($G_ROOT/SAV/BUS[(@INSTANCE = $m_instance_)])"/>
<xsl:variable name="bif_scope_">
<xsl:if test="$is_focused_bus_ = 0"> <!-- No need to waste time if we know its one of the focused bus -->
<xsl:for-each select="BUSINTERFACES/BUSINTERFACE[(not(@IS_VALID) or (@IS_VALID = 'TRUE'))]">
<xsl:variable name="b_bus_" select="@BUSNAME"/>
<xsl:variable name="b_bstd_" select="@BUSSTD"/>
<xsl:variable name="b_on_focused_bus_" select="count($G_ROOT/SAV/BUS[(@INSTANCE = $b_bus_)])"/>
<xsl:variable name="b_of_focused_bstd_" select="count(exsl:node-set($G_FOCUSED_SCOPE)/BUS[@BUSSTD = $b_bstd_])"/>
<xsl:if test="$b_on_focused_bus_ &gt; 0"><CONNECTED/></xsl:if>
<xsl:if test="$b_of_focused_bstd_ &gt; 0"><POTENTIAL/></xsl:if>
</xsl:for-each>
</xsl:if>
</xsl:variable>
<xsl:variable name="on_focused_bus_" select="count(exsl:node-set($bif_scope_)/CONNECTED)"/>
<xsl:variable name="of_focused_bstd_" select="count(exsl:node-set($bif_scope_)/POTENTIAL)"/>
<xsl:if test="(($is_focused_bus_ + $on_focused_bus_ + $of_focused_bstd_) &gt; 0)">
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message>PLACING MODULE ON BUS <xsl:value-of select="@INSTANCE"/></xsl:message></xsl:if>
<xsl:choose>
<!-- TREE VIEW -->
<xsl:when test="$G_ROOT/SAV/@MODE = 'TREE'">
<xsl:element name="SET">
<xsl:attribute name="ID"><xsl:value-of select="@INSTANCE"/></xsl:attribute>
<xsl:attribute name="CLASS">MODULE</xsl:attribute>
<xsl:if test="($is_focused_bus_ &gt; 0)">
<xsl:attribute name="RGB_BG"><xsl:value-of select="$COL_FOCUSED_MASTER"/></xsl:attribute>
</xsl:if>
<xsl:choose>
<xsl:when test="(($is_focused_bus_ + $on_focused_bus_) &gt; 0)">
<xsl:attribute name="CONNECTED_INDEX"><xsl:value-of select="@MHS_INDEX"/></xsl:attribute>
</xsl:when>
<xsl:otherwise>
<xsl:attribute name="POTENTIAL_INDEX"><xsl:value-of select="@MHS_INDEX"/></xsl:attribute>
</xsl:otherwise>
</xsl:choose>
<!-- CR452579 Can only modify INSTANCE name in Hierarchal view. -->
<VARIABLE VIEWTYPE="TEXTBOX" VIEWDISP="Name" NAME="INSTANCE" VALUE="{@INSTANCE}"/>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Type" NAME="MODTYPE" VALUE="{@MODTYPE}" VIEWICON="{LICENSEINFO/@ICON_NAME}"/>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Version" NAME="HWVERSION" VALUE="{@HWVERSION}"/>
<xsl:variable name="ipClassification_">
<xsl:call-template name="F_ModClass_To_IpClassification">
<xsl:with-param name="iModClass" select="@MODCLASS"/>
<xsl:with-param name="iBusStd" select="@BUSSTD"/>
</xsl:call-template>
</xsl:variable>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Classification" NAME="IPCLASS" VALUE="{$ipClassification_}"/>
<xsl:for-each select="BUSINTERFACES/BUSINTERFACE[(not(@IS_VALID) or (@IS_VALID = 'TRUE'))]">
<xsl:variable name="b_bus_" select="@BUSNAME"/>
<xsl:variable name="b_bstd_" select="@BUSSTD"/>
<xsl:variable name="b_on_focused_bus_" select="count($G_ROOT/SAV/BUS[(@INSTANCE = $b_bus_)])"/>
<xsl:variable name="b_of_focused_bstd_" select="count(exsl:node-set($G_FOCUSED_SCOPE)/BUS[@BUSSTD = $b_bstd_])"/>
<xsl:variable name="bif_col_">
<xsl:choose>
<xsl:when test="(not($b_bus_ ='__NOC__') and ($b_on_focused_bus_ = 0) and ($b_of_focused_bstd_ &gt; 0))"><xsl:value-of select="$COL_BG_OUTOF_FOCUS_CONNECTIONS"/></xsl:when>
<xsl:otherwise>__NONE__</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:if test="(($b_on_focused_bus_ + $b_of_focused_bstd_) &gt; 0)">
<xsl:if test="$G_ROOT/SAV/@MODE = 'TREE'">
<xsl:call-template name="WRITE_VIEW_BIF_TREE_SET">
<xsl:with-param name="iModRef" select="../.."/>
<xsl:with-param name="iBifRef" select="self::node()"/>
<xsl:with-param name="iBifCol" select="$bif_col_"/>
</xsl:call-template>
</xsl:if>
<xsl:if test="$G_ROOT/SAV/@MODE = 'FLAT'">
<xsl:call-template name="WRITE_VIEW_BIF_FLAT_SET">
<xsl:with-param name="iModRef" select="../.."/>
<xsl:with-param name="iBifRef" select="self::node()"/>
<xsl:with-param name="iBifCol" select="$bif_col_"/>
</xsl:call-template>
</xsl:if>
</xsl:if>
</xsl:for-each>
</xsl:element>
</xsl:when>
<!-- FLAT VIEW -->
<xsl:otherwise>
<xsl:for-each select="BUSINTERFACES/BUSINTERFACE[(not(@IS_VALID) or (@IS_VALID = 'TRUE'))]">
<xsl:variable name="b_bus_" select="@BUSNAME"/>
<xsl:variable name="b_on_focused_bus_" select="count($G_ROOT/SAV/BUS[(@INSTANCE = $b_bus_)])"/>
<xsl:if test="($b_on_focused_bus_ &gt; 0)">
<xsl:if test="$G_ROOT/SAV/@MODE = 'TREE'">
<xsl:call-template name="WRITE_VIEW_BIF_TREE_SET">
<xsl:with-param name="iModRef" select="../.."/>
<xsl:with-param name="iBifRef" select="self::node()"/>
</xsl:call-template>
</xsl:if>
<xsl:if test="$G_ROOT/SAV/@MODE = 'FLAT'">
<xsl:call-template name="WRITE_VIEW_BIF_FLAT_SET">
<xsl:with-param name="iModRef" select="../.."/>
<xsl:with-param name="iBifRef" select="self::node()"/>
</xsl:call-template>
</xsl:if>
</xsl:if>
</xsl:for-each>
</xsl:otherwise>
</xsl:choose>
</xsl:if>
</xsl:template>
<!--
===================================================
THE MODULE TEMPLATE FOR CONNECTED MODULES
IN BIF VIEW PROC FOCUS
===================================================
-->
<xsl:template match="MODULE" mode="_bif_view_focusing_on_connected">
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message>EXAMINING CONNECTED MODULE <xsl:value-of select="@INSTANCE"/></xsl:message></xsl:if>
<xsl:variable name="m_instance_" select="@INSTANCE"/>
<xsl:variable name="m_class_" select="@MODCLASS"/>
<xsl:variable name="bif_scope_">
<xsl:for-each select="BUSINTERFACES/BUSINTERFACE[(not(@IS_VALID) or (@IS_VALID = 'TRUE'))]">
<xsl:variable name="b_std_" select="@BUSSTD"/>
<xsl:variable name="b_bus_" select="@BUSNAME"/>
<xsl:variable name="b_name_" select="@NAME"/>
<xsl:choose>
<xsl:when test="($b_bus_ = '__NOC__')"><POTENTIAL/></xsl:when>
<xsl:when test="((@TYPE = 'TARGET') or (@TYPE = 'INITIATOR')) and (count(key('G_MAP_P2P_BIFS',$b_bus_)[not(@BUSNAME = '__NOC__')]) &gt; 0)">
<xsl:variable name="p2p_scope_">
<xsl:for-each select="$G_SYS_MODS">
<xsl:for-each select="key('G_MAP_P2P_BIFS',$b_bus_)[not(@BUSNAME = '__NOC__')]">
<xsl:variable name="b_instance_" select="../../@INSTANCE"/>
<xsl:variable name="b_modclass_" select="../../@MODCLASS"/>
<xsl:variable name="b_bifname_" select="@NAME"/>
<xsl:if test="not(($b_bifname_ = $b_name_) and ($b_instance_ = $m_instance_))">
<xsl:variable name="num_mast_connections_" select="count(exsl:node-set($G_FOCUSED_SCOPE)/BUS[@NAME = $b_bus_])"/>
<xsl:variable name="num_peri_connections_" select="count(exsl:node-set($G_FOCUSED_SCOPE)/PERIPHERAL[(@NAME = $b_instance_)])"/>
<xsl:if test="(($num_mast_connections_ + $num_peri_connections_) &gt; 0)"><INSCOPE/></xsl:if>
<xsl:if test="(($num_mast_connections_ + $num_peri_connections_) = 0) and not($m_class_ = 'MEMORY') and not($m_class_ = 'MEMORY_CNTLR')"><UNFOCUSED/></xsl:if>
</xsl:if>
</xsl:for-each>
</xsl:for-each>
</xsl:variable>
<xsl:variable name="num_p2p_inscope_" select="count(exsl:node-set($p2p_scope_)/INSCOPE)"/>
<xsl:variable name="num_p2p_unfocused_" select="count(exsl:node-set($p2p_scope_)/UNFOCUSED)"/>
<xsl:if test="$num_p2p_inscope_ &gt; 0"><CONNECTED/></xsl:if>
<xsl:if test="$num_p2p_unfocused_ &gt; 0"><UNFOCUSED/></xsl:if>
</xsl:when>
<!--
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message> P2P <xsl:value-of select="$b_instance_"/> == <xsl:value-of select="$num_peri_connections_"/> UNFOCUSED</xsl:message></xsl:if>
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message> P2P <xsl:value-of select="$m_instance_"/>.<xsl:value-of select="$b_name_"/> = <xsl:value-of select="$num_p2p_unfocused_"/> UNFOCUSED</xsl:message></xsl:if>
-->
<xsl:when test="((@TYPE = 'SLAVE') and not(MASTERS/MASTER)) or (@TYPE = 'MASTER')">
<xsl:if test="count(exsl:node-set($G_FOCUSED_SCOPE)/BUS[@NAME = $b_bus_]) &gt; 0"><CONNECTED/></xsl:if>
<xsl:if test="($b_bus_ = '__NOC__') and count(exsl:node-set($G_FOCUSED_SCOPE)/BUS[@BUSSTD = $b_std_]) &gt; 0"><POTENTIAL/></xsl:if>
</xsl:when>
<xsl:when test="(MASTERS/MASTER)">
<xsl:if test="count(exsl:node-set($G_FOCUSED_SCOPE)/BUS[@NAME = $b_bus_]) &gt; 0"><POTENTIAL/></xsl:if>
<xsl:for-each select="MASTERS/MASTER">
<xsl:variable name="m_inst_" select="@INSTANCE"/>
<xsl:choose>
<xsl:when test="count($G_ROOT/SAV/MASTER[(@INSTANCE = $m_inst_)]) &gt; 0"><CONNECTED/></xsl:when>
<xsl:when test="count(exsl:node-set($G_FOCUSED_SCOPE)/PERIPHERAL[(@NAME = $m_inst_)]) &gt; 0"><CONNECTED/></xsl:when>
<xsl:otherwise><UNFOCUSED/></xsl:otherwise>
</xsl:choose>
</xsl:for-each>
</xsl:when>
</xsl:choose>
</xsl:for-each>
<xsl:if test="$m_class_ = 'BUS'">
<xsl:variable name="num_bifs_on_bus_" select="count(key('G_MAP_ALL_BIFS_BY_BUS',$m_instance_))"/>
<!-- <xsl:if test="$G_DEBUG='TRUE'"><xsl:message>BBBBBB <xsl:value-of select="$m_instance_"/> has <xsl:value-of select="$num_bifs_on_bus_"/> bifs </xsl:message></xsl:if> -->
<xsl:for-each select="key('G_MAP_ALL_BIFS_BY_BUS',$m_instance_)">
<xsl:variable name="b_name_" select="@NAME"/>
<xsl:variable name="b_type_" select="@TYPE"/>
<xsl:variable name="b_inst_" select="../../@INSTANCE"/>
<xsl:variable name="b_icls_" select="../../@MODCLASS"/>
<xsl:variable name="is_mast_in_focus_" select="count($G_ROOT/SAV/MASTER[(@INSTANCE = $b_inst_)])"/>
<xsl:variable name="is_peri_in_focus_" select="count(exsl:node-set($G_FOCUSED_SCOPE)/PERIPHERAL[@NAME = $b_inst_])"/>
<xsl:if test="(($is_peri_in_focus_ + $is_mast_in_focus_) = 0)"><UNFOCUSED/></xsl:if>
</xsl:for-each>
</xsl:if>
</xsl:variable>
<xsl:variable name="mod_id_" select="@INSTANCE"/>
<xsl:variable name="potential_masts_id_" select="concat('__GROUP_MASTER__.',@INSTANCE)"/>
<xsl:variable name="is_master_" select="count($G_GROUPS/BLOCK[(@ID = $potential_masts_id_)])"/>
<xsl:variable name="is_focused_on_" select="count($G_ROOT/SAV/MASTER[(@INSTANCE = $mod_id_)])"/>
<xsl:variable name="is_peripheral_" select="count(exsl:node-set($G_FOCUSED_SCOPE)/PERIPHERAL[@NAME = $mod_id_])"/>
<xsl:variable name="num_potential_bifs_" select="count(exsl:node-set($bif_scope_)/POTENTIAL)"/>
<xsl:variable name="num_connected_bifs_" select="count(exsl:node-set($bif_scope_)/CONNECTED)"/>
<xsl:variable name="num_unfocused_bifs_" select="count(exsl:node-set($bif_scope_)/UNFOCUSED)"/>
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message> CONNECTED BIFS <xsl:value-of select="$num_connected_bifs_"/></xsl:message></xsl:if>
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message> POTENTIAL BIFS <xsl:value-of select="$num_potential_bifs_"/></xsl:message></xsl:if>
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message> IS PERIPHERAL <xsl:value-of select="$is_peripheral_"/></xsl:message></xsl:if>
<xsl:if test="((@MODCLASS = 'BUS') or ($num_connected_bifs_ + $is_focused_on_ + $num_potential_bifs_ + $is_peripheral_) &gt; 0)">
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message> PLACING MODULE <xsl:value-of select="@INSTANCE"/></xsl:message></xsl:if>
<xsl:choose>
<xsl:when test="$G_ROOT/SAV/@MODE = 'TREE'">
<xsl:element name="SET">
<xsl:attribute name="ID"><xsl:value-of select="@INSTANCE"/></xsl:attribute>
<xsl:attribute name="CLASS">MODULE</xsl:attribute>
<xsl:choose>
<xsl:when test="((@MODCLASS = 'BUS') or (($num_connected_bifs_ + $is_peripheral_ + $is_focused_on_) &gt; 0))">
<xsl:attribute name="CONNECTED_INDEX"><xsl:value-of select="@MHS_INDEX"/></xsl:attribute>
</xsl:when>
<xsl:otherwise>
<xsl:attribute name="POTENTIAL_INDEX"><xsl:value-of select="@MHS_INDEX"/></xsl:attribute>
</xsl:otherwise>
</xsl:choose>
<xsl:choose>
<xsl:when test="count($G_ROOT/SAV/MASTER[(@INSTANCE = $mod_id_)]) &gt; 0">
<xsl:attribute name="RGB_BG"><xsl:value-of select="$COL_FOCUSED_MASTER"/></xsl:attribute>
</xsl:when>
<xsl:when test="$num_unfocused_bifs_ &gt; 0">
<xsl:attribute name="RGB_FG"><xsl:value-of select="$COL_BG_OUTOF_FOCUS_CONNECTIONS"/></xsl:attribute>
</xsl:when>
</xsl:choose>
<!--
CR452579
Can only modify INSTANCE name in Hierarchal view.
-->
<VARIABLE VIEWTYPE="TEXTBOX" VIEWDISP="Name" NAME="INSTANCE" VALUE="{@INSTANCE}"/>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Type" NAME="MODTYPE" VALUE="{@MODTYPE}" VIEWICON="{LICENSEINFO/@ICON_NAME}"/>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Version" NAME="HWVERSION" VALUE="{@HWVERSION}"/>
<xsl:variable name="ipClassification_">
<xsl:call-template name="F_ModClass_To_IpClassification">
<xsl:with-param name="iModClass" select="@MODCLASS"/>
<xsl:with-param name="iBusStd" select="@BUSSTD"/>
</xsl:call-template>
</xsl:variable>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Classification" NAME="IPCLASS" VALUE="{$ipClassification_}"/>
<xsl:apply-templates select="BUSINTERFACES/BUSINTERFACE[(not(@IS_VALID) or (@IS_VALID = 'TRUE'))]" mode="_bif_view_focusing_on_connected"/>
</xsl:element>
</xsl:when>
<xsl:otherwise>
<xsl:apply-templates select="BUSINTERFACES/BUSINTERFACE[(not(@IS_VALID) or (@IS_VALID = 'TRUE'))]" mode="_bif_view_focusing_on_connected"/>
</xsl:otherwise>
</xsl:choose>
</xsl:if>
</xsl:template>
<!--
===================================================
THE MODULE TEMPLATE FOR POTENTIAL MODULES
IN BIF VIEW PROC FOCUS
===================================================
-->
<xsl:template match="MODULE" mode="_bif_view_focusing_on_potentials">
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message>EXAMINING POTENTIAL MODULE <xsl:value-of select="@INSTANCE"/></xsl:message></xsl:if>
<xsl:variable name="m_instance_" select="@INSTANCE"/>
<xsl:variable name="m_modclass_" select="@MODCLASS"/>
<xsl:variable name="bif_scope_">
<xsl:for-each select="BUSINTERFACES/BUSINTERFACE[(not(@IS_VALID) or (@IS_VALID = 'TRUE'))]">
<xsl:variable name="b_std_" select="@BUSSTD"/>
<xsl:variable name="b_bus_" select="@BUSNAME"/>
<xsl:choose>
<xsl:when test="($b_bus_ = '__NOC__')"><POTENTIAL/></xsl:when>
<xsl:when test="((@TYPE = 'TARGET') or (@TYPE = 'INITIATOR')) and (count(key('G_MAP_P2P_BIFS',$b_bus_)[not(@BUSNAME = '__NOC__')]) &gt; 0)">
<xsl:variable name="p2p_scope_">
<xsl:for-each select="$G_SYS_MODS"> <!-- To set the right scope for the keys -->
<xsl:for-each select="key('G_MAP_P2P_BIFS',$b_bus_)[not(@BUSNAME = '__NOC__')]">
<xsl:variable name="b_instance_" select="../../@INSTANCE"/>
<xsl:variable name="b_modclass_" select="../../@MODCLASS"/>
<xsl:variable name="num_mast_connections_" select="count(exsl:node-set($G_FOCUSED_SCOPE)/BUS[@NAME = $b_bus_])"/>
<xsl:variable name="num_peri_connections_">
<xsl:choose>
<xsl:when test="((($m_modclass_ = 'PROCESSOR') and ($b_modclass_ = 'PROCESSOR')) or not($b_modclass_ = 'PROCESSOR'))">
<xsl:value-of select="count(exsl:node-set($G_FOCUSED_SCOPE)/PERIPHERAL[(@NAME = $b_instance_)])"/>
</xsl:when>
<xsl:otherwise>0</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:if test="(($num_mast_connections_ + $num_peri_connections_) &gt; 0)"><INSCOPE/></xsl:if>
<xsl:if test="(($num_mast_connections_ + $num_peri_connections_) = 0) and not($m_modclass_ = 'MEMORY') and not($m_modclass_ = 'MEMORY_CNTLR')"><UNFOCUSED/></xsl:if>
</xsl:for-each>
</xsl:for-each>
</xsl:variable>
<xsl:variable name="num_p2p_inscope_" select="count(exsl:node-set($p2p_scope_)/INSCOPE)"/>
<xsl:variable name="num_p2p_unfocused_" select="count(exsl:node-set($p2p_scope_)/UNFOCUSED)"/>
<xsl:if test="$num_p2p_inscope_ &gt; 0"><CONNECTED/></xsl:if>
<xsl:if test="$num_p2p_unfocused_ &gt; 0"><UNFOCUSED/></xsl:if>
</xsl:when>
<xsl:when test="(@TYPE = 'SLAVE') and not(MASTERS/MASTER)">
<xsl:if test="count(exsl:node-set($G_FOCUSED_SCOPE)/BUS[@NAME = $b_bus_]) &gt; 0"><CONNECTED/></xsl:if>
<xsl:if test="($b_bus_ = '__NOC__') and count(exsl:node-set($G_FOCUSED_SCOPE)/BUS[@BUSSTD = $b_std_]) &gt; 0"><POTENTIAL/></xsl:if>
</xsl:when>
<xsl:when test="(MASTERS/MASTER)">
<xsl:if test="count(exsl:node-set($G_FOCUSED_SCOPE)/BUS[@NAME = $b_bus_]) &gt; 0"><POTENTIAL/></xsl:if>
<xsl:for-each select="MASTERS/MASTER">
<xsl:variable name="m_inst_" select="@INSTANCE"/>
<xsl:choose>
<xsl:when test="count($G_ROOT/SAV/MASTER[(@INSTANCE = $m_inst_)]) &gt; 0"><CONNECTED/></xsl:when>
<xsl:when test="count(exsl:node-set($G_FOCUSED_SCOPE)/PERIPHERAL[(@NAME = $m_inst_)]) &gt; 0"><CONNECTED/></xsl:when>
<xsl:otherwise><UNFOCUSED/></xsl:otherwise>
</xsl:choose>
</xsl:for-each>
</xsl:when>
</xsl:choose>
</xsl:for-each>
<xsl:if test="$m_modclass_ = 'BUS'">
<xsl:variable name="num_bifs_on_bus_" select="count(key('G_MAP_ALL_BIFS_BY_BUS',$m_instance_))"/>
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message>BUS <xsl:value-of select="$m_instance_"/> has <xsl:value-of select="$num_bifs_on_bus_"/> bifs </xsl:message></xsl:if>
<xsl:for-each select="key('G_MAP_ALL_BIFS_BY_BUS',$m_instance_)">
<xsl:variable name="b_name_" select="@NAME"/>
<xsl:variable name="b_type_" select="@TYPE"/>
<xsl:variable name="b_inst_" select="../../@INSTANCE"/>
<xsl:variable name="b_icls_" select="../../@MODCLASS"/>
<xsl:variable name="is_mast_in_focus_" select="count($G_ROOT/SAV/MASTER[(@INSTANCE = $b_inst_)])"/>
<xsl:variable name="is_peri_in_focus_" select="count(exsl:node-set($G_FOCUSED_SCOPE)/PERIPHERAL[@NAME = $b_inst_])"/>
<xsl:if test="(($is_peri_in_focus_ + $is_mast_in_focus_) = 0)"><UNFOCUSED/></xsl:if>
</xsl:for-each>
</xsl:if>
</xsl:variable>
<xsl:variable name="mod_id_" select="@INSTANCE"/>
<xsl:variable name="potential_masts_id_" select="concat('__GROUP_MASTER__.',@INSTANCE)"/>
<xsl:variable name="is_master_" select="count($G_GROUPS/BLOCK[(@ID = $potential_masts_id_)])"/>
<xsl:variable name="is_peripheral_" select="count(exsl:node-set($G_FOCUSED_SCOPE)/PERIPHERAL[@NAME = $mod_id_])"/>
<xsl:variable name="num_potential_bifs_" select="count(exsl:node-set($bif_scope_)/POTENTIAL)"/>
<xsl:variable name="num_connected_bifs_" select="count(exsl:node-set($bif_scope_)/CONNECTED)"/>
<xsl:variable name="num_unfocused_bifs_" select="count(exsl:node-set($bif_scope_)/UNFOCUSED)"/>
<!--
-->
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message> <xsl:value-of select="$num_connected_bifs_"/> connected BIFS</xsl:message></xsl:if>
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message> <xsl:value-of select="$num_potential_bifs_"/> potential bifs </xsl:message></xsl:if>
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message> <xsl:value-of select="$num_unfocused_bifs_"/> unfocused bifs </xsl:message></xsl:if>
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message> <xsl:value-of select="$is_peripheral_"/> is a peripheral</xsl:message></xsl:if>
<xsl:if test="(($num_connected_bifs_ + $num_potential_bifs_ + $is_peripheral_) &gt; 0)">
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message>PLACING POTENTIAL MODULE <xsl:value-of select="@INSTANCE"/></xsl:message></xsl:if>
<xsl:choose>
<xsl:when test="$G_ROOT/SAV/@MODE = 'TREE'">
<xsl:element name="SET">
<xsl:attribute name="ID"><xsl:value-of select="@INSTANCE"/></xsl:attribute>
<xsl:attribute name="CLASS">MODULE</xsl:attribute>
<xsl:choose>
<xsl:when test="(($is_peripheral_ &gt; 0) or ($num_connected_bifs_ &gt; 0))">
<xsl:attribute name="CONNECTED_INDEX"><xsl:value-of select="@MHS_INDEX"/></xsl:attribute>
</xsl:when>
<xsl:otherwise>
<xsl:attribute name="POTENTIAL_INDEX"><xsl:value-of select="@MHS_INDEX"/></xsl:attribute>
</xsl:otherwise>
</xsl:choose>
<xsl:choose>
<xsl:when test="count($G_ROOT/SAV/MASTER[(@INSTANCE = $mod_id_)]) &gt; 0">
<xsl:attribute name="RGB_BG"><xsl:value-of select="$COL_FOCUSED_MASTER"/></xsl:attribute>
</xsl:when>
<xsl:when test="$num_unfocused_bifs_ &gt; 0">
<xsl:attribute name="RGB_FG"><xsl:value-of select="$COL_BG_OUTOF_FOCUS_CONNECTIONS"/></xsl:attribute>
</xsl:when>
</xsl:choose>
<!-- CR452579 Can only modify INSTANCE name in Hierarchal view. -->
<VARIABLE VIEWTYPE="TEXTBOX" VIEWDISP="Name" NAME="INSTANCE" VALUE="{@INSTANCE}"/>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Type" NAME="MODTYPE" VALUE="{@MODTYPE}" VIEWICON="{LICENSEINFO/@ICON_NAME}"/>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Version" NAME="HWVERSION" VALUE="{@HWVERSION}"/>
<xsl:variable name="ipClassification_">
<xsl:call-template name="F_ModClass_To_IpClassification">
<xsl:with-param name="iModClass" select="@MODCLASS"/>
<xsl:with-param name="iBusStd" select="@BUSSTD"/>
</xsl:call-template>
</xsl:variable>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Classification" NAME="IPCLASS" VALUE="{$ipClassification_}"/>
<xsl:apply-templates select="BUSINTERFACES/BUSINTERFACE[(not(@IS_VALID) or (@IS_VALID = 'TRUE'))]" mode="_bif_view_focusing_on_potentials"/>
</xsl:element>
</xsl:when>
<xsl:otherwise>
<xsl:apply-templates select="BUSINTERFACES/BUSINTERFACE[(not(@IS_VALID) or (@IS_VALID = 'TRUE'))]" mode="_bif_view_focusing_on_potentials"/>
</xsl:otherwise>
</xsl:choose>
</xsl:if>
</xsl:template>
<!--
+++++++++++++++++++++++++++++++++++++++++++++++++++++
BUS INTERFACE TEMPLATES
+++++++++++++++++++++++++++++++++++++++++++++++++++++
-->
<!--
===================================================
THE BIF TEMPLATE FOR CONNECTED MODULES
IN BIF VIEW PROC FOCUS
===================================================
-->
<xsl:template match="BUSINTERFACE[(not(@IS_VALID) or (@IS_VALID = 'TRUE'))]" mode="_bif_view_focusing_on_connected">
<xsl:variable name="m_instance_" select="../../@INSTANCE"/>
<xsl:variable name="b_std_" select="@BUSSTD"/>
<xsl:variable name="b_bus_" select="@BUSNAME"/>
<xsl:variable name="b_name_" select="@NAME"/>
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message> EXAMINING CONNECTED INTERFACE <xsl:value-of select="$m_instance_"/>.<xsl:value-of select="$b_name_"/></xsl:message></xsl:if>
<xsl:variable name="bif_scope_">
<xsl:choose>
<xsl:when test="($b_bus_ = '__NOC__')"><POTENTIAL/></xsl:when>
<xsl:when test="((@TYPE = 'TARGET') or (@TYPE = 'INITIATOR')) and (count(key('G_MAP_P2P_BIFS',$b_bus_)[not(@BUSNAME = '__NOC__')]) &gt; 0)">
<xsl:variable name="p2p_scope_">
<xsl:for-each select="$G_SYS_MODS"> <!-- to put in right scope for key below -->
<xsl:for-each select="key('G_MAP_P2P_BIFS',$b_bus_)[not(@BUSNAME = '__NOC__')]">
<xsl:variable name="p2p_bifname_" select="@NAME"/>
<xsl:variable name="p2p_instance_" select="../../@INSTANCE"/>
<xsl:variable name="num_proc_connections_" select="count(key('G_MAP_PROCESSORS',$p2p_instance_))"/>
<xsl:variable name="num_mast_connections_" select="count(exsl:node-set($G_FOCUSED_SCOPE)/BUS[@NAME = $b_bus_])"/>
<xsl:variable name="num_peri_connections_" select="count(exsl:node-set($G_FOCUSED_SCOPE)/PERIPHERAL[(@NAME = $p2p_instance_)])"/>
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message> <xsl:value-of select="$p2p_instance_"/>.<xsl:value-of select="$p2p_bifname_"/></xsl:message></xsl:if>
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message> PROC CONNECTIONS <xsl:value-of select="$num_proc_connections_"/></xsl:message></xsl:if>
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message> MAST CONNECTIONS <xsl:value-of select="$num_mast_connections_"/></xsl:message></xsl:if>
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message> PERI CONNECTIONS <xsl:value-of select="$num_peri_connections_"/></xsl:message></xsl:if>
<xsl:if test="($num_mast_connections_ = 0) and ($num_proc_connections_ &gt; 0)"><OUTSCOPE/></xsl:if>
<xsl:if test="($num_mast_connections_ &gt; 0) or ($num_peri_connections_ &gt; 0)"><INSCOPE/></xsl:if>
</xsl:for-each>
</xsl:for-each>
</xsl:variable>
<xsl:variable name="num_p2p_inscope_" select="count(exsl:node-set($p2p_scope_)/INSCOPE)"/>
<xsl:variable name="num_p2p_outscope_" select="count(exsl:node-set($p2p_scope_)/OUTSCOPE)"/>
<xsl:if test="(($num_p2p_inscope_ &gt; 0) and ($num_p2p_outscope_ = 0))"><CONNECTED/></xsl:if>
</xsl:when>
<xsl:when test="(@TYPE = 'MASTER')">
<xsl:if test="count(exsl:node-set($G_FOCUSED_SCOPE)/BUS[@NAME = $b_bus_]) &gt; 0"><CONNECTED/></xsl:if>
</xsl:when>
<xsl:when test="(@TYPE = 'SLAVE') and not(MASTERS/MASTER)">
<xsl:if test="count(exsl:node-set($G_FOCUSED_SCOPE)/BUS[@NAME = $b_bus_]) &gt; 0"><CONNECTED/></xsl:if>
<xsl:if test="($b_bus_ = '__NOC__') and count(exsl:node-set($G_FOCUSED_SCOPE)/BUS[@BUSSTD = $b_std_]) &gt; 0"><POTENTIAL/></xsl:if>
</xsl:when>
<xsl:when test="(MASTERS/MASTER)">
<xsl:if test="count(exsl:node-set($G_FOCUSED_SCOPE)/BUS[@NAME = $b_bus_]) &gt; 0"><POTENTIAL/></xsl:if>
<xsl:for-each select="MASTERS/MASTER">
<xsl:variable name="m_inst_" select="@INSTANCE"/>
<xsl:choose>
<xsl:when test="count($G_ROOT/SAV/MASTER[(@INSTANCE = $m_inst_)]) &gt; 0"><CONNECTED/></xsl:when>
<xsl:when test="count(exsl:node-set($G_FOCUSED_SCOPE)/PERIPHERAL[(@NAME = $m_inst_)]) &gt; 0"><CONNECTED/></xsl:when>
<xsl:otherwise><UNFOCUSED/></xsl:otherwise>
</xsl:choose>
</xsl:for-each>
</xsl:when>
</xsl:choose>
</xsl:variable>
<xsl:variable name="num_scope_unfocuseds_" select="count(exsl:node-set($bif_scope_)/UNFOCUSED)"/>
<xsl:variable name="num_scope_potentials_" select="count(exsl:node-set($bif_scope_)/POTENTIAL)"/>
<xsl:variable name="num_scope_connecteds_" select="count(exsl:node-set($bif_scope_)/CONNECTED)"/>
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message> CONNECTED SCOPE <xsl:value-of select="$num_scope_connecteds_"/></xsl:message></xsl:if>
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message> POTENTIAL SCOPE <xsl:value-of select="$num_scope_potentials_"/></xsl:message></xsl:if>
<xsl:variable name="include_bif_">
<xsl:choose>
<xsl:when test="($b_bus_ = '__NOC__')">TRUE</xsl:when>
<xsl:when test="(((@TYPE = 'TARGET') or (@TYPE = 'INITIATOR')) and ($num_scope_connecteds_ &gt; 0))">TRUE</xsl:when>
<xsl:when test="((@TYPE = 'MASTER') or (@TYPE = 'SLAVE') or (@TYPE = 'MASTER_SLAVE')) and (($num_scope_potentials_ &gt; 0) or ($num_scope_connecteds_ &gt; 0))">TRUE</xsl:when>
<xsl:otherwise>FALSE</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:if test="($include_bif_ = 'TRUE')">
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message> PLACING CONNECTED INTERFACE <xsl:value-of select="$m_instance_"/>.<xsl:value-of select="$b_name_"/></xsl:message></xsl:if>
<xsl:variable name="bif_col_">
<xsl:choose>
<xsl:when test="($num_scope_unfocuseds_ &gt; 0)"><xsl:value-of select="$COL_BG_OUTOF_FOCUS_CONNECTIONS"/></xsl:when>
<xsl:otherwise>__NONE__</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:if test="$G_ROOT/SAV/@MODE = 'TREE'">
<xsl:call-template name="WRITE_VIEW_BIF_TREE_SET">
<xsl:with-param name="iModRef" select="../.."/>
<xsl:with-param name="iBifRef" select="self::node()"/>
<xsl:with-param name="iBifCol" select="$bif_col_"/>
</xsl:call-template>
</xsl:if>
<xsl:if test="$G_ROOT/SAV/@MODE = 'FLAT'">
<xsl:call-template name="WRITE_VIEW_BIF_FLAT_SET">
<xsl:with-param name="iModRef" select="../.."/>
<xsl:with-param name="iBifRef" select="self::node()"/>
<xsl:with-param name="iBifCol" select="$bif_col_"/>
</xsl:call-template>
</xsl:if>
</xsl:if>
</xsl:template>
<!--
===================================================
THE BIF TEMPLATE FOR POTENTIAL MODULES
IN BIF VIEW PROC FOCUS
===================================================
-->
<xsl:template match="BUSINTERFACES/BUSINTERFACE[(not(@IS_VALID) or (@IS_VALID = 'TRUE'))]" mode="_bif_view_focusing_on_potentials">
<xsl:variable name="m_instance_" select="../../@INSTANCE"/>
<xsl:variable name="b_name_" select="@NAME"/>
<xsl:variable name="b_std_" select="@BUSSTD"/>
<xsl:variable name="b_bus_" select="@BUSNAME"/>
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message> EXAMINING POTENTIAL INTERFACE <xsl:value-of select="$m_instance_"/>.<xsl:value-of select="$b_name_"/></xsl:message></xsl:if>
<xsl:variable name="bif_scope_">
<xsl:choose>
<xsl:when test="($b_bus_ = '__NOC__')"><POTENTIAL/></xsl:when>
<xsl:when test="((@TYPE = 'TARGET') or (@TYPE = 'INITIATOR')) and (count(key('G_MAP_P2P_BIFS',$b_bus_)[not(@BUSNAME = '__NOC__')]) &gt; 0)">
<xsl:variable name="p2p_scope_">
<xsl:for-each select="$G_SYS_MODS">
<xsl:for-each select="key('G_MAP_P2P_BIFS',$b_bus_)[not(@BUSNAME = '__NOC__')]">
<xsl:variable name="b_instance_" select="../../@INSTANCE"/>
<xsl:variable name="num_proc_connections_" select="count(key('G_MAP_PROCESSORS',$b_instance_))"/>
<xsl:variable name="num_mast_connections_" select="count(exsl:node-set($G_FOCUSED_SCOPE)/BUS[@NAME = $b_bus_])"/>
<xsl:variable name="num_peri_connections_" select="count(exsl:node-set($G_FOCUSED_SCOPE)/PERIPHERAL[(@NAME = $b_instance_)])"/>
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message> PROC CONNECTIONS <xsl:value-of select="$num_proc_connections_"/></xsl:message></xsl:if>
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message> MAST CONNECTIONS <xsl:value-of select="$num_mast_connections_"/></xsl:message></xsl:if>
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message> PERI CONNECTIONS <xsl:value-of select="$num_peri_connections_"/></xsl:message></xsl:if>
<xsl:if test="($num_mast_connections_ = 0) and ($num_proc_connections_ &gt; 0)"><OUTSCOPE/></xsl:if>
<xsl:if test="($num_mast_connections_ &gt; 0) or ($num_peri_connections_ &gt; 0)"><INSCOPE/></xsl:if>
</xsl:for-each>
</xsl:for-each>
</xsl:variable>
<xsl:variable name="num_p2p_inscope_" select="count(exsl:node-set($p2p_scope_)/INSCOPE)"/>
<xsl:variable name="num_p2p_outscope_" select="count(exsl:node-set($p2p_scope_)/OUTSCOPE)"/>
<xsl:if test="(($num_p2p_inscope_ &gt; 0) and ($num_p2p_outscope_ = 0))"><CONNECTED/></xsl:if>
</xsl:when>
<xsl:when test="(((@TYPE = 'SLAVE') and not(MASTERS/MASTER)) or (@TYPE = 'MASTER'))">
<xsl:if test="count(exsl:node-set($G_FOCUSED_SCOPE)/BUS[@NAME = $b_bus_]) &gt; 0"><CONNECTED/></xsl:if>
<xsl:if test="($b_bus_ = '__NOC__') and count(exsl:node-set($G_FOCUSED_SCOPE)/BUS[@BUSSTD = $b_std_]) &gt; 0"><POTENTIAL/></xsl:if>
</xsl:when>
<xsl:when test="(MASTERS/MASTER)">
<xsl:if test="count(exsl:node-set($G_FOCUSED_SCOPE)/BUS[@NAME = $b_bus_]) &gt; 0"><POTENTIAL/></xsl:if>
<xsl:for-each select="MASTERS/MASTER">
<xsl:variable name="m_inst_" select="@INSTANCE"/>
<xsl:choose>
<xsl:when test="count($G_ROOT/SAV/MASTER[(@INSTANCE = $m_inst_)]) &gt; 0"><CONNECTED/></xsl:when>
<xsl:when test="count(exsl:node-set($G_FOCUSED_SCOPE)/PERIPHERAL[(@NAME = $m_inst_)]) &gt; 0"><CONNECTED/></xsl:when>
<xsl:otherwise><UNFOCUSED/></xsl:otherwise>
</xsl:choose>
</xsl:for-each>
</xsl:when>
</xsl:choose>
</xsl:variable>
<xsl:variable name="num_scope_potentials_" select="count(exsl:node-set($bif_scope_)/POTENTIAL)"/>
<xsl:variable name="num_scope_connecteds_" select="count(exsl:node-set($bif_scope_)/CONNECTED)"/>
<xsl:variable name="num_scope_unfocuseds_" select="count(exsl:node-set($bif_scope_)/UNFOCUSED)"/>
<xsl:variable name="include_bif_">
<xsl:choose>
<xsl:when test="($b_bus_ = '__NOC__')">TRUE</xsl:when>
<xsl:when test="(((@TYPE = 'TARGET') or (@TYPE = 'INITIATOR')) and ($num_scope_connecteds_ &gt; 0))">TRUE</xsl:when>
<xsl:when test="((@TYPE = 'MASTER') or (@TYPE = 'SLAVE') or (@TYPE = 'MASTER_SLAVE')) and (($num_scope_potentials_ &gt; 0) or ($num_scope_connecteds_ &gt; 0))">TRUE</xsl:when>
<xsl:otherwise>FALSE</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:variable name="bif_col_">
<xsl:choose>
<xsl:when test="($num_scope_unfocuseds_ &gt; 0)"><xsl:value-of select="$COL_BG_OUTOF_FOCUS_CONNECTIONS"/></xsl:when>
<xsl:otherwise>__NONE__</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:if test="($include_bif_ = 'TRUE')">
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message> PLACING POTENTIAL INTERFACE <xsl:value-of select="$m_instance_"/>.<xsl:value-of select="$b_name_"/></xsl:message></xsl:if>
<xsl:if test="$G_ROOT/SAV/@MODE = 'TREE'">
<xsl:call-template name="WRITE_VIEW_BIF_TREE_SET">
<xsl:with-param name="iModRef" select="../.."/>
<xsl:with-param name="iBifRef" select="self::node()"/>
<xsl:with-param name="iBifCol" select="$bif_col_"/>
</xsl:call-template>
</xsl:if>
<xsl:if test="$G_ROOT/SAV/@MODE = 'FLAT'">
<xsl:call-template name="WRITE_VIEW_BIF_FLAT_SET">
<xsl:with-param name="iModRef" select="../.."/>
<xsl:with-param name="iBifRef" select="self::node()"/>
<xsl:with-param name="iBifCol" select="$bif_col_"/>
</xsl:call-template>
</xsl:if>
</xsl:if>
</xsl:template>
<!-- THINGS TO IGNORE -->
<!-- Ignore all non valid bus interfaces -->
<xsl:template match="MODULE/DESCRIPTION" mode="_bif_view_focusing_on_potentials">
<!-- <xsl:message>Ignoring invalid bus interface <xsl:value-of select="@NAME"/></xsl:message> -->
</xsl:template>
<xsl:template match="MODULE/PARAMETERS" mode="_bif_view_focusing_on_potentials">
<!-- <xsl:message>Ignoring invalid bus interface <xsl:value-of select="@NAME"/></xsl:message> -->
</xsl:template>
<xsl:template match="MODULE/DOCUMENTATION" mode="_bif_view_focusing_on_potentials">
<!-- <xsl:message>Ignoring invalid bus interface <xsl:value-of select="@NAME"/></xsl:message> -->
</xsl:template>
<xsl:template match="MODULE/LICENSEINFO" mode="_bif_view_focusing_on_potentials">
<!-- <xsl:message>Ignoring invalid bus interface <xsl:value-of select="@NAME"/></xsl:message> -->
</xsl:template>
<!-- Ignore all non valid bus interfaces -->
<xsl:template match="BUSINTERFACES/BUSINTERFACE[(@IS_VALID = 'FALSE')]" mode="_bif_view_focusing_on_potentials">
</xsl:template>
<xsl:template match="MODULE/DESCRIPTION" mode="_bif_view_focusing_on_connected">
<!-- <xsl:message>Ignoring invalid bus interface <xsl:value-of select="@NAME"/></xsl:message> -->
</xsl:template>
<xsl:template match="MODULE/PARAMETERS" mode="_bif_view_focusing_on_connected">
<!-- <xsl:message>Ignoring invalid bus interface <xsl:value-of select="@NAME"/></xsl:message> -->
</xsl:template>
<xsl:template match="MODULE/DOCUMENTATION" mode="_bif_view_focusing_on_connected">
<!-- <xsl:message>Ignoring invalid bus interface <xsl:value-of select="@NAME"/></xsl:message> -->
</xsl:template>
<xsl:template match="MODULE/LICENSEINFO" mode="_bif_view_focusing_on_connected">
<!-- <xsl:message>Ignoring invalid bus interface <xsl:value-of select="@NAME"/></xsl:message> -->
</xsl:template>
<xsl:template match="BUSINTERFACES/BUSINTERFACE[(@IS_VALID = 'FALSE')]" mode="_bif_view_focusing_on_connected">
</xsl:template>
<!-- Ignore all non valid bus interfaces -->
<xsl:template match="SAV" mode="_port_view_focusing_on_selected">
</xsl:template>
<xsl:template match="MODULE/DESCRIPTION" mode="_port_view_focusing_on_selected">
<!-- <xsl:message>Ignoring invalid bus interface <xsl:value-of select="@NAME"/></xsl:message> -->
</xsl:template>
<xsl:template match="MODULE/PARAMETERS" mode="_port_view_focusing_on_selected">
<!-- <xsl:message>Ignoring invalid bus interface <xsl:value-of select="@NAME"/></xsl:message> -->
</xsl:template>
<xsl:template match="MODULE/DOCUMENTATION" mode="_port_view_focusing_on_selected">
<!-- <xsl:message>Ignoring invalid bus interface <xsl:value-of select="@NAME"/></xsl:message> -->
</xsl:template>
<xsl:template match="MODULE/LICENSEINFO" mode="_port_view_focusing_on_selected">
<!-- <xsl:message>Ignoring invalid bus interface <xsl:value-of select="@NAME"/></xsl:message> -->
</xsl:template>
<!-- Ignore all non valid bus interfaces -->
<xsl:template match="BUSINTERFACES/BUSINTERFACE[(@IS_VALID = 'FALSE')]" mode="_port_view_focusing_on_selected">
</xsl:template>
<!--
Only write bus interfaces that are valid for non point to point interfaces
that have busstds the processor can see
-->
<!--
===============================================
GROUP VIEW TRANSFORMS
===============================================
-->
<xsl:template name="WRITE_VIEW_GROUPS">
<xsl:param name="iModules"/>
<xsl:if test="$G_DEBUG='TRUE'">
<!--
<xsl:message>BLKD AREA = <xsl:value-of select="$blkd_full_w_"/> X <xsl:value-of select="$blkd_full_h_"/></xsl:message>
<xsl:message>NUMOF BUSSTD COLORS = <xsl:value-of select="$COL_BUSSTDS_NUMOF"/></xsl:message>
<xsl:message>NUMOF INTERFACE TYPES= <xsl:value-of select="$G_IFTYPES_NUMOF"/></xsl:message>
<xsl:message>NUMOF DIRS = <xsl:value-of select="$G_BLKD_COMPASS_DIRS_NUMOF"/></xsl:message>
<xsl:apply-templates select="$G_BLOCKS/node()" mode="_place_module_blocks_"/>
-->
</xsl:if>
<xsl:element name="SET">
<xsl:attribute name="CLASS">PROJECT</xsl:attribute>
<xsl:attribute name="VIEW_ID">BUSINTERFACE</xsl:attribute>
<xsl:attribute name="DISPLAYMODE">TREE</xsl:attribute>
<xsl:call-template name="WRITE_VIEW_BIF_GROUPS">
<xsl:with-param name="iModules" select="$G_BLOCKS"/>
</xsl:call-template>
</xsl:element>
</xsl:template>
<xsl:template name="WRITE_VIEW_BIF_GROUPS">
<xsl:param name="iModules"/>
<xsl:for-each select="$iModules/BLOCK[@ID and not(BLOCK) and not(@C)]">
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message>PLACING BUS <xsl:value-of select="@ID"/></xsl:message></xsl:if>
<xsl:variable name="m_id_" select="@ID"/>
<xsl:variable name="m_module_" select="$G_SYS_MODS/MODULE[@INSTANCE = $m_id_]"/>
<xsl:variable name="m_instance_" select="$m_module_/@INSTANCE"/>
<xsl:variable name="m_version_" select="$m_module_/@HWVERSION"/>
<xsl:variable name="m_type_" select="$m_module_/@MODTYPE"/>
<xsl:variable name="m_class_" select="$m_module_/@MODCLASS"/>
<xsl:variable name="m_busstd_" select="$m_module_/@BUSSTD"/>
<xsl:element name="SET">
<xsl:attribute name="ID"><xsl:value-of select="@ID"/></xsl:attribute>
<xsl:attribute name="CLASS">MODULE</xsl:attribute>
<xsl:element name="VARIABLE">
<xsl:attribute name="VIEWDISP">Name</xsl:attribute>
<xsl:attribute name="VIEWTYPE">TEXTBOX</xsl:attribute>
<xsl:attribute name="NAME">INSTANCE</xsl:attribute>
<xsl:attribute name="VALUE"><xsl:value-of select="$m_instance_"/></xsl:attribute>
</xsl:element>
<xsl:element name="VARIABLE">
<xsl:attribute name="VIEWDISP">IP Type</xsl:attribute>
<xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
<xsl:attribute name="NAME">MODTYPE</xsl:attribute>
<xsl:attribute name="VALUE"><xsl:value-of select="$m_type_"/></xsl:attribute>
</xsl:element>
<xsl:element name="VARIABLE">
<xsl:attribute name="VIEWDISP">IP Version</xsl:attribute>
<xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
<xsl:attribute name="NAME">HWVERSION</xsl:attribute>
<xsl:attribute name="VALUE"><xsl:value-of select="$m_version_"/></xsl:attribute>
</xsl:element>
<xsl:element name="VARIABLE">
<xsl:attribute name="VIEWDISP">IP Classification</xsl:attribute>
<xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
<xsl:attribute name="NAME">IPCLASS</xsl:attribute>
<xsl:attribute name="VALUE"><xsl:value-of select="$m_busstd_"/> BUS</xsl:attribute>
</xsl:element>
</xsl:element>
</xsl:for-each>
<xsl:for-each select="$iModules/BLOCK[@ID and BLOCK]">
<xsl:choose>
<xsl:when test="not(starts-with(@ID,'__')) and BLOCK[@C] and (not(BLOCK/BLOCK) or BLOCK/BLOCK[@CP])">
<!--
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message>PLACING MODULE <xsl:value-of select="@ID"/></xsl:message></xsl:if>
-->
<xsl:variable name="m_id_" select="@ID"/>
<xsl:variable name="m_module_" select="$G_SYS_MODS/MODULE[@INSTANCE = $m_id_]"/>
<xsl:variable name="m_instance_" select="$m_module_/@INSTANCE"/>
<xsl:variable name="m_type_" select="$m_module_/@MODTYPE"/>
<xsl:variable name="m_class_" select="$m_module_/@MODCLASS"/>
<xsl:variable name="m_version_" select="$m_module_/@HWVERSION"/>
<xsl:element name="SET">
<xsl:attribute name="ID"><xsl:value-of select="@ID"/></xsl:attribute>
<xsl:attribute name="CLASS">MODULE</xsl:attribute>
<xsl:element name="VARIABLE">
<xsl:attribute name="VIEWDISP">Name</xsl:attribute>
<xsl:attribute name="VIEWTYPE">TEXTBOX</xsl:attribute>
<xsl:attribute name="NAME">INSTANCE</xsl:attribute>
<xsl:attribute name="VALUE"><xsl:value-of select="$m_instance_"/></xsl:attribute>
</xsl:element>
<xsl:element name="VARIABLE">
<xsl:attribute name="VIEWDISP">IP Type</xsl:attribute>
<xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
<xsl:attribute name="NAME">MODTYPE</xsl:attribute>
<xsl:attribute name="VALUE"><xsl:value-of select="$m_type_"/></xsl:attribute>
</xsl:element>
<xsl:element name="VARIABLE">
<xsl:attribute name="VIEWDISP">IP Version</xsl:attribute>
<xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
<xsl:attribute name="NAME">HWVERSION</xsl:attribute>
<xsl:attribute name="VALUE"><xsl:value-of select="$m_version_"/></xsl:attribute>
</xsl:element>
<xsl:element name="VARIABLE">
<xsl:attribute name="VIEWDISP">IP Classification</xsl:attribute>
<xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
<xsl:attribute name="NAME">IPCLASS</xsl:attribute>
<xsl:attribute name="VALUE"><xsl:value-of select="$m_class_"/></xsl:attribute>
</xsl:element>
<xsl:for-each select="BLOCK[@C and @ID]">
<xsl:variable name="b_bus_" select="@C"/>
<xsl:variable name="b_name_" select="@ID"/>
<xsl:variable name="b_if_" select="$m_module_/BUSINTERFACES/BUSINTERFACE[(@NAME = $b_name_)]"/>
<xsl:variable name="b_type_" select="$b_if_/@TYPE"/>
<xsl:variable name="b_busstd_" select="$b_if_/@BUSSTD"/>
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message>PLACING BIF <xsl:value-of select="$b_name_"/></xsl:message></xsl:if>
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message> TYPE <xsl:value-of select="$b_type_"/></xsl:message></xsl:if>
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message> BUS <xsl:value-of select="$b_bus_"/></xsl:message></xsl:if>
<xsl:variable name="b_busNameViewType_">
<xsl:choose>
<xsl:when test="$b_type_ = 'INITIATOR'">TEXTBOX</xsl:when>
<xsl:when test="starts-with(@ID,'S_AXI')">BUTTON</xsl:when>
<xsl:when test="starts-with(@ID,'S0_AXI')">BUTTON</xsl:when>
<xsl:when test="starts-with(@ID,'S1_AXI')">BUTTON</xsl:when>
<xsl:otherwise>DROPDOWN</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:variable name="b_busName_">
<xsl:choose>
<xsl:when test="$b_if_/MASTERS/MASTER">
<xsl:variable name="mastersList_"><xsl:for-each select="$b_if_/MASTERS/MASTER"><xsl:if test="position() &gt; 1"> &amp; </xsl:if><xsl:value-of select="concat(@INSTANCE,'.',@BUSINTERFACE)"/></xsl:for-each></xsl:variable>
<xsl:variable name="mastersConn_" select="concat($b_bus_,':',$mastersList_)"/>
<xsl:value-of select="$mastersConn_"/>
</xsl:when>
<xsl:otherwise><xsl:value-of select="$b_bus_"/></xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message> VIEWTYPE <xsl:value-of select="$b_busNameViewType_"/></xsl:message></xsl:if>
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message> BUSNAME <xsl:value-of select="$b_busName_"/></xsl:message></xsl:if>
<xsl:element name="SET">
<xsl:attribute name="ID"><xsl:value-of select="@ID"/></xsl:attribute>
<xsl:attribute name="CLASS">BUSINTERFACE</xsl:attribute>
<xsl:element name="VARIABLE">
<xsl:attribute name="VIEWDISP">NAME</xsl:attribute>
<xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
<xsl:attribute name="NAME">NAME</xsl:attribute>
<xsl:attribute name="VALUE"><xsl:value-of select="$b_name_"/></xsl:attribute>
</xsl:element>
<xsl:element name="VARIABLE">
<xsl:attribute name="VIEWDISP">Bus Name</xsl:attribute>
<xsl:attribute name="VIEWTYPE"><xsl:value-of select="$b_busNameViewType_"/></xsl:attribute>
<xsl:attribute name="NAME">BUSNAME</xsl:attribute>
<xsl:attribute name="VALUE"><xsl:value-of select="$b_busName_"/></xsl:attribute>
</xsl:element>
<xsl:element name="VARIABLE">
<xsl:attribute name="VIEWDISP">Type</xsl:attribute>
<xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
<xsl:attribute name="NAME">TYPE</xsl:attribute>
<xsl:attribute name="VALUE"><xsl:value-of select="$b_type_"/></xsl:attribute>
</xsl:element>
<xsl:element name="VARIABLE">
<xsl:attribute name="VIEWDISP">Bus Standard</xsl:attribute>
<xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
<xsl:attribute name="NAME">BUSSTD</xsl:attribute>
<xsl:attribute name="VALUE"><xsl:value-of select="$b_busstd_"/></xsl:attribute>
</xsl:element>
</xsl:element>
</xsl:for-each>
</xsl:element>
</xsl:when>
<xsl:when test="starts-with(@ID,'__GROUP_PROCESSOR__')">
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message>PROCESSOR GROUP<xsl:value-of select="@ID"/></xsl:message></xsl:if>
<xsl:variable name="p_id_" select="substring-after(@ID,'__GROUP_PROCESSOR__')"/>
<xsl:variable name="m_id_" select="concat('PROCESSOR',$p_id_)"/>
<xsl:element name="SET">
<xsl:attribute name="ID"><xsl:value-of select="$m_id_"/></xsl:attribute>
<xsl:attribute name="CLASS">GROUP</xsl:attribute>
<xsl:element name="VARIABLE">
<xsl:attribute name="VIEWDISP">NAME</xsl:attribute>
<xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
<xsl:attribute name="NAME">INSTANCE</xsl:attribute>
<xsl:attribute name="VALUE">Subsystem of <xsl:value-of select="$p_id_"/></xsl:attribute>
</xsl:element>
<xsl:call-template name="WRITE_VIEW_BIF_GROUPS">
<xsl:with-param name="iModules" select="self::node()"/>
</xsl:call-template>
</xsl:element>
</xsl:when>
<xsl:when test="starts-with(@ID,'__GROUP_MASTER__')">
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message>MASTER GROUP<xsl:value-of select="@ID"/></xsl:message></xsl:if>
<xsl:variable name="p_id_" select="substring-after(@ID,'__GROUP_MASTER__')"/>
<xsl:variable name="m_id_" select="concat('MASTER',$p_id_)"/>
<xsl:element name="SET">
<xsl:attribute name="ID"><xsl:value-of select="$m_id_"/></xsl:attribute>
<xsl:attribute name="CLASS">GROUP</xsl:attribute>
<xsl:element name="VARIABLE">
<xsl:attribute name="VIEWDISP">NAME</xsl:attribute>
<xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
<xsl:attribute name="NAME">INSTANCE</xsl:attribute>
<xsl:attribute name="VALUE">Subsystem of <xsl:value-of select="$p_id_"/></xsl:attribute>
</xsl:element>
<xsl:call-template name="WRITE_VIEW_BIF_GROUPS">
<xsl:with-param name="iModules" select="self::node()"/>
</xsl:call-template>
</xsl:element>
</xsl:when>
<xsl:when test="starts-with(@ID,'__GROUP_SHARED__')">
<xsl:variable name="s_id_" select="substring-after(@ID,'__GROUP_SHARED__')"/>
<xsl:variable name="m_id_" select="concat('SHARED',$s_id_)"/>
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message>PLACING SHARED PERIPHERALS <xsl:value-of select="$s_id_"/></xsl:message></xsl:if>
<xsl:element name="SET">
<xsl:attribute name="ID"><xsl:value-of select="$m_id_"/></xsl:attribute>
<xsl:attribute name="CLASS">GROUP</xsl:attribute>
<xsl:element name="VARIABLE">
<xsl:attribute name="VIEWDISP">NAME</xsl:attribute>
<xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
<xsl:attribute name="NAME">INSTANCE</xsl:attribute>
<xsl:attribute name="VALUE">Peripherals shared by <xsl:value-of select="$s_id_"/></xsl:attribute>
</xsl:element>
<xsl:call-template name="WRITE_VIEW_BIF_GROUPS">
<xsl:with-param name="iModules" select="self::node()"/>
</xsl:call-template>
</xsl:element>
</xsl:when>
<xsl:when test="starts-with(@ID,'__GROUP_MEMORY__')">
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message>PLACING MEMORY <xsl:value-of select="@ID"/></xsl:message></xsl:if>
<xsl:variable name="m_id_" select="substring-after(@ID,'__GROUP_MEMORY__')"/>
<xsl:element name="SET">
<xsl:attribute name="ID"><xsl:value-of select="$m_id_"/></xsl:attribute>
<xsl:attribute name="CLASS">GROUP</xsl:attribute>
<xsl:element name="VARIABLE">
<xsl:attribute name="VIEWDISP">NAME</xsl:attribute>
<xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
<xsl:attribute name="NAME">INSTANCE</xsl:attribute>
<xsl:attribute name="VALUE">(Memory) <xsl:value-of select="$m_id_"/></xsl:attribute>
</xsl:element>
<xsl:call-template name="WRITE_VIEW_BIF_GROUPS">
<xsl:with-param name="iModules" select="self::node()"/>
</xsl:call-template>
</xsl:element>
</xsl:when>
<xsl:when test="starts-with(@ID,'__GROUP_PERIPHERAL__')">
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message>PLACING PERIPHERAL <xsl:value-of select="@ID"/></xsl:message></xsl:if>
<xsl:call-template name="WRITE_VIEW_BIF_GROUPS">
<xsl:with-param name="iModules" select="self::node()"/>
</xsl:call-template>
</xsl:when>
<xsl:when test="starts-with(@ID,'__GROUP_SLAVES__')">
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message>PLACING SLAVES <xsl:value-of select="@ID"/></xsl:message></xsl:if>
<xsl:call-template name="WRITE_VIEW_BIF_GROUPS">
<xsl:with-param name="iModules" select="self::node()"/>
</xsl:call-template>
</xsl:when>
<!--
<xsl:when test="starts-with(@ID,'__GROUP_SLAVES__')">
<xsl:if test="$G_DEBUG='TRUE'"><xsl:message>PLACING SLAVES GOUP <xsl:value-of select="@ID"/></xsl:message></xsl:if>
<xsl:variable name="m_id_" select="substring-after(@ID,'__GROUP_SLAVES__')"/>
<xsl:element name="SET">
<xsl:attribute name="ID"><xsl:value-of select="$m_id_"/></xsl:attribute>
<xsl:attribute name="CLASS">GROUP</xsl:attribute>
<xsl:element name="VARIABLE">
<xsl:attribute name="VIEWDISP">NAME</xsl:attribute>
<xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
<xsl:attribute name="NAME">INSTANCE</xsl:attribute>
<xsl:attribute name="VALUE">(Slaves of) <xsl:value-of select="$m_id_"/></xsl:attribute>
</xsl:element>
<xsl:call-template name="F_Write_XTeller_MODULES">
<xsl:with-param name="iModules" select="self::node()"/>
</xsl:call-template>
</xsl:element>
</xsl:when>
-->
</xsl:choose>
</xsl:for-each>
</xsl:template>
</xsl:stylesheet>
projnav/xps/__xps/edw2xtl_sav_view_port.xsl 0 → 100644
View file @ a64d58e7
<?xml version="1.0" standalone="no"?>
<!DOCTYPE stylesheet [
<!ENTITY UPPERCASE "ABCDEFGHIJKLMNOPQRSTUVWXYZ">
<!ENTITY LOWERCASE "abcdefghijklmnopqrstuvwxyz">
<!ENTITY UPPER2LOWER " '&UPPERCASE;' , '&LOWERCASE;' ">
<!ENTITY LOWER2UPPER " '&LOWERCASE;' , '&UPPERCASE;' ">
<!ENTITY ALPHALOWER "ABCDEFxX0123456789">
<!ENTITY HEXUPPER "ABCDEFxX0123456789">
<!ENTITY HEXLOWER "abcdefxX0123456789">
<!ENTITY HEXU2L " '&HEXLOWER;' , '&HEXUPPER;' ">
]>
<xsl:stylesheet version="1.0"
xmlns:xsl="http://www.w3.org/1999/XSL/Transform"
xmlns:exsl="http://exslt.org/common"
xmlns:dyn="http://exslt.org/dynamic"
xmlns:math="http://exslt.org/math"
xmlns:xlink="http://www.w3.org/1999/xlink"
extension-element-prefixes="math dyn exsl xlink">
<!--
================================================================================
Generate XTeller for PORTS
================================================================================
-->
<xsl:param name="SHOW_IOIF" select="'TRUE'"/>
<xsl:param name="SHOW_BUSIF" select="'TRUE'"/>
<xsl:template name="WRITE_VIEW_PORT_TREE">
<xsl:variable name="num_of_ext_ports_" select="count($G_SYS_EXPS/PORT)"/>
<xsl:if test="$G_DEBUG='TRUE'">
<xsl:message>WRITING PORT in MODE :<xsl:value-of select="@MODE"/></xsl:message>
<!--
<xsl:message>EXTERNAL PORT <xsl:value-of select="$num_of_ext_ports_"/></xsl:message>
-->
</xsl:if>
<xsl:if test="$num_of_ext_ports_ &gt; 0">
<xsl:call-template name="WRITE_VIEW_EXTP_TREE_SET"/>
</xsl:if>
<xsl:for-each select="$G_SYS_MODS/MODULE">
<xsl:sort data-type="number" select="@ROW_INDEX" order="ascending"/>
<xsl:variable name= "instName_" select="@INSTANCE"/>
<xsl:variable name="moduleRef_" select="self::node()"/>
<xsl:call-template name="WRITE_VIEW_PORT_TREE_SET">
<xsl:with-param name="iModRef" select="$moduleRef_"/>
</xsl:call-template>
</xsl:for-each> <!-- End of MODULES loop -->
</xsl:template>
<xsl:template name="WRITE_VIEW_EXTP_TREE_SET">
<xsl:element name="SET">
<xsl:attribute name="ID">ExternalPorts</xsl:attribute>
<xsl:attribute name="CLASS">MODULE</xsl:attribute>
<xsl:for-each select="$G_SYS_EXPS">
<xsl:element name="VARIABLE">
<xsl:attribute name="NAME">Name</xsl:attribute>
<xsl:attribute name="VALUE">External Ports</xsl:attribute>
<xsl:attribute name="VIEWDISP">Name</xsl:attribute>
<xsl:attribute name="VIEWTYPE">STATIC</xsl:attribute>
</xsl:element>
<xsl:for-each select="PORT">
<xsl:sort select="@NAME" order="ascending"/>
<!--
<xsl:sort data-type="number" select="@MHS_INDEX" order="ascending"/>
-->
<xsl:element name="SET">
<xsl:attribute name="ID"><xsl:value-of select="@NAME"/></xsl:attribute>
<xsl:attribute name="CLASS">PORT</xsl:attribute>
<xsl:attribute name="ROW_INDEX"><xsl:value-of select="(position() - 1)"/></xsl:attribute>
<VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Net" NAME="SIGNAME" VALUE="{@SIGNAME}" IS_EDITABLE="TRUE"/>
<VARIABLE VIEWTYPE="TEXTBOX" VIEWDISP="Name" NAME="NAME" VALUE="{@NAME}"/>
<VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Direction" NAME="DIR" VALUE="{@DIR}"/>
<xsl:if test="(@SIGIS)">
<VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Class" NAME="SIGIS" VALUE="{@SIGIS}"/>
</xsl:if>
<xsl:if test="not(@SIGIS)">
<VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Class" NAME="SIGIS" VALUE="NONE"/>
</xsl:if>
<xsl:choose>
<xsl:when test="@LEFT and @RIGHT">
<xsl:variable name="vecformula_txt_">[<xsl:value-of select="@LEFT"/>:<xsl:value-of select="@RIGHT"/>]</xsl:variable>
<VARIABLE VIEWTYPE="TEXTBOX" VIEWDISP="Range" NAME="VECFORMULA" VALUE="{$vecformula_txt_}"/>
</xsl:when>
<xsl:when test="@MSB and @LSB">
<xsl:variable name="vecformula_txt_">[<xsl:value-of select="@MSB"/>:<xsl:value-of select="@LSB"/>]</xsl:variable>
<VARIABLE VIEWTYPE="TEXTBOX" VIEWDISP="Range" NAME="VECFORMULA" VALUE="{$vecformula_txt_}"/>
</xsl:when>
<xsl:when test="(not(@MSB) and not(@LSB) and not(@SIGIS = 'CLK') and not(@SIGIS = 'CLOCK') and not(@SIGIS = 'DCMCLK') and not(@SIGIS = 'RST') and not(@SIGIS = 'RESET'))">
<VARIABLE VIEWTYPE="TEXTBOX" VIEWDISP="Range" NAME="VECFORMULA" VALUE=""/>
</xsl:when>
</xsl:choose>
<xsl:if test="((@SIGIS = 'CLK') or (@SIGIS = 'CLOCK') or (@SIGIS = 'DCMCLK'))">
<VARIABLE VIEWTYPE="TEXTBOX" VIEWDISP="Frequency(Hz)" NAME="CLKFREQUENCY" VALUE="{@CLKFREQUENCY}"/>
</xsl:if>
<xsl:if test="(@SIGIS = 'RST' or @SIGIS = 'RESET')">
<VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Reset Polarity" NAME="RSTPOLARITY" VALUE="{@RSTPOLARITY}"/>
</xsl:if>
<xsl:if test="(@SIGIS = 'INTERRUPT')">
<VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Sensitivity" NAME="SENSITIVITY" VALUE="{@SENSITIVITY}"/>
</xsl:if>
</xsl:element>
</xsl:for-each> <!-- End of EXTERNAL PORTS loop -->
</xsl:for-each> <!-- End of EXTERNAL PORTS loop -->
</xsl:element> <!-- End of EXTERNAL PORTS SET -->
</xsl:template>
<xsl:template name="WRITE_VIEW_PORT_TREE_SET">
<xsl:param name="iModRef" select="'__NONE__'"/>
<xsl:variable name="m_inst_" select="$iModRef/@INSTANCE"/>
<xsl:variable name="m_class_" select="$iModRef/@MODCLASS"/>
<xsl:variable name="m_type_" select="$iModRef/@MODTYPE"/>
<xsl:variable name="m_type_lc_" select="translate($m_type_,&UPPER2LOWER;)"/>
<xsl:variable name="m_version_" select="$iModRef/@HWVERSION"/>
<xsl:variable name="m_licinfo_" select="$iModRef/LICENSEINFO"/>
<xsl:variable name="m_ports_" select="$iModRef/PORTS"/>
<xsl:variable name="is_axi_interconnect_">
<xsl:choose>
<xsl:when test="$m_type_ = 'axi_interconnect'">TRUE</xsl:when>
<xsl:when test="$m_type_lc_ = 'axi_interconnect'">TRUE</xsl:when>
<xsl:otherwise>FALSE</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:for-each select="$G_SYS_MODS"> <!-- To put things in the right scope for the keys below -->
<xsl:variable name="m_iofs_all_" select="key('G_MAP_ALL_IOFS', $m_inst_)"/>
<xsl:variable name="m_bifs_all_" select="key('G_MAP_ALL_BIFS', $m_inst_)"/>
<xsl:variable name="m_ports_def_" select="key('G_MAP_DEF_PORTS',$m_inst_)"/>
<xsl:variable name="m_ports_ndf_" select="key('G_MAP_NDF_PORTS',$m_inst_)"/>
<!--
<xsl:if test="$G_DEBUG = 'TRUE'">
<xsl:message><xsl:value-of select="$m_inst_"/> has <xsl:value-of select="count($m_bifs_all_)"/> valid bifs </xsl:message>
<xsl:message><xsl:value-of select="$m_inst_"/> has <xsl:value-of select="count($m_iofs_all_)"/> valid iofs </xsl:message>
<xsl:message><xsl:value-of select="$m_inst_"/> has <xsl:value-of select="count($m_ports_def_)"/> default ports </xsl:message>
<xsl:message><xsl:value-of select="$m_inst_"/> has <xsl:value-of select="count($m_ports_ndf_)"/> non default ports </xsl:message>
<xsl:message></xsl:message>
</xsl:if>
-->
<SET ID="{$m_inst_}" CLASS="MODULE">
<!-- CR452579
Can only modify INSTANCE name in Hierarchal view.
-->
<VARIABLE VIEWTYPE="TEXTBOX" VIEWDISP="Name" NAME="INSTANCE" VALUE="{$m_inst_}"/>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Type" NAME="MODTYPE" VALUE="{$m_type_}" VIEWICON="{$m_licinfo_/@ICON_NAME}"/>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Version" NAME="HWVERSION" VALUE="{$m_version_}"/>
<!--
CR582477,
(among others) special case of axi_interconnect_aclk which is a member of
a bus interface, but should be treated as a non interface port, (i.e. appear even
if the bus interfaces its a member of is invalid.
-->
<xsl:if test="($is_axi_interconnect_ = 'TRUE')">
<!-- do it this way so we also catch the lower-upper case mismatches -->
<xsl:for-each select="key('G_MAP_ALL_PORTS',$m_inst_)[contains(@SIGIS,'CLK')]">
<xsl:variable name="uc_portName_" select="translate(@NAME,&LOWER2UPPER;)"/>
<xsl:if test="($uc_portName_= 'INTERCONNECT_ACLK')">
<!--
<xsl:message><xsl:value-of select="$m_inst_"/>.<xsl:value-of select="@NAME"/> = <xsl:value-of select="@SIGIS"/></xsl:message>
-->
<xsl:variable name="portName_" select="@NAME"/>
<xsl:variable name="portDir_" select="@DIR"/>
<xsl:variable name="portSig_" select="@SIGNAME"/>
<xsl:variable name="portSigIs_">
<xsl:choose>
<xsl:when test="not(@SIGIS)">__NONE__</xsl:when>
<xsl:otherwise><xsl:value-of select="@SIGIS"/></xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:variable name="portSensi_">
<xsl:choose>
<xsl:when test="(@SENSITIVITY)"><xsl:value-of select="@SENSITIVIITY"/></xsl:when>
<xsl:otherwise>__NONE__</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:variable name="portVecFormula_">
<xsl:choose>
<xsl:when test="@VECFORMULA"><xsl:value-of select="@VECFORMULA"/></xsl:when>
<xsl:otherwise>__NONE__</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:call-template name="WRITE_PORT_SET">
<xsl:with-param name="iName" select="$portName_"/>
<xsl:with-param name="iDir" select="$portDir_"/>
<xsl:with-param name="iSigName" select="$portSig_"/>
<xsl:with-param name="iSigIs" select="$portSigIs_"/>
<xsl:with-param name="iSensitivity" select="$portSensi_"/>
<xsl:with-param name="iVecFormula" select="$portVecFormula_"/>
</xsl:call-template>
</xsl:if>
</xsl:for-each>
</xsl:if>
<!-- PORTS not part of an INTERFACE -->
<xsl:for-each select="$m_ports_ndf_">
<xsl:sort data-type="number" select="@MPD_INDEX" order="ascending"/>
<xsl:variable name="uc_portName_" select="translate(@NAME,&LOWER2UPPER;)"/>
<!--
<xsl:if test="((not(@BUS) and not(@IOS)) or (($is_axi_interconnect_ = 'TRUE') and ($uc_portName_= 'INTERCONNECT_ACLK')))">
</xsl:if>
-->
<xsl:variable name="portName_" select="@NAME"/>
<xsl:variable name="portDir_" select="@DIR"/>
<xsl:variable name="portSig_" select="@SIGNAME"/>
<xsl:variable name="portSigIs_">
<xsl:choose>
<xsl:when test="not(@SIGIS)">__NONE__</xsl:when>
<xsl:otherwise><xsl:value-of select="@SIGIS"/></xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:variable name="portSensi_">
<xsl:choose>
<xsl:when test="(@SENSITIVITY)"><xsl:value-of select="@SENSITIVITY"/></xsl:when>
<xsl:otherwise>__NONE__</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:variable name="portVecFormula_">
<xsl:choose>
<xsl:when test="@VECFORMULA"><xsl:value-of select="@VECFORMULA"/></xsl:when>
<xsl:otherwise>__NONE__</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:call-template name="WRITE_PORT_SET">
<xsl:with-param name="iName" select="$portName_"/>
<xsl:with-param name="iDir" select="$portDir_"/>
<xsl:with-param name="iSigName" select="$portSig_"/>
<xsl:with-param name="iSigIs" select="$portSigIs_"/>
<xsl:with-param name="iSensitivity" select="$portSensi_"/>
<xsl:with-param name="iVecFormula" select="$portVecFormula_"/>
</xsl:call-template>
</xsl:for-each> <!-- END of PORTS NOT OF INTERFACE -->
<!-- PORTS part of a BUSINTERFACE -->
<xsl:if test="$SHOW_BUSIF = 'TRUE'">
<xsl:for-each select="$m_bifs_all_">
<xsl:sort data-type="number" select="@MPD_INDEX" order="ascending"/>
<xsl:variable name="bifName_" select="@NAME"/>
<xsl:variable name="bifRef_" select="self::node()"/>
<xsl:variable name="portmapsRef_" select="$bifRef_/PORTMAPS"/>
<!--
<xsl:variable name="bpmsCnt_" select="count($bpmsRef_/PORTMAP)"/>
<xsl:message><xsl:value-of select="$instName_"/>.<xsl:value-of select="$bifName_"/>.<xsl:value-of select="$bpmsCnt_"/></xsl:message>
-->
<xsl:variable name="is_external_">
<xsl:call-template name="F_IS_Interface_External">
<xsl:with-param name="iInstRef" select="$iModRef"/>
<xsl:with-param name="iIntfRef" select="$bifRef_"/>
</xsl:call-template>
</xsl:variable>
<xsl:variable name="bif_connection_">
<xsl:choose>
<xsl:when test="not(@BUSNAME = '__NOC__')">Connected to BUS <xsl:value-of select="@BUSNAME"/></xsl:when>
<xsl:when test="($is_external_ = 'TRUE')">Connected to External Ports</xsl:when>
<xsl:otherwise>Not connected to BUS or External Ports</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<!-- <SET ID="{@NAME}" CLASS="BUSINTERFACE.PORTS"/> -->
<xsl:element name="SET">
<xsl:attribute name="ID"><xsl:value-of select="@NAME"/></xsl:attribute>
<xsl:attribute name="CLASS">BUSINTERFACE.PORTS</xsl:attribute>
<xsl:if test="$is_external_ = 'TRUE'">
<xsl:attribute name="IS_EXTERNAL">TRUE</xsl:attribute>
</xsl:if>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="NAME" NAME="NAME" VALUE="(BUS_IF) {@NAME}"/>
<VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Net" NAME="BUSINTERFACE.CONNECTION" VALUE="{$bif_connection_}"/>
<xsl:for-each select="$portmapsRef_/PORTMAP">
<xsl:variable name="portDir_" select="@DIR"/>
<xsl:variable name="portName_" select="@PHYSICAL"/>
<xsl:if test="$m_ports_def_[(@NAME = $portName_)]"><!-- Only in map if port is valid -->
<!--
<xsl:if test="(not($portRef_/@IS_VALID) or ($portRef_/@IS_VALID = 'TRUE'))"/>
<xsl:sort select="@MPD_INDEX" order="ascending"/>
<xsl:sort data-type="number" select="@MPD_INDEX" order="ascending"/>
-->
<xsl:variable name="portRef_" select="$m_ports_def_[(@NAME = $portName_)]"/>
<xsl:variable name="portSig_" select="$portRef_/@SIGNAME"/>
<xsl:variable name="portSigIs_">
<xsl:choose>
<xsl:when test="not($portRef_/@SIGIS)">__NONE__</xsl:when>
<xsl:otherwise><xsl:value-of select="$portRef_/@SIGIS"/></xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:variable name="portSensi_">
<xsl:choose>
<xsl:when test="($portRef_/@SENSITIVITY)"><xsl:value-of select="$portRef_/@SENSITIVITY"/></xsl:when>
<xsl:otherwise>__NONE__</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:variable name="portVecFormula_">
<xsl:choose>
<xsl:when test="$portRef_/@VECFORMULA"><xsl:value-of select="$portRef_/@VECFORMULA"/></xsl:when>
<xsl:otherwise>__NONE__</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:call-template name="WRITE_PORT_SET">
<xsl:with-param name="iName" select="$portName_"/>
<xsl:with-param name="iDir" select="$portDir_"/>
<xsl:with-param name="iSigName" select="$portSig_"/>
<xsl:with-param name="iSigIs" select="$portSigIs_"/>
<xsl:with-param name="iSensitivity" select="$portSensi_"/>
<xsl:with-param name="iVecFormula" select="$portVecFormula_"/>
</xsl:call-template>
</xsl:if>
</xsl:for-each> <!-- END BIF PORTMAPS LOOP -->
</xsl:element>
</xsl:for-each> <!-- END BIFS LOOP -->
</xsl:if> <!-- END IF SHOW_BUSIFS -->
<!-- PORTS part of a IOINTERFACE -->
<xsl:if test="$SHOW_IOIF = 'TRUE'">
<xsl:for-each select="$m_iofs_all_[PORTMAPS/PORTMAP]">
<xsl:sort data-type="number" select="@MPD_INDEX" order="ascending"/>
<xsl:variable name="iifName_" select="@NAME"/>
<xsl:variable name="iifRef_" select="self::node()"/>
<xsl:variable name="portmapsRef_" select="$iifRef_/PORTMAPS"/>
<xsl:variable name="is_external_">
<xsl:call-template name="F_IS_Interface_External">
<xsl:with-param name="iInstRef" select="$iModRef"/>
<xsl:with-param name="iIntfRef" select="$iifRef_"/>
</xsl:call-template>
</xsl:variable>
<xsl:variable name="iif_connection_">
<xsl:choose>
<xsl:when test="($is_external_ ='TRUE')">Connected to External Ports</xsl:when>
<xsl:otherwise>Not connected to External Ports</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:element name="SET">
<xsl:attribute name="ID"><xsl:value-of select="@NAME"/></xsl:attribute>
<xsl:attribute name="CLASS">IOINTERFACE.PORTS</xsl:attribute>
<xsl:if test="$is_external_ = 'TRUE'">
<xsl:attribute name="IS_EXTERNAL">TRUE</xsl:attribute>
</xsl:if>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="NAME" NAME="NAME" VALUE="(IO_IF) {@NAME}"/>
<VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Net" NAME="IOINTERFACE.CONNECTION" VALUE="{$iif_connection_}"/>
<xsl:for-each select="$portmapsRef_/PORTMAP">
<xsl:variable name="portName_" select="@PHYSICAL"/>
<xsl:variable name="portDir_" select="@DIR"/>
<!--
<xsl:variable name="port_is_valid_">
<xsl:choose>
<xsl:when test="$portRef_/@IS_VALID = 'FALSE'">FALSE</xsl:when>
<xsl:otherwise>TRUE</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:message><xsl:value-of select="$portName_"/> : <xsl:value-of select="$port_is_valid_"/> : <xsl:value-of select="$portRef_/@IS_VALID"/></xsl:message>
-->
<xsl:if test="$m_ports_def_[(@NAME = $portName_)]"> <!-- Only in map if port is valid -->
<!--
<xsl:message><xsl:value-of select="$portName_"/> </xsl:message>
-->
<xsl:variable name="portRef_" select="$m_ports_def_[(@NAME = $portName_)]"/>
<xsl:variable name="portSig_" select="$portRef_/@SIGNAME"/>
<xsl:variable name="portSigIs_">
<xsl:choose>
<xsl:when test="not($portRef_/@SIGIS)">__NONE__</xsl:when>
<xsl:otherwise><xsl:value-of select="$portRef_/@SIGIS"/></xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:variable name="portSensi_">
<xsl:choose>
<xsl:when test="($portRef_/@SENSITIVITY)"><xsl:value-of select="$portRef_/@SENSITIVITY"/></xsl:when>
<xsl:otherwise>__NONE__</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:variable name="portVecFormula_">
<xsl:choose>
<xsl:when test="$portRef_/@VECFORMULA"><xsl:value-of select="$portRef_/@VECFORMULA"/></xsl:when>
<xsl:otherwise>__NONE__</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:call-template name="WRITE_PORT_SET">
<xsl:with-param name="iName" select="$portName_"/>
<xsl:with-param name="iDir" select="$portDir_"/>
<xsl:with-param name="iSigName" select="$portSig_"/>
<xsl:with-param name="iSigIs" select="$portSigIs_"/>
<xsl:with-param name="iSensitivity" select="$portSensi_"/>
<xsl:with-param name="iVecFormula" select="$portVecFormula_"/>
</xsl:call-template>
</xsl:if> <!-- End of port is valid check -->
</xsl:for-each> <!-- END IO INTERFACE PORTMAPS LOOP -->
</xsl:element>
</xsl:for-each> <!-- END IIFS LOOP -->
</xsl:if> <!-- END IF SHOW_IOIFS -->
</SET>
</xsl:for-each> <!-- End of the scoping for key functions-->
</xsl:template>
<xsl:template name="WRITE_VIEW_PORT_FLAT">
<xsl:if test="$G_DEBUG='TRUE'">
<xsl:message>WRITING PORT MODE <xsl:value-of select="@MODE"/></xsl:message>
</xsl:if>
<xsl:variable name="num_of_ext_ports_" select="count($G_SYS_EXPS/PORT)"/>
<xsl:if test="$num_of_ext_ports_ &gt; 0">
<xsl:call-template name="WRITE_VIEW_EXTP_FLAT_SET"/>
</xsl:if>
<xsl:for-each select="$G_SYS_MODS/MODULE">
<xsl:sort data-type="number" select="@ROW_INDEX" order="ascending"/>
<xsl:variable name="instName_" select="@INSTANCE"/>
<xsl:variable name="moduleRef_" select="self::node()"/>
<xsl:call-template name="WRITE_VIEW_PORT_FLAT_SET">
<xsl:with-param name="iModRef" select="$moduleRef_"/>
</xsl:call-template>
</xsl:for-each> <!-- End of Modules Loop -->
</xsl:template>
<xsl:template name="WRITE_VIEW_EXTP_FLAT_SET">
<xsl:for-each select="$G_SYS_EXPS">
<xsl:for-each select="PORT[(not(@IS_VALID) or (@IS_VALID = 'TRUE'))]">
<xsl:sort data-type="number" select="@MHS_INDEX" order="ascending"/>
<xsl:variable name="ext_is_interrupt_">
<xsl:if test="@SIGIS = 'INTERRUPT'">TRUE</xsl:if>
<xsl:if test="not(@SIGIS = 'INTERRUPT')">FALSE</xsl:if>
</xsl:variable>
<SET ID="{@NAME}" CLASS="PORT">
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="Instance" NAME="INSTANCE" VALUE="External Ports"/>
<VARIABLE VIEWTYPE="TEXTBOX" VIEWDISP="Port Name" NAME="NAME" VALUE="{@NAME}"/>
<xsl:choose>
<xsl:when test="@LEFT and @RIGHT">
<xsl:variable name="vecformula_txt_">[<xsl:value-of select="@LEFT"/>:<xsl:value-of select="@RIGHT"/>]</xsl:variable>
<VARIABLE VIEWTYPE="TEXTBOX" VIEWDISP="Range" NAME="VECFORMULA" VALUE="{$vecformula_txt_}"/>
</xsl:when>
<xsl:when test="@MSB and @LSB">
<xsl:variable name="vecformula_txt_">[<xsl:value-of select="@MSB"/>:<xsl:value-of select="@LSB"/>]</xsl:variable>
<VARIABLE VIEWTYPE="TEXTBOX" VIEWDISP="Range" NAME="VECFORMULA" VALUE="{$vecformula_txt_}"/>
</xsl:when>
<xsl:when test="(not(@MSB) and not(@LSB) and not(@SIGIS = 'CLK') and not(@SIGIS = 'CLOCK') and not(@SIGIS = 'DCMCLK') and not(@SIGIS = 'RST') and not(@SIGIS = 'RESET'))">
<VARIABLE VIEWTYPE="TEXTBOX" VIEWDISP="Range" NAME="VECFORMULA" VALUE=""/>
</xsl:when>
</xsl:choose>
<VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Net" NAME="SIGNAME" VALUE="{@SIGNAME}" IS_EDITABLE="TRUE"/>
<VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Direction" NAME="DIR" VALUE="{@DIR}"/>
<xsl:if test="(@SIGIS)">
<VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Class" NAME="SIGIS" VALUE="{@SIGIS}"/>
</xsl:if>
<xsl:if test="not(@SIGIS)">
<VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Class" NAME="SIGIS" VALUE="NONE"/>
</xsl:if>
<xsl:if test="(@SIGIS = 'RST' or @SIGIS = 'RESET')">
<VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Reset Polarity" NAME="RSTPOLARITY" VALUE="{@RSTPOLARITY}"/>
</xsl:if>
<xsl:if test="((@SIGIS = 'CLK') or (@SIGIS = 'CLOCK') or (@SIGIS = 'DCMCLK'))">
<VARIABLE VIEWTYPE="TEXTBOX" VIEWDISP="Frequency(Hz)" NAME="CLKFREQUENCY" VALUE="{@CLKFREQUENCY}"/>
</xsl:if>
<!-- SENSITIVITY Settings on Interrupt ports -->
<xsl:choose>
<xsl:when test="((@SIGNAME = '__NOC__') and ($ext_is_interrupt_ = 'TRUE') and not(@SENSITIVITY))">
<VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Sensitivity" NAME="SENSITIVITY" VALUE=""/>
</xsl:when>
<xsl:when test="((@SIGNAME = '__NOC__') and ($ext_is_interrupt_ = 'TRUE') and (@SENSITIVITY))">
<VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Sensitivity" NAME="SENSITIVITY" VALUE="{@SENSITIVITY}"/>
</xsl:when>
<xsl:when test="((@SIGNAME = '__DEF__') and ($ext_is_interrupt_ = 'TRUE') and not(@SENSITIVITY))">
<VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Sensitivity" NAME="SENSITIVITY" VALUE=""/>
</xsl:when>
<xsl:when test="((@SIGNAME = '__DEF__') and ($ext_is_interrupt_ = 'TRUE') and (@SENSITIVITY))">
<VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Sensitivity" NAME="SENSITIVITY" VALUE="{@SENSITIVITY}"/>
</xsl:when>
<xsl:when test="(not(@SIGNAME = '__DEF__') and not(@SIGNAME = '__NOC__') and ($ext_is_interrupt_ = 'TRUE') and not(@SENSITIVITY))">
<VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Sensitivity" NAME="SENSITIVITY" VALUE=""/>
</xsl:when>
<xsl:when test="(not(@SIGNAME = '__DEF__') and not(@SIGNAME = '__NOC__') and ($ext_is_interrupt_ = 'TRUE') and (@SENSITIVITY))">
<VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Sensitivity" NAME="SENSITIVITY" VALUE="{@SENSITIVITY}"/>
</xsl:when>
</xsl:choose>
</SET>
</xsl:for-each>
</xsl:for-each>
</xsl:template>
<xsl:template name="WRITE_VIEW_PORT_FLAT_SET">
<xsl:param name="iModRef" select="'__NONE__'"/>
<xsl:variable name="m_inst_" select="$iModRef/@INSTANCE"/>
<xsl:variable name="m_class_" select="$iModRef/@MODCLASS"/>
<xsl:variable name="m_type_" select="$iModRef/@MODTYPE"/>
<xsl:variable name="m_type_lc_" select="translate($m_type_,&UPPER2LOWER;)"/>
<xsl:variable name="m_version_" select="$iModRef/@HWVERSION"/>
<xsl:variable name="m_licinfo_" select="$iModRef/LICENSEINFO"/>
<xsl:variable name="is_axi_interconnect_">
<xsl:choose>
<xsl:when test="$m_type_ = 'axi_interconnect'">TRUE</xsl:when>
<xsl:when test="$m_type_lc_ = 'axi_interconnect'">TRUE</xsl:when>
<xsl:otherwise>FALSE</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:for-each select="$G_SYS_MODS"> <!-- To put things in the right scope for the keys below -->
<xsl:variable name="m_bifs_all_" select="key('G_MAP_ALL_BIFS', $m_inst_)"/>
<xsl:variable name="m_ports_all_" select="key('G_MAP_ALL_PORTS',$m_inst_)"/>
<xsl:if test="$G_DEBUG = 'TRUE'">
<xsl:message><xsl:value-of select="$m_inst_"/> has <xsl:value-of select="count($m_ports_all_)"/> valid ports </xsl:message>
</xsl:if>
<xsl:for-each select="$m_ports_all_">
<xsl:sort data-type="number" select="@MPD_INDEX" order="ascending"/>
<!-- <xsl:message>PORTNM : <xsl:value-of select="@NAME"/></xsl:message> -->
<xsl:variable name="p_nm_uc_" select="translate(@NAME,&LOWER2UPPER;)"/>
<xsl:variable name="p_bif_" select="@BUS"/>
<xsl:variable name="port_is_valid_">
<xsl:choose>
<xsl:when test="@IS_VALID = 'FALSE'">FALSE</xsl:when>
<xsl:when test="(($is_axi_interconnect_ = 'TRUE') and ($p_nm_uc_= 'INTERCONNECT_ACLK'))">TRUE</xsl:when>
<xsl:when test="not(@BUS) or (@BUS and key('G_MAP_ALL_BIFS', $m_inst_)[(@NAME = $p_bif_)])">TRUE</xsl:when>
<xsl:otherwise>FALSE</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<xsl:if test="$port_is_valid_ = 'TRUE'">
<!--
<xsl:message>PORT <xsl:value-of select="@BUS"/>.<xsl:value-of select="@NAME"/></xsl:message>
-->
<SET ID="{@NAME}" CLASS="PORT">
<!--
CR452579
Can only modify INSTANCE name in Hierarchal view.
-->
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="Instance" NAME="INSTANCE" VALUE="{$m_inst_}"/>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Type" NAME="MODTYPE" VALUE="{$m_type_}" VIEWICON="{$m_licinfo_/@ICON_NAME}"/>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="IP Version" NAME="HWVERSION" VALUE="{$m_version_}"/>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="Port Name" NAME="NAME" VALUE="{@NAME}"/>
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="Direction" NAME="DIR" VALUE="{@DIR}"/>
<xsl:if test="@SIGIS">
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="Class" NAME="SIGIS" VALUE="{@SIGIS}"/>
</xsl:if>
<xsl:if test="@VECFORMULA">
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="Range" NAME="VECFORMULA" VALUE="{@VECFORMULA}"/>
</xsl:if>
<xsl:if test="@SENSITIVITY">
<VARIABLE VIEWTYPE="STATIC" VIEWDISP="Sensitivity" NAME="SENSITIVITY" VALUE="{@SENSITIVITY}"/>
</xsl:if>
<xsl:variable name="is_interrupt">
<xsl:if test="@SIGIS = 'INTERRUPT'">TRUE</xsl:if>
<xsl:if test="not(@SIGIS = 'INTERRUPT')">FALSE</xsl:if>
</xsl:variable>
<xsl:variable name="is_input">
<xsl:choose>
<xsl:when test="(@DIR= 'I')">TRUE</xsl:when>
<xsl:when test="(@DIR= 'IN')">TRUE</xsl:when>
<xsl:when test="(@DIR= 'INPUT')">TRUE</xsl:when>
<xsl:otherwise>FALSE</xsl:otherwise>
</xsl:choose>
</xsl:variable>
<!-- VECFORMULA Settings if Interrupt settings -->
<xsl:choose>
<xsl:when test="((@SIGNAME = '__NOC__') and ($is_interrupt = 'TRUE') and ($is_input = 'TRUE') and not(@VECFORMULA))">
<VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Net" NAME="SIGNAME" VALUE="No Connection" IS_INTERRUPT="{$is_interrupt}"/>
</xsl:when>
<xsl:when test="((@SIGNAME = '__NOC__') and ($is_interrupt = 'TRUE') and ($is_input = 'TRUE') and (@VECFORMULA))">
<VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Net" NAME="SIGNAME" VALUE="No Connection" IS_INTERRUPT="{$is_interrupt}" IS_RANGE="TRUE"/>
</xsl:when>
<xsl:when test="@SIGNAME = '__NOC__'">
<VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Net" NAME="SIGNAME" VALUE="No Connection" IS_EDITABLE="TRUE"/>
</xsl:when>
<xsl:when test="((@SIGNAME = '__DEF__') and ($is_interrupt = 'TRUE') and ($is_input = 'TRUE') and not(@VECFORMULA))">
<VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Net" NAME="SIGNAME" VALUE="Default Connection" IS_INTERRUPT="{$is_interrupt}"/>
</xsl:when>
<xsl:when test="((@SIGNAME = '__DEF__') and ($is_interrupt = 'TRUE') and ($is_input = 'TRUE') and (@VECFORMULA))">
<VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Net" NAME="SIGNAME" VALUE="Default Connection" IS_INTERRUPT="{$is_interrupt}" IS_RANGE="TRUE"/>
</xsl:when>
<xsl:when test="@SIGNAME = '__DEF__'">
<VARIABLE VIEWTYPE="DROPDOWN" VIEWDISP="Net" NAME="SIGNAME" VALUE="Default Connection"/>
</xsl:when>
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<xsl:if test="not($iSigIs = 'INTERRUPT')">FALSE</xsl:if>
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<xsl:choose>
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projnav/xps/__xps/gensav_cmd.xml 0 → 100644
View file @ a64d58e7
<SAV MODE="TREE" VIEW="ADDRESS"/>
\ No newline at end of file
projnav/xps/__xps/ise/system.xreport 0 → 100644
View file @ a64d58e7
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2012-03-15T15:58:06</DateModified>
<ModuleName>system</ModuleName>
<SummaryTimeStamp>2012-03-15T15:58:05</SummaryTimeStamp>
<SavedFilePath>C:/Users/mjlyons/workspace/vSPI/projnav/xps/__xps/ise/system.xreport</SavedFilePath>
<FilterFile>filter.filter</FilterFile>
<SavedFilterFilePath>C:/Users/mjlyons/workspace/vSPI/projnav/xps/__xps/ise</SavedFilterFilePath>
<DateInitialized>2012-02-28T10:59:37</DateInitialized>
<EnableMessageFiltering>false</EnableMessageFiltering>
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<viewgroup label="Design Overview" >
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<toc-item title="Design Overview" target="Design Overview" />
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<toc-item title="Performance Summary" target="Performance Summary" />
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<toc-item title="Detailed Reports" target="Detailed Reports" />
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<toc-item title="Synthesis Options Summary" target=" Synthesis Options Summary " />
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<toc-item title="HDL Analysis" target=" HDL Analysis " />
<toc-item title="HDL Parsing" target=" HDL Parsing " />
<toc-item title="HDL Elaboration" target=" HDL Elaboration " />
<toc-item title="HDL Synthesis" target=" HDL Synthesis " />
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<toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
<toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
<toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" />
<toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" />
<toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" />
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<toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" />
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<toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" />
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<toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
<toc-item title="Final Summary" target="DRC detected" />
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<toc-item title="Component" target="Component " />
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<toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
</view>
<view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Secondary_Report" file="implementation\netgen/fit/system_timesim.nlf" label="Post-Fit Simulation Model Report" />
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="implementation\usage_statistics_webtalk.html" label="WebTalk Report" />
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="implementation\webtalk.log" label="WebTalk Log File" />
</viewgroup>
</body>
</report-views>
projnav/xps/__xps/ise/xmsgprops.lst 0 → 100644
View file @ a64d58e7
MessageCaptureEnabled: TRUE
MessageFilteringEnabled: FALSE
IncrementalMessagingEnabled: TRUE
projnav/xps/__xps/platgen.opt 0 → 100644
View file @ a64d58e7
-p xc6slx45csg324-2 -lang vhdl$(PROJECT_SEARCHPATHOPT) $(GLOBAL_SEARCHPATHOPT) -msg __xps/ise/xmsgprops.lst
projnav/xps/__xps/simgen.opt 0 → 100644
View file @ a64d58e7
-p spartan6 -lang vhdl$(PROJECT_SEARCHPATHOPT) $(GLOBAL_SEARCHPATHOPT) -msg __xps/ise/xmsgprops.lst -s isim
projnav/xps/__xps/system.xml 0 → 100644
View file @ a64d58e7
This source diff could not be displayed because it is too large. You can view the blob instead.
projnav/xps/__xps/xplorer.opt 0 → 100644
View file @ a64d58e7
-device xc6slx45csg324-2 data\system.ucf 7 0
projnav/xps/__xps/xpsxflow.opt 0 → 100644
View file @ a64d58e7
-device xc6slx45csg324-2 data\system.ucf 0
projnav/xps/clock_generator_0.log 0 → 100644
View file @ a64d58e7
------------------------------------------------------------------------------
-- clock_generator_0.log
------------------------------------------------------------------------------
Clock generation result : PASSED
------------------------------------------------------------------------------
-- end of clock_generator_0.log
------------------------------------------------------------------------------
projnav/xps/data/system.ucf 0 → 100644
View file @ a64d58e7
# Atlys
Net fpga_0_DIP_Switches_8Bits_GPIO_IO_I_pin<0> LOC=E4 | IOSTANDARD=LVCMOS18;
Net fpga_0_DIP_Switches_8Bits_GPIO_IO_I_pin<1> LOC=T5 | IOSTANDARD=LVCMOS33;
Net fpga_0_DIP_Switches_8Bits_GPIO_IO_I_pin<2> LOC=R5 | IOSTANDARD=LVCMOS33;
Net fpga_0_DIP_Switches_8Bits_GPIO_IO_I_pin<3> LOC=P12 | IOSTANDARD=LVCMOS33;
Net fpga_0_DIP_Switches_8Bits_GPIO_IO_I_pin<4> LOC=P15 | IOSTANDARD=LVCMOS33;
Net fpga_0_DIP_Switches_8Bits_GPIO_IO_I_pin<5> LOC=C14 | IOSTANDARD=LVCMOS33;
Net fpga_0_DIP_Switches_8Bits_GPIO_IO_I_pin<6> LOC=D14 | IOSTANDARD=LVCMOS33;
Net fpga_0_DIP_Switches_8Bits_GPIO_IO_I_pin<7> LOC=A10 | IOSTANDARD=LVCMOS33;
Net fpga_0_LEDs_8Bits_GPIO_IO_O_pin<0> LOC=N12 | IOSTANDARD=LVCMOS33;
Net fpga_0_LEDs_8Bits_GPIO_IO_O_pin<1> LOC=P16 | IOSTANDARD=LVCMOS33;
Net fpga_0_LEDs_8Bits_GPIO_IO_O_pin<2> LOC=D4 | IOSTANDARD=LVCMOS33;
Net fpga_0_LEDs_8Bits_GPIO_IO_O_pin<3> LOC=M13 | IOSTANDARD=LVCMOS33;
Net fpga_0_LEDs_8Bits_GPIO_IO_O_pin<4> LOC=L14 | IOSTANDARD=LVCMOS33;
Net fpga_0_LEDs_8Bits_GPIO_IO_O_pin<5> LOC=N14 | IOSTANDARD=LVCMOS33;
Net fpga_0_LEDs_8Bits_GPIO_IO_O_pin<6> LOC=M14 | IOSTANDARD=LVCMOS33;
Net fpga_0_LEDs_8Bits_GPIO_IO_O_pin<7> LOC=U18 | IOSTANDARD=LVCMOS33;
Net fpga_0_Push_Buttons_5Bits_GPIO_IO_I_pin<0> LOC=N4 | IOSTANDARD=LVCMOS18;
Net fpga_0_Push_Buttons_5Bits_GPIO_IO_I_pin<1> LOC=P4 | IOSTANDARD=LVCMOS18;
Net fpga_0_Push_Buttons_5Bits_GPIO_IO_I_pin<2> LOC=P3 | IOSTANDARD=LVCMOS18;
Net fpga_0_Push_Buttons_5Bits_GPIO_IO_I_pin<3> LOC=F6 | IOSTANDARD=LVCMOS18;
Net fpga_0_Push_Buttons_5Bits_GPIO_IO_I_pin<4> LOC=F5 | IOSTANDARD=LVCMOS18;
Net fpga_0_clk_1_sys_clk_pin TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100000 kHz;
Net fpga_0_clk_1_sys_clk_pin LOC=L15 | IOSTANDARD=LVCMOS33;
Net fpga_0_rst_1_sys_rst_pin TIG;
Net fpga_0_rst_1_sys_rst_pin LOC=T15 | IOSTANDARD=LVCMOS33;
# SPI
NET "spiifc_0_SPI_CLK_pin" LOC = R10 | IOSTANDARD = LVCMOS33;
NET "spiifc_0_SPI_MISO_pin" LOC = U16 | IOSTANDARD = LVCMOS33;
NET "spiifc_0_SPI_MOSI_pin" LOC = U15 | IOSTANDARD = LVCMOS33;
NET "spiifc_0_SPI_SS_pin" LOC = M11 | IOSTANDARD = LVCMOS33;
projnav/xps/drivers/spiifc_v1_00_a/data/spiifc_v2_1_0.mdd 0 → 100644
View file @ a64d58e7
##############################################################################
## Filename: C:\Users\mjlyons\workspace\vSPI\projnav\xps/drivers/spiifc_v1_00_a/data/spiifc_v2_1_0.mdd
## Description: Microprocessor Driver Definition
## Date: Tue Feb 28 11:11:28 2012 (by Create and Import Peripheral Wizard)
##############################################################################
OPTION psf_version = 2.1.0;
BEGIN DRIVER spiifc
OPTION supported_peripherals = (spiifc);
OPTION depends = (common_v1_00_a);
OPTION copyfiles = all;
BEGIN ARRAY interrupt_handler
PROPERTY desc = "Interrupt Handler Information";
PROPERTY size = 1, permit = none;
PARAM name = int_handler, default = SPIIFC_Intr_DefaultHandler, desc = "Name of Interrupt Handler", type = string;
PARAM name = int_port, default = IP2INTC_Irpt, desc = "Interrupt pin associated with the interrupt handler", permit = none;
END ARRAY
END DRIVER
projnav/xps/drivers/spiifc_v1_00_a/data/spiifc_v2_1_0.tcl 0 → 100644
View file @ a64d58e7
##############################################################################
## Filename: C:\Users\mjlyons\workspace\vSPI\projnav\xps/drivers/spiifc_v1_00_a/data/spiifc_v2_1_0.tcl
## Description: Microprocess Driver Command (tcl)
## Date: Tue Feb 28 11:11:28 2012 (by Create and Import Peripheral Wizard)
##############################################################################
#uses "xillib.tcl"
proc generate {drv_handle} {
xdefine_include_file $drv_handle "xparameters.h" "spiifc" "NUM_INSTANCES" "DEVICE_ID" "C_BASEADDR" "C_HIGHADDR" "C_MEM0_BASEADDR" "C_MEM0_HIGHADDR" "C_MEM1_BASEADDR" "C_MEM1_HIGHADDR"
}
projnav/xps/drivers/spiifc_v1_00_a/src/Makefile 0 → 100644
View file @ a64d58e7
##############################################################################
## Filename: C:\Users\mjlyons\workspace\vSPI\projnav\xps/drivers/spiifc_v1_00_a/src/Makefile
## Description: Microprocessor Driver Makefile
## Date: Tue Feb 28 11:11:28 2012 (by Create and Import Peripheral Wizard)
##############################################################################
COMPILER=
ARCHIVER=
CP=cp
COMPILER_FLAGS=
EXTRA_COMPILER_FLAGS=
LIB=libxil.a
RELEASEDIR=../../../lib
INCLUDEDIR=../../../include
INCLUDES=-I./. -I${INCLUDEDIR}
INCLUDEFILES=*.h
LIBSOURCES=*.c
OUTS = *.o
libs:
echo "Compiling spiifc"
$(COMPILER) $(COMPILER_FLAGS) $(EXTRA_COMPILER_FLAGS) $(INCLUDES) $(LIBSOURCES)
$(ARCHIVER) -r ${RELEASEDIR}/${LIB} ${OUTS}
make clean
include:
${CP} $(INCLUDEFILES) $(INCLUDEDIR)
clean:
rm -rf ${OUTS}
projnav/xps/drivers/spiifc_v1_00_a/src/spiifc.c 0 → 100644
View file @ a64d58e7
/*****************************************************************************
* Filename: C:\Users\mjlyons\workspace\vSPI\projnav\xps/drivers/spiifc_v1_00_a/src/spiifc.c
* Version: 1.00.a
* Description: spiifc Driver Source File
* Date: Tue Feb 28 11:11:28 2012 (by Create and Import Peripheral Wizard)
*****************************************************************************/
/***************************** Include Files *******************************/
#include "spiifc.h"
/************************** Function Definitions ***************************/
/**
*
* Enable all possible interrupts from SPIIFC device.
*
* @param baseaddr_p is the base address of the SPIIFC device.
*
* @return None.
*
* @note None.
*
*/
void SPIIFC_EnableInterrupt(void * baseaddr_p)
{
Xuint32 baseaddr;
baseaddr = (Xuint32) baseaddr_p;
/*
* Enable all interrupt source from user logic.
*/
SPIIFC_mWriteReg(baseaddr, SPIIFC_INTR_IPIER_OFFSET, 0x00000001);
/*
* Set global interrupt enable.
*/
SPIIFC_mWriteReg(baseaddr, SPIIFC_INTR_DGIER_OFFSET, INTR_GIE_MASK);
}
/**
*
* Example interrupt controller handler for SPIIFC device.
* This is to show example of how to toggle write back ISR to clear interrupts.
*
* @param baseaddr_p is the base address of the SPIIFC device.
*
* @return None.
*
* @note None.
*
*/
void SPIIFC_Intr_DefaultHandler(void * baseaddr_p)
{
Xuint32 baseaddr;
Xuint32 IntrStatus;
Xuint32 IpStatus;
baseaddr = (Xuint32) baseaddr_p;
{
xil_printf("User logic interrupt! \n\r");
IpStatus = SPIIFC_mReadReg(baseaddr, SPIIFC_INTR_IPISR_OFFSET);
SPIIFC_mWriteReg(baseaddr, SPIIFC_INTR_IPISR_OFFSET, IpStatus);
}
}
projnav/xps/drivers/spiifc_v1_00_a/src/spiifc.h 0 → 100644
View file @ a64d58e7
/*****************************************************************************
* Filename: C:\Users\mjlyons\workspace\vSPI\projnav\xps/drivers/spiifc_v1_00_a/src/spiifc.h
* Version: 1.00.a
* Description: spiifc Driver Header File
* Date: Tue Feb 28 11:11:28 2012 (by Create and Import Peripheral Wizard)
*****************************************************************************/
#ifndef SPIIFC_H
#define SPIIFC_H
/***************************** Include Files *******************************/
#include "xbasic_types.h"
#include "xstatus.h"
#include "xil_io.h"
/************************** Constant Definitions ***************************/
/**
* User Logic Slave Space Offsets
* -- SLV_REG0 : user logic slave module register 0
* -- SLV_REG1 : user logic slave module register 1
* -- SLV_REG2 : user logic slave module register 2
* -- SLV_REG3 : user logic slave module register 3
* -- SLV_REG4 : user logic slave module register 4
* -- SLV_REG5 : user logic slave module register 5
* -- SLV_REG6 : user logic slave module register 6
* -- SLV_REG7 : user logic slave module register 7
* -- SLV_REG8 : user logic slave module register 8
* -- SLV_REG9 : user logic slave module register 9
* -- SLV_REG10 : user logic slave module register 10
* -- SLV_REG11 : user logic slave module register 11
* -- SLV_REG12 : user logic slave module register 12
* -- SLV_REG13 : user logic slave module register 13
* -- SLV_REG14 : user logic slave module register 14
* -- SLV_REG15 : user logic slave module register 15
*/
#define SPIIFC_USER_SLV_SPACE_OFFSET (0x00000000)
#define SPIIFC_SLV_REG0_OFFSET (SPIIFC_USER_SLV_SPACE_OFFSET + 0x00000000)
#define SPIIFC_SLV_REG1_OFFSET (SPIIFC_USER_SLV_SPACE_OFFSET + 0x00000004)
#define SPIIFC_SLV_REG2_OFFSET (SPIIFC_USER_SLV_SPACE_OFFSET + 0x00000008)
#define SPIIFC_SLV_REG3_OFFSET (SPIIFC_USER_SLV_SPACE_OFFSET + 0x0000000C)
#define SPIIFC_SLV_REG4_OFFSET (SPIIFC_USER_SLV_SPACE_OFFSET + 0x00000010)
#define SPIIFC_SLV_REG5_OFFSET (SPIIFC_USER_SLV_SPACE_OFFSET + 0x00000014)
#define SPIIFC_SLV_REG6_OFFSET (SPIIFC_USER_SLV_SPACE_OFFSET + 0x00000018)
#define SPIIFC_SLV_REG7_OFFSET (SPIIFC_USER_SLV_SPACE_OFFSET + 0x0000001C)
#define SPIIFC_SLV_REG8_OFFSET (SPIIFC_USER_SLV_SPACE_OFFSET + 0x00000020)
#define SPIIFC_SLV_REG9_OFFSET (SPIIFC_USER_SLV_SPACE_OFFSET + 0x00000024)
#define SPIIFC_SLV_REG10_OFFSET (SPIIFC_USER_SLV_SPACE_OFFSET + 0x00000028)
#define SPIIFC_SLV_REG11_OFFSET (SPIIFC_USER_SLV_SPACE_OFFSET + 0x0000002C)
#define SPIIFC_SLV_REG12_OFFSET (SPIIFC_USER_SLV_SPACE_OFFSET + 0x00000030)
#define SPIIFC_SLV_REG13_OFFSET (SPIIFC_USER_SLV_SPACE_OFFSET + 0x00000034)
#define SPIIFC_SLV_REG14_OFFSET (SPIIFC_USER_SLV_SPACE_OFFSET + 0x00000038)
#define SPIIFC_SLV_REG15_OFFSET (SPIIFC_USER_SLV_SPACE_OFFSET + 0x0000003C)
/**
* Interrupt Controller Space Offsets
* -- INTR_DGIER : device (peripheral) global interrupt enable register
* -- INTR_ISR : ip (user logic) interrupt status register
* -- INTR_IER : ip (user logic) interrupt enable register
*/
#define SPIIFC_INTR_CNTRL_SPACE_OFFSET (0x00000100)
#define SPIIFC_INTR_DGIER_OFFSET (SPIIFC_INTR_CNTRL_SPACE_OFFSET + 0x0000001C)
#define SPIIFC_INTR_IPISR_OFFSET (SPIIFC_INTR_CNTRL_SPACE_OFFSET + 0x00000020)
#define SPIIFC_INTR_IPIER_OFFSET (SPIIFC_INTR_CNTRL_SPACE_OFFSET + 0x00000028)
/**
* Interrupt Controller Masks
* -- INTR_TERR_MASK : transaction error
* -- INTR_DPTO_MASK : data phase time-out
* -- INTR_IPIR_MASK : ip interrupt requeset
* -- INTR_RFDL_MASK : read packet fifo deadlock interrupt request
* -- INTR_WFDL_MASK : write packet fifo deadlock interrupt request
* -- INTR_IID_MASK : interrupt id
* -- INTR_GIE_MASK : global interrupt enable
* -- INTR_NOPEND : the DIPR has no pending interrupts
*/
#define INTR_TERR_MASK (0x00000001UL)
#define INTR_DPTO_MASK (0x00000002UL)
#define INTR_IPIR_MASK (0x00000004UL)
#define INTR_RFDL_MASK (0x00000020UL)
#define INTR_WFDL_MASK (0x00000040UL)
#define INTR_IID_MASK (0x000000FFUL)
#define INTR_GIE_MASK (0x80000000UL)
#define INTR_NOPEND (0x80)
/**************************** Type Definitions *****************************/
/***************** Macros (Inline Functions) Definitions *******************/
/**
*
* Write a value to a SPIIFC register. A 32 bit write is performed.
* If the component is implemented in a smaller width, only the least
* significant data is written.
*
* @param BaseAddress is the base address of the SPIIFC device.
* @param RegOffset is the register offset from the base to write to.
* @param Data is the data written to the register.
*
* @return None.
*
* @note
* C-style signature:
* void SPIIFC_mWriteReg(Xuint32 BaseAddress, unsigned RegOffset, Xuint32 Data)
*
*/
#define SPIIFC_mWriteReg(BaseAddress, RegOffset, Data) \
Xil_Out32((BaseAddress) + (RegOffset), (Xuint32)(Data))
/**
*
* Read a value from a SPIIFC register. A 32 bit read is performed.
* If the component is implemented in a smaller width, only the least
* significant data is read from the register. The most significant data
* will be read as 0.
*
* @param BaseAddress is the base address of the SPIIFC device.
* @param RegOffset is the register offset from the base to write to.
*
* @return Data is the data from the register.
*
* @note
* C-style signature:
* Xuint32 SPIIFC_mReadReg(Xuint32 BaseAddress, unsigned RegOffset)
*
*/
#define SPIIFC_mReadReg(BaseAddress, RegOffset) \
Xil_In32((BaseAddress) + (RegOffset))
/**
*
* Write/Read 32 bit value to/from SPIIFC user logic slave registers.
*
* @param BaseAddress is the base address of the SPIIFC device.
* @param RegOffset is the offset from the slave register to write to or read from.
* @param Value is the data written to the register.
*
* @return Data is the data from the user logic slave register.
*
* @note
* C-style signature:
* void SPIIFC_mWriteSlaveRegn(Xuint32 BaseAddress, unsigned RegOffset, Xuint32 Value)
* Xuint32 SPIIFC_mReadSlaveRegn(Xuint32 BaseAddress, unsigned RegOffset)
*
*/
#define SPIIFC_mWriteSlaveReg0(BaseAddress, RegOffset, Value) \
Xil_Out32((BaseAddress) + (SPIIFC_SLV_REG0_OFFSET) + (RegOffset), (Xuint32)(Value))
#define SPIIFC_mWriteSlaveReg1(BaseAddress, RegOffset, Value) \
Xil_Out32((BaseAddress) + (SPIIFC_SLV_REG1_OFFSET) + (RegOffset), (Xuint32)(Value))
#define SPIIFC_mWriteSlaveReg2(BaseAddress, RegOffset, Value) \
Xil_Out32((BaseAddress) + (SPIIFC_SLV_REG2_OFFSET) + (RegOffset), (Xuint32)(Value))
#define SPIIFC_mWriteSlaveReg3(BaseAddress, RegOffset, Value) \
Xil_Out32((BaseAddress) + (SPIIFC_SLV_REG3_OFFSET) + (RegOffset), (Xuint32)(Value))
#define SPIIFC_mWriteSlaveReg4(BaseAddress, RegOffset, Value) \
Xil_Out32((BaseAddress) + (SPIIFC_SLV_REG4_OFFSET) + (RegOffset), (Xuint32)(Value))
#define SPIIFC_mWriteSlaveReg5(BaseAddress, RegOffset, Value) \
Xil_Out32((BaseAddress) + (SPIIFC_SLV_REG5_OFFSET) + (RegOffset), (Xuint32)(Value))
#define SPIIFC_mWriteSlaveReg6(BaseAddress, RegOffset, Value) \
Xil_Out32((BaseAddress) + (SPIIFC_SLV_REG6_OFFSET) + (RegOffset), (Xuint32)(Value))
#define SPIIFC_mWriteSlaveReg7(BaseAddress, RegOffset, Value) \
Xil_Out32((BaseAddress) + (SPIIFC_SLV_REG7_OFFSET) + (RegOffset), (Xuint32)(Value))
#define SPIIFC_mWriteSlaveReg8(BaseAddress, RegOffset, Value) \
Xil_Out32((BaseAddress) + (SPIIFC_SLV_REG8_OFFSET) + (RegOffset), (Xuint32)(Value))
#define SPIIFC_mWriteSlaveReg9(BaseAddress, RegOffset, Value) \
Xil_Out32((BaseAddress) + (SPIIFC_SLV_REG9_OFFSET) + (RegOffset), (Xuint32)(Value))
#define SPIIFC_mWriteSlaveReg10(BaseAddress, RegOffset, Value) \
Xil_Out32((BaseAddress) + (SPIIFC_SLV_REG10_OFFSET) + (RegOffset), (Xuint32)(Value))
#define SPIIFC_mWriteSlaveReg11(BaseAddress, RegOffset, Value) \
Xil_Out32((BaseAddress) + (SPIIFC_SLV_REG11_OFFSET) + (RegOffset), (Xuint32)(Value))
#define SPIIFC_mWriteSlaveReg12(BaseAddress, RegOffset, Value) \
Xil_Out32((BaseAddress) + (SPIIFC_SLV_REG12_OFFSET) + (RegOffset), (Xuint32)(Value))
#define SPIIFC_mWriteSlaveReg13(BaseAddress, RegOffset, Value) \
Xil_Out32((BaseAddress) + (SPIIFC_SLV_REG13_OFFSET) + (RegOffset), (Xuint32)(Value))
#define SPIIFC_mWriteSlaveReg14(BaseAddress, RegOffset, Value) \
Xil_Out32((BaseAddress) + (SPIIFC_SLV_REG14_OFFSET) + (RegOffset), (Xuint32)(Value))
#define SPIIFC_mWriteSlaveReg15(BaseAddress, RegOffset, Value) \
Xil_Out32((BaseAddress) + (SPIIFC_SLV_REG15_OFFSET) + (RegOffset), (Xuint32)(Value))
#define SPIIFC_mReadSlaveReg0(BaseAddress, RegOffset) \
Xil_In32((BaseAddress) + (SPIIFC_SLV_REG0_OFFSET) + (RegOffset))
#define SPIIFC_mReadSlaveReg1(BaseAddress, RegOffset) \
Xil_In32((BaseAddress) + (SPIIFC_SLV_REG1_OFFSET) + (RegOffset))
#define SPIIFC_mReadSlaveReg2(BaseAddress, RegOffset) \
Xil_In32((BaseAddress) + (SPIIFC_SLV_REG2_OFFSET) + (RegOffset))
#define SPIIFC_mReadSlaveReg3(BaseAddress, RegOffset) \
Xil_In32((BaseAddress) + (SPIIFC_SLV_REG3_OFFSET) + (RegOffset))
#define SPIIFC_mReadSlaveReg4(BaseAddress, RegOffset) \
Xil_In32((BaseAddress) + (SPIIFC_SLV_REG4_OFFSET) + (RegOffset))
#define SPIIFC_mReadSlaveReg5(BaseAddress, RegOffset) \
Xil_In32((BaseAddress) + (SPIIFC_SLV_REG5_OFFSET) + (RegOffset))
#define SPIIFC_mReadSlaveReg6(BaseAddress, RegOffset) \
Xil_In32((BaseAddress) + (SPIIFC_SLV_REG6_OFFSET) + (RegOffset))
#define SPIIFC_mReadSlaveReg7(BaseAddress, RegOffset) \
Xil_In32((BaseAddress) + (SPIIFC_SLV_REG7_OFFSET) + (RegOffset))
#define SPIIFC_mReadSlaveReg8(BaseAddress, RegOffset) \
Xil_In32((BaseAddress) + (SPIIFC_SLV_REG8_OFFSET) + (RegOffset))
#define SPIIFC_mReadSlaveReg9(BaseAddress, RegOffset) \
Xil_In32((BaseAddress) + (SPIIFC_SLV_REG9_OFFSET) + (RegOffset))
#define SPIIFC_mReadSlaveReg10(BaseAddress, RegOffset) \
Xil_In32((BaseAddress) + (SPIIFC_SLV_REG10_OFFSET) + (RegOffset))
#define SPIIFC_mReadSlaveReg11(BaseAddress, RegOffset) \
Xil_In32((BaseAddress) + (SPIIFC_SLV_REG11_OFFSET) + (RegOffset))
#define SPIIFC_mReadSlaveReg12(BaseAddress, RegOffset) \
Xil_In32((BaseAddress) + (SPIIFC_SLV_REG12_OFFSET) + (RegOffset))
#define SPIIFC_mReadSlaveReg13(BaseAddress, RegOffset) \
Xil_In32((BaseAddress) + (SPIIFC_SLV_REG13_OFFSET) + (RegOffset))
#define SPIIFC_mReadSlaveReg14(BaseAddress, RegOffset) \
Xil_In32((BaseAddress) + (SPIIFC_SLV_REG14_OFFSET) + (RegOffset))
#define SPIIFC_mReadSlaveReg15(BaseAddress, RegOffset) \
Xil_In32((BaseAddress) + (SPIIFC_SLV_REG15_OFFSET) + (RegOffset))
/**
*
* Write/Read 32 bit value to/from SPIIFC user logic memory (BRAM).
*
* @param Address is the memory address of the SPIIFC device.
* @param Data is the value written to user logic memory.
*
* @return The data from the user logic memory.
*
* @note
* C-style signature:
* void SPIIFC_mWriteMemory(Xuint32 Address, Xuint32 Data)
* Xuint32 SPIIFC_mReadMemory(Xuint32 Address)
*
*/
#define SPIIFC_mWriteMemory(Address, Data) \
Xil_Out32(Address, (Xuint32)(Data))
#define SPIIFC_mReadMemory(Address) \
Xil_In32(Address)
/************************** Function Prototypes ****************************/
/**
*
* Enable all possible interrupts from SPIIFC device.
*
* @param baseaddr_p is the base address of the SPIIFC device.
*
* @return None.
*
* @note None.
*
*/
void SPIIFC_EnableInterrupt(void * baseaddr_p);
/**
*
* Example interrupt controller handler.
*
* @param baseaddr_p is the base address of the SPIIFC device.
*
* @return None.
*
* @note None.
*
*/
void SPIIFC_Intr_DefaultHandler(void * baseaddr_p);
/**
*
* Run a self-test on the driver/device. Note this may be a destructive test if
* resets of the device are performed.
*
* If the hardware system is not built correctly, this function may never
* return to the caller.
*
* @param baseaddr_p is the base address of the SPIIFC instance to be worked on.
*
* @return
*
* - XST_SUCCESS if all self-test code passed
* - XST_FAILURE if any self-test code failed
*
* @note Caching must be turned off for this function to work.
* @note Self test may fail if data memory and device are not on the same bus.
*
*/
XStatus SPIIFC_SelfTest(void * baseaddr_p);
#endif /** SPIIFC_H */
projnav/xps/drivers/spiifc_v1_00_a/src/spiifc_selftest.c 0 → 100644
View file @ a64d58e7
/*****************************************************************************
* Filename: C:\Users\mjlyons\workspace\vSPI\projnav\xps/drivers/spiifc_v1_00_a/src/spiifc_selftest.c
* Version: 1.00.a
* Description: Contains a diagnostic self-test function for the spiifc driver
* Date: Tue Feb 28 11:11:28 2012 (by Create and Import Peripheral Wizard)
*****************************************************************************/
/***************************** Include Files *******************************/
#include "spiifc.h"
/************************** Constant Definitions ***************************/
/************************** Variable Definitions ****************************/
extern Xuint32 LocalBRAM; /* User logic local memory (BRAM) base address */
/************************** Function Definitions ***************************/
/**
*
* Run a self-test on the driver/device. Note this may be a destructive test if
* resets of the device are performed.
*
* If the hardware system is not built correctly, this function may never
* return to the caller.
*
* @param baseaddr_p is the base address of the SPIIFC instance to be worked on.
*
* @return
*
* - XST_SUCCESS if all self-test code passed
* - XST_FAILURE if any self-test code failed
*
* @note Caching must be turned off for this function to work.
* @note Self test may fail if data memory and device are not on the same bus.
*
*/
XStatus SPIIFC_SelfTest(void * baseaddr_p)
{
int Index;
Xuint32 baseaddr;
Xuint8 Reg8Value;
Xuint16 Reg16Value;
Xuint32 Reg32Value;
Xuint32 Mem32Value;
/*
* Check and get the device address
*/
/*
* Base Address maybe 0. Up to developer to uncomment line below.
XASSERT_NONVOID(baseaddr_p != XNULL);
*/
baseaddr = (Xuint32) baseaddr_p;
xil_printf("******************************\n\r");
xil_printf("* User Peripheral Self Test\n\r");
xil_printf("******************************\n\n\r");
/*
* Write to user logic slave module register(s) and read back
*/
xil_printf("User logic slave module test...\n\r");
xil_printf(" - write 1 to slave register 0 word 0\n\r");
SPIIFC_mWriteSlaveReg0(baseaddr, 0, 1);
Reg32Value = SPIIFC_mReadSlaveReg0(baseaddr, 0);
xil_printf(" - read %d from register 0 word 0\n\r", Reg32Value);
if ( Reg32Value != (Xuint32) 1 )
{
xil_printf(" - slave register 0 word 0 write/read failed\n\r");
return XST_FAILURE;
}
xil_printf(" - write 2 to slave register 1 word 0\n\r");
SPIIFC_mWriteSlaveReg1(baseaddr, 0, 2);
Reg32Value = SPIIFC_mReadSlaveReg1(baseaddr, 0);
xil_printf(" - read %d from register 1 word 0\n\r", Reg32Value);
if ( Reg32Value != (Xuint32) 2 )
{
xil_printf(" - slave register 1 word 0 write/read failed\n\r");
return XST_FAILURE;
}
xil_printf(" - write 3 to slave register 2 word 0\n\r");
SPIIFC_mWriteSlaveReg2(baseaddr, 0, 3);
Reg32Value = SPIIFC_mReadSlaveReg2(baseaddr, 0);
xil_printf(" - read %d from register 2 word 0\n\r", Reg32Value);
if ( Reg32Value != (Xuint32) 3 )
{
xil_printf(" - slave register 2 word 0 write/read failed\n\r");
return XST_FAILURE;
}
xil_printf(" - write 4 to slave register 3 word 0\n\r");
SPIIFC_mWriteSlaveReg3(baseaddr, 0, 4);
Reg32Value = SPIIFC_mReadSlaveReg3(baseaddr, 0);
xil_printf(" - read %d from register 3 word 0\n\r", Reg32Value);
if ( Reg32Value != (Xuint32) 4 )
{
xil_printf(" - slave register 3 word 0 write/read failed\n\r");
return XST_FAILURE;
}
xil_printf(" - write 5 to slave register 4 word 0\n\r");
SPIIFC_mWriteSlaveReg4(baseaddr, 0, 5);
Reg32Value = SPIIFC_mReadSlaveReg4(baseaddr, 0);
xil_printf(" - read %d from register 4 word 0\n\r", Reg32Value);
if ( Reg32Value != (Xuint32) 5 )
{
xil_printf(" - slave register 4 word 0 write/read failed\n\r");
return XST_FAILURE;
}
xil_printf(" - write 6 to slave register 5 word 0\n\r");
SPIIFC_mWriteSlaveReg5(baseaddr, 0, 6);
Reg32Value = SPIIFC_mReadSlaveReg5(baseaddr, 0);
xil_printf(" - read %d from register 5 word 0\n\r", Reg32Value);
if ( Reg32Value != (Xuint32) 6 )
{
xil_printf(" - slave register 5 word 0 write/read failed\n\r");
return XST_FAILURE;
}
xil_printf(" - write 7 to slave register 6 word 0\n\r");
SPIIFC_mWriteSlaveReg6(baseaddr, 0, 7);
Reg32Value = SPIIFC_mReadSlaveReg6(baseaddr, 0);
xil_printf(" - read %d from register 6 word 0\n\r", Reg32Value);
if ( Reg32Value != (Xuint32) 7 )
{
xil_printf(" - slave register 6 word 0 write/read failed\n\r");
return XST_FAILURE;
}
xil_printf(" - write 8 to slave register 7 word 0\n\r");
SPIIFC_mWriteSlaveReg7(baseaddr, 0, 8);
Reg32Value = SPIIFC_mReadSlaveReg7(baseaddr, 0);
xil_printf(" - read %d from register 7 word 0\n\r", Reg32Value);
if ( Reg32Value != (Xuint32) 8 )
{
xil_printf(" - slave register 7 word 0 write/read failed\n\r");
return XST_FAILURE;
}
xil_printf(" - write 9 to slave register 8 word 0\n\r");
SPIIFC_mWriteSlaveReg8(baseaddr, 0, 9);
Reg32Value = SPIIFC_mReadSlaveReg8(baseaddr, 0);
xil_printf(" - read %d from register 8 word 0\n\r", Reg32Value);
if ( Reg32Value != (Xuint32) 9 )
{
xil_printf(" - slave register 8 word 0 write/read failed\n\r");
return XST_FAILURE;
}
xil_printf(" - write 10 to slave register 9 word 0\n\r");
SPIIFC_mWriteSlaveReg9(baseaddr, 0, 10);
Reg32Value = SPIIFC_mReadSlaveReg9(baseaddr, 0);
xil_printf(" - read %d from register 9 word 0\n\r", Reg32Value);
if ( Reg32Value != (Xuint32) 10 )
{
xil_printf(" - slave register 9 word 0 write/read failed\n\r");
return XST_FAILURE;
}
xil_printf(" - write 11 to slave register 10 word 0\n\r");
SPIIFC_mWriteSlaveReg10(baseaddr, 0, 11);
Reg32Value = SPIIFC_mReadSlaveReg10(baseaddr, 0);
xil_printf(" - read %d from register 10 word 0\n\r", Reg32Value);
if ( Reg32Value != (Xuint32) 11 )
{
xil_printf(" - slave register 10 word 0 write/read failed\n\r");
return XST_FAILURE;
}
xil_printf(" - write 12 to slave register 11 word 0\n\r");
SPIIFC_mWriteSlaveReg11(baseaddr, 0, 12);
Reg32Value = SPIIFC_mReadSlaveReg11(baseaddr, 0);
xil_printf(" - read %d from register 11 word 0\n\r", Reg32Value);
if ( Reg32Value != (Xuint32) 12 )
{
xil_printf(" - slave register 11 word 0 write/read failed\n\r");
return XST_FAILURE;
}
xil_printf(" - write 13 to slave register 12 word 0\n\r");
SPIIFC_mWriteSlaveReg12(baseaddr, 0, 13);
Reg32Value = SPIIFC_mReadSlaveReg12(baseaddr, 0);
xil_printf(" - read %d from register 12 word 0\n\r", Reg32Value);
if ( Reg32Value != (Xuint32) 13 )
{
xil_printf(" - slave register 12 word 0 write/read failed\n\r");
return XST_FAILURE;
}
xil_printf(" - write 14 to slave register 13 word 0\n\r");
SPIIFC_mWriteSlaveReg13(baseaddr, 0, 14);
Reg32Value = SPIIFC_mReadSlaveReg13(baseaddr, 0);
xil_printf(" - read %d from register 13 word 0\n\r", Reg32Value);
if ( Reg32Value != (Xuint32) 14 )
{
xil_printf(" - slave register 13 word 0 write/read failed\n\r");
return XST_FAILURE;
}
xil_printf(" - write 15 to slave register 14 word 0\n\r");
SPIIFC_mWriteSlaveReg14(baseaddr, 0, 15);
Reg32Value = SPIIFC_mReadSlaveReg14(baseaddr, 0);
xil_printf(" - read %d from register 14 word 0\n\r", Reg32Value);
if ( Reg32Value != (Xuint32) 15 )
{
xil_printf(" - slave register 14 word 0 write/read failed\n\r");
return XST_FAILURE;
}
xil_printf(" - write 16 to slave register 15 word 0\n\r");
SPIIFC_mWriteSlaveReg15(baseaddr, 0, 16);
Reg32Value = SPIIFC_mReadSlaveReg15(baseaddr, 0);
xil_printf(" - read %d from register 15 word 0\n\r", Reg32Value);
if ( Reg32Value != (Xuint32) 16 )
{
xil_printf(" - slave register 15 word 0 write/read failed\n\r");
return XST_FAILURE;
}
xil_printf(" - slave register write/read passed\n\n\r");
/*
* Write data to user logic BRAMs and read back
*/
xil_printf("User logic BRAM test...\n\r");
xil_printf(" - local BRAM address is 0x%08x\n\r", LocalBRAM);
xil_printf(" - write pattern to local BRAM and read back\n\r");
for ( Index = 0; Index < 256; Index++ )
{
SPIIFC_mWriteMemory(LocalBRAM+4*Index, 0xDEADBEEF);
Mem32Value = SPIIFC_mReadMemory(LocalBRAM+4*Index);
if ( Mem32Value != 0xDEADBEEF )
{
xil_printf(" - write/read BRAM failed on address 0x%08x\n\r", LocalBRAM+4*Index);
return XST_FAILURE;
}
}
xil_printf(" - write/read BRAM passed\n\n\r");
/*
* Enable all possible interrupts and clear interrupt status register(s)
*/
xil_printf("Interrupt controller test...\n\r");
Reg32Value = SPIIFC_mReadReg(baseaddr, SPIIFC_INTR_IPISR_OFFSET);
xil_printf(" - IP (user logic) interrupt status : 0x%08x\n\r", Reg32Value);
xil_printf(" - clear IP (user logic) interrupt status register\n\r");
SPIIFC_mWriteReg(baseaddr, SPIIFC_INTR_IPISR_OFFSET, Reg32Value);
xil_printf(" - enable all possible interrupt(s)\n\r");
SPIIFC_EnableInterrupt(baseaddr_p);
xil_printf(" - write/read interrupt register passed\n\n\r");
return XST_SUCCESS;
}
projnav/xps/etc/bitgen.ut 0 → 100644
View file @ a64d58e7
-g TdoPin:PULLNONE
-g StartUpClk:JTAGCLK
#add other options here.
projnav/xps/etc/download.cmd 0 → 100644
View file @ a64d58e7
setMode -bscan
setCable -p auto
identify
assignfile -p 1 -file implementation/download.bit
program -p 1
quit
projnav/xps/etc/fast_runtime.opt 0 → 100644
View file @ a64d58e7
FLOWTYPE = FPGA;
###############################################################
## Filename: fast_runtime.opt
##
## Option File For Xilinx FPGA Implementation Flow for Fast
## Runtime.
##
## Version: 4.1.1
###############################################################
#
# Options for Translator
#
# Type "ngdbuild -h" for a detailed list of ngdbuild command line options
#
Program ngdbuild
-p <partname>; # Partname to use - picked from xflow commandline
-nt timestamp; # NGO File generation. Regenerate only when
# source netlist is newer than existing
# NGO file (default)
-bm <design>.bmm # Block RAM memory map file
<userdesign>; # User design - pick from xflow command line
-uc <design>.ucf; # ucf constraints
<design>.ngd; # Name of NGD file. Filebase same as design filebase
End Program ngdbuild
#
# Options for Mapper
#
# Type "map -h <arch>" for a detailed list of map command line options
#
Program map
-o <design>_map.ncd; # Output Mapped ncd file
-w; # Overwrite output files.
-pr b; # Pack internal FF/latches into IOBs
#-fp <design>.mfp; # Floorplan file
-ol high;
-timing;
-detail;
<inputdir><design>.ngd; # Input NGD file
<inputdir><design>.pcf; # Physical constraints file
END Program map
#
# Options for Post Map Trace
#
# Type "trce -h" for a detailed list of trce command line options
#
Program post_map_trce
-e 3; # Produce error report limited to 3 items per constraint
#-o <design>_map.twr; # Output trace report file
-xml <design>_map.twx; # Output XML version of the timing report
#-tsi <design>_map.tsi; # Produce Timing Specification Interaction report
<inputdir><design>_map.ncd; # Input mapped ncd
<inputdir><design>.pcf; # Physical constraints file
END Program post_map_trce
#
# Options for Place and Route
#
# Type "par -h" for a detailed list of par command line options
#
Program par
-w; # Overwrite existing placed and routed ncd
-ol high; # Overall effort level
<inputdir><design>_map.ncd; # Input mapped NCD file
<design>.ncd; # Output placed and routed NCD
<inputdir><design>.pcf; # Input physical constraints file
END Program par
#
# Options for Post Par Trace
#
# Type "trce -h" for a detailed list of trce command line options
#
Program post_par_trce
-e 3; # Produce error report limited to 3 items per constraint
#-o <design>.twr; # Output trace report file
-xml <design>.twx; # Output XML version of the timing report
#-tsi <design>.tsi; # Produce Timing Specification Interaction report
<inputdir><design>.ncd; # Input placed and routed ncd
<inputdir><design>.pcf; # Physical constraints file
END Program post_par_trce
projnav/xps/etc/system.filters 0 → 100644
View file @ a64d58e7
<FILTERS>
<IDENTIFICATION VERSION="1.2" XTLVERSION="1.2"/>
<SET CLASS="PROJECT" VIEW_ID="BUSINTERFACE">
<HEADERS HSCROLL="0" VSCROLL="0">
<VARIABLE COL_INDEX="0" COL_WIDTH="447" IS_VISIBLE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="HEADER"/>
</HEADERS>
<SET CLASS="FILTER_GROUP" ID="By Connection" IS_EXPANDED="TRUE">
<VARIABLE NAME="By Connection" VALUE="By Connection" VIEWDISP="Bus Interface Filters" VIEWTYPE="STATIC"/>
<SET CLASS="FILTER" ID="Connected" ROW_INDEX="0">
<VARIABLE IS_LABELED="TRUE" NAME="Connected" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="Unconnected" ROW_INDEX="1">
<VARIABLE IS_LABELED="TRUE" NAME="Unconnected" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
</SET>
<SET CLASS="FILTER_GROUP" ID="By Bus Standard" IS_EXPANDED="TRUE">
<VARIABLE COL_INDEX="0" NAME="By Bus Standard" VALUE="By Bus Standard" VIEWDISP="Bus Interface Filters" VIEWTYPE="STATIC"/>
<SET CLASS="FILTER" ID="AXI" IS_VISIBLE="FALSE" ROW_INDEX="0">
<VARIABLE IS_LABELED="TRUE" NAME="AXI" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="AXIS" IS_VISIBLE="FALSE" ROW_INDEX="1">
<VARIABLE IS_LABELED="TRUE" NAME="AXIS" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="OPB" IS_VISIBLE="FALSE" ROW_INDEX="2">
<VARIABLE IS_LABELED="TRUE" NAME="OPB" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="LMB" ROW_INDEX="3">
<VARIABLE IS_LABELED="TRUE" NAME="LMB" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="PLBV34" IS_VISIBLE="FALSE" ROW_INDEX="4">
<VARIABLE IS_LABELED="TRUE" NAME="PLBV34" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="PLBV46" ROW_INDEX="5">
<VARIABLE IS_LABELED="TRUE" NAME="PLBV46" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="OCM" IS_VISIBLE="FALSE" ROW_INDEX="6">
<VARIABLE IS_LABELED="TRUE" NAME="OCM" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="FSL" IS_VISIBLE="FALSE" ROW_INDEX="7">
<VARIABLE IS_LABELED="TRUE" NAME="FSL" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="DCR" IS_VISIBLE="FALSE" ROW_INDEX="8">
<VARIABLE IS_LABELED="TRUE" NAME="DCR" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="FCB" IS_VISIBLE="FALSE" ROW_INDEX="9">
<VARIABLE IS_LABELED="TRUE" NAME="FCB" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="XIL" IS_EXPANDED="TRUE" ROW_INDEX="10">
<VARIABLE IS_LABELED="TRUE" NAME="Xilinx Point To Point" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
<SET CLASS="SUB_FILTER" ID="XIL_BRAM" ROW_INDEX="0">
<VARIABLE IS_LABELED="TRUE" NAME="XIL_BRAM" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="SUB_FILTER" ID="XIL_BSCAN" ROW_INDEX="1">
<VARIABLE IS_LABELED="TRUE" NAME="XIL_BSCAN" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="SUB_FILTER" ID="XIL_MBDEBUG3" ROW_INDEX="2">
<VARIABLE IS_LABELED="TRUE" NAME="XIL_MBDEBUG3" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="SUB_FILTER" ID="XIL_MBTRACE2" ROW_INDEX="3">
<VARIABLE IS_LABELED="TRUE" NAME="XIL_MBTRACE2" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="SUB_FILTER" ID="XIL_MEMORY_CHANNEL" ROW_INDEX="4">
<VARIABLE IS_LABELED="TRUE" NAME="XIL_MEMORY_CHANNEL" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
</SET>
<SET CLASS="FILTER" ID="USER" IS_VISIBLE="FALSE" ROW_INDEX="11">
<VARIABLE IS_LABELED="TRUE" NAME="User Defined" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="XCL" IS_VISIBLE="FALSE" ROW_INDEX="12">
<VARIABLE IS_LABELED="TRUE" NAME="XCL" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
</SET>
<SET CLASS="FILTER_GROUP" ID="By Interface Type" IS_EXPANDED="TRUE">
<VARIABLE NAME="By Interface Type" VALUE="By Interface Type" VIEWDISP="Bus Interface Filters" VIEWTYPE="STATIC"/>
<SET CLASS="FILTER" ID="Slaves" ROW_INDEX="0">
<VARIABLE IS_LABELED="TRUE" NAME="Slaves" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="Masters" ROW_INDEX="1">
<VARIABLE IS_LABELED="TRUE" NAME="Masters" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="Master Slaves" ROW_INDEX="2">
<VARIABLE IS_LABELED="TRUE" NAME="Master Slaves" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="Monitors" ROW_INDEX="3">
<VARIABLE IS_LABELED="TRUE" NAME="Monitors" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="Targets" ROW_INDEX="4">
<VARIABLE IS_LABELED="TRUE" NAME="Targets" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="Initiators" ROW_INDEX="5">
<VARIABLE IS_LABELED="TRUE" NAME="Initiators" VALUE="TRUE" VIEWDISP="Bus Interface Filters" VIEWTYPE="CHECKBOX"/>
</SET>
</SET>
</SET>
<SET CLASS="PROJECT" VIEW_ID="PORT">
<HEADERS HSCROLL="0" VSCROLL="0">
<VARIABLE COL_INDEX="0" COL_WIDTH="485" IS_VISIBLE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="HEADER"/>
</HEADERS>
<SET CLASS="FILTER_GROUP" ID="By Interface" IS_EXPANDED="TRUE">
<VARIABLE NAME="By Interface" VALUE="By Interface" VIEWDISP="Port Filters" VIEWTYPE="STATIC"/>
<SET CLASS="FILTER" ID="BUS" ROW_INDEX="0">
<VARIABLE IS_LABELED="TRUE" NAME="BUS" VALUE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="IO" ROW_INDEX="1">
<VARIABLE IS_LABELED="TRUE" NAME="IO" VALUE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/>
</SET>
</SET>
<SET CLASS="FILTER_GROUP" ID="By Connection" IS_EXPANDED="TRUE">
<VARIABLE NAME="By Connection" VALUE="By Connection" VIEWDISP="Port Filters" VIEWTYPE="STATIC"/>
<SET CLASS="FILTER" ID="Defaults" ROW_INDEX="0">
<VARIABLE IS_LABELED="TRUE" NAME="Defaults" VALUE="FALSE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="Connected" ROW_INDEX="1">
<VARIABLE IS_LABELED="TRUE" NAME="Connected" VALUE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="Unconnected" ROW_INDEX="2">
<VARIABLE IS_LABELED="TRUE" NAME="Unconnected" VALUE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/>
</SET>
</SET>
<SET CLASS="FILTER_GROUP" ID="By Class" IS_EXPANDED="TRUE">
<VARIABLE COL_INDEX="0" NAME="By Class" VALUE="By Class" VIEWDISP="Port Filters" VIEWTYPE="STATIC"/>
<SET CLASS="FILTER" ID="Clocks Only" ROW_INDEX="0">
<VARIABLE NAME="Clocks Only" VALUE="Clocks Only" VIEWDISP="Port Filters" VIEWTYPE="BUTTON"/>
</SET>
<SET CLASS="FILTER" ID="Clocks" ROW_INDEX="1">
<VARIABLE IS_LABELED="TRUE" NAME="Clocks" VALUE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="Resets Only" ROW_INDEX="2">
<VARIABLE NAME="Resets Only" VALUE="Resets Only" VIEWDISP="Port Filters" VIEWTYPE="BUTTON"/>
</SET>
<SET CLASS="FILTER" ID="Resets" ROW_INDEX="3">
<VARIABLE IS_LABELED="TRUE" NAME="Resets" VALUE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="Interrupts Only" ROW_INDEX="4">
<VARIABLE NAME="Interrupts Only" VALUE="Interrupts Only" VIEWDISP="Port Filters" VIEWTYPE="BUTTON"/>
</SET>
<SET CLASS="FILTER" ID="Interrupts" ROW_INDEX="5">
<VARIABLE IS_LABELED="TRUE" NAME="Interrupts" VALUE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="Others" ROW_INDEX="6">
<VARIABLE IS_LABELED="TRUE" NAME="Others" VALUE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/>
</SET>
</SET>
<SET CLASS="FILTER_GROUP" ID="By Direction" IS_EXPANDED="TRUE">
<VARIABLE NAME="By Direction" VALUE="By Direction" VIEWDISP="Port Filters" VIEWTYPE="STATIC"/>
<SET CLASS="FILTER" ID="Inputs" ROW_INDEX="0">
<VARIABLE IS_LABELED="TRUE" NAME="Inputs" VALUE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="Outputs" ROW_INDEX="1">
<VARIABLE IS_LABELED="TRUE" NAME="Outputs" VALUE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/>
</SET>
<SET CLASS="FILTER" ID="InOuts" ROW_INDEX="2">
<VARIABLE IS_LABELED="TRUE" NAME="InOuts" VALUE="TRUE" VIEWDISP="Port Filters" VIEWTYPE="CHECKBOX"/>
</SET>
</SET>
</SET>
</FILTERS>
\ No newline at end of file
projnav/xps/etc/system.gui 0 → 100644
View file @ a64d58e7
<SETTINGS>
<IDENTIFICATION VERSION="1.2" XTLVERSION="1.2"/>
<SET CLASS="PROJECT" DISPLAYMODE="TREE" VIEW_ID="BUSINTERFACE">
<HEADERS HSCROLL="0" VSCROLL="0">
<VARIABLE COL_INDEX="0" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Name" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="1" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Bus Name" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="2" IS_VISIBLE="FALSE" VIEWDISP="Bus Standard" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="3" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="4" COL_WIDTH="726" IS_VISIBLE="TRUE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="5" IS_VISIBLE="FALSE" VIEWDISP="IP Classification" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="6" IS_VISIBLE="FALSE" VIEWDISP="Type" VIEWTYPE="HEADER"/>
</HEADERS>
<SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="180,450,180" VERSION="0"/>
<SET ID="spiifc_0" IS_EXPANDED="TRUE"/>
<SET ID="xps_central_dma_0" IS_EXPANDED="TRUE"/>
<STATUS>
<SELECTIONS/>
</STATUS>
<SEQUENCES IS_DEF_SEQUENCES="TRUE">
<VARIABLE ID="microblaze_0" ROW_INDEX="3"/>
<VARIABLE ID="mb_plb" ROW_INDEX="2"/>
<VARIABLE ID="ilmb" ROW_INDEX="1"/>
<VARIABLE ID="dlmb" ROW_INDEX="0"/>
<VARIABLE ID="dlmb_cntlr" ROW_INDEX="5"/>
<VARIABLE ID="ilmb_cntlr" ROW_INDEX="6"/>
<VARIABLE ID="lmb_bram" ROW_INDEX="4"/>
<VARIABLE ID="DIP_Switches_8Bits" ROW_INDEX="10"/>
<VARIABLE ID="LEDs_8Bits" ROW_INDEX="11"/>
<VARIABLE ID="Push_Buttons_5Bits" ROW_INDEX="12"/>
<VARIABLE ID="clock_generator_0" ROW_INDEX="13"/>
<VARIABLE ID="mdm_0" ROW_INDEX="8"/>
<VARIABLE ID="proc_sys_reset_0" ROW_INDEX="14"/>
<VARIABLE ID="spiifc_0" IS_EXPANDED="TRUE" ROW_INDEX="7"/>
<VARIABLE ID="xps_central_dma_0" IS_EXPANDED="TRUE" ROW_INDEX="9"/>
</SEQUENCES>
</SET>
<SET CLASS="PROJECT" DISPLAYMODE="FOCUS_TREE" VIEW_ID="BUSINTERFACE">
<HEADERS>
<VARIABLE COL_INDEX="0" IS_VISIBLE="TRUE" VIEWDISP="Name" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="1" IS_VISIBLE="TRUE" VIEWDISP="Bus Name" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="2" IS_VISIBLE="FALSE" VIEWDISP="Bus Standard" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="3" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
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<VARIABLE COL_INDEX="5" IS_VISIBLE="FALSE" VIEWDISP="IP Classification" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="6" IS_VISIBLE="FALSE" VIEWDISP="Type" VIEWTYPE="HEADER"/>
</HEADERS>
<SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="180,450,180" VERSION="0"/>
</SET>
<SET CLASS="PROJECT" DISPLAYMODE="FLAT" VIEW_ID="BUSINTERFACE">
<HEADERS>
<VARIABLE COL_INDEX="0" IS_VISIBLE="TRUE" VIEWDISP="Instance" VIEWTYPE="HEADER"/>
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<VARIABLE COL_INDEX="3" IS_VISIBLE="FALSE" VIEWDISP="Bus Standard" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="4" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="5" IS_VISIBLE="TRUE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="6" IS_VISIBLE="FALSE" VIEWDISP="IP Classification" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="7" IS_VISIBLE="FALSE" VIEWDISP="Type" VIEWTYPE="HEADER"/>
</HEADERS>
<SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="180,450,180" VERSION="0"/>
</SET>
<SET CLASS="PROJECT" DISPLAYMODE="FOCUS_FLAT" VIEW_ID="BUSINTERFACE">
<HEADERS>
<VARIABLE COL_INDEX="0" IS_VISIBLE="TRUE" VIEWDISP="Instance" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="1" IS_VISIBLE="TRUE" VIEWDISP="Bus Interface" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="2" IS_VISIBLE="TRUE" VIEWDISP="Bus Name" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="3" IS_VISIBLE="FALSE" VIEWDISP="Bus Standard" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="4" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="5" IS_VISIBLE="TRUE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="6" IS_VISIBLE="FALSE" VIEWDISP="IP Classification" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="7" IS_VISIBLE="FALSE" VIEWDISP="Type" VIEWTYPE="HEADER"/>
</HEADERS>
<SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="180,450,180" VERSION="0"/>
</SET>
<SET CLASS="PROJECT" DISPLAYMODE="TREE" VIEW_ID="PORT">
<HEADERS HSCROLL="0" VSCROLL="0">
<VARIABLE COL_INDEX="0" COL_WIDTH="201" IS_VISIBLE="TRUE" VIEWDISP="Name" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="1" COL_WIDTH="180" IS_VISIBLE="TRUE" VIEWDISP="Net" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="2" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Direction" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="3" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Range" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="4" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Class" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="5" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Frequency(Hz)" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="6" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Reset Polarity" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="7" COL_WIDTH="413" IS_VISIBLE="TRUE" VIEWDISP="Sensitivity" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="8" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="9" IS_VISIBLE="FALSE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="10" IS_VISIBLE="TRUE" VIEWDISP="IP Classification" VIEWTYPE="HEADER"/>
</HEADERS>
<SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="0,630,180" VERSION="0"/>
<SET ID="ExternalPorts" IS_EXPANDED="TRUE"/>
<SET ID="spiifc_0" IS_EXPANDED="TRUE"/>
<STATUS>
<SELECTIONS/>
</STATUS>
<SEQUENCES IS_DEF_SEQUENCES="TRUE">
<VARIABLE ID="ExternalPorts" IS_EXPANDED="TRUE" ROW_INDEX="0"/>
<VARIABLE ID="microblaze_0" ROW_INDEX="4"/>
<VARIABLE ID="mb_plb" ROW_INDEX="3"/>
<VARIABLE ID="ilmb" ROW_INDEX="2"/>
<VARIABLE ID="dlmb" ROW_INDEX="1"/>
<VARIABLE ID="dlmb_cntlr" ROW_INDEX="6"/>
<VARIABLE ID="ilmb_cntlr" ROW_INDEX="7"/>
<VARIABLE ID="lmb_bram" ROW_INDEX="5"/>
<VARIABLE ID="DIP_Switches_8Bits" ROW_INDEX="11"/>
<VARIABLE ID="LEDs_8Bits" ROW_INDEX="12"/>
<VARIABLE ID="Push_Buttons_5Bits" ROW_INDEX="13"/>
<VARIABLE ID="clock_generator_0" ROW_INDEX="14"/>
<VARIABLE ID="mdm_0" ROW_INDEX="9"/>
<VARIABLE ID="proc_sys_reset_0" ROW_INDEX="15"/>
<VARIABLE ID="spiifc_0" IS_EXPANDED="TRUE" ROW_INDEX="8"/>
<VARIABLE ID="xps_central_dma_0" ROW_INDEX="10"/>
</SEQUENCES>
</SET>
<SET CLASS="PROJECT" DISPLAYMODE="FOCUS_TREE" VIEW_ID="PORT">
<HEADERS>
<VARIABLE COL_INDEX="0" IS_VISIBLE="TRUE" VIEWDISP="Name" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="1" IS_VISIBLE="TRUE" VIEWDISP="Net" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="2" IS_VISIBLE="TRUE" VIEWDISP="Direction" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="3" IS_VISIBLE="TRUE" VIEWDISP="Range" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="4" IS_VISIBLE="TRUE" VIEWDISP="Class" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="5" IS_VISIBLE="TRUE" VIEWDISP="Frequency(Hz)" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="6" IS_VISIBLE="TRUE" VIEWDISP="Reset Polarity" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="7" IS_VISIBLE="TRUE" VIEWDISP="Sensitivity" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="8" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="9" IS_VISIBLE="FALSE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="10" IS_VISIBLE="TRUE" VIEWDISP="IP Classification" VIEWTYPE="HEADER"/>
</HEADERS>
<SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="0,630,180" VERSION="0"/>
</SET>
<SET CLASS="PROJECT" DISPLAYMODE="FLAT" VIEW_ID="PORT">
<HEADERS>
<VARIABLE COL_INDEX="0" IS_VISIBLE="TRUE" VIEWDISP="Instance" VIEWTYPE="HEADER"/>
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<VARIABLE COL_INDEX="3" IS_VISIBLE="TRUE" VIEWDISP="Direction" VIEWTYPE="HEADER"/>
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<VARIABLE COL_INDEX="5" IS_VISIBLE="TRUE" VIEWDISP="Class" VIEWTYPE="HEADER"/>
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<VARIABLE COL_INDEX="8" IS_VISIBLE="TRUE" VIEWDISP="Sensitivity" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="9" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="10" IS_VISIBLE="FALSE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="11" IS_VISIBLE="TRUE" VIEWDISP="IP Classification" VIEWTYPE="HEADER"/>
</HEADERS>
<SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="0,630,180" VERSION="0"/>
</SET>
<SET CLASS="PROJECT" DISPLAYMODE="FOCUS_FLAT" VIEW_ID="PORT">
<HEADERS>
<VARIABLE COL_INDEX="0" IS_VISIBLE="TRUE" VIEWDISP="Instance" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="1" IS_VISIBLE="TRUE" VIEWDISP="Port Name" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="2" IS_VISIBLE="TRUE" VIEWDISP="Net" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="3" IS_VISIBLE="TRUE" VIEWDISP="Direction" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="4" IS_VISIBLE="TRUE" VIEWDISP="Range" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="5" IS_VISIBLE="TRUE" VIEWDISP="Class" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="6" IS_VISIBLE="TRUE" VIEWDISP="Frequency(Hz)" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="7" IS_VISIBLE="TRUE" VIEWDISP="Reset Polarity" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="8" IS_VISIBLE="TRUE" VIEWDISP="Sensitivity" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="9" IS_VISIBLE="TRUE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="10" IS_VISIBLE="FALSE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="11" IS_VISIBLE="TRUE" VIEWDISP="IP Classification" VIEWTYPE="HEADER"/>
</HEADERS>
<SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="0,630,180" VERSION="0"/>
</SET>
<SET CLASS="PROJECT" DISPLAYMODE="TREE" VIEW_ID="ADDRESS">
<HEADERS HSCROLL="0" VSCROLL="0">
<VARIABLE COL_INDEX="0" COL_WIDTH="200" IS_VISIBLE="TRUE" VIEWDISP="Instance" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="1" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Base Name" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="2" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Base Address" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="3" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="High Address" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="4" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Size" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="5" COL_WIDTH="105" IS_VISIBLE="TRUE" VIEWDISP="Bus Interface(s)" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="6" COL_WIDTH="100" IS_VISIBLE="TRUE" VIEWDISP="Bus Name" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="7" IS_VISIBLE="FALSE" VIEWDISP="ICache" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="8" IS_VISIBLE="FALSE" VIEWDISP="DCache" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="8" IS_VISIBLE="FALSE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="10" IS_VISIBLE="FALSE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="7" IS_VISIBLE="FALSE" VIEWDISP="Address Type" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="9" COL_WIDTH="894" IS_VISIBLE="TRUE" VIEWDISP="Lock" VIEWTYPE="HEADER"/>
</HEADERS>
<SPLITTERS COLLAPSIBLE="1" HANDLEWIDTH="4" MARKER="255" ORIENTATION="1" RESIZE="1" SIZES="0,630,180" VERSION="0"/>
<SET ID="microblaze_0" IS_EXPANDED="TRUE"/>
<STATUS>
<SELECTIONS/>
</STATUS>
<SEQUENCES IS_DEF_SEQUENCES="TRUE">
<VARIABLE ID="microblaze_0" IS_EXPANDED="TRUE" ROW_INDEX="0"/>
</SEQUENCES>
</SET>
<SET CLASS="PROJECT" DISPLAYMODE="FLAT" VIEW_ID="ADDRESS">
<HEADERS>
<VARIABLE COL_INDEX="0" IS_VISIBLE="TRUE" VIEWDISP="Instance" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="1" IS_VISIBLE="TRUE" VIEWDISP="Base Name" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="2" IS_VISIBLE="TRUE" VIEWDISP="Base Address" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="3" IS_VISIBLE="TRUE" VIEWDISP="High Address" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="4" IS_VISIBLE="TRUE" VIEWDISP="Size" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="5" IS_VISIBLE="TRUE" VIEWDISP="Bus Interface(s)" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="6" IS_VISIBLE="TRUE" VIEWDISP="Bus Name" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="7" IS_VISIBLE="FALSE" VIEWDISP="ICache" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="8" IS_VISIBLE="FALSE" VIEWDISP="DCache" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="9" IS_VISIBLE="FALSE" VIEWDISP="IP Type" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="10" IS_VISIBLE="FALSE" VIEWDISP="IP Version" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="11" IS_VISIBLE="FALSE" VIEWDISP="Address Type" VIEWTYPE="HEADER"/>
<VARIABLE COL_INDEX="12" IS_VISIBLE="TRUE" VIEWDISP="Lock" VIEWTYPE="HEADER"/>
</HEADERS>
</SET>
</SETTINGS>
\ No newline at end of file
projnav/xps/implementation/system_summary.html 0 → 100644
View file @ a64d58e7
<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>system Project Status</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>system.xmp</TD>
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
<TD>New</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
<TD>system</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>EDK 13.2</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='5'><B>XPS Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=EDKReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD>Platgen Log File</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Simgen Log File</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>BitInit Log File</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/mjlyons/workspace/vSPI/projnav/xps\system.log'>System Log File</A></TD><TD>Thu Mar 15 15:58:44 2012</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
</TABLE>
<br><center><b>Date Generated:</b> 03/15/2012 - 15:58:44</center>
</BODY></HTML>
\ No newline at end of file
projnav/xps/pcores/spiifc.prj 0 → 100644
View file @ a64d58e7
vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v3_00_a\hdl\vhdl\proc_common_pkg.vhd"
vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v3_00_a\hdl\vhdl\or_muxcy.vhd"
vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v3_00_a\hdl\vhdl\family_support.vhd"
vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v3_00_a\hdl\vhdl\pselect_f.vhd"
vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v3_00_a\hdl\vhdl\or_gate128.vhd"
vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v3_00_a\hdl\vhdl\ipif_pkg.vhd"
vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\proc_common_v3_00_a\hdl\vhdl\counter_f.vhd"
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_slave_burst_v1_01_a\hdl\vhdl\flex_addr_cntr.vhd"
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_slave_burst_v1_01_a\hdl\vhdl\wr_buffer.vhd"
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_slave_burst_v1_01_a\hdl\vhdl\plb_address_decoder.vhd"
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_slave_burst_v1_01_a\hdl\vhdl\burst_support.vhd"
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_slave_burst_v1_01_a\hdl\vhdl\be_reset_gen.vhd"
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_slave_burst_v1_01_a\hdl\vhdl\addr_reg_cntr_brst_flex.vhd"
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_slave_burst_v1_01_a\hdl\vhdl\plb_slave_attachment.vhd"
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_slave_burst_v1_01_a\hdl\vhdl\data_mirror_128.vhd"
verilog spiifc_v1_00_a "C:\Users\mjlyons\workspace\vSPI\src\spi_base\spiifc.v"
verilog spiifc_v1_00_a "C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav\ipcore_dir\buffermem.v"
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_slave_burst_v1_01_a\hdl\vhdl\plbv46_slave_burst.vhd"
vhdl interrupt_control_v2_01_a "C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\interrupt_control_v2_01_a\hdl\vhdl\interrupt_control.vhd"
verilog spiifc_v1_00_a "C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\hdl\verilog\user_logic.v"
vhdl spiifc_v1_00_a "C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\hdl\vhdl\spiifc.vhd"
projnav/xps/pcores/spiifc_v1_00_a/data/_spiifc_xst.prj 0 → 100644
View file @ a64d58e7
vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/proc_common_pkg.vhd"
vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ipif_pkg.vhd"
vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_muxcy.vhd"
vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_gate128.vhd"
vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/family_support.vhd"
vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd"
vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter_f.vhd"
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/flex_addr_cntr.vhd"
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/addr_reg_cntr_brst_flex.vhd"
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plb_address_decoder.vhd"
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/burst_support.vhd"
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/wr_buffer.vhd"
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/be_reset_gen.vhd"
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plb_slave_attachment.vhd"
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/data_mirror_128.vhd"
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plbv46_slave_burst.vhd"
vhdl interrupt_control_v2_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v2_01_a/hdl/vhdl/interrupt_control.vhd"
verilog spiifc_v1_00_a "../hdl/verilog/user_logic.v"
vhdl spiifc_v1_00_a "../hdl/vhdl/spiifc.vhd"
projnav/xps/pcores/spiifc_v1_00_a/data/spiifc_v2_1_0.bbd 0 → 100644
View file @ a64d58e7
##############################################################################
## Filename: C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores/spiifc_v1_00_a/data/spiifc_v2_1_0.bbd
## Description: Black Box Definition
## Date: Wed Mar 14 16:37:23 2012 (by Create and Import Peripheral Wizard)
##############################################################################
Files
################################################################################
buffermem.ngc
projnav/xps/pcores/spiifc_v1_00_a/data/spiifc_v2_1_0.mpd 0 → 100644
View file @ a64d58e7
###################################################################
##
## Name : spiifc
## Desc : Microprocessor Peripheral Description
## : Automatically generated by PsfUtility
##
###################################################################
BEGIN spiifc
## Peripheral Options
OPTION IPTYPE = PERIPHERAL
OPTION IMP_NETLIST = TRUE
OPTION HDL = MIXED
OPTION IP_GROUP = MICROBLAZE:PPC:USER
OPTION STYLE = MIX
OPTION RUN_NGCBUILD = TRUE
## Bus Interfaces
BUS_INTERFACE BUS = SPLB, BUS_STD = PLBV46, BUS_TYPE = SLAVE
## Generics for VHDL or Parameters for Verilog
PARAMETER C_BASEADDR = 0xffffffff, DT = std_logic_vector, PAIR = C_HIGHADDR, ADDRESS = BASE, BUS = SPLB
PARAMETER C_HIGHADDR = 0x00000000, DT = std_logic_vector, PAIR = C_BASEADDR, ADDRESS = HIGH, BUS = SPLB
PARAMETER C_SPLB_AWIDTH = 32, DT = INTEGER, BUS = SPLB
PARAMETER C_SPLB_DWIDTH = 128, DT = INTEGER, BUS = SPLB
PARAMETER C_SPLB_NUM_MASTERS = 8, DT = INTEGER, BUS = SPLB
PARAMETER C_SPLB_MID_WIDTH = 3, DT = INTEGER, BUS = SPLB
PARAMETER C_SPLB_NATIVE_DWIDTH = 32, DT = INTEGER, BUS = SPLB
PARAMETER C_SPLB_P2P = 0, DT = INTEGER, BUS = SPLB
PARAMETER C_SPLB_SUPPORT_BURSTS = 1, DT = INTEGER, BUS = SPLB
PARAMETER C_SPLB_SMALLEST_MASTER = 32, DT = INTEGER, BUS = SPLB
PARAMETER C_SPLB_CLK_PERIOD_PS = 10000, DT = INTEGER, BUS = SPLB
PARAMETER C_INCLUDE_DPHASE_TIMER = 1, DT = INTEGER
PARAMETER C_FAMILY = virtex6, DT = STRING
PARAMETER C_MEM0_BASEADDR = 0xffffffff, DT = std_logic_vector, PAIR = C_MEM0_HIGHADDR, ADDRESS = BASE, BUS = SPLB, ADDR_TYPE = MEMORY
PARAMETER C_MEM0_HIGHADDR = 0x00000000, DT = std_logic_vector, PAIR = C_MEM0_BASEADDR, ADDRESS = HIGH, BUS = SPLB, ADDR_TYPE = MEMORY
PARAMETER C_MEM1_BASEADDR = 0xffffffff, DT = std_logic_vector, PAIR = C_MEM1_HIGHADDR, ADDRESS = BASE, BUS = SPLB, ADDR_TYPE = MEMORY
PARAMETER C_MEM1_HIGHADDR = 0x00000000, DT = std_logic_vector, PAIR = C_MEM1_BASEADDR, ADDRESS = HIGH, BUS = SPLB, ADDR_TYPE = MEMORY
## Ports
PORT SPI_CLK = "", DIR = I
PORT SPI_MOSI = "", DIR = I
PORT SPI_MISO = "", DIR = O
PORT SPI_SS = "", DIR = I
PORT SPLB_Clk = "", DIR = I, SIGIS = CLK, BUS = SPLB
PORT SPLB_Rst = SPLB_Rst, DIR = I, SIGIS = RST, BUS = SPLB
PORT PLB_ABus = PLB_ABus, DIR = I, VEC = [0:31], BUS = SPLB
PORT PLB_UABus = PLB_UABus, DIR = I, VEC = [0:31], BUS = SPLB
PORT PLB_PAValid = PLB_PAValid, DIR = I, BUS = SPLB
PORT PLB_SAValid = PLB_SAValid, DIR = I, BUS = SPLB
PORT PLB_rdPrim = PLB_rdPrim, DIR = I, BUS = SPLB
PORT PLB_wrPrim = PLB_wrPrim, DIR = I, BUS = SPLB
PORT PLB_masterID = PLB_masterID, DIR = I, VEC = [0:(C_SPLB_MID_WIDTH-1)], BUS = SPLB
PORT PLB_abort = PLB_abort, DIR = I, BUS = SPLB
PORT PLB_busLock = PLB_busLock, DIR = I, BUS = SPLB
PORT PLB_RNW = PLB_RNW, DIR = I, BUS = SPLB
PORT PLB_BE = PLB_BE, DIR = I, VEC = [0:((C_SPLB_DWIDTH/8)-1)], BUS = SPLB
PORT PLB_MSize = PLB_MSize, DIR = I, VEC = [0:1], BUS = SPLB
PORT PLB_size = PLB_size, DIR = I, VEC = [0:3], BUS = SPLB
PORT PLB_type = PLB_type, DIR = I, VEC = [0:2], BUS = SPLB
PORT PLB_lockErr = PLB_lockErr, DIR = I, BUS = SPLB
PORT PLB_wrDBus = PLB_wrDBus, DIR = I, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB
PORT PLB_wrBurst = PLB_wrBurst, DIR = I, BUS = SPLB
PORT PLB_rdBurst = PLB_rdBurst, DIR = I, BUS = SPLB
PORT PLB_wrPendReq = PLB_wrPendReq, DIR = I, BUS = SPLB
PORT PLB_rdPendReq = PLB_rdPendReq, DIR = I, BUS = SPLB
PORT PLB_wrPendPri = PLB_wrPendPri, DIR = I, VEC = [0:1], BUS = SPLB
PORT PLB_rdPendPri = PLB_rdPendPri, DIR = I, VEC = [0:1], BUS = SPLB
PORT PLB_reqPri = PLB_reqPri, DIR = I, VEC = [0:1], BUS = SPLB
PORT PLB_TAttribute = PLB_TAttribute, DIR = I, VEC = [0:15], BUS = SPLB
PORT Sl_addrAck = Sl_addrAck, DIR = O, BUS = SPLB
PORT Sl_SSize = Sl_SSize, DIR = O, VEC = [0:1], BUS = SPLB
PORT Sl_wait = Sl_wait, DIR = O, BUS = SPLB
PORT Sl_rearbitrate = Sl_rearbitrate, DIR = O, BUS = SPLB
PORT Sl_wrDAck = Sl_wrDAck, DIR = O, BUS = SPLB
PORT Sl_wrComp = Sl_wrComp, DIR = O, BUS = SPLB
PORT Sl_wrBTerm = Sl_wrBTerm, DIR = O, BUS = SPLB
PORT Sl_rdDBus = Sl_rdDBus, DIR = O, VEC = [0:(C_SPLB_DWIDTH-1)], BUS = SPLB
PORT Sl_rdWdAddr = Sl_rdWdAddr, DIR = O, VEC = [0:3], BUS = SPLB
PORT Sl_rdDAck = Sl_rdDAck, DIR = O, BUS = SPLB
PORT Sl_rdComp = Sl_rdComp, DIR = O, BUS = SPLB
PORT Sl_rdBTerm = Sl_rdBTerm, DIR = O, BUS = SPLB
PORT Sl_MBusy = Sl_MBusy, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
PORT Sl_MWrErr = Sl_MWrErr, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
PORT Sl_MRdErr = Sl_MRdErr, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
PORT Sl_MIRQ = Sl_MIRQ, DIR = O, VEC = [0:(C_SPLB_NUM_MASTERS-1)], BUS = SPLB
PORT IP2INTC_Irpt = "", DIR = O, SIGIS = INTERRUPT, SENSITIVITY = LEVEL_HIGH
END
projnav/xps/pcores/spiifc_v1_00_a/data/spiifc_v2_1_0.pao 0 → 100644
View file @ a64d58e7
##############################################################################
## Filename: C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores/spiifc_v1_00_a/data/spiifc_v2_1_0.pao
## Description: Peripheral Analysis Order
## Date: Wed Mar 14 16:37:23 2012 (by Create and Import Peripheral Wizard)
##############################################################################
lib proc_common_v3_00_a proc_common_pkg vhdl
lib proc_common_v3_00_a or_muxcy vhdl
lib proc_common_v3_00_a family_support vhdl
lib proc_common_v3_00_a pselect_f vhdl
lib proc_common_v3_00_a or_gate128 vhdl
lib proc_common_v3_00_a ipif_pkg vhdl
lib proc_common_v3_00_a counter_f vhdl
lib plbv46_slave_burst_v1_01_a flex_addr_cntr vhdl
lib plbv46_slave_burst_v1_01_a wr_buffer vhdl
lib plbv46_slave_burst_v1_01_a plb_address_decoder vhdl
lib plbv46_slave_burst_v1_01_a burst_support vhdl
lib plbv46_slave_burst_v1_01_a be_reset_gen vhdl
lib plbv46_slave_burst_v1_01_a addr_reg_cntr_brst_flex vhdl
lib plbv46_slave_burst_v1_01_a plb_slave_attachment vhdl
lib plbv46_slave_burst_v1_01_a data_mirror_128 vhdl
lib spiifc_v1_00_a spiifc verilog
lib spiifc_v1_00_a buffermem verilog
lib plbv46_slave_burst_v1_01_a plbv46_slave_burst vhdl
lib interrupt_control_v2_01_a interrupt_control vhdl
lib spiifc_v1_00_a user_logic verilog
lib spiifc_v1_00_a spiifc vhdl
projnav/xps/pcores/spiifc_v1_00_a/devl/README.txt 0 → 100644
View file @ a64d58e7
TABLE OF CONTENTS
1) Peripheral Summary
2) Description of Generated Files
3) Description of Used IPIC Signals
4) Description of Top Level Generics
================================================================================
* 1) Peripheral Summary *
================================================================================
Peripheral Summary:
XPS project / EDK repository : C:\Users\mjlyons\workspace\vSPI\projnav\xps
logical library name : spiifc_v1_00_a
top name : spiifc
version : 1.00.a
type : PLB (v4.6) slave
features : slave attachment
interrupt control
user s/w registers
user memory spaces
Address Block for User Logic and IPIF Predefined Services
user logic slave space : C_BASEADDR + 0x00000000
: C_BASEADDR + 0x000000FF
interrupt control space : C_BASEADDR + 0x00000100
: C_BASEADDR + 0x000001FF
User logic memory space 0 : C_MEM0_BASEADDR
: C_MEM0_HIGHADDR
User logic memory space 1 : C_MEM1_BASEADDR
: C_MEM1_HIGHADDR
================================================================================
* 2) Description of Generated Files *
================================================================================
- HDL source file(s)
hdl/vhdl/spiifc.vhd
This is the template file for your peripheral's top design entity. It
configures and instantiates the corresponding design units in the way you
indicated in the wizard GUI and hooks it up to the stub user logic where
the actual functionalites should get implemented. You are not expected to
modify this template file except certain marked places for adding user
specific generics and ports.
verilog/user_logic.v
This is the template file for the stub user logic design entity, either in
VHDL or Verilog, where the actual functionalities should get implemented.
Some sample code snippet may be provided for demonstration purpose.
- XPS interface file(s)
data/spiifc_v2_1_0.mpd
This Microprocessor Peripheral Description file contains information of the
interface of your peripheral, so that other EDK tools can recognize your
peripheral.
data/spiifc_v2_1_0.pao
This Peripheral Analysis Order file defines the analysis order of all the HDL
source files that are used to compile your peripheral.
- ISE project file(s)
devl/projnav/spiifc.ise
This is the ProjNavigator project file. It sets up the needed logical
libraries and dependent library files for you to help you develop your
peripheral using ProjNavigator.
devl/projnav/spiifc.cli
This is the TCL command line file used to generate the .ise file.
- XST synthesis file(s)
devl/synthesis/spiifc_xst.scr
This is the XST synthesis script file to compile your peripheral.
Note: you may want to modify the device part option for your target.
devl/synthesis/spiifc_xst.prj
This is the XST synthesis project file used by the above script file to
compile your peripheral.
- Driver source file(s)
src/spiifc.h
This is the software driver header template file, which contains address offset of
software addressable registers in your peripheral, as well as some common masks and
simple register access macros or function declaration.
src/spiifc.c
This is the software driver source template file, to define all applicable driver
functions.
src/spiifc_selftest.c
This is the software driver self test example file, which contain self test example
code to test various hardware features of your peripheral.
src/Makefile
This is the software driver makefile to compile drivers.
- Driver interface file(s)
-user needs to add these to repositories path in SDK (Xilinx Tools-->Repositories)
data/spiifc_v2_1_0.mdd
This is the Microprocessor Driver Definition file.
data/spiifc_v2_1_0.tcl
This is the Microprocessor Driver Command file.
- Other misc file(s)
devl/ipwiz.opt
This is the option setting file for the wizard batch mode, which should
generate the same result as the wizard GUI mode.
devl/README.txt
This README file for your peripheral.
devl/ipwiz.log
This is the log file by operating on this wizard.
================================================================================
* 3) Description of Used IPIC Signals *
================================================================================
For more information (usage, timing diagrams, etc.) regarding the IPIC signals
used in the templates, please refer to the following specifications:
proc_common_v3_00_a
No documentation for this library
plbv46_slave_burst_v1_01_a
C:\Users\mjlyons\workspace\vSPI\projnav\xps\C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_slave_burst_v1_01_a\doc\plbv46_slave_burst.pdf
interrupt_control_v2_01_a
C:\Users\mjlyons\workspace\vSPI\projnav\xps\C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\interrupt_control_v2_01_a\doc\interrupt_control.pdf
Bus2IP_Clk
Synchronization clock provided to the user logic. All IPIC signals are
synchronous to this clock. It is identical to the input <bus>_Clk signal of
the peripheral. No additional buffering is provided on the clock; it is
passed through as is.
Bus2IP_Reset
Active high reset used by the user logic. It is asserted whenever the
<bus>_Rst signal asserts or whenever there is a software-programmed reset
(if the soft reset block is included).
Bus2IP_Addr
Address bus to the user logic. It indicates the address of the requested
read or write operation. It can be used for additional address decoding or
as input to addressable memory devices.
Bus2IP_CS
Active high chip select bus. Assertion of a chip select indicates an active
transaction request to the chip select's target address space. This is
typically used for user logic memory space selection.
Bus2IP_RNW
Input signal to the user logic. It indicates the sense of a requested
operation with the user logic. High is a read and low is a write. It is
valid whenever at least one of the Bus2IP_CS bits is active.
Bus2IP_Data
Write data bus to the user logic. Write data is accepted by the user logic
during a write operation by assertion of the write acknowledgement signal
and the rising edge of the Bus2IP_Clk.
Bus2IP_BE
Byte Enable qualifiers for the requested read or write operation to the user
logic. A bit in the Bus2IP_BE set to '1' indicates that the associated byte
lane contains valid data. For example, if Bus2IP_BE = 0011, this indicates
that byte lanes 2 and 3 contain valid data.
Bus2IP_RdCE
Active high chip enable bus to the user logic. These chip enables are only
asserted during active read transaction requests with the target address
space and in conjunction with the corresponding sub-address within the
space. These are typically used for user logic readable registers selection.
Bus2IP_WrCE
Active high chip enable bus to the user logic. These chip enables are
asserted only during active write transaction requests with the target
address space and in conjunction with the corresponding sub-address within
the space. Typically used for user logic writable registers selection.
Bus2IP_Burst
Active high signal indicating that the active read or write operation with
the user logic is utilizing bursting protocol. This signal is asserted at
the initiation of a burst transaction with the user logic and de-asserted at
the completion of the second to last data beat of the burst data transfer.
Bus2IP_BurstLength
This value is an indication of the number of bytes being requested for
transfer and is valid when the cycle is of burst type Bus2IP_CS is active.
Bus2IP_RdReq
Active high signal indicating the initiation of a read operation with the
user logic. It is asserted for one Bus2IP_Clk during single data beat
transactions and remains high to completion on burst read operations.
Bus2IP_WrReq
Active high signal indicating the initiation of a write operation with the
user logic. It is asserted for one Bus2IP_Clk during single data beat
transactions and remains high to completion on burst write operations.
IP2Bus_AddrAck
Active high signal that advances the address counter and request state
during multiple data beat transfers, i.e. bursting.
IP2Bus_Data
Output read data bus from the user logic; data is qualified with the
assertion of IP2Bus_RdAck signal and the rising edge of the Bus2IP_Clk.
IP2Bus_RdAck
Active high read data qualifier providing the read acknowledgement from the
user logic. Read data on the IP2Bus_Data bus is deemed valid at the rising
edge of the Bus2IP_Clk and IP2Bus_RdAck asserted high by the user logic. For
immediate acknowledgement (such as for a register read), this signal can be
tied to '1'. Wait states can be inserted in the transaction by delaying the
assertion of the acknowledgement.
IP2Bus_WrAck
Active high write data qualifier providing the write acknowledgement from
the user logic. Write data on the Bus2IP_Data bus is deemed accepted by the
user logic at the rising edge of the Bus2IP_Clk and IP2Bus_WrAck asserted
high by the user logic. For immediate acknowledgement (such as for a
register write), this signal can be tied to '1'. Wait states can be inserted
in the transaction by delaying the assertion of the acknowledgement.
IP2Bus_Error
Active high signal indicating the user logic has encountered an error with
the requested operation. It is asserted in conjunction with the read/write
acknowledgement signal(s).
IP2Bus_IntrEvent
An output from the user logic to the IPIF that consists of interrupt event
signals to be detected and latched inside the IPIF.
================================================================================
* 4) Description of Top Level Generics *
================================================================================
C_BASEADDR/C_HIGHADDR
These two generics are used to define the memory mapped address space for
the peripheral registers, including Soft Reset register, Interrupt Source
Controller registers, Read/Write FIFO control/data registers, user logic
software accessible registers and etc., but excluding those user logic
memory spaces if ever existed. When instantiation, the address space
size determined by these two generics must be a power of 2 (e.g. 2^k =
C_HIGHADDR - C_BASEADDR + 1), a factor of C_BASEADDR and larger than the
minimum size as indicated in the template.
C_SPLB_AWIDTH
This is the slave interface address bus width for Processor Local Bus
version 4.6 (PLBv46). Value can be assigned automatically by EDK
tooling during system creation.
C_SPLB_DWIDTH
This is the slave interface data bus width for Processor Local Bus
version 4.6 (PLBv46). Value can be assigned automatically by EDK
tooling during system creation.
C_SPLB_NUM_MASTERS
This indicates to the slave interface the number of PLBv46 masters
present. Value can be assigned automatically by EDK tooling during
system creation.
C_SPLB_MID_WIDTH
This indicates to the slave interface the number of bits required
for the PLB_masterID input bus. It is an integer value equal to
log2(C_SPLB_NUM_MASTERS). Value will be assigned automatically by
EDK tooling during system creation.
C_SPLB_NATIVE_DWIDTH
This indicates to the slave interface the native bit width of the
internal data bus of the peripheral. Some peripheral will require
the value of this parameter to be fixed, while others might have
selectable native data widths.
C_SPLB_P2P
This indicates to the slave interface when it is exclusively attached
to a PLBv46 bus via a Point to Point interconnect scheme. In this
scenario, the slave interface may be able to reduce resource utilization
by eliminating address decode function and modifying interface behavior
to allow for a reduction in latency.
C_SPLB_SUPPORT_BURSTS
This indicates to the associated PLBv46 bus that this slave interface
support burst transfers to improve performance.
C_SPLB_SMALLEST_MASTER
This indicates the smallest native data width of any master on the
corresponding PLBv46 bus that may access the slave interface. It allows
optimizations within the slave interface logic if narrower masters don't
have to be supported for that application.
C_SPLB_CLK_PERIOD_PS
This is the period of the PLBv46 bus clock (in picoseconds) for the
corresponding PLBv46 slave interface attachment. It has been defined
for use by peripheral that needs to know the bus clock rate to improve
certain functions such as internal timers.
C_INCLUDE_DPHASE_TIMER
This indicates if the data phase timer is used or not. The value of
0 will exclude the timer. The value of 1 includes the timer.
If C_INCLUDE_DPHASE_TIMER = 1 and after 128 SPLB_Clk cycles, as
measured from the assertion of Sl_AddrAck, the User IP does not
respond with either an IP2Bus_RdAck or IP2Bus_WrAck the
plbv46_slave_single will de-assert the User IP cycle request
signals, Bus2IP_CS and Bus2IP_RdCE or Bus2IP_WrCE, and will assert
Sl_rdDAck with Sl_rdDBus=zero for a read cycle or Sl_wrDAck for
a write cycle. This will gracefully terminate the cycle. Note
that the requesting master will have no knowledge that the data
phase of the PLB request was terminated in this manner.
C_FAMILY
This is to set the target FPGA architecture, s.t. virtex6, etc.
C_MEMn_BASEADDR/C_MEMn_HIGHADDR (n = 0, 1, 2, etc.)
These two generics are used to define the memory mapped address space for
user logic memory space n, which are typically used in peripherals like
memory controllers, bridges, that need to access memory blocks other
than local register space. When instantiation, the address space size
determined by these two generics should be a power of 2 (e.g. 2^k =
C_MEMn_HIGHADDR - C_MEMn_BASEADDR + 1) and a factor of C_MEMn_BASEADDR.
================================================================================
* 5) Location to documentation of dependent libraries *
* *
* In general, the documentation is located under: *
* $XILINX_EDK/hw/XilinxProcessorIPLib/pcores/$libName/doc *
* *
================================================================================
proc_common_v3_00_a
No documentation for this library
plbv46_slave_burst_v1_01_a
C:\Users\mjlyons\workspace\vSPI\projnav\xps\C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\plbv46_slave_burst_v1_01_a\doc\plbv46_slave_burst.pdf
interrupt_control_v2_01_a
C:\Users\mjlyons\workspace\vSPI\projnav\xps\C:\Xilinx\13.2\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\interrupt_control_v2_01_a\doc\interrupt_control.pdf
projnav/xps/pcores/spiifc_v1_00_a/devl/create.cip 0 → 100644
View file @ a64d58e7
CipWiz::SetVersion "13.2";
CipWiz::SetFlow "CREATE";
CipWiz::SetParameter "ProjectDir" "C:\Users\mjlyons\workspace\vSPI\projnav\xps";
CipWiz::SetParameter "IpName" "spiifc";
CipWiz::SetParameter "IpVersion" "1.00.a";
CipWiz::SetParameter "HdlLanguage" "2";
CipWiz::SetParameter "BusType" "64";
CipWiz::SetParameter "IncludeIseFile" "TRUE";
CipWiz::SetParameter "IncludeXpsFile" "TRUE";
CipWiz::SetParameter "IncludeSoftwareDriverFile" "TRUE";
CipWiz::SetParameter "IncludeBFMSimulationFile" "FALSE";
CipWiz::SetParameter "IncludeSlaveAttachmentSupport" "TRUE";
CipWiz::SetParameter "IncludeMasterAttachmentSupport" "FALSE";
CipWiz::SetParameter "IncludeMirResetRegister" "FALSE";
CipWiz::SetParameter "IncludeFifoSupport" "FALSE";
CipWiz::SetParameter "IncludeInterruptSupport" "TRUE";
CipWiz::SetParameter "IncludeDMASupport" "FALSE";
CipWiz::SetParameter "IncludeBurstSupport" "FALSE";
CipWiz::SetParameter "IncludeUserRegisterSupport" "TRUE";
CipWiz::SetParameter "IncludeUserMasterSupport" "FALSE";
CipWiz::SetParameter "IncludeUserMemorySupport" "TRUE";
CipWiz::SetParameter "UseSlaveBurst" "TRUE";
CipWiz::SetParameter "UseMasterBurst" "FALSE";
CipWiz::SetParameter "UseReadFifo" "FALSE";
CipWiz::SetParameter "UseWriteFifo" "FALSE";
CipWiz::SetParameter "UseReadFifoPacketMode" "FALSE";
CipWiz::SetParameter "UseWriteFifoPacketMode" "FALSE";
CipWiz::SetParameter "UseReadFifoVacancyCalculation" "FALSE";
CipWiz::SetParameter "UseWriteFifoVacancyCalculation" "FALSE";
CipWiz::SetParameter "WriteFifoDataWidth" "0";
CipWiz::SetParameter "WriteFifoDepth" "0";
CipWiz::SetParameter "ReadFifoDataWidth" "0";
CipWiz::SetParameter "ReadFifoDepth" "0";
CipWiz::SetParameter "UseDeviceISC" "FALSE";
CipWiz::SetParameter "UseDevicePriorityEncoder" "FALSE";
CipWiz::SetParameter "NumberOfInterrupt" "1";
CipWiz::SetParameter "TypeOfInterrupt" "1";
CipWiz::SetParameter "TypeOfDMA" "0";
CipWiz::SetParameter "UseFastTransferProtocol" "FALSE";
CipWiz::SetParameter "BurstMaxSize" "0";
CipWiz::SetParameter "BurstPageSize" "0";
CipWiz::SetParameter "IncludeDPhaseTimer" "TRUE";
CipWiz::SetParameter "SlaveSideNativeDataWidth" "32";
CipWiz::SetParameter "SlaveBurstWriteBufferDepth" "16";
CipWiz::SetParameter "MasterSideNativeDataWidth" "0";
CipWiz::SetParameter "AXIMasterMaxBurstSize" "0";
CipWiz::SetParameter "AXIMasterWidthOfPort" "0";
CipWiz::SetParameter "AXIMasterAddrPipelineDepth" "0";
CipWiz::SetParameter "NumberOfUserRegister" "16";
CipWiz::SetParameter "UserRegisterDataWidth" "0";
CipWiz::SetParameter "WriteMode" "0";
CipWiz::SetParameter "HasInputFSL" "0";
CipWiz::SetParameter "HasOutputFSL" "0";
CipWiz::SetParameter "TotalInputData" "0";
CipWiz::SetParameter "TotalOutputData" "0";
CipWiz::SetParameter "NumOfInputArgs" "0";
CipWiz::SetParameter "NumOfOutputArgs" "0";
CipWiz::SetParameter "NumberOfUserMemoryBank" "2";
CipWiz::SetParameter "UserMemoryBankDataWidth" "0";
CipWiz::SetParameter "IpicSelectedPortNames" "Bus2IP_Clk|Bus2IP_Reset|Bus2IP_Addr|Bus2IP_CS|Bus2IP_RNW|Bus2IP_Data|Bus2IP_BE|Bus2IP_RdCE|Bus2IP_WrCE|Bus2IP_Burst|Bus2IP_BurstLength|Bus2IP_RdReq|Bus2IP_WrReq|IP2Bus_AddrAck|IP2Bus_Data|IP2Bus_RdAck|IP2Bus_WrAck|IP2Bus_Error|IP2Bus_IntrEvent|";
CipWiz::SetParameter "UserLogicModuleName" "0";
CipWiz::SetParameter "TypeOfUserLogicSource" "user_logic";
projnav/xps/pcores/spiifc_v1_00_a/devl/ipwiz.opt 0 → 100644
View file @ a64d58e7
-batch
-create spiifc
-ver 1.00.a
-dir "C:\Users\mjlyons\workspace\vSPI\projnav\xps"
-lang verilog
-bus plbv46 s
-burst s 32
-isc 1
-intrn 1 1
-reg 16
-mem 2
-wrbuf 16
-xps
-ise
-driver
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/fuse.xmsgs 0 → 100644
View file @ a64d58e7
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
</messages>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/fuseRelaunch.cmd 0 → 100644
View file @ a64d58e7
-intstyle "ise" -incremental -lib "unisims_ver" -lib "unimacro_ver" -lib "xilinxcorelib_ver" -lib "secureip" -o "C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc_writereg_tb_isim_beh.exe" -prj "C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc_writereg_tb_beh.prj" "work.spiifc_writereg_tb" "work.glbl"
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/impact.xsl 0 → 100644
View file @ a64d58e7
<xsl:stylesheet
xmlns:xsl="http://www.w3.org/1999/XSL/Transform"
version="1.0">
<xsl:output method="html"/>
<xsl:template match="/">
<b>
<xsl:text>Current iMPACT Usage Statistics.</xsl:text>
<br></br>
<xsl:text>Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.</xsl:text>
</b>
<br></br>
<br></br>
<xsl:text>This page displays the current iMPACT device usage statistics that will be sent to Xilinx using WebTalk.</xsl:text>
<table width = "100%" border="1" CELLSPACING="0" cols="50% 50%">
<xsl:for-each select="document/application/section">
<tr>
<th COLSPAN="2" BGCOLOR="#99CCFF"><xsl:value-of select="@name"/></th>
</tr>
<xsl:for-each select="property">
<tr>
<td><xsl:value-of select="@name"/></td>
<td><xsl:value-of select="@value"/></td>
</tr>
</xsl:for-each>
<xsl:for-each select="item">
<tr>
<td COLSPAN="2" BGCOLOR="#FFFF99"><b><xsl:value-of select="@name"/></b></td>
</tr>
<xsl:value-of select="@value"/>
<xsl:for-each select="property">
<tr>
<td><xsl:value-of select="@name"/></td>
<td><xsl:value-of select="@value"/>&#x20;</td>
</tr>
</xsl:for-each>
</xsl:for-each>
</xsl:for-each>
</table>
</xsl:template>
</xsl:stylesheet>
<!--
<xsl:if test="position() != last()"> <h1><xsl:text> </xsl:text></h1></xsl:if>
-->
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/impact_impact.xwbt 0 → 100644
View file @ a64d58e7
INTSTYLE=impact
INFILE=C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav\impact.xsl
OUTFILE=C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav\impact.xsl
FAMILY=Single
PART=Single
WORKINGDIR=C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav
LICENSE=iMPACT
USER_INFO=iMPACT
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/_xmsgs/cg.xmsgs 0 → 100644
View file @ a64d58e7
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="sim" num="0" delta="new" >Generating component instance &apos;<arg fmt="%s" index="1">spiloopmem</arg>&apos; of &apos;<arg fmt="%s" index="2">xilinx.com:ip:blk_mem_gen:6.2</arg>&apos; from &apos;<arg fmt="%s" index="3">C:\Xilinx\13.2\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\blk_mem_gen_v6_2\component.xml</arg>&apos;.
</msg>
</messages>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/_xmsgs/pn_parser.xmsgs 0 → 100644
View file @ a64d58e7
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated -->
<!-- by the Xilinx ISE software. Any direct editing or -->
<!-- changes made to this file may result in unpredictable -->
<!-- behavior or data corruption. It is strongly advised that -->
<!-- users do not edit the contents of this file. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
<messages>
<msg type="info" file="ProjectMgmt" num="1769" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/spiloopmem.v\&quot; into library work</arg>
</msg>
</messages>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/blk_mem_gen_v6_2_readme.txt 0 → 100644
View file @ a64d58e7
Core name: Xilinx LogiCORE Block Memory Generator
Version: 6.2
Release Date: June 22, 2011
================================================================================
This document contains the following sections:
1. Introduction
2. New Features
3. Supported Devices
4. Resolved Issues
5. Known Issues
6. Technical Support
7. Core Release History
8. Legal Disclaimer
================================================================================
1. INTRODUCTION
For installation instructions for this release, please go to:
http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
For system requirements:
http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
This file contains release notes for the Xilinx LogiCORE IP Block Memory Generator v6.2
solution. For the latest core updates, see the product page at:
http://www.xilinx.com/products/ipcenter/Block_Memory_Generator.htm
2. NEW FEATURES
- ISE 13.2 software support
- Virtex-7L, Kintex-7L, Artix-7* and Zynq-7000* device support
3. SUPPORTED DEVICES
The following device families are supported by the core for this release.
Zynq-7000*
Virtex-7
Virtex-7 XT (7vx485t)
Virtex-7 -2L
Kintex-7
Kintex-7 -2L
Artix-7*
Virtex-6 XC CXT/LXT/SXT/HXT
Virtex-6 XQ LXT/SXT
Virtex-6 -1L XQ LXT/SXT
Spartan-6 XC LX/LXT
Spartan-6 XA
Spartan-6 XQ LX/LXT
Spartan-6 -1L XQ LX
Virtex-5 XC LX/LXT/SXT/TXT/FXT
Virtex-5 XQ LX/ LXT/SXT/FXT
Virtex-4 XC LX/SX/FX
Virtex-4 XQ LX/SX/FX
Virtex-4 XQR LX/SX/FX
Spartan-3 XC
Spartan-3 XA
Spartan-3A XC 3A / 3A DSP / 3AN DSP
Spartan-3A XA 3A / 3A DSP
Spartan-3E XC
Spartan-3E XA
*To access these devices in the ISE Design Suite, contact your Xilinx FAE.
4. RESOLVED ISSUES
The following issues are resolved in Block Memory Generator v6.2:
1. Core errors in NGDBuild when the depth is too large (especially for Spartan-6 devices)
Version Fixed: v6.2
- CR 587481
- AR 39718
5. KNOWN ISSUES
The following are known issues for v6.2 of this core at time of release:
1. Virtex-6 and Spartan-6: BRAM Memory collision error, when the user selects TDP (write_mode= Read First)
Work around: The user must review the possible scenarios that causes the collission and revise
their design to avoid those situations.
- CR588505
Note: Refer to UG383, 'Conflict Avoidance' section when using TDP Memory - with
Write Mode = Read First in conjunction with asynchronous clocking
2. Power estimation figures in the datasheet are preliminary for Virtex-5 and Spartan-3.
3. Core does not generate for large memories. Depending on the
machine the ISE CORE Generator software runs on, the maximum size of the memory that
can be generated will vary. For example, a Dual Pentium-4 server
with 2 GB RAM can generate a memory core of size 1.8 MBits or 230 KBytes
- CR 415768
- AR 24034
The most recent information, including known issues, workarounds, and resolutions for
this version is provided in the IP Release Notes User Guide located at
www.xilinx.com/support/documentation/user_guides/xtp025.pdf
6. TECHNICAL SUPPORT
To obtain technical support, create a WebCase at www.xilinx.com/support.
Questions are routed to a team with expertise using this product.
Xilinx provides technical support for use of this product when used
according to the guidelines described in the core documentation, and
cannot guarantee timing, functionality, or support of this product for
designs that do not follow specified guidelines.
7. CORE RELEASE HISTORY
Date By Version Description
================================================================================
06/22/2011 Xilinx, Inc. 6.2 ISE 13.2 support;Virtex-7L,Kintex-7L,Artix7 and Zynq-7000* device support;
03/01/2011 Xilinx, Inc. 6.1 ISE 13.1 support and Virtex-7 and Kintex-7 device support; AXI4/AXI4-Lite Support
09/21/2010 Xilinx, Inc. 4.3 ISE 12.3 support
07/23/2010 Xilinx, Inc. 4.2 ISE 12.2 support
04/19/2010 Xilinx, Inc. 4.1 ISE 12.1 support
03/09/2010 Xilinx, Inc. 3.3 rev 2 Fix for V6 Memory collision issue
12/02/2009 Xilinx, Inc. 3.3 rev 1 ISE 11.4 support; Spartan-6 Low Power
Device support; Automotive Spartan 3A
DSP device support
09/16/2009 Xilinx, Inc. 3.3 Revised to v3.3
06/24/2009 Xilinx, Inc. 3.2 Revised to v3.2
04/24/2009 Xilinx, Inc. 3.1 Revised to v3.1
09/19/2008 Xilinx, Inc. 2.8 Revised to v2.8
03/24/2008 Xilinx, Inc. 2.7 10.1 support; Revised to v2.7
10/03/2007 Xilinx, Inc. 2.6 Revised to v2.6
07/2007 Xilinx, Inc. 2.5 Revised to v2.5
04/2007 Xilinx, Inc. 2.4 Revised to v2.4 rev 1
02/2007 Xilinx, Inc. 2.4 Revised to v2.4
11/2006 Xilinx, Inc. 2.3 Revised to v2.3
09/2006 Xilinx, Inc. 2.2 Revised to v2.2
06/2006 Xilinx, Inc. 2.1 Revised to v2.1
01/2006 Xilinx, Inc. 1.1 Initial release
================================================================================
8. Legal Disclaimer
(c) Copyright 2006 - 2011 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or Xilinx had been advised of the
possibility of the same.
CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of Xilinx products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem.asy 0 → 100644
View file @ a64d58e7
Version 4
SymbolType BLOCK
TEXT 32 32 LEFT 4 buffermem
RECTANGLE Normal 32 32 544 1376
LINE Wide 0 80 32 80
PIN 0 80 LEFT 36
PINATTR PinName addra[11:0]
PINATTR Polarity IN
LINE Wide 0 112 32 112
PIN 0 112 LEFT 36
PINATTR PinName dina[7:0]
PINATTR Polarity IN
LINE Normal 0 144 32 144
PIN 0 144 LEFT 36
PINATTR PinName ena
PINATTR Polarity IN
LINE Wide 0 208 32 208
PIN 0 208 LEFT 36
PINATTR PinName wea[0:0]
PINATTR Polarity IN
LINE Normal 0 272 32 272
PIN 0 272 LEFT 36
PINATTR PinName clka
PINATTR Polarity IN
LINE Wide 0 432 32 432
PIN 0 432 LEFT 36
PINATTR PinName addrb[9:0]
PINATTR Polarity IN
LINE Wide 0 464 32 464
PIN 0 464 LEFT 36
PINATTR PinName dinb[31:0]
PINATTR Polarity IN
LINE Normal 0 496 32 496
PIN 0 496 LEFT 36
PINATTR PinName enb
PINATTR Polarity IN
LINE Wide 0 560 32 560
PIN 0 560 LEFT 36
PINATTR PinName web[0:0]
PINATTR Polarity IN
LINE Normal 0 624 32 624
PIN 0 624 LEFT 36
PINATTR PinName clkb
PINATTR Polarity IN
LINE Wide 576 80 544 80
PIN 576 80 RIGHT 36
PINATTR PinName douta[7:0]
PINATTR Polarity OUT
LINE Wide 576 368 544 368
PIN 576 368 RIGHT 36
PINATTR PinName doutb[31:0]
PINATTR Polarity OUT
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem.gise 0 → 100644
View file @ a64d58e7
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="buffermem.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="blk_mem_gen_v6_2_readme.txt" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_ASY" xil_pn:name="buffermem.asy" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="buffermem.sym" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VEO" xil_pn:name="buffermem.veo" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
</generated_project>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem.ngc 0 → 100644
View file @ a64d58e7
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6e
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\ No newline at end of file
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem.sym 0 → 100644
View file @ a64d58e7
<?xml version="1.0" encoding="UTF-8"?>
<symbol version="7" name="buffermem">
<symboltype>BLOCK</symboltype>
<timestamp>2012-2-28T17:6:39</timestamp>
<pin polarity="Input" x="0" y="80" name="addra[11:0]" />
<pin polarity="Input" x="0" y="112" name="dina[7:0]" />
<pin polarity="Input" x="0" y="144" name="ena" />
<pin polarity="Input" x="0" y="208" name="wea[0:0]" />
<pin polarity="Input" x="0" y="272" name="clka" />
<pin polarity="Input" x="0" y="432" name="addrb[9:0]" />
<pin polarity="Input" x="0" y="464" name="dinb[31:0]" />
<pin polarity="Input" x="0" y="496" name="enb" />
<pin polarity="Input" x="0" y="560" name="web[0:0]" />
<pin polarity="Input" x="0" y="624" name="clkb" />
<pin polarity="Output" x="576" y="80" name="douta[7:0]" />
<pin polarity="Output" x="576" y="368" name="doutb[31:0]" />
<graph>
<text style="fontsize:40;fontname:Arial" x="32" y="32">buffermem</text>
<rect width="512" x="32" y="32" height="1344" />
<line x2="32" y1="80" y2="80" style="linewidth:W" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="80" type="pin addra[11:0]" />
<line x2="32" y1="112" y2="112" style="linewidth:W" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="112" type="pin dina[7:0]" />
<line x2="32" y1="144" y2="144" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="144" type="pin ena" />
<line x2="32" y1="208" y2="208" style="linewidth:W" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="208" type="pin wea[0:0]" />
<line x2="32" y1="272" y2="272" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="272" type="pin clka" />
<line x2="32" y1="432" y2="432" style="linewidth:W" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="432" type="pin addrb[9:0]" />
<line x2="32" y1="464" y2="464" style="linewidth:W" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="464" type="pin dinb[31:0]" />
<line x2="32" y1="496" y2="496" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="496" type="pin enb" />
<line x2="32" y1="560" y2="560" style="linewidth:W" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="560" type="pin web[0:0]" />
<line x2="32" y1="624" y2="624" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="624" type="pin clkb" />
<line x2="544" y1="80" y2="80" style="linewidth:W" x1="576" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="80" type="pin douta[7:0]" />
<line x2="544" y1="368" y2="368" style="linewidth:W" x1="576" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="368" type="pin doutb[31:0]" />
</graph>
</symbol>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem.v 0 → 100644
View file @ a64d58e7
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2012 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file buffermem.v when simulating
// the core, buffermem. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module buffermem(
clka,
ena,
wea,
addra,
dina,
douta,
clkb,
enb,
web,
addrb,
dinb,
doutb
);
input clka;
input ena;
input [0 : 0] wea;
input [11 : 0] addra;
input [7 : 0] dina;
output [7 : 0] douta;
input clkb;
input enb;
input [0 : 0] web;
input [9 : 0] addrb;
input [31 : 0] dinb;
output [31 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V6_2 #(
.C_ADDRA_WIDTH(12),
.C_ADDRB_WIDTH(10),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("spartan6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(1),
.C_HAS_ENB(1),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(2),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(4096),
.C_READ_DEPTH_B(1024),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(32),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(4096),
.C_WRITE_DEPTH_B(1024),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(32),
.C_XDEVICEFAMILY("spartan6")
)
inst (
.CLKA(clka),
.ENA(ena),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.CLKB(clkb),
.ENB(enb),
.WEB(web),
.ADDRB(addrb),
.DINB(dinb),
.DOUTB(doutb),
.RSTA(),
.REGCEA(),
.RSTB(),
.REGCEB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem.veo 0 → 100644
View file @ a64d58e7
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2012 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
/*******************************************************************************
* Generated from core with identifier: xilinx.com:ip:blk_mem_gen:6.2 *
* *
* The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port *
* Block Memory and Single Port Block Memory LogiCOREs, but is not a *
* direct drop-in replacement. It should be used in all new Xilinx *
* designs. The core supports RAM and ROM functions over a wide range of *
* widths and depths. Use this core to generate block memories with *
* symmetric or asymmetric read and write port widths, as well as cores *
* which can perform simultaneous write operations to separate *
* locations, and simultaneous read operations from the same location. *
* For more information on differences in interface and feature support *
* between this core and the Dual Port Block Memory and Single Port *
* Block Memory LogiCOREs, please consult the data sheet. *
*******************************************************************************/
// Interfaces:
// AXI_SLAVE_S_AXI
// AXILite_SLAVE_S_AXI
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
buffermem your_instance_name (
.clka(clka), // input clka
.ena(ena), // input ena
.wea(wea), // input [0 : 0] wea
.addra(addra), // input [11 : 0] addra
.dina(dina), // input [7 : 0] dina
.douta(douta), // output [7 : 0] douta
.clkb(clkb), // input clkb
.enb(enb), // input enb
.web(web), // input [0 : 0] web
.addrb(addrb), // input [9 : 0] addrb
.dinb(dinb), // input [31 : 0] dinb
.doutb(doutb) // output [31 : 0] doutb
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file buffermem.v when simulating
// the core, buffermem. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem.xco 0 → 100644
View file @ a64d58e7
##############################################################
#
# Xilinx Core Generator version 13.2
# Date: Tue Feb 28 17:05:52 2012
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:blk_mem_gen:6.2
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc6slx45
SET devicefamily = spartan6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = csg324
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.2
# END Select
# BEGIN Parameters
CSET additional_inputs_for_power_estimation=false
CSET algorithm=Minimum_Area
CSET assume_synchronous_clk=true
CSET axi_id_width=4
CSET axi_slave_type=Memory_Slave
CSET axi_type=AXI4_Full
CSET byte_size=9
CSET coe_file=no_coe_file_loaded
CSET collision_warnings=ALL
CSET component_name=buffermem
CSET disable_collision_warnings=false
CSET disable_out_of_range_warnings=false
CSET ecc=false
CSET ecctype=No_ECC
CSET enable_a=Use_ENA_Pin
CSET enable_b=Use_ENB_Pin
CSET error_injection_type=Single_Bit_Error_Injection
CSET fill_remaining_memory_locations=false
CSET interface_type=Native
CSET load_init_file=false
CSET memory_type=True_Dual_Port_RAM
CSET operating_mode_a=WRITE_FIRST
CSET operating_mode_b=WRITE_FIRST
CSET output_reset_value_a=0
CSET output_reset_value_b=0
CSET pipeline_stages=0
CSET port_a_clock=100
CSET port_a_enable_rate=100
CSET port_a_write_rate=50
CSET port_b_clock=100
CSET port_b_enable_rate=100
CSET port_b_write_rate=50
CSET primitive=8kx2
CSET read_width_a=8
CSET read_width_b=32
CSET register_porta_input_of_softecc=false
CSET register_porta_output_of_memory_core=false
CSET register_porta_output_of_memory_primitives=false
CSET register_portb_output_of_memory_core=false
CSET register_portb_output_of_memory_primitives=false
CSET register_portb_output_of_softecc=false
CSET remaining_memory_locations=0
CSET reset_memory_latch_a=false
CSET reset_memory_latch_b=false
CSET reset_priority_a=CE
CSET reset_priority_b=CE
CSET reset_type=SYNC
CSET softecc=false
CSET use_axi_id=false
CSET use_byte_write_enable=false
CSET use_error_injection_pins=false
CSET use_regcea_pin=false
CSET use_regceb_pin=false
CSET use_rsta_pin=false
CSET use_rstb_pin=false
CSET write_depth_a=4096
CSET write_width_a=8
CSET write_width_b=32
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2011-03-11T08:24:14.000Z
# END Extra information
GENERATE
# CRC: 1fb28621
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem.xise 0 → 100644
View file @ a64d58e7
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="13.2" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="buffermem.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="buffermem.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="5"/>
</file>
</files>
<properties>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx45" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|buffermem" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="buffermem.ngc" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/buffermem" xil_pn:valueState="non-default"/>
<property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="non-default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_DesignName" xil_pn:value="buffermem" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-02-28T12:06:44" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="154A8C82339948B49E3C581C44A6E851" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem_flist.txt 0 → 100644
View file @ a64d58e7
# Output products list for <buffermem>
blk_mem_gen_ds512.pdf
blk_mem_gen_v6_2_readme.txt
buffermem.asy
buffermem.gise
buffermem.ngc
buffermem.sym
buffermem.v
buffermem.veo
buffermem.xco
buffermem.xise
buffermem_flist.txt
buffermem_ste\example_design\bmg_wrapper.vhd
buffermem_ste\example_design\buffermem_top.ucf
buffermem_ste\example_design\buffermem_top.vhd
buffermem_ste\example_design\buffermem_top.xdc
buffermem_ste\implement\implement.sh
buffermem_ste\implement\planAhead_rdn.bat
buffermem_ste\implement\planAhead_rdn.sh
buffermem_ste\implement\planAhead_rdn.tcl
buffermem_ste\implement\xst.prj
buffermem_ste\implement\xst.scr
buffermem_xmdf.tcl
summary.log
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem_ste/example_design/bmg_wrapper.vhd 0 → 100644
View file @ a64d58e7
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v6.2 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: bmg_wrapper.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 2
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 0
-- C_INIT_FILE_NAME : no_coe_file_loaded
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 1
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 8
-- C_READ_WIDTH_A : 8
-- C_WRITE_DEPTH_A : 4096
-- C_READ_DEPTH_A : 4096
-- C_ADDRA_WIDTH : 12
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 1
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 32
-- C_READ_WIDTH_B : 32
-- C_WRITE_DEPTH_B : 1024
-- C_READ_DEPTH_B : 1024
-- C_ADDRB_WIDTH : 10
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 1
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY bmg_wrapper IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END bmg_wrapper;
ARCHITECTURE xilinx OF bmg_wrapper IS
COMPONENT buffermem_top IS
PORT (
--Port A
ENA : IN STD_LOGIC; --opt port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
ENB : IN STD_LOGIC; --opt port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : buffermem_top
PORT MAP (
--Port A
ENA => ENA,
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA,
--Port B
ENB => ENB,
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
CLKB => CLKB
);
END xilinx;
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem_ste/example_design/buffermem_top.ucf 0 → 100644
View file @ a64d58e7
################################################################################
#
# (c) Copyright 2002 - 2010 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
################################################################################
# Tx Core Period Constraint. This constraint can be modified, and is
# valid as long as it is met after place and route.
NET "CLKA" TNM_NET = "CLKA";
NET "CLKB" TNM_NET = "CLKB";
TIMESPEC "TS_CLKA" = PERIOD "CLKA" 25 MHZ;
TIMESPEC "TS_CLKB" = PERIOD "CLKB" 25 MHZ;
################################################################################
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem_ste/example_design/buffermem_top.vhd 0 → 100644
View file @ a64d58e7
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v6.2 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_wrapper.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY buffermem_top IS
PORT (
--Inputs - Port A
ENA : IN STD_LOGIC; --opt port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
ENB : IN STD_LOGIC; --opt port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END buffermem_top;
ARCHITECTURE xilinx OF buffermem_top IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT buffermem IS
PORT (
--Port A
ENA : IN STD_LOGIC; --opt port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
ENB : IN STD_LOGIC; --opt port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bufg_B : BUFG
PORT MAP (
I => CLKB,
O => CLKB_buf
);
bmg0 : buffermem
PORT MAP (
--Port A
ENA => ENA,
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA_buf,
--Port B
ENB => ENB,
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
CLKB => CLKB_buf
);
END xilinx;
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem_ste/example_design/buffermem_top.xdc 0 → 100644
View file @ a64d58e7
################################################################################
#
# (c) Copyright 2002 - 2011 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
################################################################################
# Core Period Constraint. This constraint can be modified, and is
# valid as long as it is met after place and route.
create_clock -name "TS_CLKA" -period 20.0 [ get_ports CLKA ]
create_clock -name "TS_CLKB" -period 20.0 [ get_ports CLKB ]
################################################################################
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem_ste/implement/implement.sh 0 → 100644
View file @ a64d58e7
#!/bin/sh
# Clean up the results directory
rm -rf results
mkdir results
#Synthesize the Wrapper Files
echo 'Synthesizing XST wrapper file (core_top.vhd) with XST';
echo 'Synthesizing example design with XST';
xst -ifn xst.scr
cp buffermem_top.ngc ./results/
# Copy the netlist generated by Coregen
echo 'Copying files from the netlist directory to the results directory'
cp ../../buffermem.ngc results/
# Copy the constraints files generated by Coregen
echo 'Copying files from constraints directory to results directory'
cp ../example_design/buffermem_top.ucf results/
cd results
echo 'Running ngdbuild'
ngdbuild -p xc6slx45-csg324-2 buffermem_top
echo 'Running map'
map buffermem_top -o mapped.ncd -pr i
echo 'Running par'
par mapped.ncd routed.ncd
echo 'Running trce'
trce -e 10 routed.ncd mapped.pcf -o routed
echo 'Running design through bitgen'
bitgen -w routed
echo 'Running netgen to create gate level Verilog model'
netgen -ofmt verilog -sim -tm buffermem_top -pcf mapped.pcf -w routed.ncd routed.v
cp routed.sdf ../../production/timing/
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem_ste/implement/planAhead_rdn.bat 0 → 100644
View file @ a64d58e7
#!/bin/sh
rem (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
rem
rem This file contains confidential and proprietary information
rem of Xilinx, Inc. and is protected under U.S. and
rem international copyright and other intellectual property
rem laws.
rem
rem DISCLAIMER
rem This disclaimer is not a license and does not grant any
rem rights to the materials distributed herewith. Except as
rem otherwise provided in a valid license issued to you by
rem Xilinx, and to the maximum extent permitted by applicable
rem law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
rem WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
rem AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
rem BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
rem INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
rem (2) Xilinx shall not be liable (whether in contract or tort,
rem including negligence, or under any other theory of
rem liability) for any loss or damage of any kind or nature
rem related to, arising under or in connection with these
rem materials, including for any direct, or any indirect,
rem special, incidental, or consequential loss or damage
rem (including loss of data, profits, goodwill, or any type of
rem loss or damage suffered as a result of any action brought
rem by a third party) even if such damage or loss was
rem reasonably foreseeable or Xilinx had been advised of the
rem possibility of the same.
rem
rem CRITICAL APPLICATIONS
rem Xilinx products are not designed or intended to be fail-
rem safe, or for use in any application requiring fail-safe
rem performance, such as life-support or safety devices or
rem systems, Class III medical devices, nuclear facilities,
rem applications related to the deployment of airbags, or any
rem other applications that could lead to death, personal
rem injury, or severe property or environmental damage
rem (individually and collectively, "Critical
rem Applications"). Customer assumes the sole risk and
rem liability of any use of Xilinx products in Critical
rem Applications, subject only to applicable laws and
rem regulations governing limitations on product liability.
rem
rem THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
rem PART OF THIS FILE AT ALL TIMES.
rem -----------------------------------------------------------------------------
rem Script to synthesize and implement the Coregen FIFO Generator
rem -----------------------------------------------------------------------------
rmdir /S /Q results
mkdir results
cd results
copy ..\..\..\tmp\buffermem.edf .
planAhead -mode batch -source ..\planAhead_rdn.tcl
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem_ste/implement/planAhead_rdn.sh 0 → 100644
View file @ a64d58e7
#!/bin/sh
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#-----------------------------------------------------------------------------
# Script to synthesize and implement the Coregen FIFO Generator
#-----------------------------------------------------------------------------
rm -rf results
mkdir results
cd results
cp ../../../tmp/buffermem.edf .
planAhead -mode batch -source ../planAhead_rdn.tcl
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem_ste/implement/planAhead_rdn.tcl 0 → 100644
View file @ a64d58e7
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
set device xc6slx45csg324-2
set projName buffermem
set design buffermem
set projDir [file dirname [info script]]
create_project $projName $projDir/results/$projName -part $device -force
set_property design_mode RTL [current_fileset -srcset]
set top_module buffermem_top
add_files -norecurse {../../example_design/buffermem_top.vhd}
add_files -norecurse {./buffermem.edf}
import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/buffermem_top.xdc}
set_property top buffermem_top [get_property srcset [current_run]]
synth_design
opt_design
place_design
route_design
write_sdf -rename_top_module buffermem_top -file routed.sdf
write_verilog -nolib -mode sim -sdf_anno false -rename_top_module buffermem_top routed.v
report_timing -nworst 30 -path_type full -file routed.twr
report_drc -file routed.drc
#write_bitstream
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem_ste/implement/xst.scr 0 → 100644
View file @ a64d58e7
run
-ifmt VHDL
-ent buffermem_top
-p xc6slx45-csg324-2
-ifn xst.prj
-write_timing_constraints No
-iobuf YES
-max_fanout 100
-ofn buffermem_top
-ofmt NGC
-bus_delimiter ()
-hierarchy_separator /
-case Maintain
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem_xmdf.tcl 0 → 100644
View file @ a64d58e7
# The package naming convention is <core_name>_xmdf
package provide buffermem_xmdf 1.0
# This includes some utilities that support common XMDF operations
package require utilities_xmdf
# Define a namespace for this package. The name of the name space
# is <core_name>_xmdf
namespace eval ::buffermem_xmdf {
# Use this to define any statics
}
# Function called by client to rebuild the params and port arrays
# Optional when the use context does not require the param or ports
# arrays to be available.
proc ::buffermem_xmdf::xmdfInit { instance } {
# Variable containing name of library into which module is compiled
# Recommendation: <module_name>
# Required
utilities_xmdf::xmdfSetData $instance Module Attributes Name buffermem
}
# ::buffermem_xmdf::xmdfInit
# Function called by client to fill in all the xmdf* data variables
# based on the current settings of the parameters
proc ::buffermem_xmdf::xmdfApplyParams { instance } {
set fcount 0
# Array containing libraries that are assumed to exist
# Examples include unisim and xilinxcorelib
# Optional
# In this example, we assume that the unisim library will
# be available to the simulation and synthesis tool
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_ds512.pdf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v6_2_readme.txt
utilities_xmdf::xmdfSetData $instance FileSet $fcount type text
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path buffermem.asy
utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path buffermem.ngc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path buffermem.sym
utilities_xmdf::xmdfSetData $instance FileSet $fcount type symbol
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path buffermem.v
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path buffermem.veo
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path buffermem.xco
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path buffermem_ste/example_design/bmg_wrapper.vhd
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path buffermem_ste/example_design/buffermem_top.ucf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path buffermem_ste/example_design/buffermem_top.vhd
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path buffermem_ste/example_design/buffermem_top.xdc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path buffermem_ste/implement/implement.sh
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path buffermem_ste/implement/planAhead_rdn.bat
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path buffermem_ste/implement/planAhead_rdn.sh
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path buffermem_ste/implement/planAhead_rdn.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path buffermem_ste/implement/xst.prj
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path buffermem_ste/implement/xst.scr
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path buffermem_xmdf.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path summary.log
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module buffermem
incr fcount
}
# ::gen_comp_name_xmdf::xmdfApplyParams
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/coregen.cgc 0 → 100644
View file @ a64d58e7
<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xmlns:xilinx="http://www.xilinx.com" >
<spirit:vendor>xilinx.com</spirit:vendor>
<spirit:library>project</spirit:library>
<spirit:name>coregen</spirit:name>
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<spirit:componentInstance>
<spirit:instanceName>buffermem</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="blk_mem_gen" spirit:version="6.2" />
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.COMPONENT_NAME">buffermem</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_TYPE">AXI4_Full</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_SLAVE_TYPE">Memory_Slave</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_AXI_ID">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_ID_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MEMORY_TYPE">True_Dual_Port_RAM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ECCTYPE">No_ECC</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ECC">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SOFTECC">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_ERROR_INJECTION_PINS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ERROR_INJECTION_TYPE">Single_Bit_Error_Injection</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BYTE_WRITE_ENABLE">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BYTE_SIZE">9</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ALGORITHM">Minimum_Area</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMITIVE">8kx2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ASSUME_SYNCHRONOUS_CLK">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_WIDTH_A">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_DEPTH_A">4096</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WIDTH_A">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OPERATING_MODE_A">WRITE_FIRST</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_A">Use_ENA_Pin</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_WIDTH_B">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WIDTH_B">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OPERATING_MODE_B">WRITE_FIRST</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_B">Use_ENB_Pin</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_PORTA_OUTPUT_OF_MEMORY_PRIMITIVES">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_PORTA_OUTPUT_OF_MEMORY_CORE">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_REGCEA_PIN">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_PORTB_OUTPUT_OF_MEMORY_PRIMITIVES">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_PORTB_OUTPUT_OF_MEMORY_CORE">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_REGCEB_PIN">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_PORTA_INPUT_OF_SOFTECC">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_PORTB_OUTPUT_OF_SOFTECC">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PIPELINE_STAGES">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOAD_INIT_FILE">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.COE_FILE">no_coe_file_loaded</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FILL_REMAINING_MEMORY_LOCATIONS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REMAINING_MEMORY_LOCATIONS">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_RSTA_PIN">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_MEMORY_LATCH_A">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PRIORITY_A">CE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OUTPUT_RESET_VALUE_A">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_RSTB_PIN">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_MEMORY_LATCH_B">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PRIORITY_B">CE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OUTPUT_RESET_VALUE_B">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_TYPE">SYNC</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDITIONAL_INPUTS_FOR_POWER_ESTIMATION">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PORT_A_CLOCK">100</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PORT_A_WRITE_RATE">50</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PORT_B_CLOCK">100</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PORT_B_WRITE_RATE">50</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PORT_A_ENABLE_RATE">100</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PORT_B_ENABLE_RATE">100</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.COLLISION_WARNINGS">ALL</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DISABLE_COLLISION_WARNINGS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DISABLE_OUT_OF_RANGE_WARNINGS">false</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
<xilinx:instanceProperties xmlns:xilinx="http://www.xilinx.com">
<xilinx:projectOptions>
<xilinx:projectName>coregen</xilinx:projectName>
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<xilinx:workingDirectory>./tmp/</xilinx:workingDirectory>
<xilinx:subWorkingDirectory>./tmp/_cg/</xilinx:subWorkingDirectory>
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<xilinx:part>
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<xilinx:speedGrade>-2</xilinx:speedGrade>
</xilinx:part>
<xilinx:flowOptions>
<xilinx:busFormat>BusFormatAngleBracketNotRipped</xilinx:busFormat>
<xilinx:designEntry>Verilog</xilinx:designEntry>
<xilinx:asySymbol>true</xilinx:asySymbol>
<xilinx:flowVendor>Other</xilinx:flowVendor>
<xilinx:addPads>false</xilinx:addPads>
<xilinx:removeRPMs>false</xilinx:removeRPMs>
<xilinx:createNDF>false</xilinx:createNDF>
<xilinx:implementationFileType>Ngc</xilinx:implementationFileType>
<xilinx:formalVerification>false</xilinx:formalVerification>
</xilinx:flowOptions>
<xilinx:simulationOptions>
<xilinx:simulationModel>Behavioral</xilinx:simulationModel>
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<xilinx:foundationSym>false</xilinx:foundationSym>
</xilinx:simulationOptions>
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<xilinx:sourceCoreCreationDate>2011-03-11T08:24:14.000Z</xilinx:sourceCoreCreationDate>
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</spirit:componentInstance>
<spirit:componentInstance>
<spirit:instanceName>spiloopmem</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="blk_mem_gen" spirit:version="6.2" />
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.COMPONENT_NAME">spiloopmem</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_TYPE">Native</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_TYPE">AXI4_Full</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_SLAVE_TYPE">Memory_Slave</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_AXI_ID">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_ID_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MEMORY_TYPE">Simple_Dual_Port_RAM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ECCTYPE">No_ECC</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ECC">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SOFTECC">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_ERROR_INJECTION_PINS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ERROR_INJECTION_TYPE">Single_Bit_Error_Injection</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BYTE_WRITE_ENABLE">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.BYTE_SIZE">9</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ALGORITHM">Minimum_Area</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMITIVE">8kx2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ASSUME_SYNCHRONOUS_CLK">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_WIDTH_A">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_DEPTH_A">4096</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WIDTH_A">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OPERATING_MODE_A">WRITE_FIRST</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_A">Use_ENA_Pin</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.WRITE_WIDTH_B">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_WIDTH_B">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OPERATING_MODE_B">WRITE_FIRST</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_B">Use_ENB_Pin</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_PORTA_OUTPUT_OF_MEMORY_PRIMITIVES">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_PORTA_OUTPUT_OF_MEMORY_CORE">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_REGCEA_PIN">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_PORTB_OUTPUT_OF_MEMORY_PRIMITIVES">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_PORTB_OUTPUT_OF_MEMORY_CORE">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_REGCEB_PIN">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_PORTA_INPUT_OF_SOFTECC">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REGISTER_PORTB_OUTPUT_OF_SOFTECC">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PIPELINE_STAGES">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOAD_INIT_FILE">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.COE_FILE">no_coe_file_loaded</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FILL_REMAINING_MEMORY_LOCATIONS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REMAINING_MEMORY_LOCATIONS">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_RSTA_PIN">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_MEMORY_LATCH_A">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PRIORITY_A">CE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OUTPUT_RESET_VALUE_A">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_RSTB_PIN">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_MEMORY_LATCH_B">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PRIORITY_B">CE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OUTPUT_RESET_VALUE_B">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_TYPE">SYNC</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ADDITIONAL_INPUTS_FOR_POWER_ESTIMATION">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PORT_A_CLOCK">100</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PORT_A_WRITE_RATE">50</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PORT_B_CLOCK">100</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PORT_B_WRITE_RATE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PORT_A_ENABLE_RATE">100</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PORT_B_ENABLE_RATE">100</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.COLLISION_WARNINGS">ALL</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DISABLE_COLLISION_WARNINGS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DISABLE_OUT_OF_RANGE_WARNINGS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">spartan6</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">spartan6</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ELABORATION_DIR">C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_cg/</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_SLAVE_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEM_TYPE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_BYTE_SIZE">9</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALGORITHM">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_TYPE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOAD_INIT_FILE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_FILE_NAME">no_coe_file_loaded</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_DATA">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_DATA">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RST_TYPE">SYNC</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RSTA">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RST_PRIORITY_A">CE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RSTRAM_A">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INITA_VAL">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ENA">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_REGCEA">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BYTE_WEA">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEA_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_A">WRITE_FIRST</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_A">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_WIDTH_A">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_A">4096</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_A">4096</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRA_WIDTH">12</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RSTB">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RST_PRIORITY_B">CE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RSTRAM_B">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INITB_VAL">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ENB">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_REGCEB">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BYTE_WEB">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEB_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_B">WRITE_FIRST</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_B">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_WIDTH_B">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_B">4096</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_B">4096</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRB_WIDTH">12</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_A">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_B">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_A">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MUX_OUTPUT_REGS_B">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MUX_PIPELINE_STAGES">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SOFTECC_INPUT_REGS_A">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SOFTECC_OUTPUT_REGS_B">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SOFTECC">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INJECTERR">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SIM_COLLISION_CHECK">ALL</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLK">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_COLL">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_RANGE">0</spirit:configurableElementValue>
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<xilinx:package>csg324</xilinx:package>
<xilinx:speedGrade>-2</xilinx:speedGrade>
</xilinx:part>
<xilinx:flowOptions>
<xilinx:busFormat>BusFormatAngleBracketNotRipped</xilinx:busFormat>
<xilinx:designEntry>Verilog</xilinx:designEntry>
<xilinx:asySymbol>true</xilinx:asySymbol>
<xilinx:flowVendor>Other</xilinx:flowVendor>
<xilinx:addPads>false</xilinx:addPads>
<xilinx:removeRPMs>false</xilinx:removeRPMs>
<xilinx:createNDF>false</xilinx:createNDF>
<xilinx:implementationFileType>Ngc</xilinx:implementationFileType>
<xilinx:formalVerification>false</xilinx:formalVerification>
</xilinx:flowOptions>
<xilinx:simulationOptions>
<xilinx:simulationModel>Behavioral</xilinx:simulationModel>
<xilinx:simulationLanguage>Verilog</xilinx:simulationLanguage>
<xilinx:foundationSym>false</xilinx:foundationSym>
</xilinx:simulationOptions>
<xilinx:packageInfo>
<xilinx:sourceCoreCreationDate>2011-03-11T08:24:14.000Z</xilinx:sourceCoreCreationDate>
</xilinx:packageInfo>
</xilinx:instanceProperties>
<xilinx:generationHistory>
<xilinx:fileSet>
<xilinx:name>apply_current_project_options_generator</xilinx:name>
</xilinx:fileSet>
<xilinx:fileSet>
<xilinx:name>customization_generator</xilinx:name>
<xilinx:file>
<xilinx:name>./summary.log</xilinx:name>
<xilinx:userFileType>unknown</xilinx:userFileType>
<xilinx:timeStamp>Wed Mar 07 22:04:50 GMT 2012</xilinx:timeStamp>
<xilinx:checkSum>0x5BD51164</xilinx:checkSum>
<xilinx:generationId>generationid_615106653</xilinx:generationId>
</xilinx:file>
</xilinx:fileSet>
<xilinx:fileSet>
<xilinx:name>model_parameter_resolution_generator</xilinx:name>
<xilinx:file>
<xilinx:name>./summary.log</xilinx:name>
<xilinx:userFileType>unknown</xilinx:userFileType>
<xilinx:timeStamp>Wed Mar 07 22:04:54 GMT 2012</xilinx:timeStamp>
<xilinx:checkSum>0x5BD51164</xilinx:checkSum>
<xilinx:generationId>generationid_615106653</xilinx:generationId>
</xilinx:file>
</xilinx:fileSet>
<xilinx:fileSet>
<xilinx:name>ip_xco_generator</xilinx:name>
<xilinx:file>
<xilinx:name>./spiloopmem.xco</xilinx:name>
<xilinx:userFileType>xco</xilinx:userFileType>
<xilinx:timeStamp>Wed Mar 07 22:04:54 GMT 2012</xilinx:timeStamp>
<xilinx:checkSum>0xEE47DCC6</xilinx:checkSum>
<xilinx:generationId>generationid_615106653</xilinx:generationId>
</xilinx:file>
</xilinx:fileSet>
<xilinx:fileSet>
<xilinx:name>associated_files_generator</xilinx:name>
<xilinx:file>
<xilinx:name>./blk_mem_gen_ds512.pdf</xilinx:name>
<xilinx:userFileType>pdf</xilinx:userFileType>
<xilinx:timeStamp>Tue Jun 21 05:21:31 GMT 2011</xilinx:timeStamp>
<xilinx:checkSum>0xA43B8952</xilinx:checkSum>
<xilinx:generationId>generationid_615106653</xilinx:generationId>
</xilinx:file>
<xilinx:file>
<xilinx:name>./blk_mem_gen_v6_2_readme.txt</xilinx:name>
<xilinx:userFileType>txt</xilinx:userFileType>
<xilinx:timeStamp>Tue Jun 21 05:21:31 GMT 2011</xilinx:timeStamp>
<xilinx:checkSum>0x399E1D72</xilinx:checkSum>
<xilinx:generationId>generationid_615106653</xilinx:generationId>
</xilinx:file>
</xilinx:fileSet>
<xilinx:fileSet>
<xilinx:name>ejava_generator</xilinx:name>
<xilinx:file>
<xilinx:name>./spiloopmem_ste/example_design/bmg_wrapper.vhd</xilinx:name>
<xilinx:userFileType>ignore</xilinx:userFileType>
<xilinx:userFileType>vhdl</xilinx:userFileType>
<xilinx:timeStamp>Wed Mar 07 22:04:55 GMT 2012</xilinx:timeStamp>
<xilinx:checkSum>0x7F99DB77</xilinx:checkSum>
<xilinx:generationId>generationid_615106653</xilinx:generationId>
</xilinx:file>
<xilinx:file>
<xilinx:name>./spiloopmem_ste/example_design/spiloopmem_top.ucf</xilinx:name>
<xilinx:userFileType>ignore</xilinx:userFileType>
<xilinx:userFileType>ucf</xilinx:userFileType>
<xilinx:timeStamp>Wed Mar 07 22:04:55 GMT 2012</xilinx:timeStamp>
<xilinx:checkSum>0x8915DFA1</xilinx:checkSum>
<xilinx:generationId>generationid_615106653</xilinx:generationId>
</xilinx:file>
<xilinx:file>
<xilinx:name>./spiloopmem_ste/example_design/spiloopmem_top.vhd</xilinx:name>
<xilinx:userFileType>ignore</xilinx:userFileType>
<xilinx:userFileType>vhdl</xilinx:userFileType>
<xilinx:timeStamp>Wed Mar 07 22:04:55 GMT 2012</xilinx:timeStamp>
<xilinx:checkSum>0xAFD5224E</xilinx:checkSum>
<xilinx:generationId>generationid_615106653</xilinx:generationId>
</xilinx:file>
<xilinx:file>
<xilinx:name>./spiloopmem_ste/example_design/spiloopmem_top.xdc</xilinx:name>
<xilinx:userFileType>ignore</xilinx:userFileType>
<xilinx:userFileType>xdc</xilinx:userFileType>
<xilinx:timeStamp>Wed Mar 07 22:04:55 GMT 2012</xilinx:timeStamp>
<xilinx:checkSum>0x78E2D49A</xilinx:checkSum>
<xilinx:generationId>generationid_615106653</xilinx:generationId>
</xilinx:file>
<xilinx:file>
<xilinx:name>./spiloopmem_ste/implement/implement.sh</xilinx:name>
<xilinx:userFileType>ignore</xilinx:userFileType>
<xilinx:userFileType>unknown</xilinx:userFileType>
<xilinx:timeStamp>Wed Mar 07 22:04:55 GMT 2012</xilinx:timeStamp>
<xilinx:checkSum>0x452D832D</xilinx:checkSum>
<xilinx:generationId>generationid_615106653</xilinx:generationId>
</xilinx:file>
<xilinx:file>
<xilinx:name>./spiloopmem_ste/implement/planAhead_rdn.bat</xilinx:name>
<xilinx:userFileType>ignore</xilinx:userFileType>
<xilinx:userFileType>unknown</xilinx:userFileType>
<xilinx:timeStamp>Wed Mar 07 22:04:55 GMT 2012</xilinx:timeStamp>
<xilinx:checkSum>0x9360D2FC</xilinx:checkSum>
<xilinx:generationId>generationid_615106653</xilinx:generationId>
</xilinx:file>
<xilinx:file>
<xilinx:name>./spiloopmem_ste/implement/planAhead_rdn.sh</xilinx:name>
<xilinx:userFileType>ignore</xilinx:userFileType>
<xilinx:userFileType>unknown</xilinx:userFileType>
<xilinx:timeStamp>Wed Mar 07 22:04:55 GMT 2012</xilinx:timeStamp>
<xilinx:checkSum>0x46307551</xilinx:checkSum>
<xilinx:generationId>generationid_615106653</xilinx:generationId>
</xilinx:file>
<xilinx:file>
<xilinx:name>./spiloopmem_ste/implement/planAhead_rdn.tcl</xilinx:name>
<xilinx:userFileType>ignore</xilinx:userFileType>
<xilinx:userFileType>tcl</xilinx:userFileType>
<xilinx:timeStamp>Wed Mar 07 22:04:55 GMT 2012</xilinx:timeStamp>
<xilinx:checkSum>0xEA63E4A4</xilinx:checkSum>
<xilinx:generationId>generationid_615106653</xilinx:generationId>
</xilinx:file>
<xilinx:file>
<xilinx:name>./spiloopmem_ste/implement/xst.prj</xilinx:name>
<xilinx:userFileType>ignore</xilinx:userFileType>
<xilinx:userFileType>unknown</xilinx:userFileType>
<xilinx:timeStamp>Wed Mar 07 22:04:55 GMT 2012</xilinx:timeStamp>
<xilinx:checkSum>0xE2E3ED6D</xilinx:checkSum>
<xilinx:generationId>generationid_615106653</xilinx:generationId>
</xilinx:file>
<xilinx:file>
<xilinx:name>./spiloopmem_ste/implement/xst.scr</xilinx:name>
<xilinx:userFileType>ignore</xilinx:userFileType>
<xilinx:userFileType>unknown</xilinx:userFileType>
<xilinx:timeStamp>Wed Mar 07 22:04:55 GMT 2012</xilinx:timeStamp>
<xilinx:checkSum>0x04885ED0</xilinx:checkSum>
<xilinx:generationId>generationid_615106653</xilinx:generationId>
</xilinx:file>
</xilinx:fileSet>
<xilinx:fileSet>
<xilinx:name>ngc_netlist_generator</xilinx:name>
<xilinx:file>
<xilinx:name>./spiloopmem.ngc</xilinx:name>
<xilinx:userFileType>ngc</xilinx:userFileType>
<xilinx:timeStamp>Wed Mar 07 22:05:31 GMT 2012</xilinx:timeStamp>
<xilinx:checkSum>0x64C2FFF1</xilinx:checkSum>
<xilinx:generationId>generationid_615106653</xilinx:generationId>
</xilinx:file>
</xilinx:fileSet>
<xilinx:fileSet>
<xilinx:name>obfuscate_netlist_generator</xilinx:name>
</xilinx:fileSet>
<xilinx:fileSet>
<xilinx:name>padded_implementation_netlist_generator</xilinx:name>
</xilinx:fileSet>
<xilinx:fileSet>
<xilinx:name>instantiation_template_generator</xilinx:name>
<xilinx:file>
<xilinx:name>./spiloopmem.veo</xilinx:name>
<xilinx:userFileType>veo</xilinx:userFileType>
<xilinx:timeStamp>Wed Mar 07 22:05:33 GMT 2012</xilinx:timeStamp>
<xilinx:checkSum>0xF74D6B91</xilinx:checkSum>
<xilinx:generationId>generationid_615106653</xilinx:generationId>
</xilinx:file>
</xilinx:fileSet>
<xilinx:fileSet>
<xilinx:name>structural_simulation_model_generator</xilinx:name>
<xilinx:file>
<xilinx:name>./spiloopmem.v</xilinx:name>
<xilinx:userFileType>verilog</xilinx:userFileType>
<xilinx:timeStamp>Wed Mar 07 22:05:33 GMT 2012</xilinx:timeStamp>
<xilinx:checkSum>0xC7F34980</xilinx:checkSum>
<xilinx:generationId>generationid_615106653</xilinx:generationId>
</xilinx:file>
</xilinx:fileSet>
<xilinx:fileSet>
<xilinx:name>asy_generator</xilinx:name>
<xilinx:file>
<xilinx:name>./spiloopmem.asy</xilinx:name>
<xilinx:userFileType>asy</xilinx:userFileType>
<xilinx:timeStamp>Wed Mar 07 22:05:39 GMT 2012</xilinx:timeStamp>
<xilinx:checkSum>0x83946D8F</xilinx:checkSum>
<xilinx:generationId>generationid_615106653</xilinx:generationId>
</xilinx:file>
<xilinx:file>
<xilinx:name>./summary.log</xilinx:name>
<xilinx:userFileType>unknown</xilinx:userFileType>
<xilinx:timeStamp>Wed Mar 07 22:05:39 GMT 2012</xilinx:timeStamp>
<xilinx:checkSum>0x5BD51164</xilinx:checkSum>
<xilinx:generationId>generationid_615106653</xilinx:generationId>
</xilinx:file>
</xilinx:fileSet>
<xilinx:fileSet>
<xilinx:name>xmdf_generator</xilinx:name>
<xilinx:file>
<xilinx:name>./spiloopmem_xmdf.tcl</xilinx:name>
<xilinx:userFileType>tclXmdf</xilinx:userFileType>
<xilinx:userFileType>tcl</xilinx:userFileType>
<xilinx:timeStamp>Wed Mar 07 22:05:39 GMT 2012</xilinx:timeStamp>
<xilinx:checkSum>0xD51D4C14</xilinx:checkSum>
<xilinx:generationId>generationid_615106653</xilinx:generationId>
</xilinx:file>
</xilinx:fileSet>
<xilinx:fileSet>
<xilinx:name>ise_generator</xilinx:name>
<xilinx:file>
<xilinx:name>./_xmsgs/pn_parser.xmsgs</xilinx:name>
<xilinx:userFileType>ignore</xilinx:userFileType>
<xilinx:userFileType>unknown</xilinx:userFileType>
<xilinx:timeStamp>Wed Mar 07 22:05:42 GMT 2012</xilinx:timeStamp>
<xilinx:checkSum>0x24C9CB1C</xilinx:checkSum>
<xilinx:generationId>generationid_615106653</xilinx:generationId>
</xilinx:file>
<xilinx:file>
<xilinx:name>./spiloopmem.gise</xilinx:name>
<xilinx:userFileType>ignore</xilinx:userFileType>
<xilinx:userFileType>gise</xilinx:userFileType>
<xilinx:timeStamp>Wed Mar 07 22:05:43 GMT 2012</xilinx:timeStamp>
<xilinx:checkSum>0xF8869E9A</xilinx:checkSum>
<xilinx:generationId>generationid_615106653</xilinx:generationId>
</xilinx:file>
<xilinx:file>
<xilinx:name>./spiloopmem.xise</xilinx:name>
<xilinx:userFileType>ignore</xilinx:userFileType>
<xilinx:userFileType>xise</xilinx:userFileType>
<xilinx:timeStamp>Wed Mar 07 22:05:43 GMT 2012</xilinx:timeStamp>
<xilinx:checkSum>0xAB45B7A7</xilinx:checkSum>
<xilinx:generationId>generationid_615106653</xilinx:generationId>
</xilinx:file>
</xilinx:fileSet>
<xilinx:fileSet>
<xilinx:name>deliver_readme_generator</xilinx:name>
</xilinx:fileSet>
<xilinx:fileSet>
<xilinx:name>flist_generator</xilinx:name>
<xilinx:file>
<xilinx:name>./spiloopmem_flist.txt</xilinx:name>
<xilinx:userFileType>ignore</xilinx:userFileType>
<xilinx:userFileType>txtFlist</xilinx:userFileType>
<xilinx:userFileType>txt</xilinx:userFileType>
<xilinx:timeStamp>Wed Mar 07 22:05:43 GMT 2012</xilinx:timeStamp>
<xilinx:checkSum>0xCE30C720</xilinx:checkSum>
<xilinx:generationId>generationid_615106653</xilinx:generationId>
</xilinx:file>
</xilinx:fileSet>
<xilinx:fileSet>
<xilinx:name>view_readme_generator</xilinx:name>
</xilinx:fileSet>
</xilinx:generationHistory>
</spirit:vendorExtensions>
</spirit:componentInstance>
</spirit:componentInstances>
<spirit:vendorExtensions>
<xilinx:instanceProperties>
<xilinx:projectOptions>
<xilinx:projectName>coregen</xilinx:projectName>
<xilinx:outputDirectory>./</xilinx:outputDirectory>
<xilinx:workingDirectory>./tmp/</xilinx:workingDirectory>
<xilinx:subWorkingDirectory>./tmp/_cg/</xilinx:subWorkingDirectory>
</xilinx:projectOptions>
<xilinx:part>
<xilinx:device>xc6slx45</xilinx:device>
<xilinx:deviceFamily>spartan6</xilinx:deviceFamily>
<xilinx:package>csg324</xilinx:package>
<xilinx:speedGrade>-2</xilinx:speedGrade>
</xilinx:part>
<xilinx:flowOptions>
<xilinx:busFormat>BusFormatAngleBracketNotRipped</xilinx:busFormat>
<xilinx:designEntry>Verilog</xilinx:designEntry>
<xilinx:asySymbol>true</xilinx:asySymbol>
<xilinx:flowVendor>Other</xilinx:flowVendor>
<xilinx:addPads>false</xilinx:addPads>
<xilinx:removeRPMs>false</xilinx:removeRPMs>
<xilinx:createNDF>false</xilinx:createNDF>
<xilinx:implementationFileType>Ngc</xilinx:implementationFileType>
<xilinx:formalVerification>false</xilinx:formalVerification>
</xilinx:flowOptions>
<xilinx:simulationOptions>
<xilinx:simulationModel>Behavioral</xilinx:simulationModel>
<xilinx:simulationLanguage>Verilog</xilinx:simulationLanguage>
<xilinx:foundationSym>false</xilinx:foundationSym>
</xilinx:simulationOptions>
</xilinx:instanceProperties>
</spirit:vendorExtensions>
</spirit:design>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/coregen.cgp 0 → 100644
View file @ a64d58e7
SET busformat = BusFormatAngleBracketNotRipped
SET designentry = Verilog
SET device = xc6slx45
SET devicefamily = spartan6
SET flowvendor = Other
SET package = csg324
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = false
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/create_buffermem.tcl 0 → 100644
View file @ a64d58e7
##
## Core Generator Run Script, generator for Project Navigator create command
##
proc findRtfPath { relativePath } {
set xilenv ""
if { [info exists ::env(XILINX) ] } {
if { [info exists ::env(MYXILINX)] } {
set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]
} else {
set xilenv $::env(XILINX)
}
}
foreach path [ split $xilenv $::xilinx::path_sep ] {
set fullPath [ file join $path $relativePath ]
if { [ file exists $fullPath ] } {
return $fullPath
}
}
return ""
}
source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
set result [ run_cg_create "xilinx.com:ip:blk_mem_gen:6.2" "buffermem" "Block Memory Generator" "Block Memory Generator (xilinx.com:ip:blk_mem_gen:6.2) generated by Project Navigator" xc6slx45-2csg324 Verilog ]
if { $result == 0 } {
puts "Core Generator create command completed successfully."
} elseif { $result == 1 } {
puts "Core Generator create command failed."
} elseif { $result == 3 || $result == 4 } {
# convert 'version check' result to real return range, bypassing any messages.
set result [ expr $result - 3 ]
} else {
puts "Core Generator create cancelled."
}
exit $result
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/create_spiloopmem.tcl 0 → 100644
View file @ a64d58e7
##
## Core Generator Run Script, generator for Project Navigator create command
##
proc findRtfPath { relativePath } {
set xilenv ""
if { [info exists ::env(XILINX) ] } {
if { [info exists ::env(MYXILINX)] } {
set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]
} else {
set xilenv $::env(XILINX)
}
}
foreach path [ split $xilenv $::xilinx::path_sep ] {
set fullPath [ file join $path $relativePath ]
if { [ file exists $fullPath ] } {
return $fullPath
}
}
return ""
}
source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
set result [ run_cg_create "xilinx.com:ip:blk_mem_gen:6.2" "spiloopmem" "Block Memory Generator" "Block Memory Generator (xilinx.com:ip:blk_mem_gen:6.2) generated by Project Navigator" xc6slx45-2csg324 Verilog ]
if { $result == 0 } {
puts "Core Generator create command completed successfully."
} elseif { $result == 1 } {
puts "Core Generator create command failed."
} elseif { $result == 3 || $result == 4 } {
# convert 'version check' result to real return range, bypassing any messages.
set result [ expr $result - 3 ]
} else {
puts "Core Generator create cancelled."
}
exit $result
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/edit_spiloopmem.tcl 0 → 100644
View file @ a64d58e7
##
## Core Generator Run Script, generator for Project Navigator edit command
##
proc findRtfPath { relativePath } {
set xilenv ""
if { [info exists ::env(XILINX) ] } {
if { [info exists ::env(MYXILINX)] } {
set xilenv [join [list $::env(MYXILINX) $::env(XILINX)] $::xilinx::path_sep ]
} else {
set xilenv $::env(XILINX)
}
}
foreach path [ split $xilenv $::xilinx::path_sep ] {
set fullPath [ file join $path $relativePath ]
if { [ file exists $fullPath ] } {
return $fullPath
}
}
return ""
}
source [ findRtfPath "data/projnav/scripts/dpm_cgUtils.tcl" ]
set result [ run_cg_edit "spiloopmem" xc6slx45-2csg324 Verilog ]
if { $result == 0 } {
puts "Core Generator edit command completed successfully."
} elseif { $result == 1 } {
puts "Core Generator edit command failed."
} elseif { $result == 3 || $result == 4 } {
# convert 'version check' result to real return range, bypassing any messages.
set result [ expr $result - 3 ]
} else {
puts "Core Generator edit cancelled."
}
exit $result
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/spiloopmem.asy 0 → 100644
View file @ a64d58e7
Version 4
SymbolType BLOCK
TEXT 32 32 LEFT 4 spiloopmem
RECTANGLE Normal 32 32 544 1376
LINE Wide 0 80 32 80
PIN 0 80 LEFT 36
PINATTR PinName addra[11:0]
PINATTR Polarity IN
LINE Wide 0 112 32 112
PIN 0 112 LEFT 36
PINATTR PinName dina[7:0]
PINATTR Polarity IN
LINE Normal 0 144 32 144
PIN 0 144 LEFT 36
PINATTR PinName ena
PINATTR Polarity IN
LINE Wide 0 208 32 208
PIN 0 208 LEFT 36
PINATTR PinName wea[0:0]
PINATTR Polarity IN
LINE Normal 0 272 32 272
PIN 0 272 LEFT 36
PINATTR PinName clka
PINATTR Polarity IN
LINE Wide 0 432 32 432
PIN 0 432 LEFT 36
PINATTR PinName addrb[11:0]
PINATTR Polarity IN
LINE Normal 0 496 32 496
PIN 0 496 LEFT 36
PINATTR PinName enb
PINATTR Polarity IN
LINE Normal 0 624 32 624
PIN 0 624 LEFT 36
PINATTR PinName clkb
PINATTR Polarity IN
LINE Wide 576 368 544 368
PIN 576 368 RIGHT 36
PINATTR PinName doutb[7:0]
PINATTR Polarity OUT
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/spiloopmem.gise 0 → 100644
View file @ a64d58e7
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="spiloopmem.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="blk_mem_gen_v6_2_readme.txt" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_ASY" xil_pn:name="spiloopmem.asy" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="spiloopmem.sym" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VEO" xil_pn:name="spiloopmem.veo" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
</generated_project>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/spiloopmem.ngc 0 → 100644
View file @ a64d58e7
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6e
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4202?20b<:9:038?l33290/=995699m510=9;10e8=50;&202<102d:8;4>3:9j17<72-;?;787;o372?7332c>=7>5$064>3><f8>=6<;4;h53>5<#9==1:55a154953=<a?l1<7*>4685<>h6<?0:;65f6d83>!73?3<37c?;6;3;?>o1l3:1(<:8:7:8j42128307d8l:18'511=>11e=9851`98m3d=83.:8:498:l203<6j21b:l4?:%373?0?3g;?:7?l;:k52?6=,8><6;64n065>4b<3`?i6=4+15592==i9=<1=h54i4294?"6<>0=46`>4782b>=z{8>:6=4n1z?22c<bn27:9n4>c:?21f<6>27:9n4=b:?21f<5=27:9n499:?21f<1?27:9n495:?21f<1<27:9n493:?21f<1:27:9n491:?21f<1827:9n4:f:?21f<2m27:9n4:d:?21f<2k27:9n4:a:?21f<2127:9n4:8:?21f<2?27:9n4:6:?21f<2=27:9n4:4:?21f<2;27:9n4:2:?21f<2927:9n480:?21f<1n27:9n49e:?21f<1l27:9n49c:?21f<1j27:9n47a:?21f<?027:9n476:?21f<?=27:9n474:?21f<?;27:9n472:?21f<?927:9n470:?21f<0n27:9n48e:?21f<0l27:9n48b:?21f<0i27:9n489:?21f<0027:9n487:?21f<0>27:9n485:?21f<0<27:9n483:?21f<0:27:9n461:?21f<>827:9n47f:?21f<?m27:9n47d:?21f<?k27:9n47b:?21f<??27:9n48c:?21f<0927:9n466:?21f<><27:9n463:?21f<>:27:9n46b:?21f<>127:9n468:?21f<>?27:9n4>689>50e=9?=01<;l:045?872k3;=963>5b820d=:9<i1=9l4=07`>42d34;>o7?;d:?21a<6k27:9i4>6:?21a<5j27:9i4=5:?21a<1127:9i497:?21a<1=27:9i494:?21a<1;27:9i492:?21a<1927:9i490:?21a<2n27:9i4:e:?21a<2l27:9i4:c:?21a<2i27:9i4:9:?21a<2027:9i4:7:?21a<2>27:9i4:5:?21a<2<27:9i4:3:?21a<2:27:9i4:1:?21a<0827:9i49f:?21a<1m27:9i49d:?21a<1k27:9i49b:?21a<?i27:9i478:?21a<?>27:9i475:?21a<?<27:9i473:?21a<?:27:9i471:?21a<?827:9i48f:?21a<0m27:9i48d:?21a<0j27:9i48a:?21a<0127:9i488:?21a<0?27:9i486:?21a<0=27:9i484:?21a<0;27:9i482:?21a<>927:9i460:?21a<?n27:9i47e:?21a<?l27:9i47c:?21a<?j27:9i477:?21a<0k27:9i481:?21a<>>27:9i464:?21a<>;27:9i462:?21a<>j27:9i469:?21a<>027:9i467:?21a<6>016=8j51758943c28<=70?:d;351>;6=m0:8l5214f951d<58?o6<:l;<36`?73l2wx=l950;0xZ4g034;>o7lj;|q2e=<72;qU=l64=07`>f?<uz;j57>52z\2e<=:9<i1h95rs0cb>5<5sW;jm63>5b8g<>{t9hh1<7<t^0ca?872l3hn7p}>ab83>7}Y9hi01<;k:b;8yv7fl3:1>vP>ae9>50b=l=1v<oi:181[7fn27:9i4k8:p5g7=839pR<l>;<36g?ce34;>h7km;|q2=a<72:qU=4j4=07`>15<58?o69=4}r3a4?6=;rT:n=5214a9ad=:9<n1il5rs0;`>5<4sW;2o63>5b80a>;6=m08i6s|19694?5|V82?70?:c;0`?872l38h7p}>8983>6}Y91201<;l:3f8943c2;n0q~?79;297~X60016=8m52d9>50b=:l1v<6n:180[7?i27:9n4=f:?21a<5n2wx=5l50;1xZ4>e34;>o7=?;<36`?573ty:4n4?:2y]5=e<58?h6>?4=07g>67<uz;3h7>53z\2<a=:9<i1??5214f977=z{82n6=4<{_3;a>;6=j08?63>5e807>{t91l1<7=t^0:e?872k38=70?:d;05?xu6190;6>uQ1828943d2;=01<;k:358yv7?=3:1?vP>849>50e=:116=8j5299~w4>02908wS?77:?21f<5i27:9i4=a:p5<c=838pR<7j;<36g?373ty:5k4?:3y]5<`<58?h68l4}r3b4?6=:rT:m=5214a923=z{8k:6=4={_3b5>;6=j0=m6s|1`094?4|V8k970?:d;73?xu6i:0;6?uQ1`18943c2<h0q~?n4;296~X6i=16=8j5679~w4g12909wS?n6:?21a<1i2wx=:950;1xZ41034;>o7?k;<36`?7c3ty:;o4?:2y]52d<58?h6<k4=07g>4c<uz;<o7>53z\23f=:9<i1=k5214f95c=z{8=o6=4<{_34`>;6=j09<63>5e814>{t9>o1<7=t^05f?872k38:70?:d;02?xu6?o0;6>uQ16d8943d2;801<;k:308yv7?83:1?vP>819>50e=::16=8j5229~w4>62908wS?71:?21f<5<27:9i4=4:p5=4=839pR<6=;<36g?7034;>h7?8;|q2<6<72:qU=5=4=07`>4><58?o6<64}r34<?6=;rT:;55214a95<=:9<n1=45rs05b>5<4sW;<m63>5b82f>;6=m0:n6s|1c594??|V8h<70?:c;350>;6=j0::?5214a9537<58?h6<8?;<36`?71<27:9i4>639>50b=9?;01<;k:043?x{i9k>1<7?tH07f?xh6j<0;6<uG14g8yk7e>3:1=vF>5d9~j4d0290:wE?:e:m5g>=83;pD<;j;|l2f<<728qC=8k4}o3ae?6=9rB:9h5rn0`a>5<6sA;>i6sa1ca94?7|@8?n7p`>be83>4}O9<o0qc?me;295~N6=l1vb<li:182M72m2we=n>50;3xL43b3td:o<4?:0yK50c<ug;h>7>51zJ21`=zf8i86=4>{I36a>{i9j>1<7?tH07f?xh6k<0;6<uG14g8yk7d>3:1=vF>5d9~j4e0290:wE?:e:m5f>=83;pD<;j;|l2g<<728qC=8k4}o3`e?6=9rB:9h5rn0aa>5<6sA;>i6sa1ba94?7|@8?n7p`>ce83>4}O9<o0qc?le;295~N6=l1vb<mi:182M72m2we=i>50;3xL43b3td:h<4?:0yK50c<ug;o>7>51zJ21`=zf8n86=4>{I36a>{i9m>1<7?tH07f?xh6l<0;6<uG14g8yk7c>3:1=vF>5d9~j4b0290:wE?:e:m5a>=83;pD<;j;|l2`<<728qC=8k4}o3ge?6=9rB:9h5rn0fa>5<6sA;>i6sa1ea94?7|@8?n7p`>de83>4}O9<o0qc?ke;295~N6=l1vb<ji:182M72m2we=h>50;3xL43b3td:i<4?:0yK50c<utwvLMMt20295d?djk<<qMNM{1CDU}zHI
\ No newline at end of file
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/spiloopmem.sym 0 → 100644
View file @ a64d58e7
<?xml version="1.0" encoding="UTF-8"?>
<symbol version="7" name="spiloopmem">
<symboltype>BLOCK</symboltype>
<timestamp>2012-3-7T21:47:40</timestamp>
<pin polarity="Input" x="0" y="80" name="addra[11:0]" />
<pin polarity="Input" x="0" y="144" name="ena" />
<pin polarity="Input" x="0" y="272" name="clka" />
<pin polarity="Input" x="0" y="432" name="addrb[11:0]" />
<pin polarity="Input" x="0" y="496" name="enb" />
<pin polarity="Input" x="0" y="624" name="clkb" />
<pin polarity="Output" x="576" y="80" name="douta[7:0]" />
<pin polarity="Output" x="576" y="368" name="doutb[7:0]" />
<graph>
<text style="fontsize:40;fontname:Arial" x="32" y="32">spiloopmem</text>
<rect width="512" x="32" y="32" height="1344" />
<line x2="32" y1="80" y2="80" style="linewidth:W" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="80" type="pin addra[11:0]" />
<line x2="32" y1="144" y2="144" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="144" type="pin ena" />
<line x2="32" y1="272" y2="272" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="272" type="pin clka" />
<line x2="32" y1="432" y2="432" style="linewidth:W" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="432" type="pin addrb[11:0]" />
<line x2="32" y1="496" y2="496" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="496" type="pin enb" />
<line x2="32" y1="624" y2="624" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="624" type="pin clkb" />
<line x2="544" y1="80" y2="80" style="linewidth:W" x1="576" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="80" type="pin douta[7:0]" />
<line x2="544" y1="368" y2="368" style="linewidth:W" x1="576" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="368" type="pin doutb[7:0]" />
</graph>
</symbol>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/spiloopmem.v 0 → 100644
View file @ a64d58e7
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2012 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file spiloopmem.v when simulating
// the core, spiloopmem. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module spiloopmem(
clka,
ena,
wea,
addra,
dina,
clkb,
enb,
addrb,
doutb
);
input clka;
input ena;
input [0 : 0] wea;
input [11 : 0] addra;
input [7 : 0] dina;
input clkb;
input enb;
input [11 : 0] addrb;
output [7 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V6_2 #(
.C_ADDRA_WIDTH(12),
.C_ADDRB_WIDTH(12),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(0),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("spartan6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(1),
.C_HAS_ENB(1),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(1),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(4096),
.C_READ_DEPTH_B(4096),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(8),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(4096),
.C_WRITE_DEPTH_B(4096),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(8),
.C_XDEVICEFAMILY("spartan6")
)
inst (
.CLKA(clka),
.ENA(ena),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.CLKB(clkb),
.ENB(enb),
.ADDRB(addrb),
.DOUTB(doutb),
.RSTA(),
.REGCEA(),
.DOUTA(),
.RSTB(),
.REGCEB(),
.WEB(),
.DINB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/spiloopmem.veo 0 → 100644
View file @ a64d58e7
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2012 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
/*******************************************************************************
* Generated from core with identifier: xilinx.com:ip:blk_mem_gen:6.2 *
* *
* The Xilinx LogiCORE IP Block Memory Generator replaces the Dual Port *
* Block Memory and Single Port Block Memory LogiCOREs, but is not a *
* direct drop-in replacement. It should be used in all new Xilinx *
* designs. The core supports RAM and ROM functions over a wide range of *
* widths and depths. Use this core to generate block memories with *
* symmetric or asymmetric read and write port widths, as well as cores *
* which can perform simultaneous write operations to separate *
* locations, and simultaneous read operations from the same location. *
* For more information on differences in interface and feature support *
* between this core and the Dual Port Block Memory and Single Port *
* Block Memory LogiCOREs, please consult the data sheet. *
*******************************************************************************/
// Interfaces:
// AXI_SLAVE_S_AXI
// AXILite_SLAVE_S_AXI
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
spiloopmem your_instance_name (
.clka(clka), // input clka
.ena(ena), // input ena
.wea(wea), // input [0 : 0] wea
.addra(addra), // input [11 : 0] addra
.dina(dina), // input [7 : 0] dina
.clkb(clkb), // input clkb
.enb(enb), // input enb
.addrb(addrb), // input [11 : 0] addrb
.doutb(doutb) // output [7 : 0] doutb
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file spiloopmem.v when simulating
// the core, spiloopmem. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/spiloopmem.xco 0 → 100644
View file @ a64d58e7
##############################################################
#
# Xilinx Core Generator version 13.2
# Date: Wed Mar 07 22:04:54 2012
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# Generated from component: xilinx.com:ip:blk_mem_gen:6.2
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc6slx45
SET devicefamily = spartan6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = csg324
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -2
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT Block_Memory_Generator xilinx.com:ip:blk_mem_gen:6.2
# END Select
# BEGIN Parameters
CSET additional_inputs_for_power_estimation=false
CSET algorithm=Minimum_Area
CSET assume_synchronous_clk=false
CSET axi_id_width=4
CSET axi_slave_type=Memory_Slave
CSET axi_type=AXI4_Full
CSET byte_size=9
CSET coe_file=no_coe_file_loaded
CSET collision_warnings=ALL
CSET component_name=spiloopmem
CSET disable_collision_warnings=false
CSET disable_out_of_range_warnings=false
CSET ecc=false
CSET ecctype=No_ECC
CSET enable_a=Use_ENA_Pin
CSET enable_b=Use_ENB_Pin
CSET error_injection_type=Single_Bit_Error_Injection
CSET fill_remaining_memory_locations=false
CSET interface_type=Native
CSET load_init_file=false
CSET memory_type=Simple_Dual_Port_RAM
CSET operating_mode_a=WRITE_FIRST
CSET operating_mode_b=WRITE_FIRST
CSET output_reset_value_a=0
CSET output_reset_value_b=0
CSET pipeline_stages=0
CSET port_a_clock=100
CSET port_a_enable_rate=100
CSET port_a_write_rate=50
CSET port_b_clock=100
CSET port_b_enable_rate=100
CSET port_b_write_rate=0
CSET primitive=8kx2
CSET read_width_a=8
CSET read_width_b=8
CSET register_porta_input_of_softecc=false
CSET register_porta_output_of_memory_core=false
CSET register_porta_output_of_memory_primitives=false
CSET register_portb_output_of_memory_core=false
CSET register_portb_output_of_memory_primitives=false
CSET register_portb_output_of_softecc=false
CSET remaining_memory_locations=0
CSET reset_memory_latch_a=false
CSET reset_memory_latch_b=false
CSET reset_priority_a=CE
CSET reset_priority_b=CE
CSET reset_type=SYNC
CSET softecc=false
CSET use_axi_id=false
CSET use_byte_write_enable=false
CSET use_error_injection_pins=false
CSET use_regcea_pin=false
CSET use_regceb_pin=false
CSET use_rsta_pin=false
CSET use_rstb_pin=false
CSET write_depth_a=4096
CSET write_width_a=8
CSET write_width_b=8
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2011-03-11T08:24:14.000Z
# END Extra information
GENERATE
# CRC: f197b839
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/spiloopmem.xise 0 → 100644
View file @ a64d58e7
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="13.2" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="spiloopmem.ngc" xil_pn:type="FILE_NGC">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="spiloopmem.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="4"/>
</file>
</files>
<properties>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx45" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Stop View" xil_pn:value="PreSynthesis" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|spiloopmem" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="spiloopmem.ngc" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/spiloopmem" xil_pn:valueState="non-default"/>
<property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="non-default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Project Generator" xil_pn:value="CoreGen" xil_pn:valueState="non-default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_DesignName" xil_pn:value="spiloopmem" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-03-07T17:05:42" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="C2B01838CC5744EE9AD3C0D68A2179D8" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/spiloopmem_flist.txt 0 → 100644
View file @ a64d58e7
# Output products list for <spiloopmem>
_xmsgs\pn_parser.xmsgs
blk_mem_gen_ds512.pdf
blk_mem_gen_v6_2_readme.txt
spiloopmem.asy
spiloopmem.gise
spiloopmem.ngc
spiloopmem.v
spiloopmem.veo
spiloopmem.xco
spiloopmem.xise
spiloopmem_flist.txt
spiloopmem_ste\example_design\bmg_wrapper.vhd
spiloopmem_ste\example_design\spiloopmem_top.ucf
spiloopmem_ste\example_design\spiloopmem_top.vhd
spiloopmem_ste\example_design\spiloopmem_top.xdc
spiloopmem_ste\implement\implement.sh
spiloopmem_ste\implement\planAhead_rdn.bat
spiloopmem_ste\implement\planAhead_rdn.sh
spiloopmem_ste\implement\planAhead_rdn.tcl
spiloopmem_ste\implement\xst.prj
spiloopmem_ste\implement\xst.scr
spiloopmem_xmdf.tcl
summary.log
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/spiloopmem_ste/example_design/bmg_wrapper.vhd 0 → 100644
View file @ a64d58e7
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v6.2 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: bmg_wrapper.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : spartan6
-- C_XDEVICEFAMILY : spartan6
-- C_INTERFACE_TYPE : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 1
-- C_BYTE_SIZE : 9
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 0
-- C_INIT_FILE_NAME : no_coe_file_loaded
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 1
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 0
-- C_WEA_WIDTH : 1
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 8
-- C_READ_WIDTH_A : 8
-- C_WRITE_DEPTH_A : 4096
-- C_READ_DEPTH_A : 4096
-- C_ADDRA_WIDTH : 12
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 1
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 0
-- C_WEB_WIDTH : 1
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 8
-- C_READ_WIDTH_B : 8
-- C_WRITE_DEPTH_B : 4096
-- C_READ_DEPTH_B : 4096
-- C_ADDRB_WIDTH : 12
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 0
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY bmg_wrapper IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END bmg_wrapper;
ARCHITECTURE xilinx OF bmg_wrapper IS
COMPONENT spiloopmem_top IS
PORT (
--Port A
ENA : IN STD_LOGIC; --opt port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
ENB : IN STD_LOGIC; --opt port
ADDRB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : spiloopmem_top
PORT MAP (
--Port A
ENA => ENA,
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
CLKA => CLKA,
--Port B
ENB => ENB,
ADDRB => ADDRB,
DOUTB => DOUTB,
CLKB => CLKB
);
END xilinx;
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/spiloopmem_ste/example_design/spiloopmem_top.ucf 0 → 100644
View file @ a64d58e7
################################################################################
#
# (c) Copyright 2002 - 2010 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
################################################################################
# Tx Core Period Constraint. This constraint can be modified, and is
# valid as long as it is met after place and route.
NET "CLKA" TNM_NET = "CLKA";
NET "CLKB" TNM_NET = "CLKB";
TIMESPEC "TS_CLKA" = PERIOD "CLKA" 25 MHZ;
TIMESPEC "TS_CLKB" = PERIOD "CLKB" 25 MHZ;
################################################################################
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/spiloopmem_ste/example_design/spiloopmem_top.vhd 0 → 100644
View file @ a64d58e7
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v6.2 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_wrapper.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY spiloopmem_top IS
PORT (
--Inputs - Port A
ENA : IN STD_LOGIC; --opt port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Inputs - Port B
ENB : IN STD_LOGIC; --opt port
ADDRB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END spiloopmem_top;
ARCHITECTURE xilinx OF spiloopmem_top IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT spiloopmem IS
PORT (
--Port A
ENA : IN STD_LOGIC; --opt port
WEA : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
ENB : IN STD_LOGIC; --opt port
ADDRB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bufg_B : BUFG
PORT MAP (
I => CLKB,
O => CLKB_buf
);
bmg0 : spiloopmem
PORT MAP (
--Port A
ENA => ENA,
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
CLKA => CLKA_buf,
--Port B
ENB => ENB,
ADDRB => ADDRB,
DOUTB => DOUTB,
CLKB => CLKB_buf
);
END xilinx;
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/spiloopmem_ste/example_design/spiloopmem_top.xdc 0 → 100644
View file @ a64d58e7
################################################################################
#
# (c) Copyright 2002 - 2011 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#
################################################################################
# Core Period Constraint. This constraint can be modified, and is
# valid as long as it is met after place and route.
create_clock -name "TS_CLKA" -period 20.0 [ get_ports CLKA ]
create_clock -name "TS_CLKB" -period 20.0 [ get_ports CLKB ]
################################################################################
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/spiloopmem_ste/implement/implement.sh 0 → 100644
View file @ a64d58e7
#!/bin/sh
# Clean up the results directory
rm -rf results
mkdir results
#Synthesize the Wrapper Files
echo 'Synthesizing XST wrapper file (core_top.vhd) with XST';
echo 'Synthesizing example design with XST';
xst -ifn xst.scr
cp spiloopmem_top.ngc ./results/
# Copy the netlist generated by Coregen
echo 'Copying files from the netlist directory to the results directory'
cp ../../spiloopmem.ngc results/
# Copy the constraints files generated by Coregen
echo 'Copying files from constraints directory to results directory'
cp ../example_design/spiloopmem_top.ucf results/
cd results
echo 'Running ngdbuild'
ngdbuild -p xc6slx45-csg324-2 spiloopmem_top
echo 'Running map'
map spiloopmem_top -o mapped.ncd -pr i
echo 'Running par'
par mapped.ncd routed.ncd
echo 'Running trce'
trce -e 10 routed.ncd mapped.pcf -o routed
echo 'Running design through bitgen'
bitgen -w routed
echo 'Running netgen to create gate level Verilog model'
netgen -ofmt verilog -sim -tm spiloopmem_top -pcf mapped.pcf -w routed.ncd routed.v
cp routed.sdf ../../production/timing/
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/spiloopmem_ste/implement/planAhead_rdn.bat 0 → 100644
View file @ a64d58e7
#!/bin/sh
rem (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
rem
rem This file contains confidential and proprietary information
rem of Xilinx, Inc. and is protected under U.S. and
rem international copyright and other intellectual property
rem laws.
rem
rem DISCLAIMER
rem This disclaimer is not a license and does not grant any
rem rights to the materials distributed herewith. Except as
rem otherwise provided in a valid license issued to you by
rem Xilinx, and to the maximum extent permitted by applicable
rem law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
rem WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
rem AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
rem BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
rem INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
rem (2) Xilinx shall not be liable (whether in contract or tort,
rem including negligence, or under any other theory of
rem liability) for any loss or damage of any kind or nature
rem related to, arising under or in connection with these
rem materials, including for any direct, or any indirect,
rem special, incidental, or consequential loss or damage
rem (including loss of data, profits, goodwill, or any type of
rem loss or damage suffered as a result of any action brought
rem by a third party) even if such damage or loss was
rem reasonably foreseeable or Xilinx had been advised of the
rem possibility of the same.
rem
rem CRITICAL APPLICATIONS
rem Xilinx products are not designed or intended to be fail-
rem safe, or for use in any application requiring fail-safe
rem performance, such as life-support or safety devices or
rem systems, Class III medical devices, nuclear facilities,
rem applications related to the deployment of airbags, or any
rem other applications that could lead to death, personal
rem injury, or severe property or environmental damage
rem (individually and collectively, "Critical
rem Applications"). Customer assumes the sole risk and
rem liability of any use of Xilinx products in Critical
rem Applications, subject only to applicable laws and
rem regulations governing limitations on product liability.
rem
rem THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
rem PART OF THIS FILE AT ALL TIMES.
rem -----------------------------------------------------------------------------
rem Script to synthesize and implement the Coregen FIFO Generator
rem -----------------------------------------------------------------------------
rmdir /S /Q results
mkdir results
cd results
copy ..\..\..\tmp\spiloopmem.edf .
planAhead -mode batch -source ..\planAhead_rdn.tcl
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/spiloopmem_ste/implement/planAhead_rdn.sh 0 → 100644
View file @ a64d58e7
#!/bin/sh
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
#-----------------------------------------------------------------------------
# Script to synthesize and implement the Coregen FIFO Generator
#-----------------------------------------------------------------------------
rm -rf results
mkdir results
cd results
cp ../../../tmp/spiloopmem.edf .
planAhead -mode batch -source ../planAhead_rdn.tcl
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/spiloopmem_ste/implement/planAhead_rdn.tcl 0 → 100644
View file @ a64d58e7
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
set device xc6slx45csg324-2
set projName spiloopmem
set design spiloopmem
set projDir [file dirname [info script]]
create_project $projName $projDir/results/$projName -part $device -force
set_property design_mode RTL [current_fileset -srcset]
set top_module spiloopmem_top
add_files -norecurse {../../example_design/spiloopmem_top.vhd}
add_files -norecurse {./spiloopmem.edf}
import_files -fileset [get_filesets constrs_1] -force -norecurse {../../example_design/spiloopmem_top.xdc}
set_property top spiloopmem_top [get_property srcset [current_run]]
synth_design
opt_design
place_design
route_design
write_sdf -rename_top_module spiloopmem_top -file routed.sdf
write_verilog -nolib -mode sim -sdf_anno false -rename_top_module spiloopmem_top routed.v
report_timing -nworst 30 -path_type full -file routed.twr
report_drc -file routed.drc
#write_bitstream
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/spiloopmem_ste/implement/xst.scr 0 → 100644
View file @ a64d58e7
run
-ifmt VHDL
-ent spiloopmem_top
-p xc6slx45-csg324-2
-ifn xst.prj
-write_timing_constraints No
-iobuf YES
-max_fanout 100
-ofn spiloopmem_top
-ofmt NGC
-bus_delimiter ()
-hierarchy_separator /
-case Maintain
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/spiloopmem_xmdf.tcl 0 → 100644
View file @ a64d58e7
# The package naming convention is <core_name>_xmdf
package provide spiloopmem_xmdf 1.0
# This includes some utilities that support common XMDF operations
package require utilities_xmdf
# Define a namespace for this package. The name of the name space
# is <core_name>_xmdf
namespace eval ::spiloopmem_xmdf {
# Use this to define any statics
}
# Function called by client to rebuild the params and port arrays
# Optional when the use context does not require the param or ports
# arrays to be available.
proc ::spiloopmem_xmdf::xmdfInit { instance } {
# Variable containing name of library into which module is compiled
# Recommendation: <module_name>
# Required
utilities_xmdf::xmdfSetData $instance Module Attributes Name spiloopmem
}
# ::spiloopmem_xmdf::xmdfInit
# Function called by client to fill in all the xmdf* data variables
# based on the current settings of the parameters
proc ::spiloopmem_xmdf::xmdfApplyParams { instance } {
set fcount 0
# Array containing libraries that are assumed to exist
# Examples include unisim and xilinxcorelib
# Optional
# In this example, we assume that the unisim library will
# be available to the simulation and synthesis tool
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_ds512.pdf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path blk_mem_gen_v6_2_readme.txt
utilities_xmdf::xmdfSetData $instance FileSet $fcount type text
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path spiloopmem.asy
utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path spiloopmem.ngc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path spiloopmem.v
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path spiloopmem.veo
utilities_xmdf::xmdfSetData $instance FileSet $fcount type verilog_template
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path spiloopmem.xco
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path spiloopmem_ste/example_design/bmg_wrapper.vhd
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path spiloopmem_ste/example_design/spiloopmem_top.ucf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path spiloopmem_ste/example_design/spiloopmem_top.vhd
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path spiloopmem_ste/example_design/spiloopmem_top.xdc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path spiloopmem_ste/implement/implement.sh
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path spiloopmem_ste/implement/planAhead_rdn.bat
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path spiloopmem_ste/implement/planAhead_rdn.sh
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path spiloopmem_ste/implement/planAhead_rdn.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path spiloopmem_ste/implement/xst.prj
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path spiloopmem_ste/implement/xst.scr
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path spiloopmem_xmdf.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path summary.log
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module spiloopmem
incr fcount
}
# ::gen_comp_name_xmdf::xmdfApplyParams
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/summary.log 0 → 100644
View file @ a64d58e7
User Configuration
-------------------------------------
Algorithm : Minimum_Area
Memory Type : Simple_Dual_Port_RAM
Port A Write Width : 8
Port B Read Width : 8
Memory Depth : 4096
--------------------------------------------------------------
Block RAM resource(s) (9K BRAMs) : 0
Block RAM resource(s) (18K BRAMs) : 2
--------------------------------------------------------------
Clock A Frequency : 100
Port A Enable Rate : 100
Port A Write Rate : 50
----------------------------------------------------------
Estimated Power for IP : 5.357579 mW
----------------------------------------------------------
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_cg/_dbg/xil_53.in 0 → 100644
View file @ a64d58e7
SET_FLAG DEBUG FALSE
SET_FLAG MODE INTERACTIVE
SET_FLAG STANDALONE_MODE FALSE
SET_PREFERENCE devicefamily spartan6
SET_PREFERENCE device xc6slx45
SET_PREFERENCE speedgrade -2
SET_PREFERENCE package csg324
SET_PREFERENCE verilogsim true
SET_PREFERENCE vhdlsim false
SET_PREFERENCE simulationfiles Behavioral
SET_PREFERENCE busformat BusFormatAngleBracketNotRipped
SET_PREFERENCE outputdirectory C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/
SET_PREFERENCE workingdirectory C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/
SET_PREFERENCE subworkingdirectory C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_cg/
SET_PREFERENCE transientdirectory C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_cg/_dbg/
SET_PREFERENCE designentry Verilog
SET_PREFERENCE flowvendor Other
SET_PREFERENCE addpads false
SET_PREFERENCE projectname coregen
SET_PREFERENCE formalverification false
SET_PREFERENCE asysymbol false
SET_PREFERENCE implementationfiletype Ngc
SET_PREFERENCE foundationsym false
SET_PREFERENCE createndf false
SET_PREFERENCE removerpms false
SET_PARAMETER Component_Name spiloopmem
SET_PARAMETER Interface_Type Native
SET_PARAMETER AXI_Type AXI4_Full
SET_PARAMETER AXI_Slave_Type Memory_Slave
SET_PARAMETER Use_AXI_ID false
SET_PARAMETER AXI_ID_Width 4
SET_PARAMETER Memory_Type Simple_Dual_Port_RAM
SET_PARAMETER ecctype No_ECC
SET_PARAMETER ECC false
SET_PARAMETER softecc false
SET_PARAMETER Use_Error_Injection_Pins false
SET_PARAMETER Error_Injection_Type Single_Bit_Error_Injection
SET_PARAMETER Use_Byte_Write_Enable false
SET_PARAMETER Byte_Size 9
SET_PARAMETER Algorithm Minimum_Area
SET_PARAMETER Primitive 8kx2
SET_PARAMETER Assume_Synchronous_Clk false
SET_PARAMETER Write_Width_A 8
SET_PARAMETER Write_Depth_A 4096
SET_PARAMETER Read_Width_A 8
SET_PARAMETER Operating_Mode_A WRITE_FIRST
SET_PARAMETER Enable_A Use_ENA_Pin
SET_PARAMETER Write_Width_B 8
SET_PARAMETER Read_Width_B 8
SET_PARAMETER Operating_Mode_B WRITE_FIRST
SET_PARAMETER Enable_B Use_ENB_Pin
SET_PARAMETER Register_PortA_Output_of_Memory_Primitives false
SET_PARAMETER Register_PortA_Output_of_Memory_Core false
SET_PARAMETER Use_REGCEA_Pin false
SET_PARAMETER Register_PortB_Output_of_Memory_Primitives false
SET_PARAMETER Register_PortB_Output_of_Memory_Core false
SET_PARAMETER Use_REGCEB_Pin false
SET_PARAMETER register_porta_input_of_softecc false
SET_PARAMETER register_portb_output_of_softecc false
SET_PARAMETER Pipeline_Stages 0
SET_PARAMETER Load_Init_File false
SET_PARAMETER Coe_File no_coe_file_loaded
SET_PARAMETER Fill_Remaining_Memory_Locations false
SET_PARAMETER Remaining_Memory_Locations 0
SET_PARAMETER Use_RSTA_Pin false
SET_PARAMETER Reset_Memory_Latch_A false
SET_PARAMETER Reset_Priority_A CE
SET_PARAMETER Output_Reset_Value_A 0
SET_PARAMETER Use_RSTB_Pin false
SET_PARAMETER Reset_Memory_Latch_B false
SET_PARAMETER Reset_Priority_B CE
SET_PARAMETER Output_Reset_Value_B 0
SET_PARAMETER Reset_Type SYNC
SET_PARAMETER Additional_Inputs_for_Power_Estimation false
SET_PARAMETER Port_A_Clock 100
SET_PARAMETER Port_A_Write_Rate 50
SET_PARAMETER Port_B_Clock 100
SET_PARAMETER Port_B_Write_Rate 0
SET_PARAMETER Port_A_Enable_Rate 100
SET_PARAMETER Port_B_Enable_Rate 100
SET_PARAMETER Collision_Warnings ALL
SET_PARAMETER Disable_Collision_Warnings false
SET_PARAMETER Disable_Out_of_Range_Warnings false
SET_CORE_NAME Block Memory Generator
SET_CORE_VERSION 6.2
SET_CORE_VLNV xilinx.com:ip:blk_mem_gen:6.2
SET_CORE_CLASS com.xilinx.ip.blk_mem_gen_v6_2.blk_mem_gen_v6_2
SET_CORE_PATH C:/Xilinx/13.2/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/blk_mem_gen_v6_2
SET_CORE_GUIPATH C:/Xilinx/13.2/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/blk_mem_gen_v6_2/gui/blk_mem_gen_v6_2.tcl
SET_CORE_DATASHEET C:\Xilinx\13.2\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\blk_mem_gen_v6_2\doc\blk_mem_gen_ds512.pdf
ADD_CORE_DOCUMENT <C:\Xilinx\13.2\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\blk_mem_gen_v6_2\doc\blk_mem_gen_ds512.pdf><blk_mem_gen_ds512.pdf>
ADD_CORE_DOCUMENT <C:\Xilinx\13.2\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\blk_mem_gen_v6_2\doc\blk_mem_gen_v6_2_vinfo.html><blk_mem_gen_v6_2_vinfo.html>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_cg/_dbg/xil_53.out 0 → 100644
View file @ a64d58e7
SET_PARAMETER use_rstb_pin false
SET_PARAMETER pipeline_stages 0
SET_PARAMETER assume_synchronous_clk false
SET_PARAMETER use_regcea_pin false
SET_PARAMETER axi_id_width 4
SET_PARAMETER softecc false
SET_PARAMETER load_init_file false
SET_PARAMETER port_a_write_rate 50
SET_PARAMETER disable_collision_warnings false
SET_PARAMETER use_byte_write_enable false
SET_PARAMETER ecc false
SET_PARAMETER primitive 8kx2
SET_PARAMETER port_b_clock 100
SET_PARAMETER remaining_memory_locations 0
SET_PARAMETER memory_type Simple_Dual_Port_RAM
SET_PARAMETER register_porta_input_of_softecc false
SET_PARAMETER port_a_clock 100
SET_PARAMETER read_width_a 8
SET_PARAMETER disable_out_of_range_warnings false
SET_PARAMETER read_width_b 8
SET_PARAMETER register_portb_output_of_softecc false
SET_PARAMETER byte_size 9
SET_PARAMETER register_portb_output_of_memory_core false
SET_PARAMETER use_regceb_pin false
SET_PARAMETER register_porta_output_of_memory_core false
SET_PARAMETER reset_memory_latch_a false
SET_PARAMETER reset_memory_latch_b false
SET_PARAMETER register_porta_output_of_memory_primitives false
SET_PARAMETER use_error_injection_pins false
SET_PARAMETER enable_a Use_ENA_Pin
SET_PARAMETER enable_b Use_ENB_Pin
SET_PARAMETER port_a_enable_rate 100
SET_PARAMETER use_axi_id false
SET_PARAMETER write_depth_a 4096
SET_PARAMETER algorithm Minimum_Area
SET_PARAMETER output_reset_value_a 0
SET_PARAMETER output_reset_value_b 0
SET_PARAMETER error_injection_type Single_Bit_Error_Injection
SET_PARAMETER port_b_write_rate 0
SET_PARAMETER ecctype No_ECC
SET_PARAMETER write_width_a 8
SET_PARAMETER write_width_b 8
SET_PARAMETER component_name spiloopmem
SET_PARAMETER reset_priority_a CE
SET_PARAMETER reset_priority_b CE
SET_PARAMETER operating_mode_a WRITE_FIRST
SET_PARAMETER additional_inputs_for_power_estimation false
SET_PARAMETER operating_mode_b WRITE_FIRST
SET_PARAMETER interface_type Native
SET_PARAMETER reset_type SYNC
SET_PARAMETER register_portb_output_of_memory_primitives false
SET_PARAMETER use_rsta_pin false
SET_PARAMETER port_b_enable_rate 100
SET_PARAMETER coe_file no_coe_file_loaded
SET_PARAMETER fill_remaining_memory_locations false
SET_PARAMETER axi_slave_type Memory_Slave
SET_PARAMETER axi_type AXI4_Full
SET_PARAMETER collision_warnings ALL
SET_ERROR_CODE 2
SET_ERROR_MSG CANCEL: Customization cancelled.
SET_ERROR_TEXT Finished initializing IP model.
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_cg/summary.log 0 → 100644
View file @ a64d58e7
User Configuration
-------------------------------------
Algorithm : Minimum_Area
Memory Type : Simple_Dual_Port_RAM
Port A Write Width : 8
Port B Read Width : 8
Memory Depth : 4096
--------------------------------------------------------------
Block RAM resource(s) (9K BRAMs) : 0
Block RAM resource(s) (18K BRAMs) : 2
--------------------------------------------------------------
Clock A Frequency : 100
Port A Enable Rate : 100
Port A Write Rate : 50
----------------------------------------------------------
Estimated Power for IP : 5.357579 mW
----------------------------------------------------------
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_xmsgs/ngcbuild.xmsgs 0 → 100644
View file @ a64d58e7
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
</messages>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_xmsgs/pn_parser.xmsgs 0 → 100644
View file @ a64d58e7
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated -->
<!-- by the Xilinx ISE software. Any direct editing or -->
<!-- changes made to this file may result in unpredictable -->
<!-- behavior or data corruption. It is strongly advised that -->
<!-- users do not edit the contents of this file. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
<messages>
<msg type="info" file="ProjectMgmt" num="1769" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/spiloopmem.v\&quot; into library work</arg>
</msg>
</messages>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_xmsgs/xst.xmsgs 0 → 100644
View file @ a64d58e7
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="UtilitiesC" num="159" delta="old" >Message file &quot;<arg fmt="%s" index="1">usenglish/ip.msg</arg>&quot; wasn&apos;t found.
</msg>
<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">0</arg>: (<arg fmt="%d" index="2">0</arg>,<arg fmt="%d" index="3">0</arg>) : <arg fmt="%d" index="4">4</arg>x<arg fmt="%d" index="5">4096</arg> u:<arg fmt="%d" index="6">4</arg>
</msg>
<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">1</arg>: (<arg fmt="%d" index="2">4</arg>,<arg fmt="%d" index="3">0</arg>) : <arg fmt="%d" index="4">4</arg>x<arg fmt="%d" index="5">4096</arg> u:<arg fmt="%d" index="6">4</arg>
</msg>
<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">0</arg>: (<arg fmt="%d" index="2">0</arg>,<arg fmt="%d" index="3">0</arg>) : <arg fmt="%d" index="4">4</arg>x<arg fmt="%d" index="5">4096</arg> u:<arg fmt="%d" index="6">4</arg>
</msg>
<msg type="info" file="ip" num="0" delta="new" ><arg fmt="%d" index="1">1</arg>: (<arg fmt="%d" index="2">4</arg>,<arg fmt="%d" index="3">0</arg>) : <arg fmt="%d" index="4">4</arg>x<arg fmt="%d" index="5">4096</arg> u:<arg fmt="%d" index="6">4</arg>
</msg>
<msg type="warning" file="HDLCompiler" num="321" delta="old" >"C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v6_2\blk_mem_input_block.vhd" Line 691: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
</msg>
<msg type="warning" file="HDLCompiler" num="321" delta="old" >"C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v6_2\blk_mem_input_block.vhd" Line 707: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
</msg>
<msg type="warning" file="HDLCompiler" num="746" delta="old" >"C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v6_2\blk_mem_gen_prim_width.vhd" Line 977: Range is empty (null range)
</msg>
<msg type="warning" file="HDLCompiler" num="220" delta="old" >"C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v6_2\blk_mem_gen_prim_width.vhd" Line 977: Assignment ignored
</msg>
<msg type="warning" file="HDLCompiler" num="746" delta="old" >"C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v6_2\blk_mem_gen_prim_width.vhd" Line 978: Range is empty (null range)
</msg>
<msg type="warning" file="HDLCompiler" num="220" delta="old" >"C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v6_2\blk_mem_gen_prim_width.vhd" Line 978: Assignment ignored
</msg>
<msg type="warning" file="HDLCompiler" num="634" delta="new" >"C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v6_2\blk_mem_gen_prim_wrapper_s6.vhd" Line 490: Net &lt;<arg fmt="%s" index="1">douta_i[3]</arg>&gt; does not have a driver.
</msg>
<msg type="warning" file="HDLCompiler" num="321" delta="old" >"C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v6_2\blk_mem_gen_generic_cstr.vhd" Line 1544: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
</msg>
<msg type="warning" file="HDLCompiler" num="321" delta="old" >"C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav\ipcore_dir\tmp\_cg\_dbg\blk_mem_gen_v6_2\blk_mem_gen_generic_cstr.vhd" Line 1557: Comparison between arrays of unequal length always returns <arg fmt="%s" index="1">FALSE</arg>.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">c:/users/mjlyons/workspace/vspi/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_cg/_dbg/spiloopmem.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">douta</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">c:/users/mjlyons/workspace/vspi/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_cg/_dbg/spiloopmem.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">rdaddrecc</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">c:/users/mjlyons/workspace/vspi/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_cg/_dbg/spiloopmem.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_bid</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">c:/users/mjlyons/workspace/vspi/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_cg/_dbg/spiloopmem.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_bresp</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">c:/users/mjlyons/workspace/vspi/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_cg/_dbg/spiloopmem.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_rid</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">c:/users/mjlyons/workspace/vspi/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_cg/_dbg/spiloopmem.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_rdata</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">c:/users/mjlyons/workspace/vspi/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_cg/_dbg/spiloopmem.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_rresp</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">c:/users/mjlyons/workspace/vspi/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_cg/_dbg/spiloopmem.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_rdaddrecc</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">c:/users/mjlyons/workspace/vspi/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_cg/_dbg/spiloopmem.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">sbiterr</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">c:/users/mjlyons/workspace/vspi/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_cg/_dbg/spiloopmem.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">dbiterr</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">c:/users/mjlyons/workspace/vspi/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_cg/_dbg/spiloopmem.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_awready</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">c:/users/mjlyons/workspace/vspi/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_cg/_dbg/spiloopmem.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_wready</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">c:/users/mjlyons/workspace/vspi/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_cg/_dbg/spiloopmem.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_bvalid</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">c:/users/mjlyons/workspace/vspi/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_cg/_dbg/spiloopmem.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_arready</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">c:/users/mjlyons/workspace/vspi/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_cg/_dbg/spiloopmem.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_rlast</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">c:/users/mjlyons/workspace/vspi/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_cg/_dbg/spiloopmem.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_rvalid</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">c:/users/mjlyons/workspace/vspi/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_cg/_dbg/spiloopmem.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_sbiterr</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="new" >&quot;<arg fmt="%s" index="1">c:/users/mjlyons/workspace/vspi/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_cg/_dbg/spiloopmem.vhd</arg>&quot; line <arg fmt="%s" index="2">160</arg>: Output port &lt;<arg fmt="%s" index="3">s_axi_dbiterr</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">U0</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_AWID&lt;3:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_AWADDR&lt;31:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_AWLEN&lt;7:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_AWSIZE&lt;2:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_AWBURST&lt;1:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_WDATA&lt;7:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_WSTRB&lt;0:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_ARID&lt;3:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_ARADDR&lt;31:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_ARLEN&lt;7:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_ARSIZE&lt;2:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_ARBURST&lt;1:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AClk</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_ARESETN</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_AWVALID</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_WLAST</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_WVALID</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_BREADY</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_ARVALID</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_RREADY</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_INJECTSBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">S_AXI_INJECTDBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="2935" delta="old" >Signal &apos;<arg fmt="%s" index="1">S_AXI_BID</arg>&apos;, unconnected in block &apos;<arg fmt="%s" index="2">blk_mem_gen_v6_2_xst</arg>&apos;, is tied to its initial value (<arg fmt="%s" index="3">0000</arg>).
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">S_AXI_BRESP</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="2935" delta="old" >Signal &apos;<arg fmt="%s" index="1">S_AXI_RID</arg>&apos;, unconnected in block &apos;<arg fmt="%s" index="2">blk_mem_gen_v6_2_xst</arg>&apos;, is tied to its initial value (<arg fmt="%s" index="3">0000</arg>).
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">S_AXI_RDATA</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">S_AXI_RRESP</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">S_AXI_RDADDRECC</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">S_AXI_AWREADY</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">S_AXI_WREADY</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">S_AXI_BVALID</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">S_AXI_ARREADY</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">S_AXI_RLAST</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">S_AXI_RVALID</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">S_AXI_SBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">S_AXI_DBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">WEB&lt;0:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">DINB&lt;7:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">RSTA</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">REGCEA</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">RSTB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">REGCEB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">INJECTDBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">INJECTSBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">INJECTDBITERR_I</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">INJECTSBITERR_I</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">REGCEA&lt;0:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">REGCEB&lt;0:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">INJECTSBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">INJECTDBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">c:/users/mjlyons/workspace/vspi/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1341</arg>: Output port &lt;<arg fmt="%s" index="3">SBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[0].ram.r</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">c:/users/mjlyons/workspace/vspi/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1341</arg>: Output port &lt;<arg fmt="%s" index="3">DBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[0].ram.r</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">c:/users/mjlyons/workspace/vspi/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1341</arg>: Output port &lt;<arg fmt="%s" index="3">SBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[1].ram.r</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="info" file="Xst" num="3210" delta="old" >&quot;<arg fmt="%s" index="1">c:/users/mjlyons/workspace/vspi/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/tmp/_cg/_dbg/blk_mem_gen_v6_2/blk_mem_gen_generic_cstr.vhd</arg>&quot; line <arg fmt="%s" index="2">1341</arg>: Output port &lt;<arg fmt="%s" index="3">DBITERR</arg>&gt; of the instance &lt;<arg fmt="%s" index="4">ramloop[1].ram.r</arg>&gt; is unconnected or connected to loadless signal.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">RDADDRECC</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">SBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">DBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">INJECTSBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">INJECTDBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">SBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">DBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">WEB&lt;0:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">DINB&lt;3:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="2935" delta="new" >Signal &apos;<arg fmt="%s" index="1">douta_i</arg>&apos;, unconnected in block &apos;<arg fmt="%s" index="2">blk_mem_gen_prim_wrapper_s6_1</arg>&apos;, is tied to its initial value (<arg fmt="%s" index="3">0000</arg>).
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">INJECTSBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">INJECTDBITERR</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">SBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">DBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">WEB&lt;0:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">DINB&lt;3:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="2935" delta="new" >Signal &apos;<arg fmt="%s" index="1">douta_i</arg>&apos;, unconnected in block &apos;<arg fmt="%s" index="2">blk_mem_gen_prim_wrapper_s6_2</arg>&apos;, is tied to its initial value (<arg fmt="%s" index="3">0000</arg>).
</msg>
<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">DOUTA_I&lt;7:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">RDADDRECC_I&lt;11:0&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">CLKB</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">SBITERR_I</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">DBITERR_I</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">RDADDRECC</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">SBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">DBITERR</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">GND</arg>.
</msg>
<msg type="info" file="Xst" num="2169" delta="old" >HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
</msg>
</messages>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/iseconfig/spiifc.projectmgr 0 → 100644
View file @ a64d58e7
<?xml version='1.0' encoding='utf-8'?>
<!--This is an ISE project configuration file.-->
<!--It holds project specific layout data for the projectmgr plugin.-->
<!--Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.-->
<Project version="2" owner="projectmgr" name="spiifc" >
<!--This is an ISE project configuration file.-->
<ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" >
<ClosedNodes>
<ClosedNodesVersion>2</ClosedNodesVersion>
<ClosedNode>/spiifc - IMP C:|Users|mjlyons|workspace|vSPI|projnav|xps|pcores|spiifc_v1_00_a|hdl|vhdl|spiifc.vhd/PLBV46_SLAVE_BURST_I - plbv46_slave_burst - implementation</ClosedNode>
<ClosedNode>/spiifc - IMP C:|Users|mjlyons|workspace|vSPI|projnav|xps|pcores|spiifc_v1_00_a|hdl|vhdl|spiifc.vhd/PLBV46_SLAVE_BURST_I - plbv46_slave_burst - implementation/I_SLAVE_ATTACHMENT - plb_slave_attachment - implementation</ClosedNode>
<ClosedNode>/spiifc_tb2 C:|Users|mjlyons|workspace|vSPI|test|spi_base|spiifc_tb2.v</ClosedNode>
<ClosedNode>/spiloop C:|Users|mjlyons|workspace|vSPI|src|spi_base|spiloop.v</ClosedNode>
<ClosedNode>/spiwrap C:|Users|mjlyons|workspace|vSPI|src|spi_base|spiwrap.v</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem>spi - spiifc (C:/Users/mjlyons/workspace/vSPI/src/spi_base/spiifc.v)</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000225000000020000000000000000000000000200000064ffffffff000000810000000300000002000002250000000100000003000000000000000100000003</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
<CurrentItem>spi - spiifc (C:/Users/mjlyons/workspace/vSPI/src/spi_base/spiifc.v)</CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>Configure Target Device</ClosedNode>
<ClosedNode>Design Utilities</ClosedNode>
<ClosedNode>Implement Design</ClosedNode>
<ClosedNode>Synthesize - XST</ClosedNode>
<ClosedNode>User Constraints</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem>Synthesize - XST</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f8000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>Synthesize - XST</CurrentItem>
</ItemView>
<ItemView guiview="File" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
</ClosedNodes>
<SelectedItems/>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000392000000040101000100000000000000000000000064ffffffff000000810000000000000004000000a800000001000000000000004a00000001000000000000006600000001000000000000023a0000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>addr_reg_cntr_brst_flex.vhd</CurrentItem>
</ItemView>
<ItemView guiview="Library" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>interrupt_control_v2_01_a</ClosedNode>
<ClosedNode>plbv46_slave_burst_v1_01_a</ClosedNode>
<ClosedNode>proc_common_v3_00_a</ClosedNode>
<ClosedNode>work</ClosedNode>
</ClosedNodes>
<SelectedItems/>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000109000000010001000100000000000000000000000064ffffffff000000810000000000000001000001090000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>interrupt_control_v2_01_a</CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>Design Utilities</ClosedNode>
</ClosedNodes>
<SelectedItems>
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</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f8000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem/>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VERILOG" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>Design Utilities</ClosedNode>
<ClosedNode>Implement Design/Map</ClosedNode>
<ClosedNode>Implement Design/Place &amp; Route</ClosedNode>
<ClosedNode>Implement Design/Translate</ClosedNode>
<ClosedNode>User Constraints</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem></SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f8000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_XCO" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
</ClosedNodes>
<SelectedItems>
<SelectedItem/>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f8000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem/>
</ItemView>
<SourceProcessView>000000ff00000000000000020000011b0000011b01000000050100000002</SourceProcessView>
<CurrentView>Implementation</CurrentView>
<ItemView engineview="BehavioralSim" guiview="Source" compilemode="AutoCompile" >
<ClosedNodes>
<ClosedNodesVersion>2</ClosedNodesVersion>
<ClosedNode>/spiifc - IMP C:|Users|mjlyons|workspace|vSPI|projnav|xps|pcores|spiifc_v1_00_a|hdl|vhdl|spiifc.vhd</ClosedNode>
<ClosedNode>/spiifc_tb C:|Users|mjlyons|workspace|vSPI|test|spi_base|spiifc_tb.v/uut - spiifc - IMP</ClosedNode>
<ClosedNode>/spiifc_tb C:|Users|mjlyons|workspace|vSPI|test|spi_base|spiifc_writereg_tb.v/uut - spiifc - IMP</ClosedNode>
<ClosedNode>/spiifc_tb2 C:|Users|mjlyons|workspace|vSPI|test|spi_base|spiifc_tb2.v/uut - spiifc - IMP</ClosedNode>
<ClosedNode>/spiloop C:|Users|mjlyons|workspace|vSPI|src|spi_base|spiloop.v/mySpiIfc - spiifc - IMP</ClosedNode>
<ClosedNode>/spiwrap C:|Users|mjlyons|workspace|vSPI|src|spi_base|spiwrap.v/mySpiIfc - spiifc - IMP</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem>spiifc_writereg_tb (C:/Users/mjlyons/workspace/vSPI/test/spi_base/spiifc_writereg_tb.v)</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000175000000020000000000000000000000000200000064ffffffff000000810000000300000002000001750000000100000003000000000000000100000003</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
<CurrentItem>spiifc_writereg_tb (C:/Users/mjlyons/workspace/vSPI/test/spi_base/spiifc_writereg_tb.v)</CurrentItem>
</ItemView>
<ItemView engineview="BehavioralSim" sourcetype="" guiview="Process" >
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<ClosedNode>Design Utilities</ClosedNode>
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<SelectedItems>
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</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
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<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f8000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem/>
</ItemView>
<ItemView engineview="BehavioralSim" sourcetype="DESUT_VERILOG" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
</ClosedNodes>
<SelectedItems>
<SelectedItem>Simulate Behavioral Model</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f8000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>Simulate Behavioral Model</CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_UCF" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>User Constraints</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem/>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f8000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem/>
</ItemView>
<ItemView engineview="BehavioralSim" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
<ClosedNodes>
<ClosedNodesVersion>1</ClosedNodesVersion>
<ClosedNode>ISim Simulator</ClosedNode>
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<SelectedItems>
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<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
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</ItemView>
<ItemView engineview="BehavioralSim" sourcetype="DESUT_XCO" guiview="Process" >
<ClosedNodes>
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<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
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<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f8000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem/>
</ItemView>
</Project>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/rc-bytes-tx-test.txt 0 → 100644
View file @ a64d58e7
03
00
00
00
00
00
00
00
00
\ No newline at end of file
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/rc-bytes.txt 0 → 100644
View file @ a64d58e7
01
FF
F0
33
55
12
34
56
78
9A
\ No newline at end of file
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc.gise 0 → 100644
View file @ a64d58e7
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="spiifc.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_NCD" xil_pn:name="spiifc_guide.ncd" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_NCD" xil_pn:name="spiloop_guide.ncd" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_NCD" xil_pn:name="spiwrap_guide.ncd" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1331743852" xil_pn:in_ck="241267088593728842" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1331743852">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
</transforms>
</generated_project>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc.tcl 0 → 100644
View file @ a64d58e7
project new C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc.xise;
project set family spartan6;
project set device xc6slx45;
project set package csg324;
project set speed -2;
project set top_level_module_type HDL;
project set synthesis_tool "XST (VHDL/Verilog)";
lib_vhdl new spiifc_v1_00_a;
xfile add C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/hdl/vhdl/spiifc.vhd;
xfile add C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/hdl/verilog/user_logic.v;
lib_vhdl new proc_common_v3_00_a;
xfile add C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/proc_common_pkg.vhd -lib_vhdl proc_common_v3_00_a;
xfile add C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ipif_pkg.vhd -lib_vhdl proc_common_v3_00_a;
xfile add C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_muxcy.vhd -lib_vhdl proc_common_v3_00_a;
xfile add C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_gate128.vhd -lib_vhdl proc_common_v3_00_a;
xfile add C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/family_support.vhd -lib_vhdl proc_common_v3_00_a;
xfile add C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd -lib_vhdl proc_common_v3_00_a;
xfile add C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter_f.vhd -lib_vhdl proc_common_v3_00_a;
lib_vhdl new plbv46_slave_burst_v1_01_a;
xfile add C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/flex_addr_cntr.vhd -lib_vhdl plbv46_slave_burst_v1_01_a;
xfile add C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/addr_reg_cntr_brst_flex.vhd -lib_vhdl plbv46_slave_burst_v1_01_a;
xfile add C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plb_address_decoder.vhd -lib_vhdl plbv46_slave_burst_v1_01_a;
xfile add C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/burst_support.vhd -lib_vhdl plbv46_slave_burst_v1_01_a;
xfile add C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/wr_buffer.vhd -lib_vhdl plbv46_slave_burst_v1_01_a;
xfile add C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/be_reset_gen.vhd -lib_vhdl plbv46_slave_burst_v1_01_a;
xfile add C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plb_slave_attachment.vhd -lib_vhdl plbv46_slave_burst_v1_01_a;
xfile add C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/data_mirror_128.vhd -lib_vhdl plbv46_slave_burst_v1_01_a;
xfile add C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plbv46_slave_burst.vhd -lib_vhdl plbv46_slave_burst_v1_01_a;
lib_vhdl new interrupt_control_v2_01_a;
xfile add C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v2_01_a/hdl/vhdl/interrupt_control.vhd -lib_vhdl interrupt_control_v2_01_a;
project close;
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc.xise 0 → 100644
View file @ a64d58e7
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
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<!-- -->
<!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="13.2" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="../../hdl/vhdl/spiifc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="../../hdl/verilog/user_logic.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/proc_common_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
<library xil_pn:name="proc_common_v3_00_a"/>
</file>
<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ipif_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
<library xil_pn:name="proc_common_v3_00_a"/>
</file>
<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_muxcy.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
<library xil_pn:name="proc_common_v3_00_a"/>
</file>
<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_gate128.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
<library xil_pn:name="proc_common_v3_00_a"/>
</file>
<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/family_support.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
<library xil_pn:name="proc_common_v3_00_a"/>
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<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
<library xil_pn:name="proc_common_v3_00_a"/>
</file>
<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter_f.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
<library xil_pn:name="proc_common_v3_00_a"/>
</file>
<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/flex_addr_cntr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
<library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
</file>
<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/addr_reg_cntr_brst_flex.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
<library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
</file>
<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plb_address_decoder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
<library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
</file>
<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/burst_support.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
<library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
</file>
<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/wr_buffer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
<library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
</file>
<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/be_reset_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
<library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
</file>
<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plb_slave_attachment.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
<library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
</file>
<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/data_mirror_128.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
<library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
</file>
<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plbv46_slave_burst.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
<library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
</file>
<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v2_01_a/hdl/vhdl/interrupt_control.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
<library xil_pn:name="interrupt_control_v2_01_a"/>
</file>
<file xil_pn:name="ipcore_dir/buffermem.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="../../../../../../src/spi_base/spiifc.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="../../../../../../src/spi_base/spiwrap.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../../../test/spi_base/spiifc_tb.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="PostMapSimulation" xil_pn:seqID="92"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="92"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="92"/>
</file>
<file xil_pn:name="../../../../../../test/spi_base/spiifc_tb2.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../../ucf/atlys/spiwrap.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="ipcore_dir/spiloopmem.xco" xil_pn:type="FILE_COREGEN">
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../../../src/spi_base/spiloop.v" xil_pn:type="FILE_VERILOG">
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../../ucf/atlys/spiloop.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../../../test/spi_base/rc-bytes-writereg.txt" xil_pn:type="FILE_USERDOC"/>
<file xil_pn:name="../../../../../../test/spi_base/spiifc_writereg_tb.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="107"/>
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<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="107"/>
</file>
<file xil_pn:name="ipcore_dir/buffermem.xise" xil_pn:type="FILE_COREGENISE">
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</file>
<file xil_pn:name="ipcore_dir/spiloopmem.xise" xil_pn:type="FILE_COREGENISE">
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</file>
</files>
<properties>
<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
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<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
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<property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/>
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<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Custom Waveform Configuration File Behav" xil_pn:value="tb_writereg.wcfg" xil_pn:valueState="non-default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx45" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
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<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="spiifc_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="spiifc_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="spiifc_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="spiifc_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/spiifc_writereg_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.spiifc_writereg_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1s" xil_pn:valueState="non-default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.spiifc_writereg_tb" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|spiifc_writereg_tb" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="spiifc" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-02-28T11:11:25" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="8CCD92A1D6E74DAC823A444842F84F30" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings>
<binding xil_pn:location="/spiwrap" xil_pn:name="../../../../../ucf/atlys/spiwrap.ucf"/>
<binding xil_pn:location="/spiloop" xil_pn:name="../../../../../ucf/atlys/spiloop.ucf"/>
</bindings>
<libraries>
<library xil_pn:name="interrupt_control_v2_01_a"/>
<library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
<library xil_pn:name="proc_common_v3_00_a"/>
<library xil_pn:name="spiifc_v1_00_a"/>
</libraries>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc_bitgen.xwbt 0 → 100644
View file @ a64d58e7
INTSTYLE=ise
INFILE=C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav\spiifc.ncd
OUTFILE=C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav\spiifc.bit
FAMILY=Spartan6
PART=xc6slx45-2csg324
WORKINGDIR=C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav
LICENSE=ISE
USER_INFO=179841373_174164856_206270303_042
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc_guide.ncd 0 → 100644
View file @ a64d58e7
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6
###5028:XlxV32DM 3ff1 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1174eNrFW8typrwRfZnZZYOuoI/yPs+Qhat0garZ/F7M0jXvHrXUjS4fYrA9TpKa8CEE6nPU9DkSzvq6yPX3L8HkY3rw9xemp8ci1tf47/cvyVTVymMrX3//dlJOD/bg00M9uHz/h0+xj+PrD7aFh1brD26Wh2frz4XHu3+wfX5wodZ4LuJ5PMjSLKFZlXMG57qcz3A+l3Oxrm/Lkh9j88EfV+UEvUPpvcH5Vs4tnO/pNjOVZhebDSvnPg5iVO6WB7GmDAJIrC3nGs5dOQdItgoKINgSlBRwvqXHOiBofXN5LOfTwRd6FADyhR4JgHyhR3E4n/NtS2mGEHwV8h4B+TSkYwrGhFum9zRhXCzrP2xXj22CGdwectnyFFpZTyFj4mwKGePNFLJpb6aQMdlMIWNxit/YBg9Yf8dwZBeOZBgO+0M4ksKpw5NdHJnZOpzpOhzdh2MxHP6HcFgXDm/DyeOqLlzdhZumsgpHQpb6Ohy3/odP4jG/M7k8mHAPJk08+vhvj//EA+75nULe838wXhMo3376nNTe5YPPg4YdB5/wyPCYb+I84HHDY36RuJiIu6XjTqnM3T59jLvMhey4ep7KPrOmaip/MTVj7YqExCDXFwgwXoZqJ6iuxaZlXl+9gTucrFp1bF2g1YeqVcXWObUuVauMrTpVUVa1xirqFVTRqX5CrKIeYgiyhOf9+uo8PFbY0hpL6mv8Fx+Q0gBb43zEJ2zQLPa6mcXeaThp6uZpfTW5eamawx6LeYKnDip0YifzxfdEEy/XgCa7JZpY1RppsgFaQ9030mQTHm+r1kiTdYmmum+kydpEk6taI0gLkxKqWfQuYrEpaEFdZR30loJeyjUI2rAUtKpaY9BmSuHtVWsMetlTq6laY9BLei6bqlZQyJAUsn4CKCTAPriAoG1szEEfvPE6aHiMSC8VXoOgl5RkdqlaY9CLTuHpqhWCVql1rloh6JTo0161FlkPVesh60L6R4xsemwxP0jWxfpvPs1Z22WotF3n1zFXrMU8iaolUY1amvuORJDlg8xaaPLB9qIGIpZFLWoZlp78fMcsRMFqTdMQNinIrLHsCKgPAssVh4wQJ0IIhSTfaEJVrxrAR4kWKRVV/RiTH2PwIdriQ3TBmlXUp8Mb57qGE0Nze49nb/CoEzxC93iiksabqAYfYpCR+Q7ZhQqJpNE1RMnzQ+3nIfqpgyiXGxDnHqL9OxBZeiO2E6Fd3lmMnbEosjz+Y1FwuY3HKLg8/o73DcT2zWXILgw192eSlr8gvSJpXTNDPnPiPj1DfNr6GcK3wezr28xpHlnXS4kb82i6eYxO4aPzWIxck6pLR4TS+aH+s0T84qkyqfcXeNVj6/oCLwT+mOnHkn688qQ2UElTgU3tHKxE0lNNwsJCtiTQki0JP+QlXvMhikNkNjKWbkMZgN6HL+FHaY83uHgDTNgMdoHPewk4FvAUbz7OeFzg+OqSREhHsc45VgdqxT2vHoKgHWJ2CNmB50iAl7kEAw4lXfYp+kXXl/AJeEnR0BJasMuULnG6JMqlkOT5UC8ADvGaRNJMJM2orkBy8jH8MGB+Spxmkn26TZfbDjMjpC2BJU5Msnea4o0/qjG2NAZOORTvMkayO1qW2w7vIeRcEKYxlmRCOflC3owR0hjkkOxcjQHTJdRebjusQsj5Bm4iXwBXETK215S3mhrzk8HhZSpSY4YE7jjn3pxsgoIXPjrdUNkECe+vrr3C9p1egX/ZMqT0vrAM53XLPVuG+3XrrFyZgXkIX1BW8RnzEL7NPNiBedi+AFF+xjzs32UeOLswD9EosGioo4SzuFZgHH7H4Dn8Zn9YqZOH+Gbz4AbmYf/CDKlP2IKZfZst8ANbcFj9L/kCQy7A0g9HP3zjC9RENd/XvmCmlWHMiOwLZnb4AlmuZV+gyBfM9LTYu/iCov4G1d7i0eHRF/UvYhoff2w4CLlTnO7cExj0ABaPDo++9gSuPBo9gSfht/UlfAJeMjS0zcKfumRPQD4oDn9cyp6AVwxWnoBg6B21FAjOnoDRFoKXqKVAcPYEW7mt8gRbCaz2BIE6h3qM5AmOfY6YQ2WM7Al8ua3yBKEgLJ4g607q7Ooxkic4tpw8r8ZInkDbclvxBKF4gnQhKf1We4KAjXvtCfbcuE2VJ4C8y54ANiEf+yMWO0uWQGVLkN3A/r9zA1gr++3vTv/TZvtH9X8Wf1v/w0D/GfvC7kH4hAGYv2/3YBsYAMa/gHH7jANg3+YAlvE+vQC1j++miMWKxzrAQaXsA+75v+zTi7Tje6b3THx6QoRO5XSk3YqshNUVq4Ot+xihHsm1/BtyHUicN/qh6Idul/GHFulmGU/SEacQl/GCvixoWrfGpuPLQqXJATV4w6PCo640uYjZUmvyoX7qXJMDavCGR4VHXWuyLI9GTdYkvKK+hE/AS4csbSi8y6HJx05HKJdCpokRFYxUaznUl/YL4ouMqrWQ+k7ltqK+ipcQKvWdaUU+q3qMrL608eBCNUZS31mW24r60gZ9ypCivrOgzqIeI6svfVaIelLGSOo783Lbob4bq9R3FqipvFLfGVfkm6jVl4RWTqkv/Jd0FiWW4Zvlp/UnSyK//ottSV2dzH6uvFD7jhu4x7bYgu8TX3/uWGg2lV/HPGZVbNk0UQWn29QxGHzIgf7i/QWGjU9ZX6AlXl5f4X/gUxT6Mvix+9gcQgYnenC4m8DmC3DZVJ+Ac7fAiSG4+RScQHCwDZLBiQYceXz40YCTPbgFwS1X4NgAnL0FTg7B6VNwksAxAidbcIzAsRac6sEZBGeuwPEBOHMLnBqCU6fgFIHjBE614DiB4y043YOzCM5egRMDcMstcHoITp6C0wROEDjdghMETjTgVAYn4s0IzmVwYjvAve22wcbZ0mGjD2WRiNy3gqL64rMhEbT2tkQEO277ScgwwFMmmD9jQh1M7ImAF6k6JrD6AIrdrtgRPqJyrsolaHqN11MGzH0GeMwAd5UBcpAB860MmIcZIE4zYCbckjJgbnFLygDZZsDcZ0DADNgvMsB8IAP0dJ4BZr+XAUMmiP4uA4gJPVEGtEyQxQAUKQP09JwBps2Apc+ADTPAX2WAGmSAvpUByzAD+GkGLJQBijJgaTNAUQaoNgOWPgN2XLdPFxkQPpIBbJAB270MGDJBJbjLAGIiWc+UAS0T5E0BRc4A9pwBockAZTqS/IQksQuSto+QxAckhXskmSFJ5pQkQyRxIsm0JHFiYkOS+DNJW0uS7UliSBK/IGn/CEliQJK/R5IdknTqZVP/RJIgkmxLkiAmdiRJPJO0tyS5niT841kpxiTx6SMkyQFJ7h5JbkjSqSdO/RNJkkhyLUkoPYAikySfSOJTS5LvSRJIkrwgiX2EJDUgyd4jyQ9JOvXWqX8iSRFJviXpYIIhSeqZJNaStPUkSSRJXZDEP0KSHpBk7pG0DUk69eipfyJJE0lbS5ImJjiSpJ9J4jVJYg+ddHuF0h2ulsxuIN3qhnTnMc+lm53gzv3Tktll6YaWZsnsaMnsaukW+96Do/2A7QqcH4CTt8DtQ3DTKbidwHkCt7fgPIHzDTjhenC4H8AvVpViGWx2OHYHnBjWPh7OwAmsfTBsBiea2lf2s5a9BfeUlrgfwC9WlcIMNjvcdAvcOC39KThMSxgWwYUWHG1ymWazgxvZFybcD5DzRWES9wsTN/N5YWLTLUuZIzyvTGcL7Nw/UgEDp8oELRUVGBCUH5EqU+7YVSZRVya+9Jt5HjcW+EVl4stgY8Hf2czLY57ilmcGKPcH3AtuLEBLjZv2jeFHk9+2B4cbC2y/enm3QX67W/k9dHdiPs1vSy/vRvnduLvjz6qgQwNu68HhhgCfrl7ewWaes7fADbVU6FNwG728jMBt7ctLu+Cm2cwT7qns4oYA4xfg3KDs+nAHnBuWXXm2eMn9AZyjsuvasuvow4Tryu6TYOJCnrOrmRvsVDpza+aGginU6cztNHOcZm5vZ47+atE0O5Ui/x9FanC4kOdXM2cGBcXd2anMY56DOyukuX8ChwVFyKkFRx+6TFtQJOvABVyAc3EFbrAJ5+Zb4NgQnDgFxwicJHCsBUd/k2FkC66XgoALZy6vwA32l5y+BW4oBYKfguMEThE43oKjd86oFlz/XSfggperK3B6AO6WA5fD7zri1IFLQeA0gRMtOPr7n9ihBmd6nQu4UOXbVbUcibi4A86MdW4/A2dI5xy9c6bVOUvfOF33zvUfrQIuMLm+mrl5MHO3lhdy6MzE6fJCSpq5mWaucWbl7+Rih9qk+n5XP+DCUFyAi1VnMHN3HEoe81znzhxK7g/2K6ADh5bafgWsltChSctexAMuDPmV/XKDaun5rbQcijh9TOrS8hBxqpamFXFLDsV11bL/3BhoYThfpeUySMtb75wcf248feekorRcKC1Vm5bH2mlp07L/1BBwYSjmq7QceEt/6S3/C92ssjQ=###4748:XlxV32DM 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\ No newline at end of file
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiloop_bitgen.xwbt 0 → 100644
View file @ a64d58e7
INTSTYLE=ise
INFILE=C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav\spiloop.ncd
OUTFILE=C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav\spiloop.bit
FAMILY=Spartan6
PART=xc6slx45-2csg324
WORKINGDIR=C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav
LICENSE=ISE
USER_INFO=179841373_174164856_206270303_042
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiloop_guide.ncd 0 → 100644
View file @ a64d58e7
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6
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vPPE/PPEgitUv68+fH8psnlaTNJspr5+bg49OshHNhwjxCw42loGTt9fb34qgF8ZZzbPVkX8imFcGfb6xwtkHcHWEWLzdirD+mfj+OfDrH9aiGVaiG1ayGlaUH+8JwHyyrhn84xtivgVw7gy7PWP26aFWKeFILu3UxnWPxsnPx/2+qeFWqaF2qaFnqbFUr2TAH1l3H1l3LdFZnWMX3GMK8Ne/7ht2qh12qh12qgp0/pn4/Tnwz6+aw3Do+7umD5uti//xuZwJEeCQv2+DBr/D1K2YRM=###2784:XlxV32DM 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1298eNrtW8uO5KgS/Zn5APM0pDX7+w13kRIYLNVmatHLVv/7hXhApNtZj9aVqhbTUjfOwMTLwImA6Nv2oou/Lbft1w9T1/bgfv5t03Jr1K09KHqIgR8iPNz7P79+2DW2Ifon0n3a7kodQE9IN+0FvYY2sFG0dtAXaEwj+WW776lRdUlTeNYoG9omGtvY23s2XdVVT/5ZNaoCzp61CahNzo3skp+sU0XW0LbXsI29vbe/jcliheraYPcO1i5GdpFy1FVIdOPdKPQKaLXs3LWIrgUUXtkVK3iH/LV2h3gSpo699VnsKzjMzWHdgyl2arRTBbA+wsuRX24PQoYHGeRGveQpY4cvGM0c1mWEAFQ1bQEZQQNZ88taynAgQ7GMQ8gAV8dlDusyfFdYRZw7dw8Obj0aqBmpIW2oE1LRt/eUN/RGo/7KxjVTb+WWbsr//EdbdTM1b//RNmx/aV1vNrW21NtuthdQ7y9t2oxZ69Z+d1O219DJ20uIozf41hsS9h7Qm9LsPVpvytCbPTbw7suesdmBqBRQszo6uQtZfoJOOqiuoe4aHjdXV1Qxlu21eQ1WaLOrzzIjB5ntH238rS87GOgVD6zSNrUL29oXQn56qWcl4oMS/kIJ5+tZCfCtR00O/FNZHXetTrlUp5zUifp9dVZ1Uifa/486fRYttyo5u+2/2tpb+GlcvRnX5lVjYpxprW6tbW17buN+nYV3mWubEytMhlxxTlCDs6ks2ChSY6GWf7N6Bl7TsAn01lO7UhvIm349e5OnRtxebWWf7+e3ygd8bs8+Pz7h899c/QMZ9p21r9yOF52CeKF9nH1FbX93lftG0ofRvtPf9g0G9gwDwhyQ2/7ePWH7huPCLsS0vb3BVQJ6lvSOMh7ISZIb/3AAeZXkvjf2fR6nC4tdGw9gvSpWUdHWCCbiFu95ayy0NXYT+ybo/DGHdcsSMIOl16ntQTDDvdwxszqZwV7u/D6HdWYhgr7DGUUyQ59bBp8smIEPvZ3DOjOvYCMuc9OGHtyej7lpg3CgpmVu2mAfUtFR933Hr09beYPj5rh0a3tswr3choTbeHM9buN2e3W42cIG2RpcWA4XlseF9TD3XtbjYZ83+MviL1xaAVdWwIUVwkQEBoKXkCUeAAJvrwmHJxyecHjC4SlO5GDAeEmobkY9sxEo8pLBotcdf+3IbEdmOzLbL4DmZS8Sb14UbicNd8JpU0sOV22gFV8yLdfjQ+5EbWkP4y3iRddAbaQ2UZup3amlfUgdsFstUrEVFVtZsR0VS8tnvjPpVxa543xCv3LW05/9l1BN/8X+c7/5b0fF3Pfynz37r6Ca9ov9t/zmv4qKmW/lv3oOStKBauqv9R/kbw/+ywvFpt/Ifz+sJQjtjmzoeFeYiSmKJLodpSelpUMk54Kd2iHyDsmeWY7Jo6MjhxEQ3eWOmg2tasOxvqvRg+cHxw+WHxZ6aNwamCJXIDSpQOjSGwHDGwceGVIyS8ksJbOUzFIyS8kkZWEpmaQsLCVTPu7SIaUklpJYSmIpiaUklpKQuztYSkLuQAApLXHcI0gpUkpkKZGlRJYSWUpkKZGkVJYSSUplKbFJgayVI7POoX/zXMaJQ0TZ2aBobD21jlpL7YJtJXpj0Fo8kbBOsYwFJlCGMC4LGW0Osn2V7atsX2X7Kts37Br28BGFUWnKgmmZHJDLNBOmJUaxuS8Rg2SYTm3UDCmzE70L9fKZgstq9sLna72tvacAX28XvaS461qu4JGhpQevRwvUwFQIde8hg+p1UsGiYIF8TBZgEQbgObBcTxa5Gde6bEXvQr18guEgyKJetAhm6j2sYFEWvfRxukUBDnncUCeARQG//M7UFSxau45GL5MKFrkEZDVZoEUKtPIsN5BF6wyuXdaid6FePi9xED1SL1q0gkUOfAWRJvfSBOwWuT6TlMavf3dlwzcKvVEgJNczqAeZEKhr1PUeHM5iHON4jJkhP3gex6w4Jnmc5zhm4TF2JgQw/3BMgL3hvq+00knHtvfzOgq8jgKvo8DrKPA6CryOAq8jeiDZ3QMe0w7YCjUzL8yzMKvCHEpPTWxLtFr23/9SYlIUJSaKEhPXUgMtEgxCMxj6mEDngGAZM6NlILQ0bRTywBzgVfuEWIY7WD8/a+zG2SjyJuo8o3O5THKDMZi8zYhGVjfV8ytV2QxNZuhhBiI1HnVltxFk02+9EXbT735QJo7VsuLDFfptt+kWkWJRb9wo16Lf/WhGHMPtCx/DUf/euMVlplr0WlciTTYtR6Tki36v28P53W6239IxysPyTLnw3dJV2AWvfva3T16lOwSyMervZ2+QltHvZlJLzA6cCkf/Ll5OBcp7DpoKflHzAGV+BwVi53dQbQbL76BATXnIlR++AxwJztMue3QF7cWU9MfFlGQfXc7Mxuw4GbUrMmp/ZtSjLfnRFrBV2IK2PbelnmzZNdlSP22LW9TZFsr4jvLOB6pvf6CzUfMDCVvcspxtyWRL+QNbzMmWQgfI47Tuo5OtvjPZyukD7duDUfpkVLFk1P5Zo37YzKdijau4hHJ8XdMf4ICrv7A/IHnvajt+3/0bOFstqHycaHmX7dSOqxC5Wt5O4V2+xbJVcOgoC/HnvNtqawzusg7Yr//u3xZbLfbvzKd1yyJusSyc/xITuLVqTHrbX8NWz1ssnLTARLHtC9pu7DK7Rhw4ohigNl0SCM1ZUMdN00He6w/AvOuCjs0MSUeVl1BVyJwRYgmCylHliBs7965JAP1KmdQZkRUnqBzF2RwFB478jKmCytGizXwF1/bhEVMZkwWV47ARuwK1aQZxCm7gRCVv7OyNMWCX12VlnyNGLGaLEVSK39pe1sKtBtD5AaANAbQRAF0eAVkCtj0BtvskYBsB2O4BeRHA6XffviSSpxOSx3eQvHwMyeM7SO4YyQXyP2D5OExNJ0i/guyB1OMI1UAKsV4gtlJ8CHNEsYuWRwR4CyGOT0J4eYA9uz6JKoP+cFTZzFMn8xi71cKRwJGuzasn88o7AJjfQfXj0bxwMo9RPajPmKefwLlaVsbA8CE8R3XfwPM3MdDaeDaHgD0sHzfHpXN4wIiex41wEfdvH9FWKonJ3gVQx/TZRKVjV5uhAICWijpsxLaJmQCoafvutk1oVUpQBzgr+S4DuUt6Uue5ndW81zdxslqFz/M6vadGdCao+fovQ6J6h4TRqlVQefPWfM0HVE6+rT4mdYAL+pSpA1w4bQPqABe9TyqCS3MhWmO4eqJRBLgovv1s67hrHaDoRkvqgE9jBHXApxHvztIPtQjquESsUVAHWOsyqaQ1F8oMZLVBBAjmGNz1DBBcPAR1BAhWvDuDEmMFdYQ1pgrqCGu0oJJ+XOPDMWCnjOirLYSG/Q2Ga7+H1AzDlmDYXsOw2S5Sm/fR157QV12jb3pEX0RTcVV5nT4jaKcHUB6g60+gup5ANZxAOZ7S53RKt99Kp9cT9gre+/Z4tfkkqz7eyKoNSLvE6IVTwGO/BrGyXWak70FzPW32+WGz98+y6xg+ncUZOOG8RujyjnGnAASskNcvT7DhHePKk3Q7rn9gnDsbN/CZc8PjuDbueCf8qG+HHxienBHQ1yf5d/R/YJw/GcdorZb8zpc7G5cvv9y70/IxBoEyk6s8PLpP5+Gmjl3fS4S2gsoIbUeNTva0AzdVKDfn7K1RJEpbNYd0YNsRrJKgcsZtjXx35OxOCL2oPPWUnbfpjG2l9hDBieMaU19ljSkgFTGB7LwxwbZSe4gaUzNwzcnE102qwLVVUAeuKSOoA9e8eJe8yom5GkGHFUDtBZUGFP4MDISNIjJ5a4Xq7SskOFM4tKCO/N7EyX2EIqZWQb0IRawIRZwSWo9QxIp3ZyY/wxYjQjBbJ3WGYDOEMCIEU1pQRwjm3aSSjzi/dxyC+Yf8foZ9ZgaOIlQyI3DsBU75twInPHFt88v9W+D06QInuPm/KnBS6WsrJKDjssJJxe9VYpKelDipL64Rgxcva5zU9yoSq+FJkZP64iqxuj6rclLfq0ys+idlTuqL68TghP+6zkl/q0KnzEUv1ctCpzRql7QsdMqTKgud6uQhCp1M4hKkJp1qlzI/JH6I/MDFUJWLoSqVbVQuiqqaCFoUOhn4nytDSmYpmaVklpJZSmYpmaQsLCWTlIWlcKGTCauUklhKYimJpSSWklhKQu5Y6MRFUVUTQV8WOoGUyFIiS4ksJbKUyFIiSaksJZKUylJGoRNffHQOF4VOTTYWMGVqE7WRWiqEqlQIVakQqgmZhU58YdLfuih0Avsq21fZvsr2Vbavsn3DrmHPLHRapixZ6KSmmbPQySQuoqlURFPXGTGbuIrehXo5yjYhzl78fOtVoVOlIpq6ijCXrwK7pbPQKY8lFWWhk55UWehkJotZ6GQSlzJVqgRso+bZW/Sid6Hecd0VwuxFi+JVoVOlirneO4LxfTh4F4VOeWwdWRQ6cX4HH3wWOik3WcxCJ5O4lKmR0aI8A3ATrehdqHdcygU/e9GifFXo1HtpAopCpygKnfobhd7AIiAvCp26TCxASqLQqSYaE3nMKgqduudxTBaFTpUKquooqAqi0KmOgqpdFjpRQRWso8DrKPA6CryOAq+jwOso8DoKvI7ogWRHUehU9Y1txbIm4FmYVWEOUOhktPk9RdkpRfH/piifT1HUsxRFfXFwY56mKMv3Cg+XJynK8cVV8MezDKV+K/+V+iRBKV/sv/IsP9m/l//2J+lJ/mL/5WfZSbry3/8AW3v/eQ==###4904:XlxV32DM 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136ceNrNW0my5CgPvkwfwEw2zoy6SkUwRtSma9HLF3X3HwFCMmnn8HrR/6LKL4UtkAz6NFnKfFsXdf9LxnTb0/2Xibfl9pdU9iZCvJffiX5n+J3pty+/16X8LhcxyHEBsqTbwv3+W0oD9/3xSsMfa/m3fP0lZbrJIO5/S7Xe0lZWUZfj2HLSke/p9Gx5bB0hPVuHlvDkxtfh+joSrkOfqyVMaonTuvK0Ln+1Lq4WFSe1RNWWEyMuZz9VS2XPp0/T9GGaPk5qyUwt/5gdOMmvH0rrm4n3n+VfoSrPqKlQU6Hqumaglj9Mvv8MO1DrC+7UdSlUV+9dGVUUqq98M6PKQg2FKsVO1LKyQl7hZq0aGV4dMHZ7vdkyamHsXL3XMWph7GA6LTJRK2NngMWmmRxFumALVeSEMpt2s9XA2QniAQpya72ZcQYWbgPGi2TUoiAHjLXMxBjutU26jVHLvXararNEBZmtrfcujFpktlUTm2DUIrOtiqd7deVb/sF6I1GBb/kH+tkYtfAt/2C9jlEL3/Lvzz8K3wZQq3pMme6PBznErSh6K9Svv6UWNx3riUo31e1MMPxASa8OB0p6c9jR0uvDjpZeHna09IIOlK2XX9a0y0o3wTGxG/2GY2Btu20nsgOyq7z2ZtocMQlbGXXEpGz48tvSb1ipI24BJHOOfq/w29NvkNSlOo1XdVLv6yWslRhormr+ApsLzExgc8E5D2wusAOB5oqgtRBoHBQgY53Hqzoft4Z+a+YnyGZ+THLfA4lX5sifWEOjgaHhy7FtOavqy4ndGjpFGmzvvqnut1zrW0QRi4mtytxOkCc4NLHLJOObhv4oUTiVKE8SFcU2ieS/kGi/wLBiwRrT7M/fWr4/x9bwLoaRapiwZpmF9V1Y8X1hs5mEHQgZUFj1lrB18c8ciXh/36Fh5rEsEAAhbAdTmg1hihSIguXNEUwMw50N4aiMwFd//YDDUEzeD9hC9Vq0W64/i9kEKOhYCdSis0KuSCc1PexSe7hey20OJk7Vhlu2HMQnQqJCHTirBlQDFXFWmYVREWeNYhwAG+q0FcSVRuApp3GAlBneQdj6A2W9HfW7coBSBdwBqlRiyxkwTMAI3BEutXBEHdCq0s6oCMNyvDegFr7W1FWz9Q3AVQEhsOzZAaJq+EphJRBVemdUBFGjDFG73KnLjfoGSpXbyuHC9BdbzkbTVPsDdkD54yf8B7oItKuGH0aeXDbMDxs+Wzbkh7UT16nkh6mgadHDRVRBMiq6iOQlALV7H+Usl3MgbuUElbdtupOw6e4kdK+7YOlv02xAPasHF8CtRxfAqcMRla4A8W+rH3yB7gIckR8B/5dt2GvbdHt9/Lcz5AV08O+Y36G+I3wHdjJnywHW2+M+PqB7B/WO5R3CO3J3wC6X9pwQbVDU4KXAtp1x0nXYLneipe247ZYTRYqoJ1snj7au2Fhm2EWGOxOfrwOOSDgdAk4+Quhx8j4nqudXyB0u2yuTyfbr3q8dDJLv19CvqS+smgOx8JWFvrKIKwtMEa9X1hAcFxgXjucfLDBOC81q1mBs65TLf6zB9KDB1DUY/r80KGcN5r7O/B9rMM4a9Etfmf8/0mAJYWFg//oBx7k8ff8Bx6f9UbZnpySkSDDn9dpHYiOUKxCaZ6NDxwp4sDhMP/0yfJitzVT8lTpRvZZ52u/Uf8v+O8K1+TY6dF8B7i5O3E9fgQYRui5xBPHGs6mKqChUQqESCjWEGUIMf2gHTao2YYHM+gB5QBUe+mjBsTo6vCZVIQGfFf3Z4SeJQKKUHVZkqVCKyYu61pFj0GEjMijTVp8u7MhDVHXsLR/BV9WFHK6l2seqRJcok2OkKprhqOijw70RbL66ZpurGtAXsokC/7IOR7xMV/9wq5Tlo7mPoitmhoNmE+UotE5EpRyFyYz66F4BdeQohEcJZJMAYBHoK+qXJ5hUhfNxLgJuoYBbKOAWCm0LVZXVrRTaVmo6jJXQPCu1O87TI0+PPD3y9J3ngjx957kgT999OGUP59chT4c8HfJ0/fxm5On6+c3I02HWDn1ZIMOWC7FSmQJhyxXHA7JH1W1VX+Actzca+xuFh4Rr7w1c+7ajZH1mbc8U163t1dj3anumvVWIH9rJac9sVVAIqZog8d6Ftii0RaEtCm1RWItC9j/aTNUvM1/g4jb9SmQVkUPEByM4q9obyGi5W3GHEma0cndWDctoMUN+kbgyU+JqPXqtkAgbGSyWutrvR7+VZ7Cep66Yt8ozVvuU0XJTRspPGauTDNXTVFQ8pqJa6slPqalwSG0V37YioNd5LhBgKiqPAoGYMuHPM075RTh/yF3oXCPnk9TTNlJP9r3cBTDbLood2V7JMmf1n9c4znJNOq+TCJhr2uQ3RNhnEbrLn/e3XkdT9xMR5npEOr4OO8vSU0mb+IYs/qLIkt2L15Ge58eakG8WWco63CRUCcOaUMunQv2jfQcz4FoTBeUkAT17pPuWW4AbKtBpY2iIwn0tGRVTAzo6olKRx3MOo8iTGAdKelUOBqi6JrBgf7ar7VdHCS3tNfKwh4SWJCaQyAIm7Wr71VFiq23aymRH2S0moBYaGv6ZNoJRR73IK0ZFP7Ad6krdkPnaFeuHAlaWrNKJzTl8Mx0to47qEHo9wJ2qODESdXhVOhpGHTUjLxiH4espzhd9PO2wbtWTRMcUlu5JolYHEpJR0cfS2RC1a0OjNobYmqewYqAnqJgYFaOOTBHcXMB3vRUMth1809LBdz0vJ8mpnCSmcpKZUFm9QGV9P9aVOhlMAE8qcbC2U92JYeOCKE0o3uH6kGriBaVtgms7FZj2Cb7dBPcTnDcc9zqZi5pPMljzCe9VwP2LCvirhPrR5CewAOoEgdMZAl/Z+nRV7UkapUvn0qX7qVvxaZXgaPLTOgmFmJzkB0JJcdW0gF0Cwr33yvK/rIHwV9ZNfAnv4N1Vk55WZtLlKMYLZnIxjq9UNLmsZC54dD8skhSU7h+17UoddjUxFmRXI1/EsOUJrVdC65XQekWcMnHrNSJNeIKs4LBe6dSOJm5HMYIF6sifk1VM5iR/XqkjMk6ouoQIlBCBIpr5xBFo1GngCUKVxKmEFJlRB1Ks7N5RGCEESgyXlGbrQ1z64+UiwJZHsOURbbnotnwbtnxk/ePUEfDEpK8vOgT0WaCl3zXpcTLp+xR4eQq8Wu3gddHgIvo6MdfvtAKED+OvPLUClMPsW1nntAVAoG2x79VXJzh4iADCJ8XkVmU7xIOY7xXoLacehu/xuLD93JK7aT3rtB57H2ngYnNrEukMSPxoFMsfAcmr/rB41h+m/ZXlx0JPlufNC+/Ekc8RWdVS4lnpPWFiu+LP51vjZRz1bGuQRwp79yRDGFgXExU+A+9iohIu62LiFWPWBTeChEodjutIUwbWYNVCLAXUluqCbURms4qMo6mPDrfeBDaa++hw742jUUgOwijVuo1lo6KPUsV6KEyxlK7G7DTcTGloqpBrz2rso+tPewJd1r7meSvBQlQC3VUxKvkDjC/zBxgH8gdUHuTAmi5WzagYf2qRGBUjWDMaEQqVyuOj0A9UalMMjDraFBdBVMoiix5+1fRn1b6sgUyxJ8WjgWMkBYKf7OBnn4Lf+m48c8Q8+R7mufsx2RjvF/HMNzCPByVPuuS2qy65h9TjetEc1xDNTgjJCuocGP0EnKHV0lW4wL+Ite1sTo1ca556Jxy6yN2d9lBV23bIQ/Zy7IrxS8T4xb5KfBlxiaHLihZcnGPoNgnnJuHWc+EOGKqUmxvCEENH3MJb7172mJ9iZMsRHVKVGDjuKKSahDzKZifZtgmp3YRO+8FRcPICop1BRyF91F8Y3m1wPyjhqk0ujTa55YW7MoeIHzdw9v6zGm3x1iGNPUlApk63ZSHqMMXDvFYqmmJK30nWqWQc5kCdZCjRNgT0UJXDNJKDEiNBoFKQGle2tIEoiU03EKUBI4S7shXsYFqCN+3YqOijA+bk6GKXrBLc3JP+UPUXnOR9bZaNpj5K2CvZaO6jI/ANicRtcWyuNVdF5ADtY6K5BFhKr/3wjlel0a+CO1kOUrXJK7VMDg+RsxIDjYKmYJRFmp6Nij46+tmxOA6Wmfy48YGCCrwbXRCV+XHYQVAXN7yv0bGpAvPuRuefCuTdkQejAnl35O2oQI6n6NnfivxVlFrE7EnkWtqsW6H6A0bUxOZejqrY0R9Q3R/YH/2Bx+KimGLe9UXMaxj+XzfBzbnIz2NWfb9qZt8nvH4SoYbHCHVUCFU9YGcVQjdSe/ZphdB/GHUcUnmqKvEMzPbhKMQJzM4bexjaV0t1lh7c8vvpQVX9OnOCQHt+sbI3w8LDJ1SmmjJ1VptLHyx6V9OiEbDccrXo80Lvw2v0Tx0sOaeZRxEuvr36YkbRukrNq28sHnJn1kQ7Zk3o6yrHkocUfTmWPNSOUdH8Ua+4lK1HvLyadtUM4kb8uisWCGHwB1Qq5Y0YbVccfROjUuEw05pYR5DvsAQ3t+ZmWXOr/XOu6rLCsDU4rOpwi/BGfGYNq8hhFrJSx9de1D9kOA4nolJIij1BMBurL45UgtW8MckSlcXYmVFHbE0tSJp1tmNbFFC7lBVv+9dk2GMF1JGu/VOTcQLypDdsj07YHu0eseEMFJ6XtGRN+M3Wwo/m4ZHxC5945c8/lKDPHII52/zBnH2JFszZl2jB8ByOJir7Eg1eU/0SzdKXaK2yVbToz0uHr/LM+gXmqkc9n5UO/f2iwYfH5Nfg/NEnaeuLCqGe4Fv9i0/Swv20jZ0H34E3snvlt4ugWywjr5m/l1pMH7ZoHD8P3paLNqBdf9x3ory9SCGLZX8hZXw3gXrpW+h67s7agXb1DVGuPjkTy/jmTHzvm7P0vAT5kC/xxxcmLxqF9s+bnpSdv9aL+MJGK3dazvMlbnphK4uixSG1wPIjDx1b6AMFhZaYKfW9bw7Zp79+I4NLfkWh/g+SxsS6###5336:XlxV32DM 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In+Q6KYpL7innM6JNGqZrihYj8coyD+JAl066RafGiKdI2CI36gniIzPIyB9GQHl2xFQnkRAeSkC3MjppQgwW3R7dmeFWwSExwho34mA+M0ImH8QATPwvcDxTzHNEYbpeUQiNvl09H3E70y8vOSg5XTQadh4i4L+YNh9GHb5dhRY9vxV6Iz3X63xOPrX9/EXx3yhyRmR6cuITE8icv4yIuXLiHytpmDXJunFiJoZBulKf+kWUenB8TG8D8WfRZRmchPETX78PZ52FyKXkHX/g7BN3wzb9Qdhu94K1/Rl4ZpuhSt8WbieoTe/hIJ8ouAM23wz7PID76WfeG++5Yb1QUiY6ntaPySH8jQkNZvtDMiPJl8xK58jPjd58dF3k+f06Wg5RzxzUHohuLIV0y+CVL5u/ODkgsZPPlvHRz0kn9+FxSfNyKfWyL80Ep969m59w81yA2d7wE1J7yMbfRX18q2o/6TbejJ2/womZ9T/3jDygntvjlOYmKHKW3hL4R0WCmahLRwaWfNvY0t9N49F03g7ls8jWp4cqOSp778z/zPsfGd+fn4c/Ob89Wkkv7J/eXH/8if7H0fXiBOYrZRPwLRxNM55SuHL1eSL1b7v1/JkpaHRf1EvX+2P9MK+5Ow1/szfP5v/q79/Nv9XvP90/vrb+enF/acX959e3H96cf/y4v7lxf3Li/kuvpiv4ov5Kv6P9P/ov8CuLvzh/n86/+P+fzr/4/4/zP9/IFvvmQ==###2584:XlxV32DM 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\ No newline at end of file
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiwrap_bitgen.xwbt 0 → 100644
View file @ a64d58e7
INTSTYLE=ise
INFILE=C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav\spiwrap.ncd
OUTFILE=C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav\spiwrap.bit
FAMILY=Spartan6
PART=xc6slx45-2csg324
WORKINGDIR=C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav
LICENSE=ISE
USER_INFO=179841373_174164856_206270303_042
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiwrap_guide.ncd 0 → 100644
View file @ a64d58e7
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6
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stqALcYWtGqP2LJrLTvdxQHGZ/BSh7W5Qz8S/UCKxCMkGGIxcGHJvWOYwt7q0VGMFZp6dRS2FIWtiXpXrff/A7YCcZE=###4448:XlxV32DM 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4f8eNq1WlF22zAMu5IogpJ9nW3N/Y8wxW23dakikUQ+9l6fY4MURQEU3vATN3Sc0PHvDVWrdrvd/zZoLcUqBL/Gc9GGah1mdfyO8YaoaillPL3esYFggOn43Y7xG+wcaMc/b9zwGO3Yjlb1TEYTPR3RjmQ0dcTqyVhQcURr2ZVpcUSzdI80RzSkK+npSE2vzdMlNb1vnrVJem2eLinps73fJZJmEnVFyzJJd8Tq6TqaI1qWSf7ycVnGsvSeVUc0pLu/O6IpUdnW0SpN2daxJL2y4ohWiMq2inYSdW0V6yCq2ipWJ2raKlYjKtoqlhH1bBXrzh7Xm+PJH8T/InW08fzt6tkvse7ffChiDkOvd7J56AbG43d2fff4HFs5PX4nE7z3aTZbp0LNSbbwrozuv3+fUygjTDM6yVXvVDy9NImH93y17/v9vCfe+SKH0dMIuuhunXxnl+5+t6qWzmnFTHvrOgh5aLA2MWbSaafEmGmvTju1fs4kuHrBv64ZlygVTVxnVSaVZu9cp+KdaTUAVYPrgtt2NNPIOekS7/xaJVNbM5GQ63JedXkbo+NtTHzneMM+MhFf9oFz+hk9xxdC5jBx6c+ai2S5xraYFby7juVpF4KeCUHPJH0qvftlW7Vx7L9jhTNkC2UUVbN1RkLNZ62HQtYyX35Gzu/k7uYW3vP9PKhT5brni5NBKxXPqKuVcHZRbl7P0AivcdbJnbsDYbzYFOPuuPQNxMjzudDnvp3Zkz3LMubrVd27Y86P6u3OCUT6jmfBrnY6TtdfP77g1qgjEsKaTJLBvNSBlXZKtnGdt41gHctLchQXbsDj3c7QOUESdqe/BNd3EnmTJQgeMNIeMAgeMMgeMAgeMAh3ZhDuzCB7wCD7JyB4OiB4wKDemkG+84LgAYN8b0aejUKqgZdo+uTWENJee1GOupwjNeARG/l2pUGP+CH70DlWAp8YmeOM7BEbwSM2sg9hBL0zgt4ZwSM2sn9hVL/BCHdFo6qdpT1iI+ulkbXOyB6xUSd5I3vElvaIQfaIQfaIQfWIQfaIQeZmEDxikD1ikDkW5CkGVM4GwSMG2SM28hnVF8yyzDk75BUv5v+o/oLgGYOUB+N/KY5Yl5+e8ZT2MXoaYe4p/YvB8JT2c5rf1DzrOgh5aKg28znkCOH571ueOhVqThLE807cMbT5vBzdgU7F2+OV/Lz8idYILNXSLNUILNXILNUILNUILNUILNVIzvdzvDhLNQJLNZKz9BwvylKNzFIt4YJ/n9NvzUmo0A==###1524:XlxV32DM 3fff 5dceNq9Wkta4zAMvpL1ipNyjjnAAO2S3az4uPu4SSi0JLVs/WUBbWPpt962FU96tJOykEhK+qInzTqplL/lOUsuz8+/9PzbWElf7WRjGTGbyv9hk28Pb6qg2SaXntFMjMvHff68yS87uMt8NXmyHrWMW+EtFLZKQg7OoTydZ9rRilyzzyiz5luaoS0ydOENAQ1/8tlO9Gg1GusW4xk75jlzyeHPirrV7+TFlnehaBTJ2k3rTQ1epB2Z1BGn9yNhEO6K9f7ozI58HsMYdf/XMcxlX28dMJdl3FWlQTvakce65OnNt7pEBJWnnrG5sT5lqHwGlm/CetOFd9+fY9euyXbtr514tKM5Q/EMqi1VpWvbNUjVevaweki7OibAWpHAWRlfe7RqJ22LrGrl0ab9rbliNarjAFiB2s5VUs2ZVNWLqjLVMXIYQap74dQUQeTCq+2oEkCvESCHdNlm2F0Hxi68/nNMAlS1Nh3JhXf/vNdn9f7dWQLvztos5qsluN0ZAyoThysTAyoTgysTAyoTAyoTAyoTN56lxy68/srEgMrEjbtw6sLrPYUyuEpxdZfDcC9mKF5NQwp2owXcjabubjQButEEyBABd6MF2o0m8DmVALWXAN1oh/fDCNJgi71qEcjHLbywRFK1rAC6zALuMgsg6gSw4gugqyLQLrMAu8wCOOMLdH2XcJdZwDsEAa/uAu4yC3S3IOAus4S7zAzuMjO4y8zQLjM/YPVGdpnpYfWwv8ssD9vT9XeZBdCBTYBdUwJUeAbowiA5EN3kEuUz3uiQSVwYN6eZK9R+7tQo//dYucc3BWaVNaL6NK5x1+am0NzkiGMJSZDCEpBTAkTUxuRIv4KhTRj+LBBXZRQABoV9oVV/ToCYmNpza/72fGUR7pVkFwsjUVPGOvTyRpmE6oWG6p2G5rbQ3AbIbAPIH6tPBo/mmDz6KxjahNGSDQqoudpbc7t8UreFAHSSrly7vtHSmif++zAEuIsprtuKlS5kzz13tx2GkA+G0NyRaunH8PoxFocxLXIgm3xxQOF723UJNBQNCvDk8CsY2oTRukNuwZCwTdXZm+71qgA8IoA6K+E6SyE7cCg7OTR3Cs3detL0xQ0BOokCeM8jIa/H37sr4O2ruW65ReMnlsP1nsHgzIJHy2EAOdR1owcpRywysH2Yti5Be2WxTj7a5/v4eDslOqSDvL/R8Xh4zk//6Ph64Kc/dHw5sNl7Ca5R/l6Ai4Gs5JPw7dFqGV8uCRbqrGaFRlU/XwR/Hc2+jH0yMy0cuTydVbhKyvnzjDOLXKb6cZy7Q3k7i53O87Tx3HDUDpeb3JYti16/yp750sVyC8Uc+CYrdbqiZhk/W5Arha3fZZd6XtpXCg81N1DTuZHZQK1N1KmBuknHDVreof0aX2izvghdrjSU6PmMoJUnrzwL3f4r13MU8AVhjpMlU76jXMavEC78JbLOvF+jhXvNSxf6ff6TxdA7+PU0cy5jt3iXp4VK0n9vbqJB###3012:XlxV32DM 34f1 baceNq9WsmS2zYQ/Rl/APaFuriSSw4+xJXkAwiCOLrKh+Simn9PA6TIR1DiImlsj0YU8LobvTygSQ1TQnmVlNBJJSl10ow+99oy9vHxIzHRsEZef/C+b4K//Mv72IjLP7zvGiHlVXJpZUvCQnEVtVReK6UlKdNOSqm0p9+CsWFeCcIbQluldTaosuE8P2lIqqMxS0uQKmmtldQ0lhekJGPD0tRtJGtRhuTIUG1xC1nb0EnqcxIL/Lz2fBVWK7kjS5GinxyPWU+RMkWKTQidEVpq+RAtpJkQR9DiBJpLdwqtTqHZCfTaR1tj5zxM8VcTcpTaiLpYxlz1uY4nLFXFrTJGGZszNeEGmTnTGZlKvetS/aOGheRN60LqJqOU5JmS8yxJj/zKVw+17spRFT6n+YQcbCl8GhdLfVo8QuXPq41IwkYUFhuRMv4qye2XNyK+uRHxrO0XbEX8rEwlcXY7GqT7kVCsooYocmpC6IJ4hGYFbQ6hhXQF7Q6iM0kVILbRhf7g2TZaFHTlpbZ30bysu6BHxJZuPq7b7OtebGB8XJM5aIUVtDvkgblhD2jOcdRHo16wq5ir/iHWTPN7WAPz+1h1AusOY+3g20Hscd/cCd/cCd/cCd/8Cd/8Cd+oMk94l9HqFNqdQPMTPmb0GS/FKS/F2ktijFjzekTrCXHT3UlOaHm3OblJmQmph1ZFiwNSdkIOUuumRpbjWk06yjkynKSVnkctTtGw1aoc1L+pYathOaj/CQ3UvLBpbqVxHq9x+fOq6VHQ9MRF08MdvxIRX2152E7Lo35Ry6NOtzzqpZZHwd0A270Hu13PBL1/PyCkn5ADUY/fERTZT7gnGPR+zl3BoPud9wVDBM/dGWggSVqSxJdHFGyHJqL0Qls0kTs0sadpUmyepok9TRO7eYM8rOK+lF7cANePEdyEOH67PJRLv5AazjF2QKqcY7mgHhBLQqkcJ9aRk+gJUu2eHUdKn9WfsfSfoeMDKrKRSGYmUseXRGrdtbRErxLp3c/6nqHRW5717VBIj4W++YxvRNyo0G+gsV3k0MrdR2to4Q4/yxrbxaeeZhXZT3ieVfR+0hOtovutz7TKzfq5s8sC5WRFufY9lHv/U63nzq43PdXaPbsEFHzd2unVKcSAqDV6SCoHoq7v6x6RSd+5GxS7UmZCPnPSbdPwuZNul4JPnHRropw96XbJu3PSOaCdXtKuC9dys/Yq7d5/Z/Uc7d50Z7VLO7VBpPWJ9/gByb0Tj60ovU07oPZ4Th6g3XheHpeyldSZ89J+0nlpP/G8tG8/L+3p89LPxFV2+XU0v5bDUtLatHaqg68NSvENY7eKrT/TVT/aaGcbMpywoU7YCLMN0y43oLS0EUcbvHAvsyKiBfwE+rtZv+5P6NcH9cdZP48H9HPpb98+H9Lfz/oFP6FfHtSf4JnBUr+htkveyTGb1l8ySu+AuLMfuuorJpC/i13vHkOj8ngd9+0vpfMcz7zKXnMGXosnvBa7XusTXusHzY18wetBevBaj15z8lqNtaQWXvfxWv5+pbamplp6zmuQP+i1Lsx+vI5trwfpPKdKk/e8Hnar77GVPOaTeeAT21xLiS3xk2Z3I2z2NdUaS+7FnPt2uU8FdqUVtnd8VCfyNnzlen9l6sX6US+zZtaznffBiyHv6gU9a/bp1jW84dcSeX7JA/kI5+PRNG1CeSLMSFYGuhmpEiL7GpkA2QEy6DIBA7YSDQ5EPYgmXSGTmZEyIhLXyXAi1ipwnXJGUnUvkab83d0NaRApK6QEByQHpARjUsGEqo0pMCYtImtjSgOyRaSpkE4u826cmkWtBlG3ErWAFIj0NbKdkQYqxHi2zLvxohL1EkShZEysoxM5IBkiYZ0GsxldrQLXidmMoUZGQHpEVjVvOTigIb2WgzFtcSLUKsCYbhFZGxMMkFD7VvAKacE6qrS1cRuXKbIO4gyeWwfVie44DACOQ6ExHAf+OhyvtgS7qCoE1i64fgbyxZLTsvhtDyTlUNK2r0ra9sBaDnS2CVKQcBzChplJELaA4xAejvGpNzybYNE9Aus14wbYIbDa/5yAguOQMycwkkAlJ8FrbnACss8VTqjKqAlQkZAl54G/EULqAhxRLZSK60CihaC6CPsipNdzCHYHmtoesuYETkDQHfjVYv4dRCK0EDsPQQ0BCt47nEAJIGnHwXEPmewERNv3OIHBhWrqMD8tONh5qEuHEh6MW7ThgY8WV9VCSARKYI8hIOWRQZ4sbCaR4wSEJOIuE1GVg0RFlPCwqhhwAjyPQNWIx0PUOAGbQYScxx5LF/3owfMIOe8lGpc4ARmMCifQOGSwN0D3OG9RH//9zdsSRvrPrn+1tK8Skzgdk5z6QkEbj/Rk+g/emstPTlQMqvR81KETnobd5QtvZWMjzchYZhjM2PzI54b4CDIbWEMcQFTpLVYQiVpEuAcxMyT/+/r19ytnwjW97GnHNYlGfruGKx/oSg4kyZtEfWiiPSL1gRzs28sHAdQQkdgk3zUpECpIehl6ETrQeAj0ciRJYx1p6gS9PL1ovKPNngKYaINJkeSoO0kxj5EuKptE+U59tkjjid5pE0+JcJSSlLrbKoTPKRO0TFou/VCRtJcvwlNvKfIi21IcBCAfSTinSNXjqumo46tmiDY0pRtHa/TUX3hhaKvhjaf1tdI2LbWWLRG7pbUFRgcR1U7odNNRDCLvqK4sVaOjwqPPxPNIp1lPbXhlplgxDcWfE4kEnTdKmhqkMshSy8MaowJ1jhNC2L4UmSqTmmJucghEDkFsvM/voVHx8k3QGuT1m+3o908bLj9E3pXoLRf25eP+BH80kUmRrafRel6W8a4xuShq690nWXdstE4BaaynXOU/pa+th0+xTiz58/qddjd2+U7bDKd6ZPnDz/xMpnwSgnqxn4Vaqbz78b3LuSpXfc5YvqJegPJWrmSOZbnSOaLlyua4lqu2JD9fddnjcpUPG3mhBf0P7pk1dg==
\ No newline at end of file
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/tb1.wcfg 0 → 100644
View file @ a64d58e7
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc_tb_isim_beh1.wdb" id="1" type="auto">
<top_modules>
<top_module name="glbl" />
<top_module name="spiifc_tb" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="19" />
<wvobject fp_name="/spiifc_tb/SPI_MISO" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SPI_MISO</obj_property>
<obj_property name="ObjectShortName">SPI_MISO</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/txMemAddr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">txMemAddr[11:0]</obj_property>
<obj_property name="ObjectShortName">txMemAddr[11:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/txMemData" type="array" db_ref_id="1">
<obj_property name="ElementShortName">txMemData[7:0]</obj_property>
<obj_property name="ObjectShortName">txMemData[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/rcMemAddr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">rcMemAddr[11:0]</obj_property>
<obj_property name="ObjectShortName">rcMemAddr[11:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/rcMemData" type="array" db_ref_id="1">
<obj_property name="ElementShortName">rcMemData[7:0]</obj_property>
<obj_property name="ObjectShortName">rcMemData[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/rcMemWE" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rcMemWE</obj_property>
<obj_property name="ObjectShortName">rcMemWE</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/debug_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">debug_out[7:0]</obj_property>
<obj_property name="ObjectShortName">debug_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/Reset" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">Reset</obj_property>
<obj_property name="ObjectShortName">Reset</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/SysClk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SysClk</obj_property>
<obj_property name="ObjectShortName">SysClk</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/SPI_CLK" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SPI_CLK</obj_property>
<obj_property name="ObjectShortName">SPI_CLK</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/SPI_MOSI" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SPI_MOSI</obj_property>
<obj_property name="ObjectShortName">SPI_MOSI</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/SPI_SS" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SPI_SS</obj_property>
<obj_property name="ObjectShortName">SPI_SS</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/SPI_CLK_en" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SPI_CLK_en</obj_property>
<obj_property name="ObjectShortName">SPI_CLK_en</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/fdRcBytes" type="array" db_ref_id="1">
<obj_property name="ElementShortName">fdRcBytes[31:0]</obj_property>
<obj_property name="ObjectShortName">fdRcBytes[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/fdTxBytes" type="array" db_ref_id="1">
<obj_property name="ElementShortName">fdTxBytes[31:0]</obj_property>
<obj_property name="ObjectShortName">fdTxBytes[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/dummy" type="array" db_ref_id="1">
<obj_property name="ElementShortName">dummy[31:0]</obj_property>
<obj_property name="ObjectShortName">dummy[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/currRcByte" type="array" db_ref_id="1">
<obj_property name="ElementShortName">currRcByte[31:0]</obj_property>
<obj_property name="ObjectShortName">currRcByte[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/rcBytesNotEmpty" type="array" db_ref_id="1">
<obj_property name="ElementShortName">rcBytesNotEmpty[31:0]</obj_property>
<obj_property name="ObjectShortName">rcBytesNotEmpty[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/rcBytesStr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">rcBytesStr[80:1]</obj_property>
<obj_property name="ObjectShortName">rcBytesStr[80:1]</obj_property>
</wvobject>
</wave_config>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/tb2.wcfg 0 → 100644
View file @ a64d58e7
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc_tb2_isim_beh1.wdb" id="1" type="auto">
<top_modules>
<top_module name="glbl" />
<top_module name="spiifc_tb2" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="19" />
<wvobject fp_name="/spiifc_tb2/SPI_MISO" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SPI_MISO</obj_property>
<obj_property name="ObjectShortName">SPI_MISO</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/txMemAddr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">txMemAddr[11:0]</obj_property>
<obj_property name="ObjectShortName">txMemAddr[11:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/txMemData" type="array" db_ref_id="1">
<obj_property name="ElementShortName">txMemData[7:0]</obj_property>
<obj_property name="ObjectShortName">txMemData[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/rcMemAddr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">rcMemAddr[11:0]</obj_property>
<obj_property name="ObjectShortName">rcMemAddr[11:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/rcMemData" type="array" db_ref_id="1">
<obj_property name="ElementShortName">rcMemData[7:0]</obj_property>
<obj_property name="ObjectShortName">rcMemData[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/rcMemWE" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rcMemWE</obj_property>
<obj_property name="ObjectShortName">rcMemWE</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/debug_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">debug_out[7:0]</obj_property>
<obj_property name="ObjectShortName">debug_out[7:0]</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/Reset" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">Reset</obj_property>
<obj_property name="ObjectShortName">Reset</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/SysClk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SysClk</obj_property>
<obj_property name="ObjectShortName">SysClk</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/SPI_CLK" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SPI_CLK</obj_property>
<obj_property name="ObjectShortName">SPI_CLK</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/SPI_MOSI" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SPI_MOSI</obj_property>
<obj_property name="ObjectShortName">SPI_MOSI</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/SPI_SS" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SPI_SS</obj_property>
<obj_property name="ObjectShortName">SPI_SS</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/SPI_CLK_en" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SPI_CLK_en</obj_property>
<obj_property name="ObjectShortName">SPI_CLK_en</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/fdRcBytes" type="array" db_ref_id="1">
<obj_property name="ElementShortName">fdRcBytes[31:0]</obj_property>
<obj_property name="ObjectShortName">fdRcBytes[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/fdTxBytes" type="array" db_ref_id="1">
<obj_property name="ElementShortName">fdTxBytes[31:0]</obj_property>
<obj_property name="ObjectShortName">fdTxBytes[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/dummy" type="array" db_ref_id="1">
<obj_property name="ElementShortName">dummy[31:0]</obj_property>
<obj_property name="ObjectShortName">dummy[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/currRcByte" type="array" db_ref_id="1">
<obj_property name="ElementShortName">currRcByte[31:0]</obj_property>
<obj_property name="ObjectShortName">currRcByte[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/rcBytesNotEmpty" type="array" db_ref_id="1">
<obj_property name="ElementShortName">rcBytesNotEmpty[31:0]</obj_property>
<obj_property name="ObjectShortName">rcBytesNotEmpty[31:0]</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/rcBytesStr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">rcBytesStr[80:1]</obj_property>
<obj_property name="ObjectShortName">rcBytesStr[80:1]</obj_property>
</wvobject>
</wave_config>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/tb2_fastclock.wcfg 0 → 100644
View file @ a64d58e7
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc_tb2_isim_beh.wdb" id="1" type="auto">
<top_modules>
<top_module name="glbl" />
<top_module name="spiifc_tb2" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="23" />
<wvobject fp_name="/spiifc_tb2/SPI_MISO" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SPI_MISO</obj_property>
<obj_property name="ObjectShortName">SPI_MISO</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/txMemAddr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">txMemAddr[11:0]</obj_property>
<obj_property name="ObjectShortName">txMemAddr[11:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/rcMemAddr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">rcMemAddr[11:0]</obj_property>
<obj_property name="ObjectShortName">rcMemAddr[11:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/rcMemData" type="array" db_ref_id="1">
<obj_property name="ElementShortName">rcMemData[7:0]</obj_property>
<obj_property name="ObjectShortName">rcMemData[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/rcMemWE" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rcMemWE</obj_property>
<obj_property name="ObjectShortName">rcMemWE</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/debug_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">debug_out[7:0]</obj_property>
<obj_property name="ObjectShortName">debug_out[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/Reset" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">Reset</obj_property>
<obj_property name="ObjectShortName">Reset</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/SysClk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SysClk</obj_property>
<obj_property name="ObjectShortName">SysClk</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/SPI_CLK" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SPI_CLK</obj_property>
<obj_property name="ObjectShortName">SPI_CLK</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/SPI_MOSI" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SPI_MOSI</obj_property>
<obj_property name="ObjectShortName">SPI_MOSI</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/SPI_SS" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SPI_SS</obj_property>
<obj_property name="ObjectShortName">SPI_SS</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/txMemData" type="array" db_ref_id="1">
<obj_property name="ElementShortName">txMemData[7:0]</obj_property>
<obj_property name="ObjectShortName">txMemData[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/SPI_CLK_en" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SPI_CLK_en</obj_property>
<obj_property name="ObjectShortName">SPI_CLK_en</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/fdRcBytes" type="array" db_ref_id="1">
<obj_property name="ElementShortName">fdRcBytes[31:0]</obj_property>
<obj_property name="ObjectShortName">fdRcBytes[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/fdTxBytes" type="array" db_ref_id="1">
<obj_property name="ElementShortName">fdTxBytes[31:0]</obj_property>
<obj_property name="ObjectShortName">fdTxBytes[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/dummy" type="array" db_ref_id="1">
<obj_property name="ElementShortName">dummy[31:0]</obj_property>
<obj_property name="ObjectShortName">dummy[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/currRcByte" type="array" db_ref_id="1">
<obj_property name="ElementShortName">currRcByte[31:0]</obj_property>
<obj_property name="ObjectShortName">currRcByte[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/rcBytesNotEmpty" type="array" db_ref_id="1">
<obj_property name="ElementShortName">rcBytesNotEmpty[31:0]</obj_property>
<obj_property name="ObjectShortName">rcBytesNotEmpty[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/rcBytesStr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">rcBytesStr[80:1]</obj_property>
<obj_property name="ObjectShortName">rcBytesStr[80:1]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/uut/rcByteValid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rcByteValid</obj_property>
<obj_property name="ObjectShortName">rcByteValid</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/uut/rcByte" type="array" db_ref_id="1">
<obj_property name="ElementShortName">rcByte[7:0]</obj_property>
<obj_property name="ObjectShortName">rcByte[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/uut/rcBitIndex" type="array" db_ref_id="1">
<obj_property name="ElementShortName">rcBitIndex[2:0]</obj_property>
<obj_property name="ObjectShortName">rcBitIndex[2:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb2/uut/state" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">state</obj_property>
<obj_property name="ObjectShortName">state</obj_property>
</wvobject>
</wave_config>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/tb_fastclock.wcfg 0 → 100644
View file @ a64d58e7
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc_tb_isim_beh.wdb" id="1" type="auto">
<top_modules>
<top_module name="glbl" />
<top_module name="spiifc_tb" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="30" />
<wvobject fp_name="/spiifc_tb/SPI_MISO" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SPI_MISO</obj_property>
<obj_property name="ObjectShortName">SPI_MISO</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/txMemAddr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">txMemAddr[11:0]</obj_property>
<obj_property name="ObjectShortName">txMemAddr[11:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/txMemData" type="array" db_ref_id="1">
<obj_property name="ElementShortName">txMemData[7:0]</obj_property>
<obj_property name="ObjectShortName">txMemData[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/rcMemAddr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">rcMemAddr[11:0]</obj_property>
<obj_property name="ObjectShortName">rcMemAddr[11:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/rcMemData" type="array" db_ref_id="1">
<obj_property name="ElementShortName">rcMemData[7:0]</obj_property>
<obj_property name="ObjectShortName">rcMemData[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/rcMemWE" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rcMemWE</obj_property>
<obj_property name="ObjectShortName">rcMemWE</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/debug_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">debug_out[7:0]</obj_property>
<obj_property name="ObjectShortName">debug_out[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/Reset" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">Reset</obj_property>
<obj_property name="ObjectShortName">Reset</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/SysClk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SysClk</obj_property>
<obj_property name="ObjectShortName">SysClk</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/SPI_CLK" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SPI_CLK</obj_property>
<obj_property name="ObjectShortName">SPI_CLK</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/SPI_MOSI" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SPI_MOSI</obj_property>
<obj_property name="ObjectShortName">SPI_MOSI</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/SPI_SS" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SPI_SS</obj_property>
<obj_property name="ObjectShortName">SPI_SS</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/SPI_CLK_en" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SPI_CLK_en</obj_property>
<obj_property name="ObjectShortName">SPI_CLK_en</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/fdRcBytes" type="array" db_ref_id="1">
<obj_property name="ElementShortName">fdRcBytes[31:0]</obj_property>
<obj_property name="ObjectShortName">fdRcBytes[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/fdTxBytes" type="array" db_ref_id="1">
<obj_property name="ElementShortName">fdTxBytes[31:0]</obj_property>
<obj_property name="ObjectShortName">fdTxBytes[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/dummy" type="array" db_ref_id="1">
<obj_property name="ElementShortName">dummy[31:0]</obj_property>
<obj_property name="ObjectShortName">dummy[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/currRcByte" type="array" db_ref_id="1">
<obj_property name="ElementShortName">currRcByte[31:0]</obj_property>
<obj_property name="ObjectShortName">currRcByte[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/rcBytesNotEmpty" type="array" db_ref_id="1">
<obj_property name="ElementShortName">rcBytesNotEmpty[31:0]</obj_property>
<obj_property name="ObjectShortName">rcBytesNotEmpty[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/rcBytesStr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">rcBytesStr[80:1]</obj_property>
<obj_property name="ObjectShortName">rcBytesStr[80:1]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/uut/packetStart" type="logic" db_ref_id="1">
<obj_property name="DisplayName">label</obj_property>
<obj_property name="ElementShortName">packetStart</obj_property>
<obj_property name="ObjectShortName">packetStart</obj_property>
<obj_property name="label">packetStart</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/uut/validSpiBit" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">validSpiBit</obj_property>
<obj_property name="ObjectShortName">validSpiBit</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/uut/rcByteValid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rcByteValid</obj_property>
<obj_property name="ObjectShortName">rcByteValid</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/uut/state" type="array" db_ref_id="1">
<obj_property name="ElementShortName">state[7:0]</obj_property>
<obj_property name="ObjectShortName">state[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/uut/state_reg" type="array" db_ref_id="1">
<obj_property name="ElementShortName">state_reg[7:0]</obj_property>
<obj_property name="ObjectShortName">state_reg[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/uut/rcByteValid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rcByteValid</obj_property>
<obj_property name="ObjectShortName">rcByteValid</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/uut/rcByte" type="array" db_ref_id="1">
<obj_property name="ElementShortName">rcByte[7:0]</obj_property>
<obj_property name="ObjectShortName">rcByte[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/uut/txBitIndex" type="array" db_ref_id="1">
<obj_property name="ElementShortName">txBitIndex[2:0]</obj_property>
<obj_property name="ObjectShortName">txBitIndex[2:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/uut/txBitIndex_reg" type="array" db_ref_id="1">
<obj_property name="ElementShortName">txBitIndex_reg[2:0]</obj_property>
<obj_property name="ObjectShortName">txBitIndex_reg[2:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/uut/txMemAddr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">txMemAddr[11:0]</obj_property>
<obj_property name="ObjectShortName">txMemAddr[11:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_tb/uut/txMemData" type="array" db_ref_id="1">
<obj_property name="ElementShortName">txMemData[7:0]</obj_property>
<obj_property name="ObjectShortName">txMemData[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
</wave_config>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/tb_writereg.wcfg 0 → 100644
View file @ a64d58e7
<?xml version="1.0" encoding="UTF-8"?>
<wave_config>
<wave_state>
</wave_state>
<db_ref_list>
<db_ref path="C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc_writereg_tb_isim_beh.wdb" id="1" type="auto">
<top_modules>
<top_module name="glbl" />
<top_module name="spiifc_writereg_tb" />
</top_modules>
</db_ref>
</db_ref_list>
<WVObjectSize size="33" />
<wvobject fp_name="/spiifc_writereg_tb/SPI_MISO" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SPI_MISO</obj_property>
<obj_property name="ObjectShortName">SPI_MISO</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_writereg_tb/txMemAddr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">txMemAddr[11:0]</obj_property>
<obj_property name="ObjectShortName">txMemAddr[11:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_writereg_tb/rcMemAddr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">rcMemAddr[11:0]</obj_property>
<obj_property name="ObjectShortName">rcMemAddr[11:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_writereg_tb/rcMemData" type="array" db_ref_id="1">
<obj_property name="ElementShortName">rcMemData[7:0]</obj_property>
<obj_property name="ObjectShortName">rcMemData[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_writereg_tb/rcMemWE" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rcMemWE</obj_property>
<obj_property name="ObjectShortName">rcMemWE</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_writereg_tb/debug_out" type="array" db_ref_id="1">
<obj_property name="ElementShortName">debug_out[7:0]</obj_property>
<obj_property name="ObjectShortName">debug_out[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_writereg_tb/Reset" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">Reset</obj_property>
<obj_property name="ObjectShortName">Reset</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_writereg_tb/SysClk" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SysClk</obj_property>
<obj_property name="ObjectShortName">SysClk</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_writereg_tb/SPI_CLK" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SPI_CLK</obj_property>
<obj_property name="ObjectShortName">SPI_CLK</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_writereg_tb/SPI_MOSI" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SPI_MOSI</obj_property>
<obj_property name="ObjectShortName">SPI_MOSI</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_writereg_tb/SPI_SS" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SPI_SS</obj_property>
<obj_property name="ObjectShortName">SPI_SS</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_writereg_tb/txMemData" type="array" db_ref_id="1">
<obj_property name="ElementShortName">txMemData[7:0]</obj_property>
<obj_property name="ObjectShortName">txMemData[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_writereg_tb/SPI_CLK_en" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">SPI_CLK_en</obj_property>
<obj_property name="ObjectShortName">SPI_CLK_en</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_writereg_tb/fdRcBytes" type="array" db_ref_id="1">
<obj_property name="ElementShortName">fdRcBytes[31:0]</obj_property>
<obj_property name="ObjectShortName">fdRcBytes[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_writereg_tb/fdTxBytes" type="array" db_ref_id="1">
<obj_property name="ElementShortName">fdTxBytes[31:0]</obj_property>
<obj_property name="ObjectShortName">fdTxBytes[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_writereg_tb/dummy" type="array" db_ref_id="1">
<obj_property name="ElementShortName">dummy[31:0]</obj_property>
<obj_property name="ObjectShortName">dummy[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_writereg_tb/currRcByte" type="array" db_ref_id="1">
<obj_property name="ElementShortName">currRcByte[31:0]</obj_property>
<obj_property name="ObjectShortName">currRcByte[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_writereg_tb/rcBytesNotEmpty" type="array" db_ref_id="1">
<obj_property name="ElementShortName">rcBytesNotEmpty[31:0]</obj_property>
<obj_property name="ObjectShortName">rcBytesNotEmpty[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_writereg_tb/rcBytesStr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">rcBytesStr[80:1]</obj_property>
<obj_property name="ObjectShortName">rcBytesStr[80:1]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_writereg_tb/uut/regAddr" type="array" db_ref_id="1">
<obj_property name="ElementShortName">regAddr[3:0]</obj_property>
<obj_property name="ObjectShortName">regAddr[3:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_writereg_tb/uut/regReadData" type="array" db_ref_id="1">
<obj_property name="ElementShortName">regReadData[31:0]</obj_property>
<obj_property name="ObjectShortName">regReadData[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_writereg_tb/uut/regWriteEn" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">regWriteEn</obj_property>
<obj_property name="ObjectShortName">regWriteEn</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_writereg_tb/uut/regWriteData" type="array" db_ref_id="1">
<obj_property name="ElementShortName">regWriteData[31:0]</obj_property>
<obj_property name="ObjectShortName">regWriteData[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_writereg_tb/uut/rcByteValid" type="logic" db_ref_id="1">
<obj_property name="ElementShortName">rcByteValid</obj_property>
<obj_property name="ObjectShortName">rcByteValid</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_writereg_tb/uut/rcByte" type="array" db_ref_id="1">
<obj_property name="ElementShortName">rcByte[7:0]</obj_property>
<obj_property name="ObjectShortName">rcByte[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_writereg_tb/uut/state" type="array" db_ref_id="1">
<obj_property name="ElementShortName">state[7:0]</obj_property>
<obj_property name="ObjectShortName">state[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_writereg_tb/uut/state_reg" type="array" db_ref_id="1">
<obj_property name="ElementShortName">state_reg[7:0]</obj_property>
<obj_property name="ObjectShortName">state_reg[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_writereg_tb/uut/command" type="array" db_ref_id="1">
<obj_property name="ElementShortName">command[7:0]</obj_property>
<obj_property name="ObjectShortName">command[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_writereg_tb/uut/rcWordByteId" type="array" db_ref_id="1">
<obj_property name="ElementShortName">rcWordByteId[1:0]</obj_property>
<obj_property name="ObjectShortName">rcWordByteId[1:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_writereg_tb/uut/rcWord" type="array" db_ref_id="1">
<obj_property name="ElementShortName">rcWord[31:0]</obj_property>
<obj_property name="ObjectShortName">rcWord[31:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_writereg_tb/uut/regReadByte_oreg" type="array" db_ref_id="1">
<obj_property name="ElementShortName">regReadByte_oreg[7:0]</obj_property>
<obj_property name="ObjectShortName">regReadByte_oreg[7:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_writereg_tb/uut/txBitIndex" type="array" db_ref_id="1">
<obj_property name="ElementShortName">txBitIndex[2:0]</obj_property>
<obj_property name="ObjectShortName">txBitIndex[2:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
<wvobject fp_name="/spiifc_writereg_tb/uut/txBitIndex_reg" type="array" db_ref_id="1">
<obj_property name="ElementShortName">txBitIndex_reg[2:0]</obj_property>
<obj_property name="ObjectShortName">txBitIndex_reg[2:0]</obj_property>
<obj_property name="Radix">HEXRADIX</obj_property>
</wvobject>
</wave_config>
projnav/xps/pcores/spiifc_v1_00_a/devl/synthesis/spiifc_xst.prj 0 → 100644
View file @ a64d58e7
vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/proc_common_pkg.vhd"
vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ipif_pkg.vhd"
vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_muxcy.vhd"
vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_gate128.vhd"
vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/family_support.vhd"
vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd"
vhdl proc_common_v3_00_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter_f.vhd"
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/flex_addr_cntr.vhd"
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/addr_reg_cntr_brst_flex.vhd"
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plb_address_decoder.vhd"
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/burst_support.vhd"
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/wr_buffer.vhd"
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/be_reset_gen.vhd"
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plb_slave_attachment.vhd"
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/data_mirror_128.vhd"
vhdl plbv46_slave_burst_v1_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plbv46_slave_burst.vhd"
vhdl interrupt_control_v2_01_a "C:\Xilinx\13.2\ISE_DS\EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v2_01_a/hdl/vhdl/interrupt_control.vhd"
verilog spiifc_v1_00_a "../../hdl/verilog/user_logic.v"
vhdl spiifc_v1_00_a "../../hdl/vhdl/spiifc.vhd"
projnav/xps/pcores/spiifc_v1_00_a/devl/synthesis/spiifc_xst.scr 0 → 100644
View file @ a64d58e7
run
-opt_level 2
-opt_mode speed
-ifmt mixed
-ifn "C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\synthesis\spiifc_xst.prj"
-top spiifc
-p virtex6
-ofn "C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\synthesis\spiifc_xst.ngc"
-iobuf NO
-rtlview YES
-hierarchy_separator /
-work_lib spiifc_v1_00_a
projnav/xps/pcores/spiifc_v1_00_a/hdl/verilog/buffermem.v 0 → 100644
View file @ a64d58e7
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2012 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file buffermem.v when simulating
// the core, buffermem. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module buffermem(
clka,
ena,
wea,
addra,
dina,
douta,
clkb,
enb,
web,
addrb,
dinb,
doutb
);
input clka;
input ena;
input [0 : 0] wea;
input [11 : 0] addra;
input [7 : 0] dina;
output [7 : 0] douta;
input clkb;
input enb;
input [0 : 0] web;
input [9 : 0] addrb;
input [31 : 0] dinb;
output [31 : 0] doutb;
// synthesis translate_off
BLK_MEM_GEN_V6_2 #(
.C_ADDRA_WIDTH(12),
.C_ADDRB_WIDTH(10),
.C_ALGORITHM(1),
.C_AXI_ID_WIDTH(4),
.C_AXI_SLAVE_TYPE(0),
.C_AXI_TYPE(1),
.C_BYTE_SIZE(9),
.C_COMMON_CLK(1),
.C_DEFAULT_DATA("0"),
.C_DISABLE_WARN_BHV_COLL(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_FAMILY("spartan6"),
.C_HAS_AXI_ID(0),
.C_HAS_ENA(1),
.C_HAS_ENB(1),
.C_HAS_INJECTERR(0),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_HAS_REGCEA(0),
.C_HAS_REGCEB(0),
.C_HAS_RSTA(0),
.C_HAS_RSTB(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INITA_VAL("0"),
.C_INITB_VAL("0"),
.C_INTERFACE_TYPE(0),
.C_LOAD_INIT_FILE(0),
.C_MEM_TYPE(2),
.C_MUX_PIPELINE_STAGES(0),
.C_PRIM_TYPE(1),
.C_READ_DEPTH_A(4096),
.C_READ_DEPTH_B(1024),
.C_READ_WIDTH_A(8),
.C_READ_WIDTH_B(32),
.C_RST_PRIORITY_A("CE"),
.C_RST_PRIORITY_B("CE"),
.C_RST_TYPE("SYNC"),
.C_RSTRAM_A(0),
.C_RSTRAM_B(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_USE_BYTE_WEA(0),
.C_USE_BYTE_WEB(0),
.C_USE_DEFAULT_DATA(0),
.C_USE_ECC(0),
.C_USE_SOFTECC(0),
.C_WEA_WIDTH(1),
.C_WEB_WIDTH(1),
.C_WRITE_DEPTH_A(4096),
.C_WRITE_DEPTH_B(1024),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_A(8),
.C_WRITE_WIDTH_B(32),
.C_XDEVICEFAMILY("spartan6")
)
inst (
.CLKA(clka),
.ENA(ena),
.WEA(wea),
.ADDRA(addra),
.DINA(dina),
.DOUTA(douta),
.CLKB(clkb),
.ENB(enb),
.WEB(web),
.ADDRB(addrb),
.DINB(dinb),
.DOUTB(doutb),
.RSTA(),
.REGCEA(),
.RSTB(),
.REGCEB(),
.INJECTSBITERR(),
.INJECTDBITERR(),
.SBITERR(),
.DBITERR(),
.RDADDRECC(),
.S_ACLK(),
.S_ARESETN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.S_AXI_INJECTSBITERR(),
.S_AXI_INJECTDBITERR(),
.S_AXI_SBITERR(),
.S_AXI_DBITERR(),
.S_AXI_RDADDRECC()
);
// synthesis translate_on
endmodule
projnav/xps/pcores/spiifc_v1_00_a/hdl/verilog/spiifc.v 0 → 100644
View file @ a64d58e7
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 16:46:12 03/02/2012
// Design Name:
// Module Name: spiifc
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module spiifc(
Reset,
SysClk,
SPI_CLK,
SPI_MISO,
SPI_MOSI,
SPI_SS,
txMemAddr,
txMemData,
rcMemAddr,
rcMemData,
rcMemWE,
regAddr,
regReadData,
regWriteEn,
regWriteData,
debug_out
);
//
// Parameters
//
parameter AddrBits = 12;
parameter RegAddrBits = 4;
//
// Defines
//
`define CMD_READ_START 8'd1
`define CMD_READ_MORE 8'd2
`define CMD_WRITE_START 8'd3
`define CMD_WRITE_MORE 8'd4
`define CMD_INTERRUPT 8'd5
`define CMD_REG_BASE 8'd128
`define CMD_REG_BIT 7
`define CMD_REG_WE_BIT 6
`define CMD_REG_ID_MASK 8'h3F
`define STATE_GET_CMD 8'd0
`define STATE_READING 8'd1
`define STATE_WRITING 8'd2
`define STATE_WRITE_INTR 8'd3
`define STATE_BUILD_WORD 8'd4
`define STATE_SEND_WORD 8'd5
//
// Input/Outputs
//
input Reset;
input SysClk;
input SPI_CLK;
output SPI_MISO; // outgoing (from respect of this module)
input SPI_MOSI; // incoming (from respect of this module)
input SPI_SS;
output [AddrBits-1:0] txMemAddr; // outgoing data
input [7:0] txMemData;
output [AddrBits-1:0] rcMemAddr; // incoming data
output [7:0] rcMemData;
output rcMemWE;
output [RegAddrBits-1:0] regAddr; // Register read address (combinational)
input [31:0] regReadData; // Result of register read
output regWriteEn; // Enable write to register, otherwise read
output [31:0] regWriteData; // Register write data
output [7:0] debug_out;
//
// Registers
//
reg SPI_CLK_reg; // Stabalized version of SPI_CLK
reg SPI_SS_reg; // Stabalized version of SPI_SS
reg SPI_MOSI_reg; // Stabalized version of SPI_MOSI
reg prev_spiClk; // Value of SPI_CLK during last SysClk cycle
reg prev_spiSS; // Value of SPI_SS during last SysClk cycle
reg [7:0] state_reg; // Register backing the 'state' wire
reg [7:0] rcByte_reg; // Register backing 'rcByte'
reg [2:0] rcBitIndex_reg; // Register backing 'rcBitIndex'
reg [AddrBits-1:0] rcMemAddr_reg; // Byte addr to write MOSI data to
reg [7:0] debug_reg; // register backing debug_out signal
reg [2:0] txBitIndex_reg; // Register backing txBitIndex
reg [AddrBits-1:0] txMemAddr_reg; // Register backing txAddr
reg [7:0] command; // Command being handled
reg [31:0] rcWord; // Incoming word being built
reg [1:0] rcWordByteId; // Which byte the in the rcWord to map to
reg [RegAddrBits-1:0] regAddr_reg; // Address of register to read/write to
//
// Wires
//
wire risingSpiClk; // Did the SPI_CLK rise since last SysClk cycle?
wire validSpiBit; // Are the SPI MOSI/MISO bits new and valid?
reg [7:0] state; // Current state in the module's state machine (always @* effectively wire)
wire rcByteValid; // rcByte is valid and new
wire [7:0] rcByte; // Byte received from master
wire [2:0] rcBitIndex; // Bit of rcByte to write to next
reg [2:0] txBitIndex; // bit of txByte to send to master next
reg [AddrBits-1:0] txMemAddr_oreg; // Wirereg piped to txMemAddr output
reg [7:0] regReadByte_oreg; // Which byte of the reg word we're reading out master
// Save buffered SPI inputs
always @(posedge SysClk) begin
SPI_CLK_reg <= SPI_CLK;
SPI_SS_reg <= SPI_SS;
SPI_MOSI_reg <= SPI_MOSI;
end
// Detect new valid bit
always @(posedge SysClk) begin
prev_spiClk <= SPI_CLK_reg;
end
assign risingSpiClk = SPI_CLK_reg & (~prev_spiClk);
assign validSpiBit = risingSpiClk & (~SPI_SS_reg);
// Detect new SPI packet (SS dropped low)
always @(posedge SysClk) begin
prev_spiSS <= SPI_SS_reg;
end
assign packetStart = prev_spiSS & (~SPI_SS_reg);
// Build incoming byte
always @(posedge SysClk) begin
if (validSpiBit) begin
rcByte_reg[rcBitIndex] <= SPI_MOSI_reg;
rcBitIndex_reg <= (rcBitIndex > 0 ? rcBitIndex - 1 : 7);
end else begin
rcBitIndex_reg <= rcBitIndex;
end
end
assign rcBitIndex = (Reset || packetStart ? 7 : rcBitIndex_reg);
assign rcByte = {rcByte_reg[7:1], SPI_MOSI_reg};
assign rcByteValid = (validSpiBit && rcBitIndex == 0 ? 1 : 0);
// Incoming MOSI data buffer management
assign rcMemAddr = rcMemAddr_reg;
assign rcMemData = rcByte;
assign rcMemWE = (state == `STATE_READING && rcByteValid ? 1 : 0);
always @(posedge SysClk) begin
if (Reset || (`STATE_GET_CMD == state && rcByteValid)) begin
rcMemAddr_reg <= 0;
end else if (rcMemWE) begin
rcMemAddr_reg <= rcMemAddr + 1;
end else begin
rcMemAddr_reg <= rcMemAddr;
end
end
// Outgoing MISO data buffer management
always @(*) begin
if (Reset || (state == `STATE_GET_CMD && rcByteValid &&
(rcByte == `CMD_WRITE_START ||
rcByte[`CMD_REG_BIT:`CMD_REG_WE_BIT] == 2'b11)
)) begin
txBitIndex <= 3'd7;
txMemAddr_oreg <= 0;
end else begin
txBitIndex <= txBitIndex_reg;
//txMemAddr_oreg <= txMemAddr_reg;
if ((state == `STATE_WRITING || state == `STATE_SEND_WORD) &&
validSpiBit && txBitIndex == 0) begin
txMemAddr_oreg <= txMemAddr_reg + 1;
end else begin
txMemAddr_oreg <= txMemAddr_reg;
end
end
end
always @(posedge SysClk) begin
if (validSpiBit && (state == `STATE_WRITING || state == `STATE_SEND_WORD)) begin
txBitIndex_reg <= (txBitIndex == 0 ? 7 : txBitIndex - 1);
end else begin
txBitIndex_reg <= txBitIndex;
end
txMemAddr_reg <= txMemAddr;
// if (state == `STATE_WRITING && validSpiBit && txBitIndex == 0) begin
// txMemAddr_reg <= txMemAddr + 1;
// end else begin
// txMemAddr_reg <= txMemAddr;
// end
end
assign txMemAddr = txMemAddr_oreg;
assign SPI_MISO = (state == `STATE_SEND_WORD ? regReadByte_oreg[txBitIndex] : txMemData[txBitIndex]);
// State machine
always @(*) begin
if (Reset || packetStart) begin
state <= `STATE_GET_CMD;
// Handled in state_reg logic, should be latched, not immediate.
// end else if (state_reg == `STATE_GET_CMD && rcByteValid) begin
// state <= rcByte;
end else begin
state <= state_reg;
end
end
always @(posedge SysClk) begin
if (`STATE_GET_CMD == state && rcByteValid) begin
if (`CMD_READ_START == rcByte) begin
state_reg <= `STATE_READING;
end else if (`CMD_READ_MORE == rcByte) begin
state_reg <= `STATE_READING;
end else if (`CMD_WRITE_START == rcByte) begin
state_reg <= `STATE_WRITING;
end else if (`CMD_WRITE_MORE == rcByte) begin
state_reg <= `STATE_WRITING;
end else if (rcByte[`CMD_REG_BIT] != 0) begin
// Register access
rcWordByteId <= 0;
command <= `CMD_REG_BASE; // Write reg Read reg
state_reg <= (rcByte[`CMD_REG_WE_BIT] ? `STATE_BUILD_WORD : `STATE_SEND_WORD);
end else if (`CMD_INTERRUPT == rcByte) begin
// TODO: NYI
end
end else if (`STATE_BUILD_WORD == state && rcByteValid) begin
if (0 == rcWordByteId) begin
rcWord[31:24] <= rcByte;
rcWordByteId <= 1;
end else if (1 == rcWordByteId) begin
rcWord[23:16] <= rcByte;
rcWordByteId <= 2;
end else if (2 == rcWordByteId) begin
rcWord[15:8] <= rcByte;
rcWordByteId <= 3;
end else if (3 == rcWordByteId) begin
rcWord[7:0] <= rcByte;
state_reg <= `STATE_GET_CMD;
end
end else if (`STATE_SEND_WORD == state && rcByteValid) begin
rcWordByteId <= rcWordByteId + 1;
state_reg <= (rcWordByteId == 3 ? `STATE_GET_CMD : `STATE_SEND_WORD);
end else begin
state_reg <= state;
end
end
// Register logic
assign regAddr = (`STATE_GET_CMD == state && rcByteValid && rcByte[`CMD_REG_BIT] ? (rcByte & `CMD_REG_ID_MASK) : regAddr_reg);
assign regWriteEn = (`STATE_BUILD_WORD == state && rcByteValid && 3 == rcWordByteId ? 1 : 0);
assign regWriteData = {rcWord[31:8], rcByte};
always @(posedge SysClk) begin
regAddr_reg <= regAddr;
end
always @(*) begin
case (rcWordByteId)
0: regReadByte_oreg <= regReadData[31:24];
1: regReadByte_oreg <= regReadData[23:16];
2: regReadByte_oreg <= regReadData[15:8];
3: regReadByte_oreg <= regReadData[7:0];
endcase
end
// Debugging
always @(posedge SysClk) begin
if (rcByteValid) begin
debug_reg <= rcByte;
end
end
assign debug_out = debug_reg;
endmodule
projnav/xps/pcores/spiifc_v1_00_a/hdl/verilog/user_logic.v 0 → 100644
View file @ a64d58e7
//----------------------------------------------------------------------------
// user_logic.vhd - module
//----------------------------------------------------------------------------
//
// ***************************************************************************
// ** Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. **
// ** **
// ** Xilinx, Inc. **
// ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
// ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
// ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
// ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
// ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
// ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
// ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
// ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
// ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
// ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
// ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
// ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
// ** FOR A PARTICULAR PURPOSE. **
// ** **
// ***************************************************************************
//
//----------------------------------------------------------------------------
// Filename: user_logic.vhd
// Version: 1.00.a
// Description: User logic module.
// Date: Tue Feb 28 11:11:15 2012 (by Create and Import Peripheral Wizard)
// Verilog Standard: Verilog-2001
//----------------------------------------------------------------------------
// Naming Conventions:
// active low signals: "*_n"
// clock signals: "clk", "clk_div#", "clk_#x"
// reset signals: "rst", "rst_n"
// generics: "C_*"
// user defined types: "*_TYPE"
// state machine next state: "*_ns"
// state machine current state: "*_cs"
// combinatorial signals: "*_com"
// pipelined or register delay signals: "*_d#"
// counter signals: "*cnt*"
// clock enable signals: "*_ce"
// internal version of output port: "*_i"
// device pins: "*_pin"
// ports: "- Names begin with Uppercase"
// processes: "*_PROCESS"
// component instantiations: "<ENTITY_>I_<#|FUNC>"
//----------------------------------------------------------------------------
module user_logic
(
// -- ADD USER PORTS BELOW THIS LINE ---------------
// --USER ports added here
SPI_CLK,
SPI_MOSI,
SPI_MISO,
SPI_SS,
// -- ADD USER PORTS ABOVE THIS LINE ---------------
// -- DO NOT EDIT BELOW THIS LINE ------------------
// -- Bus protocol ports, do not add to or delete
Bus2IP_Clk, // Bus to IP clock
Bus2IP_Reset, // Bus to IP reset
Bus2IP_Addr, // Bus to IP address bus
Bus2IP_CS, // Bus to IP chip select for user logic memory selection
Bus2IP_RNW, // Bus to IP read/not write
Bus2IP_Data, // Bus to IP data bus
Bus2IP_BE, // Bus to IP byte enables
Bus2IP_RdCE, // Bus to IP read chip enable
Bus2IP_WrCE, // Bus to IP write chip enable
Bus2IP_Burst, // Bus to IP burst-mode qualifier
Bus2IP_BurstLength, // Bus to IP burst length
Bus2IP_RdReq, // Bus to IP read request
Bus2IP_WrReq, // Bus to IP write request
IP2Bus_AddrAck, // IP to Bus address acknowledgement
IP2Bus_Data, // IP to Bus data bus
IP2Bus_RdAck, // IP to Bus read transfer acknowledgement
IP2Bus_WrAck, // IP to Bus write transfer acknowledgement
IP2Bus_Error, // IP to Bus error response
IP2Bus_IntrEvent // IP to Bus interrupt event
// -- DO NOT EDIT ABOVE THIS LINE ------------------
); // user_logic
// -- ADD USER PARAMETERS BELOW THIS LINE ------------
// --USER parameters added here
// -- ADD USER PARAMETERS ABOVE THIS LINE ------------
// -- DO NOT EDIT BELOW THIS LINE --------------------
// -- Bus protocol parameters, do not add to or delete
parameter C_SLV_AWIDTH = 32;
parameter C_SLV_DWIDTH = 32;
parameter C_NUM_REG = 16;
parameter C_NUM_MEM = 2;
parameter C_NUM_INTR = 1;
// -- DO NOT EDIT ABOVE THIS LINE --------------------
// -- ADD USER PORTS BELOW THIS LINE -----------------
// --USER ports added here
input SPI_CLK;
input SPI_MOSI;
output SPI_MISO;
input SPI_SS;
// -- ADD USER PORTS ABOVE THIS LINE -----------------
// -- DO NOT EDIT BELOW THIS LINE --------------------
// -- Bus protocol ports, do not add to or delete
input Bus2IP_Clk;
input Bus2IP_Reset;
input [0 : C_SLV_AWIDTH-1] Bus2IP_Addr;
input [0 : C_NUM_MEM-1] Bus2IP_CS;
input Bus2IP_RNW;
input [0 : C_SLV_DWIDTH-1] Bus2IP_Data;
input [0 : C_SLV_DWIDTH/8-1] Bus2IP_BE;
input [0 : C_NUM_REG-1] Bus2IP_RdCE;
input [0 : C_NUM_REG-1] Bus2IP_WrCE;
input Bus2IP_Burst;
input [0 : 8] Bus2IP_BurstLength;
input Bus2IP_RdReq;
input Bus2IP_WrReq;
output IP2Bus_AddrAck;
output [0 : C_SLV_DWIDTH-1] IP2Bus_Data;
output IP2Bus_RdAck;
output IP2Bus_WrAck;
output IP2Bus_Error;
output [0 : C_NUM_INTR-1] IP2Bus_IntrEvent;
// -- DO NOT EDIT ABOVE THIS LINE --------------------
//----------------------------------------------------------------------------
// Implementation
//----------------------------------------------------------------------------
// --USER nets declarations added here, as needed for user logic
// Memmap memory logic lines
wire [0 : C_NUM_MEM-1 ] mem_enb; // Port B: sysbus/dma
wire [0 : C_NUM_MEM-1 ] mem_web;
wire [0 : C_NUM_MEM-1] mem_write;
wire [0 : C_NUM_MEM-1] mem_read;
reg [0 : C_NUM_MEM-1 ] mem_read_prev;
// mosiMem (mem0): data received from master
wire mosiMem_wea;
wire [0 : 11] mosiMem_addra;
wire [0 : 7 ] mosiMem_dina;
wire [0 : 9 ] mosiMem_addrb;
wire [0 : 31] mosiMem_dinb;
wire [0 : 31] mosiMem_doutb;
// misoMem (mem1): data to send to master
wire [0 : 11] misoMem_addra;
wire [0 : 7 ] misoMem_douta;
wire [0 : 9 ] misoMem_addrb;
wire [0 : 31] misoMem_dinb;
wire [0 : 31] misoMem_doutb;
// Nets for user logic slave model s/w accessible register example
reg [0 : C_SLV_DWIDTH-1] slv_reg [0:15];
wire [0 : 15] slv_reg_write_sel;
wire [0 : 15] slv_reg_read_sel;
reg [0 : C_SLV_DWIDTH-1] slv_ip2bus_data;
wire slv_read_ack;
wire slv_write_ack;
integer byte_index, bit_index;
// SPI register access
wire [3 : 0] spiRegAddr;
wire [C_SLV_DWIDTH-1 : 0] spiRegWriteData;
wire spiRegWE;
reg [C_SLV_DWIDTH-1 : 0] spiRegReadData_wreg;
// --USER logic implementation added here
// memory interface logic
assign mem_enb = mem_write | mem_read;
assign mem_web = mem_write;
assign mosiMem_addrb = Bus2IP_Addr[20:29];
assign mosiMem_dinb = Bus2IP_Data;
assign misoMem_addrb = Bus2IP_Addr[20:29];
assign misoMem_dinb = Bus2IP_Data;
assign mem_write = Bus2IP_CS & {C_NUM_MEM{Bus2IP_WrReq & (~Bus2IP_RNW)}};
assign mem_read = Bus2IP_CS & {C_NUM_MEM{Bus2IP_RdReq & Bus2IP_RNW}};
always @(posedge Bus2IP_Clk) begin
mem_read_prev <= mem_read;
end
// Mem0: Memory buffer storing data coming from master
buffermem mosiMem (
.clka(Bus2IP_Clk), // input clka
.ena(1'b1), // input ena
.wea(mosiMem_wea), // Always writing, never reading
.addra({mosiMem_addra}), // input [11 : 0] addra
.dina({mosiMem_dina}), // input [7 : 0] dina
// .douta(mosiMem_douta), // NEVER USED: output [7 : 0] douta
.clkb(Bus2IP_Clk), // input clkb
.enb(mem_enb[0]), // input enb
.web(mem_web[0]), // input [0 : 0] web
.addrb({mosiMem_addrb}), // input [9 : 0] addrb
.dinb({mosiMem_dinb}), // input [31 : 0] dinb
.doutb({mosiMem_doutb}) // output [31 : 0] doutb
);
// Mem1: Memory buffer storing data to send to master
buffermem misoMem (
.clka(Bus2IP_Clk), // input clka
.ena(1'b1), // input ena
.wea(1'b0), // Always reading, never writing
.addra({misoMem_addra}), // input [11 : 0] addra
// .dina(dina), // input [7 : 0] dina
.douta({misoMem_douta}), // output [7 : 0] douta
.clkb(Bus2IP_Clk), // input clkb
.enb(mem_enb[1]), // input enb
.web(mem_web[1]), // input [0 : 0] web
.addrb({misoMem_addrb}), // input [9 : 0] addrb
.dinb({misoMem_dinb}), // input [31 : 0] dinb
.doutb({misoMem_doutb}) // output [31 : 0] doutb
);
spiifc spi (
.Reset(Bus2IP_Reset),
.SysClk(Bus2IP_Clk),
.SPI_CLK(SPI_CLK),
.SPI_MISO(SPI_MISO),
.SPI_MOSI(SPI_MOSI),
.SPI_SS(SPI_SS),
.txMemAddr(misoMem_addra),
.txMemData(misoMem_douta),
.rcMemAddr(mosiMem_addra),
.rcMemData(mosiMem_dina),
.rcMemWE(mosiMem_wea),
.regAddr(spiRegAddr),
.regReadData(spiRegReadData_wreg),
.regWriteData(spiRegWriteData),
.regWriteEn(spiRegWE)
);
// ------------------------------------------------------
// Example code to read/write user logic slave model s/w accessible registers
//
// Note:
// The example code presented here is to show you one way of reading/writing
// software accessible registers implemented in the user logic slave model.
// Each bit of the Bus2IP_WrCE/Bus2IP_RdCE signals is configured to correspond
// to one software accessible register by the top level template. For example,
// if you have four 32 bit software accessible registers in the user logic,
// you are basically operating on the following memory mapped registers:
//
// Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
// "1000" C_BASEADDR + 0x0
// "0100" C_BASEADDR + 0x4
// "0010" C_BASEADDR + 0x8
// "0001" C_BASEADDR + 0xC
//
// ------------------------------------------------------
assign
slv_reg_write_sel = Bus2IP_WrCE[0:15],
slv_reg_read_sel = Bus2IP_RdCE[0:15],
slv_write_ack = Bus2IP_WrCE[0] || Bus2IP_WrCE[1] || Bus2IP_WrCE[2] || Bus2IP_WrCE[3] || Bus2IP_WrCE[4] || Bus2IP_WrCE[5] || Bus2IP_WrCE[6] || Bus2IP_WrCE[7] || Bus2IP_WrCE[8] || Bus2IP_WrCE[9] || Bus2IP_WrCE[10] || Bus2IP_WrCE[11] || Bus2IP_WrCE[12] || Bus2IP_WrCE[13] || Bus2IP_WrCE[14] || Bus2IP_WrCE[15],
slv_read_ack = Bus2IP_RdCE[0] || Bus2IP_RdCE[1] || Bus2IP_RdCE[2] || Bus2IP_RdCE[3] || Bus2IP_RdCE[4] || Bus2IP_RdCE[5] || Bus2IP_RdCE[6] || Bus2IP_RdCE[7] || Bus2IP_RdCE[8] || Bus2IP_RdCE[9] || Bus2IP_RdCE[10] || Bus2IP_RdCE[11] || Bus2IP_RdCE[12] || Bus2IP_RdCE[13] || Bus2IP_RdCE[14] || Bus2IP_RdCE[15];
genvar regIndex;
generate
for (regIndex = 0; regIndex < 16; regIndex = regIndex + 1) begin : REG_LOGIC
// Reg write logic
always @(posedge Bus2IP_Clk) begin
if (Bus2IP_Reset == 1) begin
slv_reg[regIndex] <= 0;
end else if (spiRegWE && regIndex == spiRegAddr) begin
slv_reg[regIndex] <= spiRegWriteData;
end else if (slv_reg_write_sel[regIndex]) begin
for ( byte_index = 0; byte_index <= (C_SLV_DWIDTH/8)-1; byte_index = byte_index + 1 ) begin
if ( Bus2IP_BE[byte_index] == 1) begin
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1) begin
slv_reg[regIndex][bit_index] <= Bus2IP_Data[bit_index];
end
end
end
end
end
end
endgenerate
// implement slave model register read mux
always @( slv_reg_read_sel or slv_reg[0] or slv_reg[1] or slv_reg[2]
or slv_reg[3] or slv_reg[4] or slv_reg[5] or slv_reg[6] or slv_reg[7]
or slv_reg[8] or slv_reg[9] or slv_reg[10] or slv_reg[11] or slv_reg[12]
or slv_reg[13] or slv_reg[14] or slv_reg[15] )
begin: SLAVE_REG_READ_PROC
case ( slv_reg_read_sel )
16'b1000000000000000 : slv_ip2bus_data <= slv_reg[0];
16'b0100000000000000 : slv_ip2bus_data <= slv_reg[1];
16'b0010000000000000 : slv_ip2bus_data <= slv_reg[2];
16'b0001000000000000 : slv_ip2bus_data <= slv_reg[3];
16'b0000100000000000 : slv_ip2bus_data <= slv_reg[4];
16'b0000010000000000 : slv_ip2bus_data <= slv_reg[5];
16'b0000001000000000 : slv_ip2bus_data <= slv_reg[6];
16'b0000000100000000 : slv_ip2bus_data <= slv_reg[7];
16'b0000000010000000 : slv_ip2bus_data <= slv_reg[8];
16'b0000000001000000 : slv_ip2bus_data <= slv_reg[9];
16'b0000000000100000 : slv_ip2bus_data <= slv_reg[10];
16'b0000000000010000 : slv_ip2bus_data <= slv_reg[11];
16'b0000000000001000 : slv_ip2bus_data <= slv_reg[12];
16'b0000000000000100 : slv_ip2bus_data <= slv_reg[13];
16'b0000000000000010 : slv_ip2bus_data <= slv_reg[14];
16'b0000000000000001 : slv_ip2bus_data <= slv_reg[15];
default : slv_ip2bus_data <= 0;
endcase
end // SLAVE_REG_READ_PROC
// implement spi register read mux
always @( spiRegAddr or slv_reg[0] or slv_reg[1] or slv_reg[2]
or slv_reg[3] or slv_reg[4] or slv_reg[5] or slv_reg[6] or slv_reg[7]
or slv_reg[8] or slv_reg[9] or slv_reg[10] or slv_reg[11] or slv_reg[12]
or slv_reg[13] or slv_reg[14] or slv_reg[15] ) begin
spiRegReadData_wreg <= slv_reg[spiRegAddr];
end
// ------------------------------------------------------------
// Example code to drive IP to Bus signals
// ------------------------------------------------------------
assign IP2Bus_AddrAck = slv_write_ack || slv_read_ack || (|mem_read) || (|mem_write);
assign IP2Bus_Data = (mem_read_prev[0] ? mosiMem_doutb : (
mem_read_prev[1] ? misoMem_doutb :
slv_ip2bus_data));
assign IP2Bus_WrAck = slv_write_ack || (|mem_write);
assign IP2Bus_RdAck = slv_read_ack || (|mem_read_prev);
assign IP2Bus_Error = 0;
endmodule
projnav/xps/pcores/spiifc_v1_00_a/hdl/vhdl/spiifc.vhd 0 → 100644
View file @ a64d58e7
------------------------------------------------------------------------------
-- spiifc.vhd - entity/architecture pair
------------------------------------------------------------------------------
-- IMPORTANT:
-- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS.
--
-- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED.
--
-- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW
-- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION
-- OF THE USER_LOGIC ENTITY.
------------------------------------------------------------------------------
--
-- ***************************************************************************
-- ** Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** Xilinx, Inc. **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" **
-- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND **
-- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, **
-- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, **
-- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION **
-- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, **
-- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE **
-- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY **
-- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE **
-- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR **
-- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF **
-- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS **
-- ** FOR A PARTICULAR PURPOSE. **
-- ** **
-- ***************************************************************************
--
------------------------------------------------------------------------------
-- Filename: spiifc.vhd
-- Version: 1.00.a
-- Description: Top level design, instantiates library components and user logic.
-- Date: Tue Feb 28 11:11:15 2012 (by Create and Import Peripheral Wizard)
-- VHDL Standard: VHDL'93
------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports: "- Names begin with Uppercase"
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>"
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
use proc_common_v3_00_a.ipif_pkg.all;
library interrupt_control_v2_01_a;
use interrupt_control_v2_01_a.interrupt_control;
library plbv46_slave_burst_v1_01_a;
use plbv46_slave_burst_v1_01_a.plbv46_slave_burst;
------------------------------------------------------------------------------
-- Entity section
------------------------------------------------------------------------------
-- Definition of Generics:
-- C_BASEADDR -- PLBv46 slave: base address
-- C_HIGHADDR -- PLBv46 slave: high address
-- C_SPLB_AWIDTH -- PLBv46 slave: address bus width
-- C_SPLB_DWIDTH -- PLBv46 slave: data bus width
-- C_SPLB_NUM_MASTERS -- PLBv46 slave: Number of masters
-- C_SPLB_MID_WIDTH -- PLBv46 slave: master ID bus width
-- C_SPLB_NATIVE_DWIDTH -- PLBv46 slave: internal native data bus width
-- C_SPLB_P2P -- PLBv46 slave: point to point interconnect scheme
-- C_SPLB_SUPPORT_BURSTS -- PLBv46 slave: support bursts
-- C_SPLB_SMALLEST_MASTER -- PLBv46 slave: width of the smallest master
-- C_SPLB_CLK_PERIOD_PS -- PLBv46 slave: bus clock in picoseconds
-- C_INCLUDE_DPHASE_TIMER -- PLBv46 slave: Data Phase Timer configuration; 0 = exclude timer, 1 = include timer
-- C_FAMILY -- Xilinx FPGA family
-- C_MEM0_BASEADDR -- User memory space 0 base address
-- C_MEM0_HIGHADDR -- User memory space 0 high address
-- C_MEM1_BASEADDR -- User memory space 1 base address
-- C_MEM1_HIGHADDR -- User memory space 1 high address
--
-- Definition of Ports:
-- SPLB_Clk -- PLB main bus clock
-- SPLB_Rst -- PLB main bus reset
-- PLB_ABus -- PLB address bus
-- PLB_UABus -- PLB upper address bus
-- PLB_PAValid -- PLB primary address valid indicator
-- PLB_SAValid -- PLB secondary address valid indicator
-- PLB_rdPrim -- PLB secondary to primary read request indicator
-- PLB_wrPrim -- PLB secondary to primary write request indicator
-- PLB_masterID -- PLB current master identifier
-- PLB_abort -- PLB abort request indicator
-- PLB_busLock -- PLB bus lock
-- PLB_RNW -- PLB read/not write
-- PLB_BE -- PLB byte enables
-- PLB_MSize -- PLB master data bus size
-- PLB_size -- PLB transfer size
-- PLB_type -- PLB transfer type
-- PLB_lockErr -- PLB lock error indicator
-- PLB_wrDBus -- PLB write data bus
-- PLB_wrBurst -- PLB burst write transfer indicator
-- PLB_rdBurst -- PLB burst read transfer indicator
-- PLB_wrPendReq -- PLB write pending bus request indicator
-- PLB_rdPendReq -- PLB read pending bus request indicator
-- PLB_wrPendPri -- PLB write pending request priority
-- PLB_rdPendPri -- PLB read pending request priority
-- PLB_reqPri -- PLB current request priority
-- PLB_TAttribute -- PLB transfer attribute
-- Sl_addrAck -- Slave address acknowledge
-- Sl_SSize -- Slave data bus size
-- Sl_wait -- Slave wait indicator
-- Sl_rearbitrate -- Slave re-arbitrate bus indicator
-- Sl_wrDAck -- Slave write data acknowledge
-- Sl_wrComp -- Slave write transfer complete indicator
-- Sl_wrBTerm -- Slave terminate write burst transfer
-- Sl_rdDBus -- Slave read data bus
-- Sl_rdWdAddr -- Slave read word address
-- Sl_rdDAck -- Slave read data acknowledge
-- Sl_rdComp -- Slave read transfer complete indicator
-- Sl_rdBTerm -- Slave terminate read burst transfer
-- Sl_MBusy -- Slave busy indicator
-- Sl_MWrErr -- Slave write error indicator
-- Sl_MRdErr -- Slave read error indicator
-- Sl_MIRQ -- Slave interrupt indicator
-- IP2INTC_Irpt -- Interrupt output to processor
------------------------------------------------------------------------------
entity spiifc is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_SPLB_AWIDTH : integer := 32;
C_SPLB_DWIDTH : integer := 128;
C_SPLB_NUM_MASTERS : integer := 8;
C_SPLB_MID_WIDTH : integer := 3;
C_SPLB_NATIVE_DWIDTH : integer := 32;
C_SPLB_P2P : integer := 0;
C_SPLB_SUPPORT_BURSTS : integer := 1;
C_SPLB_SMALLEST_MASTER : integer := 32;
C_SPLB_CLK_PERIOD_PS : integer := 10000;
C_INCLUDE_DPHASE_TIMER : integer := 1;
C_FAMILY : string := "virtex6";
C_MEM0_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_MEM0_HIGHADDR : std_logic_vector := X"00000000";
C_MEM1_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_MEM1_HIGHADDR : std_logic_vector := X"00000000"
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
SPI_CLK : in std_logic;
SPI_MOSI : in std_logic;
SPI_MISO : out std_logic;
SPI_SS : in std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_masterID : in std_logic_vector(0 to C_SPLB_MID_WIDTH-1);
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to C_SPLB_DWIDTH/8-1);
PLB_MSize : in std_logic_vector(0 to 1);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_lockErr : in std_logic;
PLB_wrDBus : in std_logic_vector(0 to C_SPLB_DWIDTH-1);
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_wrBTerm : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to C_SPLB_DWIDTH-1);
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_rdBTerm : out std_logic;
Sl_MBusy : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MWrErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MRdErr : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
Sl_MIRQ : out std_logic_vector(0 to C_SPLB_NUM_MASTERS-1);
IP2INTC_Irpt : out std_logic
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of SPLB_Clk : signal is "CLK";
attribute SIGIS of SPLB_Rst : signal is "RST";
attribute SIGIS of IP2INTC_Irpt : signal is "INTR_LEVEL_HIGH";
end entity spiifc;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of spiifc is
------------------------------------------
-- Array of base/high address pairs for each address range
------------------------------------------
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR or X"00000000";
constant USER_SLV_HIGHADDR : std_logic_vector := C_BASEADDR or X"000000FF";
constant INTR_BASEADDR : std_logic_vector := C_BASEADDR or X"00000100";
constant INTR_HIGHADDR : std_logic_vector := C_BASEADDR or X"000001FF";
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR, -- user logic slave space high address
ZERO_ADDR_PAD & INTR_BASEADDR, -- interrupt control space base address
ZERO_ADDR_PAD & INTR_HIGHADDR, -- interrupt control space high address
ZERO_ADDR_PAD & C_MEM0_BASEADDR, -- user logic memory space 0 base address
ZERO_ADDR_PAD & C_MEM0_HIGHADDR, -- user logic memory space 0 high address
ZERO_ADDR_PAD & C_MEM1_BASEADDR, -- user logic memory space 1 base address
ZERO_ADDR_PAD & C_MEM1_HIGHADDR -- user logic memory space 1 high address
);
------------------------------------------
-- Array of desired number of chip enables for each address range
------------------------------------------
constant USER_SLV_NUM_REG : integer := 16;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant INTR_NUM_CE : integer := 16;
constant USER_NUM_MEM : integer := 2;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => pad_power2(USER_SLV_NUM_REG), -- number of ce for user logic slave space
1 => INTR_NUM_CE, -- number of ce for interrupt control space
2 => 1, -- number of ce for user logic memory space 0 (always 1 chip enable)
3 => 1 -- number of ce for user logic memory space 1 (always 1 chip enable)
);
------------------------------------------
-- Cache line addressing mode (for cacheline read operations)
-- 0 = target word first on reads
-- 1 = line word first on reads
------------------------------------------
constant IPIF_CACHLINE_ADDR_MODE : integer := 0;
------------------------------------------
-- Number of storage locations for the write buffer
-- Valid depths are 0, 16, 32, or 64
-- 0 = no write buffer implemented
------------------------------------------
constant IPIF_WR_BUFFER_DEPTH : integer := 16;
------------------------------------------
-- The type out of the Bus2IP_BurstLength signal
-- 0 = length is in actual byte number
-- 1 = length is in data beats - 1
------------------------------------------
constant IPIF_BURSTLENGTH_TYPE : integer := 0;
------------------------------------------
-- Width of the slave data bus (32, 64, or 128)
------------------------------------------
constant USER_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
constant IPIF_SLV_DWIDTH : integer := C_SPLB_NATIVE_DWIDTH;
------------------------------------------
-- Number of device level interrupts
------------------------------------------
constant INTR_NUM_IPIF_IRPT_SRC : integer := 4;
------------------------------------------
-- Capture mode for each IP interrupt (generated by user logic)
-- 1 = pass through (non-inverting)
-- 2 = pass through (inverting)
-- 3 = registered level (non-inverting)
-- 4 = registered level (inverting)
-- 5 = positive edge detect
-- 6 = negative edge detect
------------------------------------------
constant USER_NUM_INTR : integer := 1;
constant USER_INTR_CAPTURE_MODE : integer := 1;
constant INTR_IP_INTR_MODE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => USER_INTR_CAPTURE_MODE
);
------------------------------------------
-- Device priority encoder feature inclusion/omission
-- true = include priority encoder
-- false = omit priority encoder
------------------------------------------
constant INTR_INCLUDE_DEV_PENCODER : boolean := false;
------------------------------------------
-- Device ISC feature inclusion/omission
-- true = include device ISC
-- false = omit device ISC
------------------------------------------
constant INTR_INCLUDE_DEV_ISC : boolean := false;
------------------------------------------
-- Width of the slave address bus (32 only)
------------------------------------------
constant USER_SLV_AWIDTH : integer := C_SPLB_AWIDTH;
------------------------------------------
-- Index for CS/CE
------------------------------------------
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant INTR_CS_INDEX : integer := 1;
constant INTR_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, INTR_CS_INDEX);
constant USER_MEM0_CS_INDEX : integer := 2;
constant USER_CS_INDEX : integer := USER_MEM0_CS_INDEX;
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
------------------------------------------
-- IP Interconnect (IPIC) signal declarations
------------------------------------------
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Reset : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_AddrAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(0 to C_SPLB_AWIDTH-1);
signal ipif_Bus2IP_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(0 to IPIF_SLV_DWIDTH/8-1);
signal ipif_Bus2IP_Burst : std_logic;
signal ipif_Bus2IP_BurstLength : std_logic_vector(0 to log2(16*(C_SPLB_DWIDTH/8)));
signal ipif_Bus2IP_WrReq : std_logic;
signal ipif_Bus2IP_RdReq : std_logic;
signal ipif_Bus2IP_CS : std_logic_vector(0 to ((IPIF_ARD_ADDR_RANGE_ARRAY'length)/2)-1);
signal ipif_Bus2IP_RdCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal ipif_Bus2IP_WrCE : std_logic_vector(0 to calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1);
signal intr_IPIF_Reg_Interrupts : std_logic_vector(0 to 1);
signal intr_IPIF_Lvl_Interrupts : std_logic_vector(0 to INTR_NUM_IPIF_IRPT_SRC-1);
signal intr_IP2Bus_Data : std_logic_vector(0 to IPIF_SLV_DWIDTH-1);
signal intr_IP2Bus_WrAck : std_logic;
signal intr_IP2Bus_RdAck : std_logic;
signal intr_IP2Bus_Error : std_logic;
signal user_Bus2IP_RdCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_Bus2IP_WrCE : std_logic_vector(0 to USER_NUM_REG-1);
signal user_Bus2IP_BurstLength : std_logic_vector(0 to 8) := (others => '0');
signal user_IP2Bus_AddrAck : std_logic;
signal user_IP2Bus_Data : std_logic_vector(0 to USER_SLV_DWIDTH-1);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
signal user_IP2Bus_IntrEvent : std_logic_vector(0 to USER_NUM_INTR-1);
------------------------------------------
-- Component declaration for verilog user logic
------------------------------------------
component user_logic is
generic
(
-- ADD USER GENERICS BELOW THIS LINE ---------------
--USER generics added here
-- ADD USER GENERICS ABOVE THIS LINE ---------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol parameters, do not add to or delete
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32;
C_NUM_REG : integer := 16;
C_NUM_MEM : integer := 2;
C_NUM_INTR : integer := 1
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
SPI_CLK : in std_logic;
SPI_MOSI : in std_logic;
SPI_MISO : out std_logic;
SPI_SS : in std_logic;
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
Bus2IP_Clk : in std_logic;
Bus2IP_Reset : in std_logic;
Bus2IP_Addr : in std_logic_vector(0 to C_SLV_AWIDTH-1);
Bus2IP_CS : in std_logic_vector(0 to C_NUM_MEM-1);
Bus2IP_RNW : in std_logic;
Bus2IP_Data : in std_logic_vector(0 to C_SLV_DWIDTH-1);
Bus2IP_BE : in std_logic_vector(0 to C_SLV_DWIDTH/8-1);
Bus2IP_RdCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_WrCE : in std_logic_vector(0 to C_NUM_REG-1);
Bus2IP_Burst : in std_logic;
Bus2IP_BurstLength : in std_logic_vector(0 to 8);
Bus2IP_RdReq : in std_logic;
Bus2IP_WrReq : in std_logic;
IP2Bus_AddrAck : out std_logic;
IP2Bus_Data : out std_logic_vector(0 to C_SLV_DWIDTH-1);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic;
IP2Bus_IntrEvent : out std_logic_vector(0 to C_NUM_INTR-1)
-- DO NOT EDIT ABOVE THIS LINE ---------------------
);
end component user_logic;
begin
------------------------------------------
-- instantiate plbv46_slave_burst
------------------------------------------
PLBV46_SLAVE_BURST_I : entity plbv46_slave_burst_v1_01_a.plbv46_slave_burst
generic map
(
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_SPLB_P2P => C_SPLB_P2P,
C_CACHLINE_ADDR_MODE => IPIF_CACHLINE_ADDR_MODE,
C_WR_BUFFER_DEPTH => IPIF_WR_BUFFER_DEPTH,
C_BURSTLENGTH_TYPE => IPIF_BURSTLENGTH_TYPE,
C_SPLB_MID_WIDTH => C_SPLB_MID_WIDTH,
C_SPLB_NUM_MASTERS => C_SPLB_NUM_MASTERS,
C_SPLB_SMALLEST_MASTER => C_SPLB_SMALLEST_MASTER,
C_SPLB_AWIDTH => C_SPLB_AWIDTH,
C_SPLB_DWIDTH => C_SPLB_DWIDTH,
C_SIPIF_DWIDTH => IPIF_SLV_DWIDTH,
C_INCLUDE_DPHASE_TIMER => C_INCLUDE_DPHASE_TIMER,
C_FAMILY => C_FAMILY
)
port map
(
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_UABus => PLB_UABus,
PLB_PAValid => PLB_PAValid,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_masterID => PLB_masterID,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_MSize => PLB_MSize,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_lockErr => PLB_lockErr,
PLB_wrDBus => PLB_wrDBus,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdDBus => Sl_rdDBus,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
Sl_MIRQ => Sl_MIRQ,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
IP2Bus_Data => ipif_IP2Bus_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_AddrAck => ipif_IP2Bus_AddrAck,
IP2Bus_Error => ipif_IP2Bus_Error,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_Burst => ipif_Bus2IP_Burst,
Bus2IP_BurstLength => ipif_Bus2IP_BurstLength,
Bus2IP_WrReq => ipif_Bus2IP_WrReq,
Bus2IP_RdReq => ipif_Bus2IP_RdReq,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE
);
------------------------------------------
-- instantiate interrupt_control
------------------------------------------
INTERRUPT_CONTROL_I : entity interrupt_control_v2_01_a.interrupt_control
generic map
(
C_NUM_CE => INTR_NUM_CE,
C_NUM_IPIF_IRPT_SRC => INTR_NUM_IPIF_IRPT_SRC,
C_IP_INTR_MODE_ARRAY => INTR_IP_INTR_MODE_ARRAY,
C_INCLUDE_DEV_PENCODER => INTR_INCLUDE_DEV_PENCODER,
C_INCLUDE_DEV_ISC => INTR_INCLUDE_DEV_ISC,
C_IPIF_DWIDTH => IPIF_SLV_DWIDTH
)
port map
(
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Interrupt_RdCE => ipif_Bus2IP_RdCE(INTR_CE_INDEX to INTR_CE_INDEX+INTR_NUM_CE-1),
Interrupt_WrCE => ipif_Bus2IP_WrCE(INTR_CE_INDEX to INTR_CE_INDEX+INTR_NUM_CE-1),
IPIF_Reg_Interrupts => intr_IPIF_Reg_Interrupts,
IPIF_Lvl_Interrupts => intr_IPIF_Lvl_Interrupts,
IP2Bus_IntrEvent => user_IP2Bus_IntrEvent,
Intr2Bus_DevIntr => IP2INTC_Irpt,
Intr2Bus_DBus => intr_IP2Bus_Data,
Intr2Bus_WrAck => intr_IP2Bus_WrAck,
Intr2Bus_RdAck => intr_IP2Bus_RdAck,
Intr2Bus_Error => intr_IP2Bus_Error,
Intr2Bus_Retry => open,
Intr2Bus_ToutSup => open
);
-- feed registered and level-pass-through interrupts into Device ISC if exists, otherwise ignored
intr_IPIF_Reg_Interrupts(0) <= '0';
intr_IPIF_Reg_Interrupts(1) <= '0';
intr_IPIF_Lvl_Interrupts(0) <= '0';
intr_IPIF_Lvl_Interrupts(1) <= '0';
intr_IPIF_Lvl_Interrupts(2) <= '0';
intr_IPIF_Lvl_Interrupts(3) <= '0';
------------------------------------------
-- instantiate User Logic
------------------------------------------
USER_LOGIC_I : component user_logic
generic map
(
-- MAP USER GENERICS BELOW THIS LINE ---------------
--USER generics mapped here
-- MAP USER GENERICS ABOVE THIS LINE ---------------
C_SLV_AWIDTH => USER_SLV_AWIDTH,
C_SLV_DWIDTH => USER_SLV_DWIDTH,
C_NUM_REG => USER_NUM_REG,
C_NUM_MEM => USER_NUM_MEM,
C_NUM_INTR => USER_NUM_INTR
)
port map
(
-- MAP USER PORTS BELOW THIS LINE ------------------
SPI_CLK => SPI_CLK,
SPI_MOSI => SPI_MOSI,
SPI_MISO => SPI_MISO,
SPI_SS => SPI_SS,
-- MAP USER PORTS ABOVE THIS LINE ------------------
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Reset => ipif_Bus2IP_Reset,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_CS => ipif_Bus2IP_CS(USER_CS_INDEX to USER_CS_INDEX+USER_NUM_MEM-1),
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
Bus2IP_Burst => ipif_Bus2IP_Burst,
Bus2IP_BurstLength => user_Bus2IP_BurstLength,
Bus2IP_RdReq => ipif_Bus2IP_RdReq,
Bus2IP_WrReq => ipif_Bus2IP_WrReq,
IP2Bus_AddrAck => user_IP2Bus_AddrAck,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error,
IP2Bus_IntrEvent => user_IP2Bus_IntrEvent
);
------------------------------------------
-- connect internal signals
------------------------------------------
IP2BUS_DATA_MUX_PROC : process( ipif_Bus2IP_CS, user_IP2Bus_Data, intr_IP2Bus_Data ) is
begin
case ipif_Bus2IP_CS is
when "1000" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
when "0100" => ipif_IP2Bus_Data <= intr_IP2Bus_Data;
when "0010" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
when "0001" => ipif_IP2Bus_Data <= user_IP2Bus_Data;
when others => ipif_IP2Bus_Data <= (others => '0');
end case;
end process IP2BUS_DATA_MUX_PROC;
ipif_IP2Bus_AddrAck <= ipif_Bus2IP_Burst and user_IP2Bus_AddrAck;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck or intr_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck or intr_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error or intr_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_CE_INDEX to USER_CE_INDEX+USER_NUM_REG-1);
user_Bus2IP_BurstLength(8-log2(16*(C_SPLB_DWIDTH/8)) to 8) <= ipif_Bus2IP_BurstLength;
end IMP;
projnav/xps/pcores/spiifc_v1_00_a/netlist/buffermem.ngc 0 → 100644
View file @ a64d58e7
XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6e
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\ No newline at end of file
projnav/xps/pcores/spiifc_v1_00_a/netlist/spiifc.ngc 0 → 100644
View file @ a64d58e7
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projnav/xps/platgen.opt 0 → 100644
View file @ a64d58e7
-p
xc6slx45csg324-2
-lang
vhdl
-msg
__xps/ise/xmsgprops.lst
system.mhs
projnav/xps/system.bsb 0 → 100644
View file @ a64d58e7
ﾄｮﾒtｦﾊ隰ﾊ蓙ﾒﾞﾜ@Dbb\b\`bDv(ﾄｮﾒtｦﾊ閼ﾞﾂ菠@D惟ﾎﾒﾘﾊﾜ錺@DりﾘD@Dv.ﾄｮﾒtｪ猜ﾂ靆ﾂ菠@Dう暢恰ｨｪ､灰@D赳ﾂ蒻ﾂﾜlDv-ﾄｮﾒtｪ猜ﾂ靆ﾂ菠@Dｬ中汗ｦ超灰@Dl齎jDv'ﾄｮﾒtｪ猜ﾂ靆ﾂ菠@Dｆ魔至D@Dﾆ賽fdhDv'ﾄｮﾒtｪ猜ﾂ靆ﾂ菠@D､ｦｨｾ椈う暢ｲD@D`Dv&ﾄｮﾒtｪ猜ﾂ靆ﾂ菠@Dｦ滑､ｈ灰@DZdDv)ﾄｮﾒtｦﾊ隕靆ﾚ@Dﾚﾄｾ獵ﾄｾﾚ獺ﾆD@Db\``\ﾂDv;ﾄｮﾒtｪ猜ﾂ靆ｦ靆ﾚ@D━ｦｾ研瓦D@Dll\llllllD@Dﾚﾒﾆ葯ﾄﾘﾂｾ`Dv<ﾄｮﾒtｪ猜ﾂ靆ｦ靆ﾚ@D明研瓦D@Db``\``````D@Dﾚﾒﾆ葯ﾄﾘﾂｾ`Dv<ﾄｮﾒtｪ猜ﾂ靆ｦ靆ﾚ@D､梟ｾ研瓦D@Dll\llllllD@Dﾚﾒﾆ葯ﾄﾘﾂｾ`Dvﾄｮﾒtｦﾊ陞琲ｦ靜DDv@ﾄｮﾒtなﾈ葯ﾆﾊ跏ﾞ隋Dﾚﾒﾆ葯ﾄﾘﾂｾ`D@D囃桷ｴ灰@Dﾚﾒﾆ葯ﾄﾘﾂｾ`Dv:ﾄｮﾒtｪ猜ﾂ靆ﾚ玻ﾜﾊﾜ錙Dﾚﾒﾆ葯ﾄﾘﾂｾ`D@D灰@D悚@灰v9ﾄｮﾒtｪ猜ﾂ靆ﾚ玻ﾜﾊﾜ錙Dﾚﾒﾆ葯ﾄﾘﾂｾ`D@D明凋ｦｨD@DﾎﾆﾘﾖDvLﾄｮﾒtｪ猜ﾂ靆ﾚ玻ﾜﾊﾜ錙Dﾚﾒﾆ葯ﾄﾘﾂｾ`D@D━疾柱D@D權Zﾒ漾整@位ﾄ@壜ﾈﾊDv>ﾄｮﾒtｪ猜ﾂ靆ﾚ玻ﾜﾊﾜ錙Dﾚﾒﾆ葯ﾄﾘﾂｾ`D@Dт､ｚ@ｦ超灰@DljjflDv4ﾄｮﾒtｪ猜ﾂ靆ﾚ玻ﾜﾊﾜ錙Dﾚﾒﾆ葯ﾄﾘﾂｾ`D@D噪@権ｪD@D`DvEﾄｮﾒtなﾈﾊ萪獎ﾊ萃ﾘ@Dｾｦ霹ﾐﾊ貔p韆D@D貔ﾎ默ﾞD@Dﾚﾒﾆ葯ﾄﾘﾂｾ`DvGﾄｮﾒtｪ猜ﾂ靆ﾚ玻ﾜﾊﾜ錙Dｾｦ霹ﾐﾊ貔p韆D@D疾ｪｦ汗凋ｨ侃､ｪｨD@D撃丿灰v=ﾄｮﾒtなﾈﾊ萪獎ﾊ萃ﾘ@D域ｾp韆D@D貔ﾎ默ﾞD@Dﾚﾒﾆ葯ﾄﾘﾂｾ`Dv?ﾄｮﾒtｪ猜ﾂ靆ﾚ玻ﾜﾊﾜ錙D域ｾp韆D@D疾ｪｦ汗凋ｨ侃､ｪｨD@D撃丿灰vEﾄｮﾒtなﾈﾊ萪獎ﾊ萃ﾘ@Dﾐｾ韋ﾞﾜ貔j韆D@D貔ﾎ默ﾞD@Dﾚﾒﾆ葯ﾄﾘﾂｾ`DvGﾄｮﾒtｪ猜ﾂ靆ﾚ玻ﾜﾊﾜ錙Dﾐｾ韋ﾞﾜ貔j韆D@D疾ｪｦ汗凋ｨ侃､ｪｨD@D撃丿灰vFﾄｮﾒtなﾈﾊ萪獎ﾊ萃ﾘ@Dﾈﾘﾚﾄｾﾆﾜ靼腑@Dﾘﾚﾄｾﾄ萃ﾚｾﾒﾌｾﾆﾜ靼腑@Dﾚﾒﾆ葯ﾄﾘﾂｾ`DvFﾄｮﾒtなﾈﾊ萪獎ﾊ萃ﾘ@Dﾒﾘﾚﾄｾﾆﾜ靼腑@Dﾘﾚﾄｾﾄ萃ﾚｾﾒﾌｾﾆﾜ靼腑@Dﾚﾒﾆ葯ﾄﾘﾂｾ`Dv
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projnav/xps/system.make 0 → 100644
View file @ a64d58e7
#################################################################
# Makefile generated by Xilinx Platform Studio
# Project:C:\Users\mjlyons\workspace\vSPI\projnav\xps\system.xmp
#
# WARNING : This file will be re-generated every time a command
# to run a make target is invoked. So, any changes made to this
# file manually, will be lost when make is invoked next.
#################################################################
# Name of the Microprocessor system
# The hardware specification of the system is in file :
# C:\Users\mjlyons\workspace\vSPI\projnav\xps\system.mhs
include system_incl.make
#################################################################
# PHONY TARGETS
#################################################################
.PHONY: dummy
.PHONY: netlistclean
.PHONY: bitsclean
.PHONY: simclean
.PHONY: exporttosdk
#################################################################
# EXTERNAL TARGETS
#################################################################
all:
@echo "Makefile to build a Microprocessor system :"
@echo "Run make with any of the following targets"
@echo " "
@echo " netlist : Generates the netlist for the given MHS "
@echo " bits : Runs Implementation tools to generate the bitstream"
@echo " exporttosdk: Export files to SDK"
@echo " "
@echo " init_bram: Initializes bitstream with BRAM data"
@echo " ace : Generate ace file from bitstream and elf"
@echo " download : Downloads the bitstream onto the board"
@echo " "
@echo " sim : Generates HDL simulation models and runs simulator for chosen simulation mode"
@echo " simmodel : Generates HDL simulation models for chosen simulation mode"
@echo " "
@echo " netlistclean: Deletes netlist"
@echo " bitsclean: Deletes bit, ncd, bmm files"
@echo " hwclean : Deletes implementation dir"
@echo " simclean : Deletes simulation dir"
@echo " clean : Deletes all generated files/directories"
@echo " "
bits: $(SYSTEM_BIT)
ace: $(SYSTEM_ACE)
exporttosdk: $(SYSTEM_HW_HANDOFF_DEP)
netlist: $(POSTSYN_NETLIST)
download: $(DOWNLOAD_BIT) dummy
@echo "*********************************************"
@echo "Downloading Bitstream onto the target board"
@echo "*********************************************"
impact -batch etc/download.cmd
init_bram: $(DOWNLOAD_BIT)
sim: $(DEFAULT_SIM_SCRIPT)
cd simulation/behavioral & \
system_fuse.cmd
cd simulation/behavioral & \
start /B $(SIM_CMD) -gui -tclbatch system_setup.tcl
simmodel: $(DEFAULT_SIM_SCRIPT)
behavioral_model: $(BEHAVIORAL_SIM_SCRIPT)
structural_model: $(STRUCTURAL_SIM_SCRIPT)
clean: hwclean simclean
rm -f _impact.cmd
hwclean: netlistclean bitsclean
rm -rf implementation synthesis xst hdl
rm -rf xst.srp $(SYSTEM).srp
rm -f __xps/ise/_xmsgs/bitinit.xmsgs
netlistclean:
rm -f $(POSTSYN_NETLIST)
rm -f platgen.log
rm -f __xps/ise/_xmsgs/platgen.xmsgs
rm -f $(BMM_FILE)
bitsclean:
rm -f $(SYSTEM_BIT)
rm -f implementation/$(SYSTEM).ncd
rm -f implementation/$(SYSTEM)_bd.bmm
rm -f implementation/$(SYSTEM)_map.ncd
rm -f implementation/download.bit
rm -f __xps/$(SYSTEM)_routed
simclean:
rm -rf simulation/behavioral
rm -f simgen.log
rm -f __xps/ise/_xmsgs/simgen.xmsgs
#################################################################
# BOOTLOOP ELF FILES
#################################################################
$(MICROBLAZE_0_BOOTLOOP): $(MICROBLAZE_BOOTLOOP)
IF NOT EXIST "$(BOOTLOOP_DIR)" @mkdir "$(BOOTLOOP_DIR)"
cp -f $(MICROBLAZE_BOOTLOOP) $(MICROBLAZE_0_BOOTLOOP)
#################################################################
# HARDWARE IMPLEMENTATION FLOW
#################################################################
$(BMM_FILE) \
$(WRAPPER_NGC_FILES): $(MHSFILE) __xps/platgen.opt \
$(CORE_STATE_DEVELOPMENT_FILES)
@echo "****************************************************"
@echo "Creating system netlist for hardware specification.."
@echo "****************************************************"
platgen $(PLATGEN_OPTIONS) $(MHSFILE)
$(POSTSYN_NETLIST): $(WRAPPER_NGC_FILES)
@echo "Running synthesis..."
cd synthesis & synthesis.cmd
__xps/$(SYSTEM)_routed: $(FPGA_IMP_DEPENDENCY)
@echo "*********************************************"
@echo "Running Xilinx Implementation tools.."
@echo "*********************************************"
@cp -f $(UCF_FILE) implementation/$(SYSTEM).ucf
@cp -f etc/fast_runtime.opt implementation/xflow.opt
xflow -wd implementation -p $(DEVICE) -implement xflow.opt $(SYSTEM).ngc
touch __xps/$(SYSTEM)_routed
$(SYSTEM_BIT): __xps/$(SYSTEM)_routed $(BITGEN_UT_FILE)
xilperl $(XILINX_EDK_DIR)/data/fpga_impl/observe_par.pl $(OBSERVE_PAR_OPTIONS) implementation/$(SYSTEM).par
@echo "*********************************************"
@echo "Running Bitgen.."
@echo "*********************************************"
@cp -f $(BITGEN_UT_FILE) implementation/bitgen.ut
cd implementation & bitgen -w -f bitgen.ut $(SYSTEM) & cd ..
$(DOWNLOAD_BIT): $(SYSTEM_BIT) $(BRAMINIT_ELF_IMP_FILES) __xps/bitinit.opt
@cp -f implementation/$(SYSTEM)_bd.bmm .
@echo "*********************************************"
@echo "Initializing BRAM contents of the bitstream"
@echo "*********************************************"
bitinit -p $(DEVICE) $(MHSFILE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_IMP_FILE_ARGS) \
-bt $(SYSTEM_BIT) -o $(DOWNLOAD_BIT)
@rm -f $(SYSTEM)_bd.bmm
$(SYSTEM_ACE):
@echo "In order to generate ace file, you must have:-"
@echo "- exactly one processor."
@echo "- opb_mdm, if using microblaze."
#################################################################
# EXPORT_TO_SDK FLOW
#################################################################
$(SYSTEM_HW_HANDOFF): $(MHSFILE) __xps/platgen.opt
IF NOT EXIST "$(SDK_EXPORT_DIR)" @mkdir "$(SDK_EXPORT_DIR)"
psf2Edward -inp $(SYSTEM).xmp -exit_on_error -edwver 1.2 -xml $(SDK_EXPORT_DIR)/$(SYSTEM).xml $(GLOBAL_SEARCHPATHOPT)
$(SYSTEM_HW_HANDOFF_BIT): $(SYSTEM_BIT)
@rm -rf $(SYSTEM_HW_HANDOFF_BIT)
@cp -f $(SYSTEM_BIT) $(SDK_EXPORT_DIR)
$(SYSTEM_HW_HANDOFF_BMM): implementation/$(SYSTEM)_bd.bmm
@rm -rf $(SYSTEM_HW_HANDOFF_BMM)
@cp -f implementation/$(SYSTEM)_bd.bmm $(SDK_EXPORT_DIR)
#################################################################
# SIMULATION FLOW
#################################################################
################## BEHAVIORAL SIMULATION ##################
$(BEHAVIORAL_SIM_SCRIPT): $(MHSFILE) __xps/simgen.opt \
$(BRAMINIT_ELF_SIM_FILES)
@echo "*********************************************"
@echo "Creating behavioral simulation models..."
@echo "*********************************************"
simgen $(SIMGEN_OPTIONS) -m behavioral $(MHSFILE)
################## STRUCTURAL SIMULATION ##################
$(STRUCTURAL_SIM_SCRIPT): $(WRAPPER_NGC_FILES) __xps/simgen.opt \
$(BRAMINIT_ELF_SIM_FILES)
@echo "*********************************************"
@echo "Creating structural simulation models..."
@echo "*********************************************"
simgen $(SIMGEN_OPTIONS) -sd implementation -m structural $(MHSFILE)
################## TIMING SIMULATION ##################
implementation/$(SYSTEM).ncd: __xps/$(SYSTEM)_routed
$(TIMING_SIM_SCRIPT): implementation/$(SYSTEM).ncd __xps/simgen.opt \
$(BRAMINIT_ELF_SIM_FILES)
@echo "*********************************************"
@echo "Creating timing simulation models..."
@echo "*********************************************"
simgen $(SIMGEN_OPTIONS) -sd implementation -m timing $(MHSFILE)
dummy:
@echo ""
projnav/xps/system.mhs 0 → 100644
View file @ a64d58e7
# ##############################################################################
# Created by Base System Builder Wizard for Xilinx EDK 13.2 Build EDK_O.61xd
# Tue Feb 28 10:59:35 2012
# Target Board: Digilent Atlys Rev C
# Family: spartan6
# Device: xc6slx45
# Package: csg324
# Speed Grade: -2
# Processor number: 1
# Processor 1: microblaze_0
# System clock frequency: 66.7
# Debug Interface: On-Chip HW Debug Module
# ##############################################################################
PARAMETER VERSION = 2.1.0
PORT fpga_0_DIP_Switches_8Bits_GPIO_IO_I_pin = fpga_0_DIP_Switches_8Bits_GPIO_IO_I_pin, DIR = I, VEC = [0:7]
PORT fpga_0_LEDs_8Bits_GPIO_IO_O_pin = fpga_0_LEDs_8Bits_GPIO_IO_O_pin, DIR = O, VEC = [0:7]
PORT fpga_0_Push_Buttons_5Bits_GPIO_IO_I_pin = fpga_0_Push_Buttons_5Bits_GPIO_IO_I_pin, DIR = I, VEC = [0:4]
PORT fpga_0_clk_1_sys_clk_pin = CLK_S, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
PORT fpga_0_rst_1_sys_rst_pin = sys_rst_s, DIR = I, SIGIS = RST, RST_POLARITY = 0
PORT spiifc_0_SPI_CLK_pin = spiifc_0_SPI_CLK, DIR = I, SIGIS = CLK, CLK_FREQ = 50000000
PORT spiifc_0_SPI_MISO_pin = spiifc_0_SPI_MISO, DIR = O
PORT spiifc_0_SPI_MOSI_pin = spiifc_0_SPI_MOSI, DIR = I
PORT spiifc_0_SPI_SS_pin = spiifc_0_SPI_SS, DIR = I
BEGIN microblaze
PARAMETER INSTANCE = microblaze_0
PARAMETER C_USE_BARREL = 1
PARAMETER C_DEBUG_ENABLED = 1
PARAMETER HW_VER = 8.20.a
BUS_INTERFACE DLMB = dlmb
BUS_INTERFACE ILMB = ilmb
BUS_INTERFACE DPLB = mb_plb
BUS_INTERFACE IPLB = mb_plb
BUS_INTERFACE DEBUG = microblaze_0_mdm_bus
PORT MB_RESET = mb_reset
END
BEGIN plb_v46
PARAMETER INSTANCE = mb_plb
PARAMETER HW_VER = 1.05.a
PORT PLB_Clk = clk_66_6667MHz
PORT SYS_Rst = sys_bus_reset
END
BEGIN lmb_v10
PARAMETER INSTANCE = ilmb
PARAMETER HW_VER = 2.00.b
PORT LMB_Clk = clk_66_6667MHz
PORT SYS_Rst = sys_bus_reset
END
BEGIN lmb_v10
PARAMETER INSTANCE = dlmb
PARAMETER HW_VER = 2.00.b
PORT LMB_Clk = clk_66_6667MHz
PORT SYS_Rst = sys_bus_reset
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = dlmb_cntlr
PARAMETER HW_VER = 3.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x0000ffff
BUS_INTERFACE SLMB = dlmb
BUS_INTERFACE BRAM_PORT = dlmb_port
END
BEGIN lmb_bram_if_cntlr
PARAMETER INSTANCE = ilmb_cntlr
PARAMETER HW_VER = 3.00.b
PARAMETER C_BASEADDR = 0x00000000
PARAMETER C_HIGHADDR = 0x0000ffff
BUS_INTERFACE SLMB = ilmb
BUS_INTERFACE BRAM_PORT = ilmb_port
END
BEGIN bram_block
PARAMETER INSTANCE = lmb_bram
PARAMETER HW_VER = 1.00.a
BUS_INTERFACE PORTA = ilmb_port
BUS_INTERFACE PORTB = dlmb_port
END
BEGIN xps_gpio
PARAMETER INSTANCE = DIP_Switches_8Bits
PARAMETER C_ALL_INPUTS = 1
PARAMETER C_GPIO_WIDTH = 8
PARAMETER C_INTERRUPT_PRESENT = 0
PARAMETER C_IS_DUAL = 0
PARAMETER HW_VER = 2.00.a
PARAMETER C_BASEADDR = 0x81440000
PARAMETER C_HIGHADDR = 0x8144ffff
BUS_INTERFACE SPLB = mb_plb
PORT GPIO_IO_I = fpga_0_DIP_Switches_8Bits_GPIO_IO_I_pin
END
BEGIN xps_gpio
PARAMETER INSTANCE = LEDs_8Bits
PARAMETER C_ALL_INPUTS = 0
PARAMETER C_GPIO_WIDTH = 8
PARAMETER C_INTERRUPT_PRESENT = 0
PARAMETER C_IS_DUAL = 0
PARAMETER HW_VER = 2.00.a
PARAMETER C_BASEADDR = 0x81420000
PARAMETER C_HIGHADDR = 0x8142ffff
BUS_INTERFACE SPLB = mb_plb
PORT GPIO_IO_O = fpga_0_LEDs_8Bits_GPIO_IO_O_pin
END
BEGIN xps_gpio
PARAMETER INSTANCE = Push_Buttons_5Bits
PARAMETER C_ALL_INPUTS = 1
PARAMETER C_GPIO_WIDTH = 5
PARAMETER C_INTERRUPT_PRESENT = 0
PARAMETER C_IS_DUAL = 0
PARAMETER HW_VER = 2.00.a
PARAMETER C_BASEADDR = 0x81400000
PARAMETER C_HIGHADDR = 0x8140ffff
BUS_INTERFACE SPLB = mb_plb
PORT GPIO_IO_I = fpga_0_Push_Buttons_5Bits_GPIO_IO_I_pin
END
BEGIN clock_generator
PARAMETER INSTANCE = clock_generator_0
PARAMETER C_CLKIN_FREQ = 100000000
PARAMETER C_CLKOUT0_FREQ = 66666666
PARAMETER C_CLKOUT0_PHASE = 0
PARAMETER C_CLKOUT0_GROUP = NONE
PARAMETER C_CLKOUT0_BUF = TRUE
PARAMETER C_EXT_RESET_HIGH = 0
PARAMETER HW_VER = 4.02.a
PORT CLKIN = CLK_S
PORT CLKOUT0 = clk_66_6667MHz
PORT RST = sys_rst_s
PORT LOCKED = Dcm_all_locked
END
BEGIN mdm
PARAMETER INSTANCE = mdm_0
PARAMETER C_MB_DBG_PORTS = 1
PARAMETER C_USE_UART = 1
PARAMETER HW_VER = 2.00.b
PARAMETER C_BASEADDR = 0x84400000
PARAMETER C_HIGHADDR = 0x8440ffff
BUS_INTERFACE SPLB = mb_plb
BUS_INTERFACE MBDEBUG_0 = microblaze_0_mdm_bus
PORT Debug_SYS_Rst = Debug_SYS_Rst
END
BEGIN proc_sys_reset
PARAMETER INSTANCE = proc_sys_reset_0
PARAMETER C_EXT_RESET_HIGH = 0
PARAMETER HW_VER = 3.00.a
PORT Slowest_sync_clk = clk_66_6667MHz
PORT Ext_Reset_In = sys_rst_s
PORT MB_Debug_Sys_Rst = Debug_SYS_Rst
PORT Dcm_locked = Dcm_all_locked
PORT MB_Reset = mb_reset
PORT Bus_Struct_Reset = sys_bus_reset
PORT Peripheral_Reset = sys_periph_reset
END
BEGIN spiifc
PARAMETER INSTANCE = spiifc_0
PARAMETER HW_VER = 1.00.a
PARAMETER C_BASEADDR = 0x85000000
PARAMETER C_HIGHADDR = 0x8500FFFF
PARAMETER C_MEM0_BASEADDR = 0x85010000
PARAMETER C_MEM0_HIGHADDR = 0x85010FFF
PARAMETER C_MEM1_BASEADDR = 0x85011000
PARAMETER C_MEM1_HIGHADDR = 0x85011FFF
BUS_INTERFACE SPLB = mb_plb
PORT SPI_CLK = spiifc_0_SPI_CLK
PORT SPI_MOSI = spiifc_0_SPI_MOSI
PORT SPI_MISO = spiifc_0_SPI_MISO
PORT SPI_SS = spiifc_0_SPI_SS
END
BEGIN xps_central_dma
PARAMETER INSTANCE = xps_central_dma_0
PARAMETER HW_VER = 2.03.a
PARAMETER C_BASEADDR = 0x86000000
PARAMETER C_HIGHADDR = 0x8600FFFF
BUS_INTERFACE MPLB = mb_plb
BUS_INTERFACE SPLB = mb_plb
END
projnav/xps/system.xmp 0 → 100644
View file @ a64d58e7
#Please do not modify this file by hand
XmpVersion: 13.2
VerMgmt: 13.2
IntStyle: default
Flow: ise
MHS File: system.mhs
Architecture: spartan6
Device: xc6slx45
Package: csg324
SpeedGrade: -2
UserCmd1:
UserCmd1Type: 0
UserCmd2:
UserCmd2Type: 0
GenSimTB: 0
SdkExportBmmBit: 1
SdkExportDir: SDK/SDK_Export
InsertNoPads: 0
WarnForEAArch: 1
HdlLang: VHDL
SimModel: BEHAVIORAL
ExternalMemSim: 0
UcfFile: data/system.ucf
EnableParTimingError: 1
ShowLicenseDialog: 1
Processor: microblaze_0
ElfImp:
ElfSim:
projnav/xps/system_incl.make 0 → 100644
View file @ a64d58e7
#################################################################
# Makefile generated by Xilinx Platform Studio
# Project:C:\Users\mjlyons\workspace\vSPI\projnav\xps\system.xmp
#
# WARNING : This file will be re-generated every time a command
# to run a make target is invoked. So, any changes made to this
# file manually, will be lost when make is invoked next.
#################################################################
SHELL = CMD
XILINX_EDK_DIR = C:/Xilinx/13.2/ISE_DS/EDK
SYSTEM = system
MHSFILE = system.mhs
FPGA_ARCH = spartan6
DEVICE = xc6slx45csg324-2
LANGUAGE = vhdl
GLOBAL_SEARCHPATHOPT =
PROJECT_SEARCHPATHOPT =
SEARCHPATHOPT = $(PROJECT_SEARCHPATHOPT) $(GLOBAL_SEARCHPATHOPT)
SUBMODULE_OPT =
PLATGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(SUBMODULE_OPT) -msg __xps/ise/xmsgprops.lst
OBSERVE_PAR_OPTIONS = -error yes
MICROBLAZE_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/microblaze/mb_bootloop.elf
MICROBLAZE_BOOTLOOP_LE = $(XILINX_EDK_DIR)/sw/lib/microblaze/mb_bootloop_le.elf
PPC405_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/ppc405/ppc_bootloop.elf
PPC440_BOOTLOOP = $(XILINX_EDK_DIR)/sw/lib/ppc440/ppc440_bootloop.elf
BOOTLOOP_DIR = bootloops
MICROBLAZE_0_BOOTLOOP = $(BOOTLOOP_DIR)/microblaze_0.elf
BRAMINIT_ELF_IMP_FILES = $(MICROBLAZE_0_BOOTLOOP)
BRAMINIT_ELF_IMP_FILE_ARGS = -pe microblaze_0 $(MICROBLAZE_0_BOOTLOOP)
BRAMINIT_ELF_SIM_FILES = $(MICROBLAZE_0_BOOTLOOP)
BRAMINIT_ELF_SIM_FILE_ARGS = -pe microblaze_0 $(MICROBLAZE_0_BOOTLOOP)
SIM_CMD = isim_system
BEHAVIORAL_SIM_SCRIPT = simulation/behavioral/$(SYSTEM)_setup.tcl
STRUCTURAL_SIM_SCRIPT = simulation/structural/$(SYSTEM)_setup.tcl
TIMING_SIM_SCRIPT = simulation/timing/$(SYSTEM)_setup.tcl
DEFAULT_SIM_SCRIPT = $(BEHAVIORAL_SIM_SCRIPT)
SIMGEN_OPTIONS = -p $(DEVICE) -lang $(LANGUAGE) $(SEARCHPATHOPT) $(BRAMINIT_ELF_SIM_FILE_ARGS) -msg __xps/ise/xmsgprops.lst -s isim
CORE_STATE_DEVELOPMENT_FILES =
WRAPPER_NGC_FILES = implementation/microblaze_0_wrapper.ngc \
implementation/mb_plb_wrapper.ngc \
implementation/ilmb_wrapper.ngc \
implementation/dlmb_wrapper.ngc \
implementation/dlmb_cntlr_wrapper.ngc \
implementation/ilmb_cntlr_wrapper.ngc \
implementation/lmb_bram_wrapper.ngc \
implementation/dip_switches_8bits_wrapper.ngc \
implementation/leds_8bits_wrapper.ngc \
implementation/push_buttons_5bits_wrapper.ngc \
implementation/clock_generator_0_wrapper.ngc \
implementation/mdm_0_wrapper.ngc \
implementation/proc_sys_reset_0_wrapper.ngc \
implementation/spiifc_0_wrapper.ngc \
implementation/xps_central_dma_0_wrapper.ngc
POSTSYN_NETLIST = implementation/$(SYSTEM).ngc
SYSTEM_BIT = implementation/$(SYSTEM).bit
DOWNLOAD_BIT = implementation/download.bit
SYSTEM_ACE = implementation/$(SYSTEM).ace
UCF_FILE = data\system.ucf
BMM_FILE = implementation/$(SYSTEM).bmm
BITGEN_UT_FILE = etc/bitgen.ut
XFLOW_OPT_FILE = etc/fast_runtime.opt
XFLOW_DEPENDENCY = __xps/xpsxflow.opt $(XFLOW_OPT_FILE)
XPLORER_DEPENDENCY = __xps/xplorer.opt
XPLORER_OPTIONS = -p $(DEVICE) -uc $(SYSTEM).ucf -bm $(SYSTEM).bmm -max_runs 7
FPGA_IMP_DEPENDENCY = $(BMM_FILE) $(POSTSYN_NETLIST) $(UCF_FILE) $(XFLOW_DEPENDENCY)
SDK_EXPORT_DIR = SDK\SDK_Export\hw
SYSTEM_HW_HANDOFF = $(SDK_EXPORT_DIR)/$(SYSTEM).xml
SYSTEM_HW_HANDOFF_BIT = $(SDK_EXPORT_DIR)/$(SYSTEM).bit
SYSTEM_HW_HANDOFF_BMM = $(SDK_EXPORT_DIR)/$(SYSTEM)_bd.bmm
SYSTEM_HW_HANDOFF_DEP = $(SYSTEM_HW_HANDOFF) $(SYSTEM_HW_HANDOFF_BIT) $(SYSTEM_HW_HANDOFF_BMM)
scripts/master/spilib.py
View file @ a64d58e7
......@@ -6,7 +6,7 @@ class SpiComm:
_port = 0 # Change if using multiple Cheetahs
_mode = 3 # spiifc SPI mode
_bitrate = 30000 # bytes
_bitrate = 22000 # kbps
handle = None # handle to Cheetah SPI
......@@ -34,24 +34,48 @@ class SpiComm:
ch_spi_queue_clear(self.handle)
ch_spi_queue_oe(self.handle, 1)
ch_spi_queue_ss(self.handle, 0x1)
ch_spi_queue_byte(self.handle, 1, 1) # Sending data to slave
for byte in byteArray:
ch_spi_queue_byte(self.handle, 1, byte)
ch_spi_queue_ss(self.handle, 0)
ch_spi_queue_oe(self.handle, 0)
(actualByteCount, data_in) = ch_spi_batch_shift(self.handle, byteCount)
def RecvFromSlave(self, byteCount):
def RecvFromSlave(self, command, byteCount):
totalByteCount = byteCount + 1 # Extra byte for cmd
data_in = array('B', [0 for i in range(totalByteCount)])
actualByteCount = 0
ch_spi_queue_clear(self.handle)
ch_spi_queue_oe(self.handle, 1)
ch_spi_queue_ss(self.handle, 0x1)
ch_spi_queue_byte(self.handle, 1, 3) # Receive data from slave
for byteIndex in range(byteCount):
ch_spi_queue_byte(self.handle, 1, 0)
ch_spi_queue_ss(self.handle, 0)
ch_spi_queue_ss(self.handle, 1)
ch_spi_queue_byte(self.handle, 1, command) # Receive data from slave
ch_spi_queue_byte(self.handle, byteCount, 0xFF)
ch_spi_queue_ss(self.handle, 0x0)
ch_spi_queue_oe(self.handle, 0)
(actualByteCount, data_in) = ch_spi_batch_shift(self.handle,
totalByteCount)
return data_in
return data_in[1:]
def ReadMemory(self, byteCount):
return self.RecvFromSlave(0x3, byteCount)
def WriteMemory(self, bytesToWrite):
bytePacket = [0x01]
bytePacket.extend(bytesToWrite)
return self.SendToSlave(bytePacket)
def ReadReg(self, regId):
commandCode = 0x80 + regId
regValBytes = self.RecvFromSlave(commandCode, 4)
regValWord = 0
for regValByte in regValBytes:
regValWord = (regValWord * 256) + regValByte
return regValWord
def WriteReg(self, regId, value):
commandCode = 0xC0 + regId
bytesToSend = [commandCode, 0, 0, 0, 0]
for sendByteId in range(4,0,-1):
bytesToSend[sendByteId] = value % 256
value = value / 256
self.SendToSlave(bytesToSend)
scripts/master/spitest.py
View file @ a64d58e7
import sys
import spilib
import time
import datetime
import random
def GenRandomByteArray(byteCount):
dataToSend = []
for byteIndex in range(byteCount):
dataToSend.append(random.randint(0, 255))
return dataToSend
#
# SingleBytePacketTest:
#
# Sends a predefined pattern of single-byte SPI transmissions (master-out)
#
def SingleBytePacketsSendTest():
packetsToSend = [[0x55],[0xAA],[0x33],[0x66],[0xCC],[0x99],[0xF0],\
[0x0F],[0xFF],[0x00]]
packetIndex = 0
while True:
dataToSend = packetsToSend[packetIndex]
sys.stdout.write("Sending: [")
for sendByte in dataToSend:
sys.stdout.write(" 0x%02x" % (sendByte))
sys.stdout.write(" ]\n")
spi.SendToSlave(dataToSend)
packetIndex = (packetIndex + 1) % len(packetsToSend)
time.sleep(1)
packetIndex + 1
#
# MultiBytePacketSendTest:
#
# Sends a predefined single multi-byte packet over SPI (master-out)
#
def MultiBytePacketSendTest():
dataToSend = [0x01, 0x55, 0xAA, 0x33, 0x66, 0xCC, 0x99, 0xF0, 0xFF, 0x0F]
sys.stdout.write("Sending: [")
for sendByte in dataToSend:
sys.stdout.write(" 0x%02x" % (sendByte))
sys.stdout.write(" ]\n")
spi.SendToSlave(dataToSend)
#
# MemLoopbackTest:
#
# Sends randomly generated blocks of data over SPI, then reads back
# data. Assumes that slave is using a common read and write buffer
# and reads the block of data back. The test verifies that the block of
# data is identical to the one sent. The test will run continuously
# until a received packet does not match the sent packet.
#
def MemLoopbackTest():
passCount = 0
loopbackErrors = 0
packetByteSize = 4000
while loopbackErrors == 0:
print("PassCount: %d" % (passCount))
dataToSend = GenRandomByteArray(packetByteSize)
print("Sending [0x%x 0x%x 0x%x 0x%x 0x%x ...]" % (
dataToSend[0], dataToSend[1], dataToSend[2],
dataToSend[3], dataToSend[4]))
# Send some data to the slave
sys.stdout.write("Sending data to slave...");
spi.WriteMemory(dataToSend)
sys.stdout.write("done!\n")
# Receive some data from the slave
recvData = spi.ReadMemory(packetByteSize)
# Make sure bytes sent match bytes received
if len(recvData) != packetByteSize:
sys.stdout.write("[FAIL] Did not receive 4096 bytes from spiifc\n")
sys.exit(0)
for byteIndex in range(packetByteSize):
if recvData[byteIndex] != dataToSend[byteIndex]:
sys.stdout.write("[FAIL] mismatch at index %d: sent=0x%x, recv=0x%x\n" \
% (byteIndex, dataToSend[byteIndex], recvData[byteIndex]))
loopbackErrors = loopbackErrors + 1
if loopbackErrors >= 5:
break
if 0 == loopbackErrors:
sys.stdout.write("[PASS] All loopback SPI bytes match.\n");
passCount = passCount + 1
# Print number of passed tests before failure
print("PassCount: %d" % (passCount))
#
# RegLoopbackTest:
#
# Randomly writes and reads to vSPI's register and makes sure
# values are as expected
#
def RegLoopbackTest():
# First, zero out all registers
print("Zeroing all registers...")
for regId in range(16):
spi.WriteReg(regId=regId, value=0)
# Second, check that all registers are zeroed
print("Checking all registers are zeroed...")
for regId in range(16):
regVal = spi.ReadReg(regId)
if (0 != regVal):
sys.stdout.write("ERROR: Reg %d was not zeroed (was 0x%08x)\n" % \
(regId, regVal))
return
# Local mapping of expected register values
expectedRegs = list(0 for i in range(16))
# Random read and writes
passCount = 0
while (True):
print("")
regWriteId = random.randint(0, 15)
regReadId = random.randint(0, 15)
regWriteVal = random.randint(0, 0xFFFFFFFF)
print("Writing Reg%d=0x%08x" % (regWriteId, regWriteVal))
spi.WriteReg(regId=regWriteId, value=regWriteVal)
expectedRegs[regWriteId] = regWriteVal
print("Checking Reg%d==0x%08x" % (regReadId, expectedRegs[regReadId]))
regReadVal = spi.ReadReg(regReadId)
if (expectedRegs[regReadId] != regReadVal):
sys.stderr.write("ERROR: Reg %d - expected=0x%08x, actual=0x%08x\n" % \
(expectedRegs[regReadId], regReadVal))
return
passCount = passCount + 1
print("PASS [%d]" % (passCount))
#
# ReadRegsTest
#
# Reads out the value of all registers
#
def ReadRegsTest():
for regId in range(16):
regVal = spi.ReadReg(regId)
print("Reg%d = 0x%08x" % (regId, regVal))
#
# WriteRegsTest
#
# Writes a test pattern to the spi registers
#
def WriteRegsTest():
for regId in range(16):
regVal = 255 - regId
regVal = (regVal * 256) + regVal
regVal = (regVal * 256 * 256) + regVal
print("Reg%d = 0x%08x" % (regId, regVal))
spi.WriteReg(regId=regId, value=regVal)
#
# XpsLoopbackTest
#
# Tests loopback utilizing the XPS/XSDK system and SPI memory + SPI.r0
#
def XpsLoopbackTest():
dataBytes = 4096
passCount = 0
while (True):
print("Starting run %d..." % (passCount + 1))
# Generate random data blob
dataToSend = GenRandomByteArray(dataBytes)
# Send data blob
print("Sending data to FPGA")
spi.WriteMemory(dataToSend)
# Set SPI.reg0 = 0x1 (M->S transfer complete)
print("Setting spi.r0[0] = 1")
spi.WriteReg(regId=0, value=0x1)
# Wait for microblaze to finish DMAing data from MOSI to MISO buffer
print("Waiting for FPGA's DMA to complete (poll spi.r0[1])")
while 0 == (spi.ReadReg(regId=0) & 0x2):
pass
# Read MISO buffer
print("Read data back from FPGA")
recvData = spi.ReadMemory(len(dataToSend))
print("Verify: comparing send and received data")
# Verify loopbacked data matches original data
errorCount = 0
if len(recvData) != len(dataToSend):
sys.stdout.write("[ERROR] received data blob length (%d) does not " + \
"match original length (%d)" % \
(len(recvData), len(dataToSend)))
errorCount = errorCount + 1
return
for byteIndex in range(len(dataToSend)):
if dataToSend[byteIndex] != recvData[byteIndex]:
print("[ERROR] transmission mismatch - Index %d, Expect:0x%02x, " + \
"Actual:0x%02x" % (byteIndex, dataToSend[byteIndex], \
recvData[byteIndex]))
errorCount = errorCount + 1
if errorCount >= 5:
print("Stopping due to errors...")
return
if 0 == errorCount:
print("[PASS] Loopbacked without any errors\n")
passCount = passCount + 1
else:
return
#
# PrintCliSyntax:
#
# Displays the syntax for the command line interface (CLI)
def PrintCliSyntax():
print """
Syntax:
spitest.py test [random-seed]
Valid tests (case sensitive):
- SingleBytePacketsSend
- MultiBytePacketSend
- MemLoopback
- RegLoopback
- ReadRegs
- WriteRegsTest
- XpsLoopback
"""
#
# Main
#
# Parse CLI
if len(sys.argv) < 2 or len(sys.argv) > 3:
PrintCliSyntax()
sys.exit(1)
# Retreive specified test function(s)
cliTest = sys.argv[1]
testMapping = {'SingleBytePacketsSend' : [SingleBytePacketsSendTest],
'MultiBytePacketSend' : [MultiBytePacketSendTest],
'MemLoopback' : [MemLoopbackTest],
'RegLoopback' : [RegLoopbackTest],
'ReadRegs' : [ReadRegsTest],
'WriteRegs' : [WriteRegsTest],
'XpsLoopback' : [XpsLoopbackTest]}
if cliTest not in testMapping:
sys.stderr.write('%s is not a valid test.\n' % (cliTest,))
PrintCliSyntax()
sys.exit(1)
testsToRun = testMapping[cliTest]
# Seed random number generator
if len(sys.argv) == 3:
seed = int(sys.argv[2])
else:
seed = datetime.datetime.utcnow().microsecond
# Initialize Cheetah SPI/USB adapter
spi = spilib.SpiComm()
# Send some data to the slave
sys.stdout.write("Sending data to slave...");
spi.SendToSlave([0xFF, 0xF0, 0x33, 0x55, 0x12, 0x34, 0x56, 0x53, 0x9A])
sys.stdout.write("done!")
# Receive some data from the slave
recvData = spi.RecvFromSlave(4096)
sys.stdout.write("Received data from slave:\n")
for recvByte in recvData:
sys.stdout.write("%x " % recvByte)
sys.stdout.write("\nDone!\n")
# Seed random
print("Random seed: %d" % seed)
random.seed(seed)
# Run specified test
for testToRun in testsToRun:
testToRun()
# Close and exit
sys.stdout.write("Exiting...\n")
......
scripts/pre-xilinx-checkin.sh 0 → 100644
View file @ a64d58e7
#!/bin/sh
#
# pre-xilinx-checkin.sh
#
# Michael J. Lyons, 2012
#
# Deletes temporary files left over, even after xilinx tools do a 'clean'
#
VSPI_ROOT=..
RM="rm -f"
$RM $VSPI_ROOT/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/iseconfig/*.xreport
$RM $VSPI_ROOT/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/*.html
$RM $VSPI_ROOT/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/webtalk_impact.xml
$RM $VSPI_ROOT/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/*.xrpt
$RM $VSPI_ROOT/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/*.xreport
scripts/update-tb-vectors.sh 0 → 100644
View file @ a64d58e7
#!/bin/sh
cp ../test/spi_base/rc-bytes*.txt ../projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/
src/spi_base/spiifc.v
View file @ a64d58e7
......@@ -3,7 +3,7 @@
// Company:
// Engineer:
//
// Create Date: 19:24:33 10/18/2011
// Create Date: 16:46:12 03/02/2012
// Design Name:
// Module Name: spiifc
// Project Name:
......@@ -30,203 +30,259 @@ module spiifc(
rcMemAddr,
rcMemData,
rcMemWE,
regAddr,
regReadData,
regWriteEn,
regWriteData,
debug_out
);
//
// Parameters
//
parameter AddrBits = 12;
// Defines
`define CMD_READ_START 8'd1
`define CMD_READ_MORE 8'd2
`define CMD_WRITE_START 8'd3
`define STATE_GET_CMD 8'd0
`define STATE_READING 8'd1
`define STATE_WRITING 8'd2
//
// Input/Output defs
//
input Reset;
input SysClk;
input SPI_CLK;
output SPI_MISO;
input SPI_MOSI;
input SPI_SS;
output [AddrBits-1:0] txMemAddr;
input [7:0] txMemData;
output [AddrBits-1:0] rcMemAddr;
output [7:0] rcMemData;
output rcMemWE;
output [7:0] debug_out;
//
// Registers
//
reg [ 7: 0] debug_reg;
reg [ 7: 0] rcByteReg;
reg rcStarted;
reg [ 2: 0] rcBitIndexReg;
reg [11: 0] rcMemAddrReg;
reg [11: 0] rcMemAddrNext;
reg [ 7: 0] rcMemDataReg;
reg rcMemWEReg;
reg ssPrev;
reg ssFastToggleReg;
reg ssSlowToggle;
reg ssTurnOnReg;
reg ssTurnOnHandled;
reg [ 7: 0] cmd;
reg [ 7: 0] stateReg;
reg [11: 0] txMemAddrReg;
reg [ 2: 0] txBitAddr;
//
// Wires
//
wire rcByteValid;
wire [ 7: 0] rcByte;
wire rcStarting;
wire [ 2: 0] rcBitIndex;
wire ssTurnOn;
wire ssFastToggle;
wire [ 7: 0] state;
wire txMemAddrReset;
//
// Output assigns
//
assign debug_out = debug_reg;
assign rcMemAddr = rcMemAddrReg;
assign rcMemData = rcMemDataReg;
assign rcMemWE = rcMemWEReg;
assign txMemAddrReset = (rcByteValid && rcByte == `CMD_WRITE_START ? 1 : 0);
assign txMemAddr = (txMemAddrReset ? 0 : txMemAddrReg);
assign SPI_MISO = txMemData[txBitAddr];
assign ssFastToggle =
(ssPrev == 1 && SPI_SS == 0 ? ~ssFastToggleReg : ssFastToggleReg);
//
// Wire assigns
//
assign rcByteValid = rcStarted && rcBitIndex == 0;
assign rcByte = {rcByteReg[7:1], SPI_MOSI};
assign rcStarting = ssTurnOn;
assign rcBitIndex = (rcStarting ? 3'd7 : rcBitIndexReg);
assign ssTurnOn = ssSlowToggle ^ ssFastToggle;
assign state = (rcStarting ? `STATE_GET_CMD : stateReg);
initial begin
ssSlowToggle <= 0;
);
//
// Parameters
//
parameter AddrBits = 12;
parameter RegAddrBits = 4;
//
// Defines
//
`define CMD_READ_START 8'd1
`define CMD_READ_MORE 8'd2
`define CMD_WRITE_START 8'd3
`define CMD_WRITE_MORE 8'd4
`define CMD_INTERRUPT 8'd5
`define CMD_REG_BASE 8'd128
`define CMD_REG_BIT 7
`define CMD_REG_WE_BIT 6
`define CMD_REG_ID_MASK 8'h3F
`define STATE_GET_CMD 8'd0
`define STATE_READING 8'd1
`define STATE_WRITING 8'd2
`define STATE_WRITE_INTR 8'd3
`define STATE_BUILD_WORD 8'd4
`define STATE_SEND_WORD 8'd5
//
// Input/Outputs
//
input Reset;
input SysClk;
input SPI_CLK;
output SPI_MISO; // outgoing (from respect of this module)
input SPI_MOSI; // incoming (from respect of this module)
input SPI_SS;
output [AddrBits-1:0] txMemAddr; // outgoing data
input [7:0] txMemData;
output [AddrBits-1:0] rcMemAddr; // incoming data
output [7:0] rcMemData;
output rcMemWE;
output [RegAddrBits-1:0] regAddr; // Register read address (combinational)
input [31:0] regReadData; // Result of register read
output regWriteEn; // Enable write to register, otherwise read
output [31:0] regWriteData; // Register write data
output [7:0] debug_out;
//
// Registers
//
reg SPI_CLK_reg; // Stabalized version of SPI_CLK
reg SPI_SS_reg; // Stabalized version of SPI_SS
reg SPI_MOSI_reg; // Stabalized version of SPI_MOSI
reg prev_spiClk; // Value of SPI_CLK during last SysClk cycle
reg prev_spiSS; // Value of SPI_SS during last SysClk cycle
reg [7:0] state_reg; // Register backing the 'state' wire
reg [7:0] rcByte_reg; // Register backing 'rcByte'
reg [2:0] rcBitIndex_reg; // Register backing 'rcBitIndex'
reg [AddrBits-1:0] rcMemAddr_reg; // Byte addr to write MOSI data to
reg [7:0] debug_reg; // register backing debug_out signal
reg [2:0] txBitIndex_reg; // Register backing txBitIndex
reg [AddrBits-1:0] txMemAddr_reg; // Register backing txAddr
reg [7:0] command; // Command being handled
reg [31:0] rcWord; // Incoming word being built
reg [1:0] rcWordByteId; // Which byte the in the rcWord to map to
reg [RegAddrBits-1:0] regAddr_reg; // Address of register to read/write to
//
// Wires
//
wire risingSpiClk; // Did the SPI_CLK rise since last SysClk cycle?
wire validSpiBit; // Are the SPI MOSI/MISO bits new and valid?
reg [7:0] state; // Current state in the module's state machine (always @* effectively wire)
wire rcByteValid; // rcByte is valid and new
wire [7:0] rcByte; // Byte received from master
wire [2:0] rcBitIndex; // Bit of rcByte to write to next
reg [2:0] txBitIndex; // bit of txByte to send to master next
reg [AddrBits-1:0] txMemAddr_oreg; // Wirereg piped to txMemAddr output
reg [7:0] regReadByte_oreg; // Which byte of the reg word we're reading out master
// Save buffered SPI inputs
always @(posedge SysClk) begin
SPI_CLK_reg <= SPI_CLK;
SPI_SS_reg <= SPI_SS;
SPI_MOSI_reg <= SPI_MOSI;
end
// Detect new valid bit
always @(posedge SysClk) begin
prev_spiClk <= SPI_CLK_reg;
end
assign risingSpiClk = SPI_CLK_reg & (~prev_spiClk);
assign validSpiBit = risingSpiClk & (~SPI_SS_reg);
// Detect new SPI packet (SS dropped low)
always @(posedge SysClk) begin
prev_spiSS <= SPI_SS_reg;
end
assign packetStart = prev_spiSS & (~SPI_SS_reg);
// Build incoming byte
always @(posedge SysClk) begin
if (validSpiBit) begin
rcByte_reg[rcBitIndex] <= SPI_MOSI_reg;
rcBitIndex_reg <= (rcBitIndex > 0 ? rcBitIndex - 1 : 7);
end else begin
rcBitIndex_reg <= rcBitIndex;
end
always @(posedge SysClk) begin
ssPrev <= SPI_SS;
if (Reset) begin
ssTurnOnReg <= 0;
ssFastToggleReg <= 0;
end
assign rcBitIndex = (Reset || packetStart ? 7 : rcBitIndex_reg);
assign rcByte = {rcByte_reg[7:1], SPI_MOSI_reg};
assign rcByteValid = (validSpiBit && rcBitIndex == 0 ? 1 : 0);
// Incoming MOSI data buffer management
assign rcMemAddr = rcMemAddr_reg;
assign rcMemData = rcByte;
assign rcMemWE = (state == `STATE_READING && rcByteValid ? 1 : 0);
always @(posedge SysClk) begin
if (Reset || (`STATE_GET_CMD == state && rcByteValid)) begin
rcMemAddr_reg <= 0;
end else if (rcMemWE) begin
rcMemAddr_reg <= rcMemAddr + 1;
end else begin
rcMemAddr_reg <= rcMemAddr;
end
end
// Outgoing MISO data buffer management
always @(*) begin
if (Reset || (state == `STATE_GET_CMD && rcByteValid &&
(rcByte == `CMD_WRITE_START ||
rcByte[`CMD_REG_BIT:`CMD_REG_WE_BIT] == 2'b11)
)) begin
txBitIndex <= 3'd7;
txMemAddr_oreg <= 0;
end else begin
txBitIndex <= txBitIndex_reg;
//txMemAddr_oreg <= txMemAddr_reg;
if ((state == `STATE_WRITING || state == `STATE_SEND_WORD) &&
validSpiBit && txBitIndex == 0) begin
txMemAddr_oreg <= txMemAddr_reg + 1;
end else begin
if (ssPrev & (~SPI_SS)) begin
ssTurnOnReg <= 1;
ssFastToggleReg <= ~ssFastToggleReg;
end else if (ssTurnOnHandled) begin
ssTurnOnReg <= 0;
end
txMemAddr_oreg <= txMemAddr_reg;
end
end
always @(posedge SPI_CLK) begin
ssSlowToggle <= ssFastToggle;
if (Reset) begin
// Resetting
rcByteReg <= 8'h00;
rcStarted <= 0;
rcBitIndexReg <= 3'd7;
ssTurnOnHandled <= 0;
debug_reg <= 8'hFF;
end else begin
// Not resetting
ssTurnOnHandled <= ssTurnOn;
stateReg <= state;
rcMemAddrReg <= rcMemAddrNext;
if (~SPI_SS) begin
rcByteReg[rcBitIndex] <= SPI_MOSI;
rcBitIndexReg <= rcBitIndex - 3'd1;
rcStarted <= 1;
// Update txBitAddr if writing out
if (`STATE_WRITING == state) begin
if (txBitAddr == 3'd1) begin
txMemAddrReg <= txMemAddr + 1;
end
txBitAddr <= txBitAddr - 1;
end
end
// We've just received a byte (well, currently receiving the last bit)
if (rcByteValid) begin
// For now, just display on LEDs
debug_reg <= rcByte;
if (`STATE_GET_CMD == state) begin
cmd <= rcByte; // Will take effect next cycle
if (`CMD_READ_START == rcByte) begin
rcMemAddrNext <= 0;
stateReg <= `STATE_READING;
end else if (`CMD_READ_MORE == rcByte) begin
stateReg <= `STATE_READING;
end else if (`CMD_WRITE_START == rcByte) begin
txBitAddr <= 3'd7;
stateReg <= `STATE_WRITING;
txMemAddrReg <= txMemAddr; // Keep at 0
end
end else if (`STATE_READING == state) begin
rcMemDataReg <= rcByte;
rcMemAddrNext <= rcMemAddr + 1;
rcMemWEReg <= 1;
end
end else begin
// Not a valid byte
rcMemWEReg <= 0;
end // valid/valid' byte
end
always @(posedge SysClk) begin
if (validSpiBit && (state == `STATE_WRITING || state == `STATE_SEND_WORD)) begin
txBitIndex_reg <= (txBitIndex == 0 ? 7 : txBitIndex - 1);
end else begin
txBitIndex_reg <= txBitIndex;
end
txMemAddr_reg <= txMemAddr;
// if (state == `STATE_WRITING && validSpiBit && txBitIndex == 0) begin
// txMemAddr_reg <= txMemAddr + 1;
// end else begin
// txMemAddr_reg <= txMemAddr;
// end
end
assign txMemAddr = txMemAddr_oreg;
assign SPI_MISO = (state == `STATE_SEND_WORD ? regReadByte_oreg[txBitIndex] : txMemData[txBitIndex]);
// State machine
always @(*) begin
if (Reset || packetStart) begin
state <= `STATE_GET_CMD;
// Handled in state_reg logic, should be latched, not immediate.
// end else if (state_reg == `STATE_GET_CMD && rcByteValid) begin
// state <= rcByte;
end else begin
state <= state_reg;
end
end
always @(posedge SysClk) begin
if (`STATE_GET_CMD == state && rcByteValid) begin
if (`CMD_READ_START == rcByte) begin
state_reg <= `STATE_READING;
end else if (`CMD_READ_MORE == rcByte) begin
state_reg <= `STATE_READING;
end else if (`CMD_WRITE_START == rcByte) begin
state_reg <= `STATE_WRITING;
end else if (`CMD_WRITE_MORE == rcByte) begin
state_reg <= `STATE_WRITING;
end else if (rcByte[`CMD_REG_BIT] != 0) begin
// Register access
rcWordByteId <= 0;
command <= `CMD_REG_BASE; // Write reg Read reg
state_reg <= (rcByte[`CMD_REG_WE_BIT] ? `STATE_BUILD_WORD : `STATE_SEND_WORD);
end else if (`CMD_INTERRUPT == rcByte) begin
// TODO: NYI
end
end else if (`STATE_BUILD_WORD == state && rcByteValid) begin
if (0 == rcWordByteId) begin
rcWord[31:24] <= rcByte;
rcWordByteId <= 1;
end else if (1 == rcWordByteId) begin
rcWord[23:16] <= rcByte;
rcWordByteId <= 2;
end else if (2 == rcWordByteId) begin
rcWord[15:8] <= rcByte;
rcWordByteId <= 3;
end else if (3 == rcWordByteId) begin
rcWord[7:0] <= rcByte;
state_reg <= `STATE_GET_CMD;
end
end else if (`STATE_SEND_WORD == state && rcByteValid) begin
rcWordByteId <= rcWordByteId + 1;
state_reg <= (rcWordByteId == 3 ? `STATE_GET_CMD : `STATE_SEND_WORD);
end // Reset/Reset'
end else begin
state_reg <= state;
end
end
// Register logic
assign regAddr = (`STATE_GET_CMD == state && rcByteValid && rcByte[`CMD_REG_BIT] ? (rcByte & `CMD_REG_ID_MASK) : regAddr_reg);
assign regWriteEn = (`STATE_BUILD_WORD == state && rcByteValid && 3 == rcWordByteId ? 1 : 0);
assign regWriteData = {rcWord[31:8], rcByte};
always @(posedge SysClk) begin
regAddr_reg <= regAddr;
end
always @(*) begin
case (rcWordByteId)
0: regReadByte_oreg <= regReadData[31:24];
1: regReadByte_oreg <= regReadData[23:16];
2: regReadByte_oreg <= regReadData[15:8];
3: regReadByte_oreg <= regReadData[7:0];
endcase
end
// Debugging
always @(posedge SysClk) begin
if (rcByteValid) begin
debug_reg <= rcByte;
end
end
assign debug_out = debug_reg;
endmodule
src/spi_base/spiifc_twoclock.v 0 → 100644
View file @ a64d58e7
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:24:33 10/18/2011
// Design Name:
// Module Name: spiifc
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module spiifc(
Reset,
SysClk,
SPI_CLK,
SPI_MISO,
SPI_MOSI,
SPI_SS,
txMemAddr,
txMemData,
rcMemAddr,
rcMemData,
rcMemWE,
debug_out
);
//
// Parameters
//
parameter AddrBits = 12;
// Defines
`define CMD_READ_START 8'd1
`define CMD_READ_MORE 8'd2
`define CMD_WRITE_START 8'd3
`define STATE_GET_CMD 8'd0
`define STATE_READING 8'd1
`define STATE_WRITING 8'd2
//
// Input/Output defs
//
input Reset;
input SysClk;
input SPI_CLK;
output SPI_MISO;
input SPI_MOSI;
input SPI_SS;
output [AddrBits-1:0] txMemAddr;
input [7:0] txMemData;
output [AddrBits-1:0] rcMemAddr;
output [7:0] rcMemData;
output rcMemWE;
output [7:0] debug_out;
//
// Registers
//
reg [ 7: 0] debug_reg;
reg [ 7: 0] rcByteReg;
reg rcStarted;
reg [ 2: 0] rcBitIndexReg;
reg [11: 0] rcMemAddrReg;
reg [11: 0] rcMemAddrNext;
reg [ 7: 0] rcMemDataReg;
reg rcMemWEReg;
reg ssPrev;
reg ssFastToggleReg;
reg ssSlowToggle;
reg ssTurnOnReg;
reg ssTurnOnHandled;
reg [ 7: 0] cmd;
reg [ 7: 0] stateReg;
reg [11: 0] txMemAddrReg;
reg [ 2: 0] txBitAddr;
//
// Wires
//
wire rcByteValid;
wire [ 7: 0] rcByte;
wire rcStarting;
wire [ 2: 0] rcBitIndex;
wire ssTurnOn;
wire ssFastToggle;
wire [ 7: 0] state;
wire txMemAddrReset;
//
// Output assigns
//
assign debug_out = debug_reg;
assign rcMemAddr = rcMemAddrReg;
assign rcMemData = rcMemDataReg;
assign rcMemWE = rcMemWEReg;
assign txMemAddrReset = (rcByteValid && rcByte == `CMD_WRITE_START ? 1 : 0);
assign txMemAddr = (txMemAddrReset ? 0 : txMemAddrReg);
assign SPI_MISO = txMemData[txBitAddr];
assign ssFastToggle =
(ssPrev == 1 && SPI_SS == 0 ? ~ssFastToggleReg : ssFastToggleReg);
//
// Wire assigns
//
assign rcByteValid = rcStarted && rcBitIndex == 0;
assign rcByte = {rcByteReg[7:1], SPI_MOSI};
assign rcStarting = ssTurnOn;
assign rcBitIndex = (rcStarting ? 3'd7 : rcBitIndexReg);
assign ssTurnOn = ssSlowToggle ^ ssFastToggle;
assign state = (rcStarting ? `STATE_GET_CMD : stateReg);
initial begin
ssSlowToggle <= 0;
end
always @(posedge SysClk) begin
ssPrev <= SPI_SS;
if (Reset) begin
ssTurnOnReg <= 0;
ssFastToggleReg <= 0;
end else begin
if (ssPrev & (~SPI_SS)) begin
ssTurnOnReg <= 1;
ssFastToggleReg <= ~ssFastToggleReg;
end else if (ssTurnOnHandled) begin
ssTurnOnReg <= 0;
end
end
end
always @(posedge SPI_CLK) begin
ssSlowToggle <= ssFastToggle;
if (Reset) begin
// Resetting
rcByteReg <= 8'h00;
rcStarted <= 0;
rcBitIndexReg <= 3'd7;
ssTurnOnHandled <= 0;
debug_reg <= 8'hFF;
end else begin
// Not resetting
ssTurnOnHandled <= ssTurnOn;
stateReg <= state;
rcMemAddrReg <= rcMemAddrNext;
if (~SPI_SS) begin
rcByteReg[rcBitIndex] <= SPI_MOSI;
rcBitIndexReg <= rcBitIndex - 3'd1;
rcStarted <= 1;
// Update txBitAddr if writing out
if (`STATE_WRITING == state) begin
if (txBitAddr == 3'd1) begin
txMemAddrReg <= txMemAddr + 1;
end
txBitAddr <= txBitAddr - 1;
end
end
// We've just received a byte (well, currently receiving the last bit)
if (rcByteValid) begin
// For now, just display on LEDs
debug_reg <= rcByte;
if (`STATE_GET_CMD == state) begin
cmd <= rcByte; // Will take effect next cycle
if (`CMD_READ_START == rcByte) begin
rcMemAddrNext <= 0;
stateReg <= `STATE_READING;
end else if (`CMD_READ_MORE == rcByte) begin
stateReg <= `STATE_READING;
end else if (`CMD_WRITE_START == rcByte) begin
txBitAddr <= 3'd7;
stateReg <= `STATE_WRITING;
txMemAddrReg <= txMemAddr; // Keep at 0
end
end else if (`STATE_READING == state) begin
rcMemDataReg <= rcByte;
rcMemAddrNext <= rcMemAddr + 1;
rcMemWEReg <= 1;
end else if (`STATE_WRITING == state) begin
txBitAddr <= 3'd7;
stateReg <= `STATE_WRITING;
end
end else begin
// Not a valid byte
rcMemWEReg <= 0;
end // valid/valid' byte
end // Reset/Reset'
end
endmodule
src/spi_base/spiloop.v 0 → 100644
View file @ a64d58e7
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:49:15 11/02/2011
// Design Name:
// Module Name: spiwrap
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module spiloop(
input Reset,
input SysClk,
input spi_ss,
input spi_mosi,
input spi_clk,
output spi_miso,
output [7:0] leds
);
wire [7:0] debug_out;
wire [11:0] txMemAddr;
wire [7:0] txMemData;
wire [11:0] rcMemAddr;
wire [7:0] rcMemData;
wire rcMemWE;
wire [3:0] regAddr;
wire [31:0] regWriteData;
wire regWE;
reg [31:0] regReadData_wreg;
reg [31:0] regbank [0:15];
always @(*) begin // Read reg
regReadData_wreg <= regbank[regAddr];
end
always @(posedge SysClk) begin // Write reg
if (regWE) begin
regbank[regAddr] <= regWriteData;
end
end
spiloopmem your_instance_name (
.clka(SysClk), // input clka
.ena(1'b1), // input ena
.wea(rcMemWE), // input [0 : 0] wea
.addra(rcMemAddr), // input [11 : 0] addra
.dina(rcMemData), // input [7 : 0] dina
.clkb(SysClk), // input clkb
.enb(1'b1), // input enb
.addrb(txMemAddr), // input [11 : 0] addrb
.doutb(txMemData) // output [7 : 0] doutb
);
spiifc mySpiIfc (
.Reset(Reset),
.SysClk(SysClk),
.SPI_CLK(spi_clk),
.SPI_MISO(spi_miso),
.SPI_MOSI(spi_mosi),
.SPI_SS(spi_ss),
.txMemAddr(txMemAddr),
.txMemData(txMemData),
.rcMemAddr(rcMemAddr),
.rcMemData(rcMemData),
.rcMemWE(rcMemWE),
.regAddr(regAddr),
.regReadData(regReadData_wreg),
.regWriteData(regWriteData),
.regWriteEn(regWE),
.debug_out(debug_out)
);
//assign leds = debug_out ;
assign leds = txMemData;
endmodule
src/spi_base/spiwrap.v
View file @ a64d58e7
......@@ -56,19 +56,19 @@ always @(posedge SysClk) begin
end
end
spimem spiMemTx (
.clka(SysClk), // input clka
.ena(1'b1), // input ena
.wea(initMem), // input [0 : 0] wea
.addra(initMemAddr), // input [9 : 0] addra
.dina(initMemData), // input [31 : 0] dina
.douta(douta_dummy), // output [31 : 0] douta
.clkb(spi_clk), // input clkb
.enb(1'b1), // input enb
.web(1'b0), // input [0 : 0] web
.addrb(spi_addr), // input [11 : 0] addrb
.dinb(8'h00), // input [7 : 0] dinb
.doutb(spi_data) // output [7 : 0] doutb
buffermem spiMemTx (
.clka(SysClk), // input clkb
.ena(1'b1), // input enb
.wea(1'b0), // input [0 : 0] web
.addra(spi_addr), // input [11 : 0] addrb
.dina(8'h00), // input [7 : 0] dinb
.douta(spi_data), // output [7 : 0] doutb
.clkb(SysClk), // input clka
.enb(1'b1), // input ena
.web(initMem), // input [0 : 0] wea
.addrb(initMemAddr), // input [9 : 0] addra
.dinb(initMemData), // input [31 : 0] dina
.doutb(douta_dummy) // output [31 : 0] douta
);
wire spi_rcMem_we;
......@@ -76,18 +76,18 @@ wire [11:0] spi_rcMem_addr;
wire [ 7:0] spi_rcMem_data;
wire [ 7:0] debug_out;
wire [ 7:0] spi_rcMem_doutb_dummy;
spimem spiMemRc (
buffermem spiMemRc (
.clka(SysClk),
.ena(1'b1),
.wea(1'b0),
.addra(10'h001),
.douta(rcMem_douta),
.clkb(spi_clk),
.wea(spi_rcMem_we),
.addra(spi_rcMem_addr),
.dina(spi_rcMem_data),
.douta(spi_rcMem_doutb_dummy),
.clkb(SysClk),
.enb(1'b1),
.web(spi_rcMem_we),
.addrb(spi_rcMem_addr),
.dinb(spi_rcMem_data),
.doutb(spi_rcMem_doutb_dummy)
.web(1'b0),
.addrb(10'h001),
.doutb(rcMem_douta)
);
spiifc mySpiIfc (
......@@ -105,8 +105,6 @@ spiifc mySpiIfc (
.debug_out(debug_out)
);
assign leds = rcMem_douta[31:24];
assign leds = rcMem_douta[7:0] /* debug_out */;
endmodule
test/spi_base/rc-bytes-writereg.txt 0 → 100644
View file @ a64d58e7
C3
F0
0F
5C
C5
83
00
00
00
00
test/spi_base/spiifc_writereg_tb.v 0 → 100644
View file @ a64d58e7
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:08:12 02/15/2012
// Design Name: spiifc
// Module Name: C:/workspace/robobees/hbp/fpga/spitest/pcores/spi_v1_00_a/hdl/verilog/spiifc_tb2.v
// Project Name: spi
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: spiifc
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module spiifc_writereg_tb;
// Inputs
reg Reset;
reg SysClk;
reg SPI_CLK;
reg SPI_MOSI;
reg SPI_SS;
reg [7:0] txMemData;
reg [31:0] regReadData_wreg;
// Outputs
wire SPI_MISO;
wire [11:0] txMemAddr;
wire [11:0] rcMemAddr;
wire [7:0] rcMemData;
wire rcMemWE;
wire [7:0] debug_out;
wire [3:0] regAddr;
wire [31:0] regWriteData;
wire regWE;
// Register bank
reg [31:0] regbank [0:15];
// Instantiate the Unit Under Test (UUT)
spiifc uut (
.Reset(Reset),
.SysClk(SysClk),
.SPI_CLK(SPI_CLK),
.SPI_MISO(SPI_MISO),
.SPI_MOSI(SPI_MOSI),
.SPI_SS(SPI_SS),
.txMemAddr(txMemAddr),
.txMemData(txMemData),
.rcMemAddr(rcMemAddr),
.rcMemData(rcMemData),
.rcMemWE(rcMemWE),
.regAddr(regAddr),
.regReadData(regReadData_wreg),
.regWriteData(regWriteData),
.regWriteEn(regWE),
.debug_out(debug_out)
);
task recvByte;
input [7:0] rcByte;
integer rcBitIndex;
begin
$display("%g - spiifc receiving byte '0x%h'", $time, rcByte);
for (rcBitIndex = 0; rcBitIndex < 8; rcBitIndex = rcBitIndex + 1) begin
SPI_MOSI = rcByte[7 - rcBitIndex];
#100;
end
end
endtask
always begin
#20 SysClk = ~SysClk;
end
// Register bank
always @(*) begin // Read reg
regReadData_wreg <= regbank[regAddr];
end
always @(posedge SysClk) begin // Write reg
if (regWE) begin
regbank[regAddr] <= regWriteData;
end
end
reg SPI_CLK_en;
initial begin
#310
SPI_CLK_en = 1;
end
always begin
#10
if (SPI_CLK_en) begin
#40 SPI_CLK = ~SPI_CLK;
end
end
integer fdRcBytes;
integer fdTxBytes;
integer dummy;
integer currRcByte;
integer rcBytesNotEmpty;
reg [8*10:1] rcBytesStr;
initial begin
// Initialize Inputs
Reset = 0;
SysClk = 0;
SPI_CLK = 0;
SPI_CLK_en = 0;
SPI_MOSI = 0;
SPI_SS = 1;
txMemData = 0;
// Wait 100 ns for global reset to finish
#100;
Reset = 1;
#100;
Reset = 0;
#100;
// Add stimulus here
SPI_SS = 0;
// For each byte, transmit its bits
fdRcBytes = $fopen("rc-bytes-writereg.txt", "r");
rcBytesNotEmpty = 1;
while (rcBytesNotEmpty) begin
rcBytesNotEmpty = $fgets(rcBytesStr, fdRcBytes);
if (rcBytesNotEmpty) begin
dummy = $sscanf(rcBytesStr, "%x", currRcByte);
recvByte(currRcByte);
end
end
// Wrap it up.
SPI_SS = 1;
#1000;
$finish;
end
endmodule
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