Merge branch 'fastclock' into xps_proj

scripts/master/spilib.py

@@ -7,7 +7,7 @@ class SpiComm:
   
   _port = 0         # Change if using multiple Cheetahs
   _mode = 3         # spiifc SPI mode
-  _bitrate = 27900  # kbps
+  _bitrate = 22000  # kbps
 
   handle = None     # handle to Cheetah SPI
 

scripts/master/spitest.py

@@ -136,6 +136,16 @@ def RegLoopbackTest():
     passCount = passCount + 1
     print("PASS [%d]" % (passCount))
 
+#
+# ReadRegsTest
+#
+# Reads out the value of all registers
+#
+def ReadRegsTest():
+  for regId in range(16):
+    regVal = spi.ReadReg(regId)
+    print("Reg%d = 0x%08x" % (regId, regVal))
+
 #
 # PrintCliSyntax:
 #
@@ -150,6 +160,7 @@ Valid tests (case sensitive):
   - MultiBytePacketSend
   - MemLoopback
   - RegLoopback
+  - ReadRegs
 """
 
 #
@@ -166,7 +177,8 @@ cliTest = sys.argv[1]
 testMapping = {'SingleBytePacketsSend' : [SingleBytePacketsSendTest],
                'MultiBytePacketSend' : [MultiBytePacketSendTest],
                'MemLoopback' : [MemLoopbackTest],
-               'RegLoopback' : [RegLoopbackTest]}
+               'RegLoopback' : [RegLoopbackTest],
+               'ReadRegs' : [ReadRegsTest]}
 if cliTest not in testMapping:
   sys.stderr.write('%s is not a valid test.\n' % (cliTest,))
   PrintCliSyntax()