Loopback (send+receive without XPS/XSDK) works at up to 28mbps!

Signed-off-by: Mike Lyons <github@explosivedonut.com>

Loopback (send+receive without XPS/XSDK) works at up to 28mbps!
Signed-off-by: Mike Lyons <github@explosivedonut.com>
74ff52fb · Mike Lyons · 651c43f0 · 74ff52fb · 74ff52fb · 74ff52fb
Commit 74ff52fb authored Mar 08, 2012 by Mike Lyons
19 changed files
--- a/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/auto_project.ipf
+++ b/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/auto_project.ipf
--- a/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/auto_project_1.ipf
+++ b/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/auto_project_1.ipf
--- a/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/fuseRelaunch.cmd
+++ b/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/fuseRelaunch.cmd
-intstyle "ise" -incremental -lib "unisims_ver" -lib "unimacro_ver" -lib "xilinxcorelib_ver" -lib "secureip" -o "C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc_tb2_isim_beh.exe" -prj "C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc_tb2_beh.prj" "work.spiifc_tb2" "work.glbl" 
+-intstyle "ise" -incremental -lib "unisims_ver" -lib "unimacro_ver" -lib "xilinxcorelib_ver" -lib "secureip" -o "C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiloop_isim_beh.exe" -prj "C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiloop_beh.prj" "work.spiloop" "work.glbl" 
--- a/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/_xmsgs/pn_parser.xmsgs
+++ b/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/_xmsgs/pn_parser.xmsgs
@@ -8,7 +8,7 @@
 <!-- Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.    -->

 <messages>
-<msg type="info" file="ProjectMgmt" num="1769" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/spiloopmem.v\&quot; into library work</arg>
+<msg type="info" file="ProjectMgmt" num="1769" ><arg fmt="%s" index="1">Analyzing Verilog file \&quot;C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem.v\&quot; into library work</arg>
 </msg>

 </messages>

--- a/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem.xise
+++ b/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/ipcore_dir/buffermem.xise
@@ -16,11 +16,11 @@

  <files>
    <file xil_pn:name="buffermem.ngc" xil_pn:type="FILE_NGC">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
    </file>
    <file xil_pn:name="buffermem.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="5"/>
      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="5"/>

--- a/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/iseconfig/spiifc.projectmgr
+++ b/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/iseconfig/spiifc.projectmgr
@@ -84,7 +84,6 @@
         <ClosedNode>Implement Design/Map</ClosedNode>
         <ClosedNode>Implement Design/Place &amp; Route</ClosedNode>
         <ClosedNode>Implement Design/Translate</ClosedNode>
-         <ClosedNode>Synthesize - XST</ClosedNode>
         <ClosedNode>User Constraints</ClosedNode>
      </ClosedNodes>
      <SelectedItems>
@@ -117,13 +116,13 @@
         <ClosedNode>/spiifc - IMP C:|Users|mjlyons|workspace|vSPI|projnav|xps|pcores|spiifc_v1_00_a|hdl|vhdl|spiifc.vhd</ClosedNode>
      </ClosedNodes>
      <SelectedItems>
-         <SelectedItem>spiifc_tb2 (C:/Users/mjlyons/workspace/vSPI/test/spi_base/spiifc_tb2.v)</SelectedItem>
+         <SelectedItem>spiloop (C:/Users/mjlyons/workspace/vSPI/src/spi_base/spiloop.v)</SelectedItem>
      </SelectedItems>
      <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
-      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000133000000020000000000000000000000000200000064ffffffff000000810000000300000002000001330000000100000003000000000000000100000003</ViewHeaderState>
+      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000175000000020000000000000000000000000200000064ffffffff000000810000000300000002000001750000000100000003000000000000000100000003</ViewHeaderState>
      <UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
-      <CurrentItem>spiifc_tb2 (C:/Users/mjlyons/workspace/vSPI/test/spi_base/spiifc_tb2.v)</CurrentItem>
+      <CurrentItem>spiloop (C:/Users/mjlyons/workspace/vSPI/src/spi_base/spiloop.v)</CurrentItem>
   </ItemView>
   <ItemView engineview="BehavioralSim" sourcetype="" guiview="Process" >
      <ClosedNodes>
@@ -166,4 +165,18 @@
      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
      <CurrentItem></CurrentItem>
   </ItemView>
+   <ItemView engineview="BehavioralSim" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
+      <ClosedNodes>
+         <ClosedNodesVersion>1</ClosedNodesVersion>
+         <ClosedNode>ISim Simulator</ClosedNode>
+      </ClosedNodes>
+      <SelectedItems>
+         <SelectedItem></SelectedItem>
+      </SelectedItems>
+      <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
+      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
+      <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f8000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000</ViewHeaderState>
+      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
+      <CurrentItem></CurrentItem>
+   </ItemView>
 </Project>
--- a/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/iseconfig/spiloop.xreport
+++ b/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/iseconfig/spiloop.xreport
 <?xml version='1.0' encoding='UTF-8'?>
 <report-views version="2.0" >
 <header>
-  <DateModified>2012-03-07T19:13:42</DateModified>
+  <DateModified>2012-03-07T19:21:13</DateModified>
  <ModuleName>spiloop</ModuleName>
  <SummaryTimeStamp>2012-03-07T18:47:55</SummaryTimeStamp>
  <SavedFilePath>C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/iseconfig/spiloop.xreport</SavedFilePath>
-  <ImplementationReportsDirectory>C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav</ImplementationReportsDirectory>
+  <ImplementationReportsDirectory>C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav\</ImplementationReportsDirectory>
  <DateInitialized>2012-03-07T18:30:28</DateInitialized>
  <EnableMessageFiltering>false</EnableMessageFiltering>
 </header>

--- a/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/par_usage_statistics.html
+++ b/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/par_usage_statistics.html
 <TABLE BORDER CELLSPACING=0 WIDTH='100%'>
 <xtag-section name="ParStatistics">
 <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>Par Statistics</B></TD></TR>
-<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>32</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>141</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>141</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>128</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>5.1 sec</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>5.6 sec</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>5.8 sec</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>7.4 sec</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>7.5 sec</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>7.5 sec</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>7.5 sec</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>7.5 sec</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>7.5 sec</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>7.5 sec</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>18.0</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>11.0</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>3.3</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>14.0</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>2.0</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Total Non-vccgnd Signals</xtag-par-property-name>=<xtag-par-property-value>117</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Total Non-vccgnd Design Pins</xtag-par-property-name>=<xtag-par-property-value>398</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Total Non-vccgnd Conns</xtag-par-property-name>=<xtag-par-property-value>398</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Total Non-vccgnd Timing Constrained Conns</xtag-par-property-name>=<xtag-par-property-value>361</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Phase 1 CPU</xtag-par-property-name>=<xtag-par-property-value>5.4 sec</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Phase 2 CPU</xtag-par-property-name>=<xtag-par-property-value>6.4 sec</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Phase 3 CPU</xtag-par-property-name>=<xtag-par-property-value>6.7 sec</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Phase 4 CPU</xtag-par-property-name>=<xtag-par-property-value>8.3 sec</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Phase 5 CPU</xtag-par-property-name>=<xtag-par-property-value>8.5 sec</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Phase 6 CPU</xtag-par-property-name>=<xtag-par-property-value>8.5 sec</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Phase 7 CPU</xtag-par-property-name>=<xtag-par-property-value>8.5 sec</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Phase 8 CPU</xtag-par-property-name>=<xtag-par-property-value>8.5 sec</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Phase 9 CPU</xtag-par-property-name>=<xtag-par-property-value>8.5 sec</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>Phase 10 CPU</xtag-par-property-name>=<xtag-par-property-value>8.5 sec</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 1</xtag-par-property-name>=<xtag-par-property-value>3.0</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 2</xtag-par-property-name>=<xtag-par-property-value>7.5</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 3</xtag-par-property-name>=<xtag-par-property-value>3.3</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 4</xtag-par-property-name>=<xtag-par-property-value>4.5</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 10</xtag-par-property-name>=<xtag-par-property-value>7.6</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50</xtag-par-property-name>=<xtag-par-property-value>3.8</xtag-par-property-value></TD></TR>
 <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
 <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 500</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
 <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 5000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
 <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 20000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
 <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 50000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
 <TR><TD><xtag-par-property-name>AvgWirelenPerPin Fanout 100000</xtag-par-property-name>=<xtag-par-property-value>0.0</xtag-par-property-value></TD></TR>
-<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0025</xtag-par-property-value></TD></TR>
+<TR><TD><xtag-par-property-name>IRR Gamma</xtag-par-property-name>=<xtag-par-property-value>1.0114</xtag-par-property-value></TD></TR>
 </xtag-section>
 </TABLE>
--- a/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc.gise
+++ b/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc.gise
@@ -27,6 +27,11 @@
    <file xil_pn:fileType="FILE_NCD" xil_pn:name="spiwrap_guide.ncd" xil_pn:origination="imported"/>
  </files>

-  <transforms xmlns="http://www.xilinx.com/XMLSchema"/>
+  <transforms xmlns="http://www.xilinx.com/XMLSchema">
+    <transform xil_pn:end_ts="1331171506" xil_pn:in_ck="241267088593728842" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1331171506">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+  </transforms>

 </generated_project>
--- a/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc.xise
+++ b/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc.xise
@@ -127,18 +127,18 @@
      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="92"/>
    </file>
    <file xil_pn:name="../../../../../../test/spi_base/spiifc_tb2.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
    <file xil_pn:name="../../../../../ucf/atlys/spiwrap.ucf" xil_pn:type="FILE_UCF">
      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
    </file>
    <file xil_pn:name="ipcore_dir/spiloopmem.xco" xil_pn:type="FILE_COREGEN">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="35"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
    </file>
    <file xil_pn:name="../../../../../../src/spi_base/spiloop.v" xil_pn:type="FILE_VERILOG">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="42"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
    </file>
    <file xil_pn:name="../../../../../ucf/atlys/spiloop.ucf" xil_pn:type="FILE_UCF">
@@ -387,8 +387,8 @@
    <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
    <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
    <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/spiifc_tb2" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.spiifc_tb2" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/spiloop" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.spiloop" xil_pn:valueState="non-default"/>
    <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
    <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
@@ -406,7 +406,7 @@
    <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
    <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
    <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.spiifc_tb2" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.spiloop" xil_pn:valueState="default"/>
    <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
    <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
    <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
@@ -457,7 +457,7 @@
    <!--                                                                                  -->
    <!-- The following properties are for internal use only. These should not be modified.-->
    <!--                                                                                  -->
-    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|spiifc_tb2" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|spiloop" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_DesignName" xil_pn:value="spiifc" xil_pn:valueState="non-default"/>
    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
    <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>

--- a/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc_tb2_isim_beh.wdb
+++ b/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc_tb2_isim_beh.wdb
--- a/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiloop_guide.ncd
+++ b/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiloop_guide.ncd
 XILINX-XDB 0.1 STUB 0.1 ASCII
 XILINX-XDM V1.6
-###6200:XlxV32DM    3fff    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    940     3c0eNq1Vrtu3DAQ/Bl/AJcrPtUYSZPCRYzkB/gQSwMu4ka4f89QtqGxcClzvgWlnSH3yfVlybL/kbZks95erBvZQPEizWWJ6wHYCXiovzBTO5nLRsxiD4AUy2VrcbS18tZwMuVQxJPpFmaW65mVmMLMfmFudKYOYm7pwhxCflpiDntlLsR0zHRXZiAmJ3jEr0y1nfzUk6lKxtQzcDGmSsY0MfNqTAsxGzPrhRnIeuQzizmBSjnQZmkHhayddsTKwHYCiYrpuMqeKuJqIoAaxTWy4SlZPlCnh0JApO4M5K5PSgAF6DdKXqDk+UGtFjYGyN1oTiAY2hEpwMDdUAIBbNxRHGFQEh1FHh11RRUG6KiqDFCuKrkbPblb6C7FQsZLJ6DSnSobA56AxgAZL9QlyVBpS2SAGq4kBijAQrkqXHPPegrDU+AlURiV9ZRbtzHAk+wM7/b2W8LR1Pgz+680MHYhyJ+omjlYtGG8/hA01quEsdbFTLbJuIc71Nv6ICHNhqyLvCOGkD6v8yfjVm0K9yiDKHrM1itlMUyR5R5FTsr8PD5+35tIdq4tkuqA4ttednkvaFZMiZprhXRFbA0TH+BHMpDWxQDtkAFJubYAgb5hZxPIBmmQghOg78A79B38jn19nox9m4csEPtpxR6dbuECqoJvWh+sa1nr9CAclQLaTMtjZr6QWqHu2ZqsW7yHoW6xZOvdFZznjVxsugKCbSiccxbScVUjGsRnLx0jLmaPigV4EjCiA7ooGslRbI4+5YjpliTmFDQnpKMU+3m61e3okeXwR5AbazG/7Iy0zqGKNc3/VU/Wxaz7E+a67q9BV/wIQBNj8Ton/n1A/gXMnp7Wx4d1ZCLbarOd4+hqffkv1tFnP/dnVNisz+gmQdXNfHlFL863ZmqOWPA65mLfl/mDp8yHMNM1H9LM2XxoR0HxsM1Y8ID6I6AVlv4CUJ6QXA==
\ No newline at end of file
--- a/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiloop_isim_beh1.wdb
+++ b/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiloop_isim_beh1.wdb
--- a/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiloop_summary.html
+++ b/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiloop_summary.html
-<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
-<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
-<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
-<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
-<TD ALIGN=CENTER COLSPAN='4'><B>spiloop Project Status</B></TD></TR>
-<TR ALIGN=LEFT>
-<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
-<TD>spiifc.xise</TD>
-<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
-</TR>
-<TR ALIGN=LEFT>
-<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
-<TD>spiloop</TD>
-<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
-<TD>New</TD>
-</TR>
-<TR ALIGN=LEFT>
-<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
-<TD>xc6slx45-2csg324</TD>
-<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
-<TD>&nbsp;</TD>
-</TR>
-<TR ALIGN=LEFT>
-<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 13.2</TD>
-<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
-<TD>&nbsp;</TD>
-</TR>
-<TR ALIGN=LEFT>
-<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
-<TD>Balanced</TD>
-<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
-<TD>
-&nbsp;</TD>
-</TR>
-<TR ALIGN=LEFT>
-<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
-<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
-<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
-<TD>&nbsp;</TD>
-</TR>
-<TR ALIGN=LEFT>
-<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
-<TD>&nbsp;</TD>
-<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
-<TD>&nbsp;&nbsp;</TD>
-</TR>
-</TABLE>
-
-
-
-
-
-
-
-
-
-
-
-&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
-<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
-<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
-<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
-<TR ALIGN=LEFT><TD>Synthesis Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
-</TABLE>
-&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
-<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
-<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
-</TABLE>
-
-
-<br><center><b>Date Generated:</b> 03/07/2012 - 19:13:42</center>
-</BODY></HTML>
\ No newline at end of file
--- a/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiwrap_guide.ncd
+++ b/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiwrap_guide.ncd
--- a/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/tb_fastclock.wcfg
+++ b/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/tb_fastclock.wcfg
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc_tb_isim_beh.wdb" id="1" type="auto">
+         <top_modules>
+            <top_module name="glbl" />
+            <top_module name="spiifc_tb" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <WVObjectSize size="29" />
+   <wvobject fp_name="/spiifc_tb/SPI_MISO" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">SPI_MISO</obj_property>
+      <obj_property name="ObjectShortName">SPI_MISO</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spiifc_tb/txMemAddr" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">txMemAddr[11:0]</obj_property>
+      <obj_property name="ObjectShortName">txMemAddr[11:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spiifc_tb/txMemData" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">txMemData[7:0]</obj_property>
+      <obj_property name="ObjectShortName">txMemData[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spiifc_tb/rcMemAddr" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">rcMemAddr[11:0]</obj_property>
+      <obj_property name="ObjectShortName">rcMemAddr[11:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spiifc_tb/rcMemData" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">rcMemData[7:0]</obj_property>
+      <obj_property name="ObjectShortName">rcMemData[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spiifc_tb/rcMemWE" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">rcMemWE</obj_property>
+      <obj_property name="ObjectShortName">rcMemWE</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spiifc_tb/debug_out" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">debug_out[7:0]</obj_property>
+      <obj_property name="ObjectShortName">debug_out[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spiifc_tb/Reset" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">Reset</obj_property>
+      <obj_property name="ObjectShortName">Reset</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spiifc_tb/SysClk" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">SysClk</obj_property>
+      <obj_property name="ObjectShortName">SysClk</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spiifc_tb/SPI_CLK" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">SPI_CLK</obj_property>
+      <obj_property name="ObjectShortName">SPI_CLK</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spiifc_tb/SPI_MOSI" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">SPI_MOSI</obj_property>
+      <obj_property name="ObjectShortName">SPI_MOSI</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spiifc_tb/SPI_SS" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">SPI_SS</obj_property>
+      <obj_property name="ObjectShortName">SPI_SS</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spiifc_tb/SPI_CLK_en" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">SPI_CLK_en</obj_property>
+      <obj_property name="ObjectShortName">SPI_CLK_en</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spiifc_tb/fdRcBytes" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">fdRcBytes[31:0]</obj_property>
+      <obj_property name="ObjectShortName">fdRcBytes[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spiifc_tb/fdTxBytes" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">fdTxBytes[31:0]</obj_property>
+      <obj_property name="ObjectShortName">fdTxBytes[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spiifc_tb/dummy" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">dummy[31:0]</obj_property>
+      <obj_property name="ObjectShortName">dummy[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spiifc_tb/currRcByte" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">currRcByte[31:0]</obj_property>
+      <obj_property name="ObjectShortName">currRcByte[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spiifc_tb/rcBytesNotEmpty" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">rcBytesNotEmpty[31:0]</obj_property>
+      <obj_property name="ObjectShortName">rcBytesNotEmpty[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spiifc_tb/rcBytesStr" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">rcBytesStr[80:1]</obj_property>
+      <obj_property name="ObjectShortName">rcBytesStr[80:1]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spiifc_tb/uut/packetStart" type="logic" db_ref_id="1">
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="ElementShortName">packetStart</obj_property>
+      <obj_property name="ObjectShortName">packetStart</obj_property>
+      <obj_property name="label">packetStart</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spiifc_tb/uut/validSpiBit" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">validSpiBit</obj_property>
+      <obj_property name="ObjectShortName">validSpiBit</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spiifc_tb/uut/rcByteValid" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">rcByteValid</obj_property>
+      <obj_property name="ObjectShortName">rcByteValid</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spiifc_tb/uut/state" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">state[7:0]</obj_property>
+      <obj_property name="ObjectShortName">state[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spiifc_tb/uut/state_reg" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">state_reg[7:0]</obj_property>
+      <obj_property name="ObjectShortName">state_reg[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spiifc_tb/uut/rcByteValid" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">rcByteValid</obj_property>
+      <obj_property name="ObjectShortName">rcByteValid</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spiifc_tb/uut/rcByte" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">rcByte[7:0]</obj_property>
+      <obj_property name="ObjectShortName">rcByte[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spiifc_tb/uut/txBitIndex_reg" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">txBitIndex_reg[2:0]</obj_property>
+      <obj_property name="ObjectShortName">txBitIndex_reg[2:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spiifc_tb/uut/txMemAddr" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">txMemAddr[11:0]</obj_property>
+      <obj_property name="ObjectShortName">txMemAddr[11:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/spiifc_tb/uut/txMemData" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">txMemData[7:0]</obj_property>
+      <obj_property name="ObjectShortName">txMemData[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+</wave_config>
--- a/src/spi_base/spiifc.v
+++ b/src/spi_base/spiifc.v
@@ -85,15 +85,19 @@ reg             [7:0] rcByte_reg;     // Register backing 'rcByte'
 reg             [2:0] rcBitIndex_reg; // Register backing 'rcBitIndex'
 reg    [AddrBits-1:0] rcMemAddr_reg;  // Byte addr to write MOSI data to
 reg             [7:0] debug_reg;      // register backing debug_out signal
+reg             [2:0] txBitIndex_reg; // Register backing txBitIndex
+reg    [AddrBits-1:0] txMemAddr_reg;  // Register backing txAddr
 //
 // Wires
 //
 wire                  risingSpiClk;   // Did the SPI_CLK rise since last SysClk cycle?
 wire                  validSpiBit;    // Are the SPI MOSI/MISO bits new and valid?
-reg                   state;          // Current state in the module's state machine (always @* effectively wire)
+reg             [7:0] state;          // Current state in the module's state machine (always @* effectively wire)
 wire                  rcByteValid;    // rcByte is valid and new
 wire            [7:0] rcByte;         // Byte received from master
 wire            [2:0] rcBitIndex;     // Bit of rcByte to write to next
+reg             [2:0] txBitIndex;     // bit of txByte to send to master next
+reg    [AddrBits-1:0] txMemAddr_oreg; // Wirereg piped to txMemAddr output

 // Save buffered SPI inputs
 always @(posedge SysClk) begin
@@ -156,8 +160,29 @@ always @(posedge SysClk) begin
 end

 // Outgoing MISO data buffer management
-// TODO: implement
-assign SPI_MISO = 1'b0;
+always @(*) begin
+  if (Reset || (state == `STATE_GET_CMD && rcByteValid && rcByte == `CMD_WRITE_START)) begin
+    txBitIndex <= 3'd7;
+    txMemAddr_oreg <= 0;
+  end else begin
+    txBitIndex <= txBitIndex_reg;
+    if (state == `STATE_WRITING && validSpiBit && txBitIndex == 0) begin
+      txMemAddr_oreg <= txMemAddr_reg + 1;
+    end else begin
+      txMemAddr_oreg <= txMemAddr_reg;
+    end
+  end
+end
+always @(posedge SysClk) begin
+  txMemAddr_reg <= txMemAddr;
+  if (validSpiBit && state == `STATE_WRITING) begin
+    txBitIndex_reg <= (txBitIndex == 0 ? 7 : txBitIndex - 1);
+  end else begin
+    txBitIndex_reg <= txBitIndex;
+  end
+end
+assign txMemAddr = txMemAddr_oreg;
+assign SPI_MISO = txMemData[txBitIndex];

 // State machine
 always @(*) begin

--- a/src/spi_base/spiloop.v
+++ b/src/spi_base/spiloop.v
@@ -36,12 +36,12 @@ wire [7:0]  rcMemData;
 wire        rcMemWE;

 spiloopmem your_instance_name (
-  .clka(spi_clk), // input clka
+  .clka(SysClk), // input clka
  .ena(1'b1), // input ena
  .wea(rcMemWE), // input [0 : 0] wea
  .addra(rcMemAddr), // input [11 : 0] addra
  .dina(rcMemData), // input [7 : 0] dina
-  .clkb(spi_clk), // input clkb
+  .clkb(SysClk), // input clkb
  .enb(1'b1), // input enb
  .addrb(txMemAddr), // input [11 : 0] addrb
  .doutb(txMemData) // output [7 : 0] doutb
@@ -62,6 +62,7 @@ spiifc mySpiIfc (
  .debug_out(debug_out)
 );

-assign leds = debug_out ;
+//assign leds = debug_out ;
+assign leds = txMemData;

 endmodule
--- a/src/spi_base/spiwrap.v
+++ b/src/spi_base/spiwrap.v
@@ -60,7 +60,7 @@ always @(posedge SysClk) begin
 end

 buffermem spiMemTx (
-  .clka(spi_clk), // input clkb
+  .clka(SysClk), // input clkb
  .ena(1'b1), // input enb
  .wea(1'b0), // input [0 : 0] web
  .addra(spi_addr), // input [11 : 0] addrb
@@ -80,7 +80,7 @@ wire [ 7:0] spi_rcMem_data;
 wire [ 7:0] debug_out;
 wire [ 7:0] spi_rcMem_doutb_dummy;
 buffermem spiMemRc (
-  .clka(spi_clk),
+  .clka(SysClk),
  .ena(1'b1),
  .wea(spi_rcMem_we),
  .addra(spi_rcMem_addr),
@@ -108,6 +108,6 @@ spiifc mySpiIfc (
  .debug_out(debug_out)
 );

-assign leds = /* rcMem_douta[7:0] */ debug_out ;
+assign leds =  rcMem_douta[7:0] /* debug_out */;

 endmodule