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Commit 0a8efd71 authored by Michael Lyons's avatar Michael Lyons
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Cleaning up some verilog src and tbs

parent beb5a7fe
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Showing with 9 additions and 256 deletions
src/spi_base/spiifc.v
View file @ 0a8efd71
...@@ -218,9 +218,6 @@ module spiifc( ...@@ -218,9 +218,6 @@ module spiifc(
rcMemAddrNext <= rcMemAddr + 1; rcMemAddrNext <= rcMemAddr + 1;
rcMemWEReg <= 1; rcMemWEReg <= 1;
// end else if (`STATE_WRITING == state) begin
// txBitAddr <= 3'd7;
// stateReg <= `STATE_WRITING;
end end
end else begin end else begin
...@@ -232,251 +229,4 @@ module spiifc( ...@@ -232,251 +229,4 @@ module spiifc(
end // Reset/Reset' end // Reset/Reset'
end end
/*
reg rcByte_valid;
wire rcClockBridgeEmpty;
wire readRcByte;
assign getRcByte = ~rcClockBridgeEmpty;
wire rcClockBridgeReadValid;
wire rcClockBridgeFull;
wire [7:0] rcByte;
clock_bridge recvClockBridge (
.rst(Reset), // input rst
.wr_clk(~SPI_CLK), // input wr_clk
.rd_clk(SysClk), // input rd_clk
.din(SPI_MOSI), // input [0 : 0] din
.wr_en(~SPI_SS), // input wr_en
.rd_en(getRcByte), // input rd_en
.dout(rcByte), // output [7 : 0] dout
.full(rcClockBridgeFull), // output full
.empty(rcClockBridgeEmpty), // output empty
.valid(rcClockBridgeReadValid) // output valid
);
always @(posedge SysClk) begin
rcByte_valid <= getRcByte;
end
wire txCmdClkBridgeEmpty;
wire txCmdClkBridgeFull;
wire [7:0] txCmd;
wire txCmdValid;
assign txCmdValid = ~txCmdClkBridgeEmpty;
wire postTxCmd;
assign postTxCmd =
fifo_8bit_to_8bit txCmdClkBridge(
.rst(Reset), // input rst
.wr_clk(SysClk), // input wr_clk
.rd_clk(SPI_CLK), // input rd_clk
.din(din), // input [7 : 0] din
.wr_en(post), // input wr_en
.rd_en(txCmdValid), // input rd_en
.dout(txCmd), // output [7 : 0] dout
.full(txCmdClkBridgeFull), // output full
.empty(txCmdClkBridgeEmpty) // output empty
);
//
// TRANSMIT: FPGA TO PC
//
assign SPI_MISO = txMemData[bitIndex];
reg [2:0] bitIndex;
reg [AddrBits-1:0] byteAddr;
assign txMemAddr = byteAddr;
reg [7:0] debug_reg;
assign debug_out = debug_reg;
initial begin
debug_reg <= 8'h00;
//rcState <= 0;
end
//
// Clocked logic
//
always @(posedge SPI_CLK) begin
if (Reset) begin
bitIndex <= 3'd0;
byteAddr <= 0;
end else if (SPI_SS == 1'b0) begin
bitIndex <= bitIndex - 3'd1;
if (bitIndex == 3'd1) begin
byteAddr <= byteAddr + 1;
end
end
end
//
// RECEIVE: PC TO FPGA
//
// Detect start of receive
reg ss_prev;
wire ss_negedge;
always @(posedge SysClk) begin
ss_prev <= SPI_SS;
end
assign ss_negedge = (ss_prev == 1'b1 && SPI_SS == 1'b0 ? 1'b1 : 1'b0);
`define RC_MODE_GET_STATUS 8'd0
`define RC_MODE_GET_BUFFER 8'd1
`define RC_MODE_PUT_BUFFER 8'd2
reg [7:0] rcMode;
`define RC_STATE_CMD 8'd0
`define RC_STATE_SIZE 8'd1
`define RC_STATE_PAYLOAD 8'd2
reg [7:0] rcState;
reg [31:0] rcByteCount;
reg [31:0] rcByteSize;
reg [7:0] rcMemData_reg;
reg [AddrBits-1:0] rcMemAddr_reg;
reg rcMemWE_reg;
assign rcMemData = rcMemData_reg;
assign rcMemAddr = rcMemAddr_reg;
assign rcMemWE = rcMemWE_reg;
always @(posedge SysClk) begin
// // About to receive
// if (ss_negedge) begin
// rcBitIndex <= 3'd7;
// rcState <= `RC_STATE_CMD;
//
// debug_reg[0] <= 1;
// end
//
// // Receiving
// if (receiving) begin
// rcByte[rcBitIndex] <= SPI_MOSI;
// rcBitIndex <= rcBitIndex - 3'd1;
// end
// rcByte_valid <= (receiving && rcBitIndex == 3'd0 ? 1'b1 : 1'b0);
// Handle the complete incoming byte
if (rcByte_valid) begin
debug_reg[7:4] <= rcByte[3:0];
// First byte: the command
if (`RC_STATE_CMD == rcState || ss_negedge) begin
// Disable writing to the read buffer (will be left on if the prev
// cycle was writing to it)
rcMemWE_reg <= 1'b0;
debug_reg[0] <= 1;
// Decode the SPI command
case (rcByte)
`RC_MODE_GET_STATUS: begin end // no status yet
`RC_MODE_GET_BUFFER: begin rcMode <= `RC_MODE_GET_BUFFER; rcState <= `RC_STATE_SIZE; end
`RC_MODE_PUT_BUFFER: begin rcMode <= `RC_MODE_PUT_BUFFER; rcState <= `RC_STATE_SIZE; end
endcase
// Initialize counters
rcByteCount <= 32'd0;
rcByteSize <= 32'd0;
end
// Record size (in bytes) of payload
if (`RC_STATE_SIZE == rcState) begin
debug_reg[1] <= 1;
case (rcByteCount)
32'd0: begin rcByteSize[31:24] <= rcByte; rcByteCount <= 32'd1; end
32'd1: begin rcByteSize[23:16] <= rcByte; rcByteCount <= 32'd2; end
32'd2: begin rcByteSize[15: 8] <= rcByte; rcByteCount <= 32'd3; end
32'd3: begin
rcByteSize[ 7: 0] <= rcByte;
rcByteCount <= 32'd0;
rcState <= `RC_STATE_PAYLOAD;
rcByteCount <= 32'd0;
if (`RC_MODE_GET_BUFFER == rcMode) begin
// TODO: want reset tx byte addr here probably
end
end
endcase
end
// The payload
if (rcState == `RC_STATE_PAYLOAD) begin
debug_reg[2] <= 1;
case (rcMode)
`RC_MODE_GET_BUFFER: begin
// IGNORE EVERYTHING SO STUFF CAN BE READ OUT
end
`RC_MODE_PUT_BUFFER: begin
//debug_reg[4] <= 1;
rcMemWE_reg <= 1'b1;
rcMemData_reg <= rcByte;
rcMemAddr_reg <= rcByteCount[AddrBits-1:0];
end
endcase
if (rcByteCount == rcByteSize - 1) begin
rcState <= `RC_STATE_CMD;
//debug_reg[5] <= 1;
end else begin
rcByteCount <= rcByteCount + 32'd1;
end
end
end
else begin // not valid byte
if (ss_negedge) begin
rcState <= `RC_STATE_CMD;
end
end
end
//reg [7:0] rcByteReg;
//wire [7:0] rcByte;
//assign rcByte = {rcByteReg[7:1], (SPI_SS == 1'b0 && bitIndex ==
// //
// // Receive (GPU to SPI)
// //
// reg SPI_SS_prev_cycle;
//
// // This is the register backing rcByteId. It is always one cycle
// // behind the true value of rcByteId, which we have to do a little
// // work to get instantaneously correct using wire logic.
// reg [31:0] rcByteIdPrev;
// wire [31:0] rcByteId;
// assign rcByteId = (SPI_SS_prev_cycle == 1 && SPI_SS == 0 ? 32'd0 : 32'd1 + rcByteIdPrev);
//
// // 1 if we're receiving from GPC, 0 if not.
// wire isRecv;
// assign isRecv = ~SPI_SS;
//
// // Bits to Byte aggregator
// reg [2:0] rcBitId;
// reg [7:0] rcByte;
//
//
// reg [31:0] rcSizeBytes;
//
// always @(posedge SPI_CLK) begin
// if (1 == isRecv) begin
// case (rcByteId)
// 0: rcSizeBytes[ 7: 0] <=
// end
//
// // Update registers for next cycle
// SPI_SS_prev_cycle <= SPI_SS;
// rcByteId <= rcByteIdPrev;
// end
*/
endmodule endmodule
src/spi_base/spiwrap.v
View file @ 0a8efd71
...@@ -42,9 +42,7 @@ always @(posedge SysClk) begin ...@@ -42,9 +42,7 @@ always @(posedge SysClk) begin
if (Reset) begin if (Reset) begin
initMem <= 1'b1; initMem <= 1'b1;
initMemAddr <= 10'h000; initMemAddr <= 10'h000;
//initMemData <= 32'hFF00_FF00; initMemData <= 32'h5A6C_C6A5;
initMemData <= 32'h5A6C_C6A5; /*32'h55CC_55CC*/;
end else begin end else begin
if (initMem == 1'b1) begin if (initMem == 1'b1) begin
// Turn off init mem mode if formatted memory // Turn off init mem mode if formatted memory
...@@ -54,7 +52,6 @@ always @(posedge SysClk) begin ...@@ -54,7 +52,6 @@ always @(posedge SysClk) begin
// Increment init mem addr/data // Increment init mem addr/data
initMemAddr <= initMemAddr + 10'h001; initMemAddr <= initMemAddr + 10'h001;
//initMemData <= ~initMemData;
end end
end end
end end
......
test/spi_base/spiifc_tb2.v → test/spi_base/spiifc_tb_rc.v
View file @ 0a8efd71
...@@ -20,6 +20,9 @@ ...@@ -20,6 +20,9 @@
// Revision 0.01 - File Created // Revision 0.01 - File Created
// Additional Comments: // Additional Comments:
// //
// This testbench tests the spiifc module's ability to receive and buffer
// data sent from the master, such as the Cheetah SPI/USB adapter
//
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
module spiifc_tb2; module spiifc_tb2;
...@@ -115,7 +118,7 @@ module spiifc_tb2; ...@@ -115,7 +118,7 @@ module spiifc_tb2;
// Add stimulus here // Add stimulus here
SPI_SS = 0; SPI_SS = 0;
// For each byte, transmit its bits // For each byte, transmit its bits
fdRcBytes = $fopen("rc-bytes.txt", "r"); fdRcBytes = $fopen("rc-bytes-rc-test.txt", "r");
rcBytesNotEmpty = 1; rcBytesNotEmpty = 1;
while (rcBytesNotEmpty) begin while (rcBytesNotEmpty) begin
rcBytesNotEmpty = $fgets(rcBytesStr, fdRcBytes); rcBytesNotEmpty = $fgets(rcBytesStr, fdRcBytes);
......
test/spi_base/spiifc_tb.v → test/spi_base/spiifc_tb_tx.v
View file @ 0a8efd71
...@@ -20,9 +20,12 @@ ...@@ -20,9 +20,12 @@
// Revision 0.01 - File Created // Revision 0.01 - File Created
// Additional Comments: // Additional Comments:
// //
// This testbench tests sending data from the SPI IFC module to a
// master device, such as the Cheetah SPI/USB adapter.
//
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
module spiifc_tb; module spiifc_tb_tx;
// Inputs // Inputs
reg Reset; reg Reset;
......
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