Skip to content

V
vSPI
Commit 05b98f2c authored by Mike Lyons's avatar Mike Lyons
Browse files
Options

Checking in ISE/XPS/XSDK project files

parent 6bc46422
Hide whitespace changes
Inline Side-by-side
Showing with 374 additions and 2595 deletions
projnav/xps/SDK/SDK_Export/hw/system_bd.bmm
View file @ 05b98f2c
......@@ -21,38 +21,38 @@ ADDRESS_MAP microblaze_0 MICROBLAZE 100
ADDRESS_SPACE lmb_bram_combined RAMB16 [0x00000000:0x0000FFFF]
BUS_BLOCK
lmb_bram/lmb_bram/ramb16bwer_0 [31:31] INPUT = lmb_bram_combined_0.mem PLACED = X2Y26;
lmb_bram/lmb_bram/ramb16bwer_1 [30:30] INPUT = lmb_bram_combined_1.mem PLACED = X1Y24;
lmb_bram/lmb_bram/ramb16bwer_2 [29:29] INPUT = lmb_bram_combined_2.mem PLACED = X1Y36;
lmb_bram/lmb_bram/ramb16bwer_3 [28:28] INPUT = lmb_bram_combined_3.mem PLACED = X1Y22;
lmb_bram/lmb_bram/ramb16bwer_4 [27:27] INPUT = lmb_bram_combined_4.mem PLACED = X2Y24;
lmb_bram/lmb_bram/ramb16bwer_5 [26:26] INPUT = lmb_bram_combined_5.mem PLACED = X2Y36;
lmb_bram/lmb_bram/ramb16bwer_6 [25:25] INPUT = lmb_bram_combined_6.mem PLACED = X1Y26;
lmb_bram/lmb_bram/ramb16bwer_7 [24:24] INPUT = lmb_bram_combined_7.mem PLACED = X1Y34;
lmb_bram/lmb_bram/ramb16bwer_8 [23:23] INPUT = lmb_bram_combined_8.mem PLACED = X0Y32;
lmb_bram/lmb_bram/ramb16bwer_9 [22:22] INPUT = lmb_bram_combined_9.mem PLACED = X1Y28;
lmb_bram/lmb_bram/ramb16bwer_10 [21:21] INPUT = lmb_bram_combined_10.mem PLACED = X1Y30;
lmb_bram/lmb_bram/ramb16bwer_11 [20:20] INPUT = lmb_bram_combined_11.mem PLACED = X1Y32;
lmb_bram/lmb_bram/ramb16bwer_12 [19:19] INPUT = lmb_bram_combined_12.mem PLACED = X1Y40;
lmb_bram/lmb_bram/ramb16bwer_13 [18:18] INPUT = lmb_bram_combined_13.mem PLACED = X0Y36;
lmb_bram/lmb_bram/ramb16bwer_14 [17:17] INPUT = lmb_bram_combined_14.mem PLACED = X0Y34;
lmb_bram/lmb_bram/ramb16bwer_15 [16:16] INPUT = lmb_bram_combined_15.mem PLACED = X2Y40;
lmb_bram/lmb_bram/ramb16bwer_16 [15:15] INPUT = lmb_bram_combined_16.mem PLACED = X2Y30;
lmb_bram/lmb_bram/ramb16bwer_17 [14:14] INPUT = lmb_bram_combined_17.mem PLACED = X2Y34;
lmb_bram/lmb_bram/ramb16bwer_18 [13:13] INPUT = lmb_bram_combined_18.mem PLACED = X2Y32;
lmb_bram/lmb_bram/ramb16bwer_19 [12:12] INPUT = lmb_bram_combined_19.mem PLACED = X2Y28;
lmb_bram/lmb_bram/ramb16bwer_20 [11:11] INPUT = lmb_bram_combined_20.mem PLACED = X1Y38;
lmb_bram/lmb_bram/ramb16bwer_21 [10:10] INPUT = lmb_bram_combined_21.mem PLACED = X2Y52;
lmb_bram/lmb_bram/ramb16bwer_22 [9:9] INPUT = lmb_bram_combined_22.mem PLACED = X2Y50;
lmb_bram/lmb_bram/ramb16bwer_23 [8:8] INPUT = lmb_bram_combined_23.mem PLACED = X2Y48;
lmb_bram/lmb_bram/ramb16bwer_24 [7:7] INPUT = lmb_bram_combined_24.mem PLACED = X2Y42;
lmb_bram/lmb_bram/ramb16bwer_25 [6:6] INPUT = lmb_bram_combined_25.mem PLACED = X3Y34;
lmb_bram/lmb_bram/ramb16bwer_26 [5:5] INPUT = lmb_bram_combined_26.mem PLACED = X3Y32;
lmb_bram/lmb_bram/ramb16bwer_27 [4:4] INPUT = lmb_bram_combined_27.mem PLACED = X2Y44;
lmb_bram/lmb_bram/ramb16bwer_28 [3:3] INPUT = lmb_bram_combined_28.mem PLACED = X2Y38;
lmb_bram/lmb_bram/ramb16bwer_0 [31:31] INPUT = lmb_bram_combined_0.mem PLACED = X3Y24;
lmb_bram/lmb_bram/ramb16bwer_1 [30:30] INPUT = lmb_bram_combined_1.mem PLACED = X2Y26;
lmb_bram/lmb_bram/ramb16bwer_2 [29:29] INPUT = lmb_bram_combined_2.mem PLACED = X3Y26;
lmb_bram/lmb_bram/ramb16bwer_3 [28:28] INPUT = lmb_bram_combined_3.mem PLACED = X3Y22;
lmb_bram/lmb_bram/ramb16bwer_4 [27:27] INPUT = lmb_bram_combined_4.mem PLACED = X3Y30;
lmb_bram/lmb_bram/ramb16bwer_5 [26:26] INPUT = lmb_bram_combined_5.mem PLACED = X2Y28;
lmb_bram/lmb_bram/ramb16bwer_6 [25:25] INPUT = lmb_bram_combined_6.mem PLACED = X2Y30;
lmb_bram/lmb_bram/ramb16bwer_7 [24:24] INPUT = lmb_bram_combined_7.mem PLACED = X3Y32;
lmb_bram/lmb_bram/ramb16bwer_8 [23:23] INPUT = lmb_bram_combined_8.mem PLACED = X1Y34;
lmb_bram/lmb_bram/ramb16bwer_9 [22:22] INPUT = lmb_bram_combined_9.mem PLACED = X2Y52;
lmb_bram/lmb_bram/ramb16bwer_10 [21:21] INPUT = lmb_bram_combined_10.mem PLACED = X2Y50;
lmb_bram/lmb_bram/ramb16bwer_11 [20:20] INPUT = lmb_bram_combined_11.mem PLACED = X2Y48;
lmb_bram/lmb_bram/ramb16bwer_12 [19:19] INPUT = lmb_bram_combined_12.mem PLACED = X2Y46;
lmb_bram/lmb_bram/ramb16bwer_13 [18:18] INPUT = lmb_bram_combined_13.mem PLACED = X2Y32;
lmb_bram/lmb_bram/ramb16bwer_14 [17:17] INPUT = lmb_bram_combined_14.mem PLACED = X1Y30;
lmb_bram/lmb_bram/ramb16bwer_15 [16:16] INPUT = lmb_bram_combined_15.mem PLACED = X1Y32;
lmb_bram/lmb_bram/ramb16bwer_16 [15:15] INPUT = lmb_bram_combined_16.mem PLACED = X2Y18;
lmb_bram/lmb_bram/ramb16bwer_17 [14:14] INPUT = lmb_bram_combined_17.mem PLACED = X2Y20;
lmb_bram/lmb_bram/ramb16bwer_18 [13:13] INPUT = lmb_bram_combined_18.mem PLACED = X2Y14;
lmb_bram/lmb_bram/ramb16bwer_19 [12:12] INPUT = lmb_bram_combined_19.mem PLACED = X2Y16;
lmb_bram/lmb_bram/ramb16bwer_20 [11:11] INPUT = lmb_bram_combined_20.mem PLACED = X2Y44;
lmb_bram/lmb_bram/ramb16bwer_21 [10:10] INPUT = lmb_bram_combined_21.mem PLACED = X2Y42;
lmb_bram/lmb_bram/ramb16bwer_22 [9:9] INPUT = lmb_bram_combined_22.mem PLACED = X2Y38;
lmb_bram/lmb_bram/ramb16bwer_23 [8:8] INPUT = lmb_bram_combined_23.mem PLACED = X2Y40;
lmb_bram/lmb_bram/ramb16bwer_24 [7:7] INPUT = lmb_bram_combined_24.mem PLACED = X2Y24;
lmb_bram/lmb_bram/ramb16bwer_25 [6:6] INPUT = lmb_bram_combined_25.mem PLACED = X1Y28;
lmb_bram/lmb_bram/ramb16bwer_26 [5:5] INPUT = lmb_bram_combined_26.mem PLACED = X2Y22;
lmb_bram/lmb_bram/ramb16bwer_27 [4:4] INPUT = lmb_bram_combined_27.mem PLACED = X3Y28;
lmb_bram/lmb_bram/ramb16bwer_28 [3:3] INPUT = lmb_bram_combined_28.mem PLACED = X3Y34;
lmb_bram/lmb_bram/ramb16bwer_29 [2:2] INPUT = lmb_bram_combined_29.mem PLACED = X3Y36;
lmb_bram/lmb_bram/ramb16bwer_30 [1:1] INPUT = lmb_bram_combined_30.mem PLACED = X3Y38;
lmb_bram/lmb_bram/ramb16bwer_31 [0:0] INPUT = lmb_bram_combined_31.mem PLACED = X2Y46;
lmb_bram/lmb_bram/ramb16bwer_30 [1:1] INPUT = lmb_bram_combined_30.mem PLACED = X2Y34;
lmb_bram/lmb_bram/ramb16bwer_31 [0:0] INPUT = lmb_bram_combined_31.mem PLACED = X2Y36;
END_BUS_BLOCK;
END_ADDRESS_SPACE;
......
projnav/xps/SDK/SDK_Workspace/xps_hw_platform/system_bd.bmm
View file @ 05b98f2c
......@@ -21,38 +21,38 @@ ADDRESS_MAP microblaze_0 MICROBLAZE 100
ADDRESS_SPACE lmb_bram_combined RAMB16 [0x00000000:0x0000FFFF]
BUS_BLOCK
lmb_bram/lmb_bram/ramb16bwer_0 [31:31] INPUT = lmb_bram_combined_0.mem PLACED = X2Y26;
lmb_bram/lmb_bram/ramb16bwer_1 [30:30] INPUT = lmb_bram_combined_1.mem PLACED = X1Y24;
lmb_bram/lmb_bram/ramb16bwer_2 [29:29] INPUT = lmb_bram_combined_2.mem PLACED = X1Y36;
lmb_bram/lmb_bram/ramb16bwer_3 [28:28] INPUT = lmb_bram_combined_3.mem PLACED = X1Y22;
lmb_bram/lmb_bram/ramb16bwer_4 [27:27] INPUT = lmb_bram_combined_4.mem PLACED = X2Y24;
lmb_bram/lmb_bram/ramb16bwer_5 [26:26] INPUT = lmb_bram_combined_5.mem PLACED = X2Y36;
lmb_bram/lmb_bram/ramb16bwer_6 [25:25] INPUT = lmb_bram_combined_6.mem PLACED = X1Y26;
lmb_bram/lmb_bram/ramb16bwer_7 [24:24] INPUT = lmb_bram_combined_7.mem PLACED = X1Y34;
lmb_bram/lmb_bram/ramb16bwer_8 [23:23] INPUT = lmb_bram_combined_8.mem PLACED = X0Y32;
lmb_bram/lmb_bram/ramb16bwer_9 [22:22] INPUT = lmb_bram_combined_9.mem PLACED = X1Y28;
lmb_bram/lmb_bram/ramb16bwer_10 [21:21] INPUT = lmb_bram_combined_10.mem PLACED = X1Y30;
lmb_bram/lmb_bram/ramb16bwer_11 [20:20] INPUT = lmb_bram_combined_11.mem PLACED = X1Y32;
lmb_bram/lmb_bram/ramb16bwer_12 [19:19] INPUT = lmb_bram_combined_12.mem PLACED = X1Y40;
lmb_bram/lmb_bram/ramb16bwer_13 [18:18] INPUT = lmb_bram_combined_13.mem PLACED = X0Y36;
lmb_bram/lmb_bram/ramb16bwer_14 [17:17] INPUT = lmb_bram_combined_14.mem PLACED = X0Y34;
lmb_bram/lmb_bram/ramb16bwer_15 [16:16] INPUT = lmb_bram_combined_15.mem PLACED = X2Y40;
lmb_bram/lmb_bram/ramb16bwer_16 [15:15] INPUT = lmb_bram_combined_16.mem PLACED = X2Y30;
lmb_bram/lmb_bram/ramb16bwer_17 [14:14] INPUT = lmb_bram_combined_17.mem PLACED = X2Y34;
lmb_bram/lmb_bram/ramb16bwer_18 [13:13] INPUT = lmb_bram_combined_18.mem PLACED = X2Y32;
lmb_bram/lmb_bram/ramb16bwer_19 [12:12] INPUT = lmb_bram_combined_19.mem PLACED = X2Y28;
lmb_bram/lmb_bram/ramb16bwer_20 [11:11] INPUT = lmb_bram_combined_20.mem PLACED = X1Y38;
lmb_bram/lmb_bram/ramb16bwer_21 [10:10] INPUT = lmb_bram_combined_21.mem PLACED = X2Y52;
lmb_bram/lmb_bram/ramb16bwer_22 [9:9] INPUT = lmb_bram_combined_22.mem PLACED = X2Y50;
lmb_bram/lmb_bram/ramb16bwer_23 [8:8] INPUT = lmb_bram_combined_23.mem PLACED = X2Y48;
lmb_bram/lmb_bram/ramb16bwer_24 [7:7] INPUT = lmb_bram_combined_24.mem PLACED = X2Y42;
lmb_bram/lmb_bram/ramb16bwer_25 [6:6] INPUT = lmb_bram_combined_25.mem PLACED = X3Y34;
lmb_bram/lmb_bram/ramb16bwer_26 [5:5] INPUT = lmb_bram_combined_26.mem PLACED = X3Y32;
lmb_bram/lmb_bram/ramb16bwer_27 [4:4] INPUT = lmb_bram_combined_27.mem PLACED = X2Y44;
lmb_bram/lmb_bram/ramb16bwer_28 [3:3] INPUT = lmb_bram_combined_28.mem PLACED = X2Y38;
lmb_bram/lmb_bram/ramb16bwer_0 [31:31] INPUT = lmb_bram_combined_0.mem PLACED = X3Y24;
lmb_bram/lmb_bram/ramb16bwer_1 [30:30] INPUT = lmb_bram_combined_1.mem PLACED = X2Y26;
lmb_bram/lmb_bram/ramb16bwer_2 [29:29] INPUT = lmb_bram_combined_2.mem PLACED = X3Y26;
lmb_bram/lmb_bram/ramb16bwer_3 [28:28] INPUT = lmb_bram_combined_3.mem PLACED = X3Y22;
lmb_bram/lmb_bram/ramb16bwer_4 [27:27] INPUT = lmb_bram_combined_4.mem PLACED = X3Y30;
lmb_bram/lmb_bram/ramb16bwer_5 [26:26] INPUT = lmb_bram_combined_5.mem PLACED = X2Y28;
lmb_bram/lmb_bram/ramb16bwer_6 [25:25] INPUT = lmb_bram_combined_6.mem PLACED = X2Y30;
lmb_bram/lmb_bram/ramb16bwer_7 [24:24] INPUT = lmb_bram_combined_7.mem PLACED = X3Y32;
lmb_bram/lmb_bram/ramb16bwer_8 [23:23] INPUT = lmb_bram_combined_8.mem PLACED = X1Y34;
lmb_bram/lmb_bram/ramb16bwer_9 [22:22] INPUT = lmb_bram_combined_9.mem PLACED = X2Y52;
lmb_bram/lmb_bram/ramb16bwer_10 [21:21] INPUT = lmb_bram_combined_10.mem PLACED = X2Y50;
lmb_bram/lmb_bram/ramb16bwer_11 [20:20] INPUT = lmb_bram_combined_11.mem PLACED = X2Y48;
lmb_bram/lmb_bram/ramb16bwer_12 [19:19] INPUT = lmb_bram_combined_12.mem PLACED = X2Y46;
lmb_bram/lmb_bram/ramb16bwer_13 [18:18] INPUT = lmb_bram_combined_13.mem PLACED = X2Y32;
lmb_bram/lmb_bram/ramb16bwer_14 [17:17] INPUT = lmb_bram_combined_14.mem PLACED = X1Y30;
lmb_bram/lmb_bram/ramb16bwer_15 [16:16] INPUT = lmb_bram_combined_15.mem PLACED = X1Y32;
lmb_bram/lmb_bram/ramb16bwer_16 [15:15] INPUT = lmb_bram_combined_16.mem PLACED = X2Y18;
lmb_bram/lmb_bram/ramb16bwer_17 [14:14] INPUT = lmb_bram_combined_17.mem PLACED = X2Y20;
lmb_bram/lmb_bram/ramb16bwer_18 [13:13] INPUT = lmb_bram_combined_18.mem PLACED = X2Y14;
lmb_bram/lmb_bram/ramb16bwer_19 [12:12] INPUT = lmb_bram_combined_19.mem PLACED = X2Y16;
lmb_bram/lmb_bram/ramb16bwer_20 [11:11] INPUT = lmb_bram_combined_20.mem PLACED = X2Y44;
lmb_bram/lmb_bram/ramb16bwer_21 [10:10] INPUT = lmb_bram_combined_21.mem PLACED = X2Y42;
lmb_bram/lmb_bram/ramb16bwer_22 [9:9] INPUT = lmb_bram_combined_22.mem PLACED = X2Y38;
lmb_bram/lmb_bram/ramb16bwer_23 [8:8] INPUT = lmb_bram_combined_23.mem PLACED = X2Y40;
lmb_bram/lmb_bram/ramb16bwer_24 [7:7] INPUT = lmb_bram_combined_24.mem PLACED = X2Y24;
lmb_bram/lmb_bram/ramb16bwer_25 [6:6] INPUT = lmb_bram_combined_25.mem PLACED = X1Y28;
lmb_bram/lmb_bram/ramb16bwer_26 [5:5] INPUT = lmb_bram_combined_26.mem PLACED = X2Y22;
lmb_bram/lmb_bram/ramb16bwer_27 [4:4] INPUT = lmb_bram_combined_27.mem PLACED = X3Y28;
lmb_bram/lmb_bram/ramb16bwer_28 [3:3] INPUT = lmb_bram_combined_28.mem PLACED = X3Y34;
lmb_bram/lmb_bram/ramb16bwer_29 [2:2] INPUT = lmb_bram_combined_29.mem PLACED = X3Y36;
lmb_bram/lmb_bram/ramb16bwer_30 [1:1] INPUT = lmb_bram_combined_30.mem PLACED = X3Y38;
lmb_bram/lmb_bram/ramb16bwer_31 [0:0] INPUT = lmb_bram_combined_31.mem PLACED = X2Y46;
lmb_bram/lmb_bram/ramb16bwer_30 [1:1] INPUT = lmb_bram_combined_30.mem PLACED = X2Y34;
lmb_bram/lmb_bram/ramb16bwer_31 [0:0] INPUT = lmb_bram_combined_31.mem PLACED = X2Y36;
END_BUS_BLOCK;
END_ADDRESS_SPACE;
......
projnav/xps/__xps/ise/system.xreport
View file @ 05b98f2c
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2012-03-07T21:30:05</DateModified>
<DateModified>2012-03-15T15:58:06</DateModified>
<ModuleName>system</ModuleName>
<SummaryTimeStamp>2012-03-07T21:30:05</SummaryTimeStamp>
<SummaryTimeStamp>2012-03-15T15:58:05</SummaryTimeStamp>
<SavedFilePath>C:/Users/mjlyons/workspace/vSPI/projnav/xps/__xps/ise/system.xreport</SavedFilePath>
<FilterFile>filter.filter</FilterFile>
<SavedFilterFilePath>C:/Users/mjlyons/workspace/vSPI/projnav/xps/__xps/ise</SavedFilterFilePath>
......
projnav/xps/__xps/system.xml
View file @ 05b98f2c
<EDKSYSTEM EDKVERSION="13.2" EDWVERSION="1.2" TIMESTAMP="Wed Mar 07 21:30:08 2012">
<EDKSYSTEM EDKVERSION="13.2" EDWVERSION="1.2" TIMESTAMP="Thu Mar 15 15:58:17 2012">
<SYSTEMINFO ARCH="spartan6" DEVICE="xc6slx45" PACKAGE="csg324" PART="xc6slx45csg324-2" SOURCE="C:/Users/mjlyons/workspace/vSPI/projnav/xps/system.xmp" SPEEDGRADE="-2"/>
......
projnav/xps/implementation/system_summary.html
View file @ 05b98f2c
......@@ -31,7 +31,7 @@
<TR ALIGN=LEFT><TD>Platgen Log File</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Simgen Log File</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>BitInit Log File</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/mjlyons/workspace/vSPI/projnav/xps\system.log'>System Log File</A></TD><TD>Mon Mar 12 22:03:20 2012</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/Users/mjlyons/workspace/vSPI/projnav/xps\system.log'>System Log File</A></TD><TD>Thu Mar 15 15:58:44 2012</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
</TABLE>
......@@ -57,5 +57,5 @@
</TABLE>
<br><center><b>Date Generated:</b> 03/12/2012 - 22:03:21</center>
<br><center><b>Date Generated:</b> 03/15/2012 - 15:58:44</center>
</BODY></HTML>
\ No newline at end of file
projnav/xps/pcores/spiifc_v1_00_a/data/spiifc_v2_1_0.bbd
View file @ 05b98f2c
##############################################################################
## Filename: C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores/spiifc_v1_00_a/data/spiifc_v2_1_0.bbd
## Description: Black Box Definition
## Date: Tue Mar 06 14:12:58 2012 (by Create and Import Peripheral Wizard)
## Date: Wed Mar 14 16:37:23 2012 (by Create and Import Peripheral Wizard)
##############################################################################
Files
......
projnav/xps/pcores/spiifc_v1_00_a/data/spiifc_v2_1_0.pao
View file @ 05b98f2c
##############################################################################
## Filename: C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores/spiifc_v1_00_a/data/spiifc_v2_1_0.pao
## Description: Peripheral Analysis Order
## Date: Tue Mar 06 14:12:58 2012 (by Create and Import Peripheral Wizard)
## Date: Wed Mar 14 16:37:23 2012 (by Create and Import Peripheral Wizard)
##############################################################################
lib proc_common_v3_00_a proc_common_pkg vhdl
......
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/iseconfig/spiifc.projectmgr
View file @ 05b98f2c
......@@ -7,20 +7,20 @@
<ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" >
<ClosedNodes>
<ClosedNodesVersion>2</ClosedNodesVersion>
<ClosedNode>/spiifc - IMP C:|Users|mjlyons|workspace|vSPI|projnav|xps|pcores|spiifc_v1_00_a|hdl|vhdl|spiifc.vhd</ClosedNode>
<ClosedNode>/spiifc - IMP C:|Users|mjlyons|workspace|vSPI|projnav|xps|pcores|spiifc_v1_00_a|hdl|vhdl|spiifc.vhd/PLBV46_SLAVE_BURST_I - plbv46_slave_burst - implementation</ClosedNode>
<ClosedNode>/spiifc - IMP C:|Users|mjlyons|workspace|vSPI|projnav|xps|pcores|spiifc_v1_00_a|hdl|vhdl|spiifc.vhd/PLBV46_SLAVE_BURST_I - plbv46_slave_burst - implementation/I_SLAVE_ATTACHMENT - plb_slave_attachment - implementation</ClosedNode>
<ClosedNode>/spiifc_tb2 C:|Users|mjlyons|workspace|vSPI|test|spi_base|spiifc_tb2.v</ClosedNode>
<ClosedNode>/spiloop C:|Users|mjlyons|workspace|vSPI|src|spi_base|spiloop.v</ClosedNode>
<ClosedNode>/spiwrap C:|Users|mjlyons|workspace|vSPI|src|spi_base|spiwrap.v</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem>spiloop (C:/Users/mjlyons/workspace/vSPI/src/spi_base/spiloop.v)</SelectedItem>
<SelectedItem>spi - spiifc (C:/Users/mjlyons/workspace/vSPI/src/spi_base/spiifc.v)</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000175000000020000000000000000000000000200000064ffffffff000000810000000300000002000001750000000100000003000000000000000100000003</ViewHeaderState>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000225000000020000000000000000000000000200000064ffffffff000000810000000300000002000002250000000100000003000000000000000100000003</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
<CurrentItem>spiloop (C:/Users/mjlyons/workspace/vSPI/src/spi_base/spiloop.v)</CurrentItem>
<CurrentItem>spi - spiifc (C:/Users/mjlyons/workspace/vSPI/src/spi_base/spiifc.v)</CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
<ClosedNodes>
......@@ -32,13 +32,13 @@
<ClosedNode>User Constraints</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem>Implement Design</SelectedItem>
<SelectedItem>Synthesize - XST</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f8000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>Implement Design</CurrentItem>
<CurrentItem>Synthesize - XST</CurrentItem>
</ItemView>
<ItemView guiview="File" >
<ClosedNodes>
......@@ -90,13 +90,13 @@
<ClosedNode>User Constraints</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem>Generate Programming File</SelectedItem>
<SelectedItem></SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f8000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem>Generate Programming File</CurrentItem>
<CurrentItem></CurrentItem>
</ItemView>
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_XCO" guiview="Process" >
<ClosedNodes>
......@@ -138,13 +138,13 @@
<ClosedNode>Design Utilities</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem></SelectedItem>
<SelectedItem/>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f8000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem>
<CurrentItem/>
</ItemView>
<ItemView engineview="BehavioralSim" sourcetype="DESUT_VERILOG" guiview="Process" >
<ClosedNodes>
......
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/iseconfig/spiifc.xreport deleted 100644 → 0
View file @ 6bc46422
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2012-03-07T22:01:00</DateModified>
<ModuleName>spiloop</ModuleName>
<SummaryTimeStamp>2012-03-07T10:02:06</SummaryTimeStamp>
<SavedFilePath>C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/iseconfig/spiifc.xreport</SavedFilePath>
<ImplementationReportsDirectory>C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav\</ImplementationReportsDirectory>
<DateInitialized>2012-03-07T22:01:00</DateInitialized>
<EnableMessageFiltering>false</EnableMessageFiltering>
</header>
<body>
<viewgroup label="Design Overview" >
<view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="spiwrap_summary.html" label="Summary" >
<toc-item title="Design Overview" target="Design Overview" />
<toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
<toc-item title="Performance Summary" target="Performance Summary" />
<toc-item title="Failing Constraints" target="Failing Constraints" />
<toc-item title="Detailed Reports" target="Detailed Reports" />
</view>
<view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="spiwrap_envsettings.html" label="System Settings" />
<view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="spiwrap_map.xrpt" label="IOB Properties" />
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="spiwrap_map.xrpt" label="Control Set Information" />
<view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="spiwrap_map.xrpt" label="Module Level Utilization" />
<view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="spiwrap.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
<view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="spiwrap_par.xrpt" label="Pinout Report" />
<view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="spiwrap_par.xrpt" label="Clock Report" />
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="spiwrap.twx" label="Static Timing" />
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="spiwrap_html/fit/report.htm" label="CPLD Fitter Report" />
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="spiwrap_html/tim/report.htm" label="CPLD Timing Report" />
</viewgroup>
<viewgroup label="XPS Errors and Warnings" >
<view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" />
<view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" />
<view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" />
</viewgroup>
<viewgroup label="XPS Reports" >
<view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" />
<view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
<view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
<view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="spiwrap.log" label="System Log File" />
</viewgroup>
<viewgroup label="Errors and Warnings" >
<view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
<view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" />
<view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" />
<view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" />
<view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" />
<view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" />
<view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" />
<view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" />
<view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" />
<view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages" />
<view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" />
</viewgroup>
<viewgroup label="Detailed Reports" >
<view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="spiwrap.syr" label="Synthesis Report" >
<toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
<toc-item title="Synthesis Options Summary" target=" Synthesis Options Summary " />
<toc-item title="HDL Compilation" target=" HDL Compilation " />
<toc-item title="Design Hierarchy Analysis" target=" Design Hierarchy Analysis " />
<toc-item title="HDL Analysis" target=" HDL Analysis " />
<toc-item title="HDL Parsing" target=" HDL Parsing " />
<toc-item title="HDL Elaboration" target=" HDL Elaboration " />
<toc-item title="HDL Synthesis" target=" HDL Synthesis " />
<toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" />
<toc-item title="Advanced HDL Synthesis" target=" Advanced HDL Synthesis " searchDir="Backward" />
<toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" />
<toc-item title="Low Level Synthesis" target=" Low Level Synthesis " />
<toc-item title="Partition Report" target=" Partition Report " />
<toc-item title="Final Report" target=" Final Report " />
<toc-item title="Design Summary" target=" Design Summary " />
<toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" />
<toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" />
<toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" />
<toc-item title="Timing Report" target="Timing Report" subItemLevel="1" />
<toc-item title="Clock Information" target="Clock Information" subItemLevel="2" />
<toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" />
<toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" />
<toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
<toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
</view>
<view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="spiwrap.srr" label="Synplify Report" />
<view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="spiwrap.prec_log" label="Precision Report" />
<view inputState="Synthesized" program="ngdbuild" type="Report" file="spiwrap.bld" label="Translation Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Command Line" target="Command Line:" />
<toc-item title="Partition Status" target="Partition Implementation Status" />
<toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
</view>
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="spiwrap_map.mrp" label="Map Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
<toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
<toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
<toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" />
<toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" />
<toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" />
<toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" />
<toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" />
<toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" />
<toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" />
<toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" />
<toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" />
<toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
<toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="spiwrap.par" label="Place and Route Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Device Utilization" target="Device Utilization Summary:" />
<toc-item title="Router Information" target="Starting Router" />
<toc-item title="Partition Status" target="Partition Implementation Status" />
<toc-item title="Clock Report" target="Generating Clock Report" />
<toc-item title="Timing Results" target="Timing Score:" />
<toc-item title="Final Summary" target="Peak Memory Usage:" />
</view>
<view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="spiwrap.twr" label="Post-PAR Static Timing Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Timing Report Description" target="Device,package,speed:" />
<toc-item title="Informational Messages" target="INFO:" />
<toc-item title="Warning Messages" target="WARNING:" />
<toc-item title="Timing Constraints" target="Timing constraint:" />
<toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
<toc-item title="Data Sheet Report" target="Data Sheet report:" />
<toc-item title="Timing Summary" target="Timing summary:" />
<toc-item title="Trace Settings" target="Trace Settings:" />
</view>
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="spiwrap.rpt" label="CPLD Fitter Report (Text)" >
<toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
<toc-item title="Resources Summary" target="** Mapped Resource Summary **" />
<toc-item title="Pin Resources" target="** Pin Resources **" />
<toc-item title="Global Resources" target="** Global Control Resources **" />
</view>
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="spiwrap.tim" label="CPLD Timing Report (Text)" >
<toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
<toc-item title="Performance Summary" target="Performance Summary:" />
</view>
<view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="spiwrap.pwr" label="Power Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Power summary" target="Power summary" />
<toc-item title="Thermal summary" target="Thermal summary" />
</view>
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="spiwrap.bgn" label="Bitgen Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
<toc-item title="Final Summary" target="DRC detected" />
</view>
</viewgroup>
<viewgroup label="Secondary Reports" >
<view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
<view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/spiwrap_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/spiwrap_translate.nlf" label="Post-Translate Simulation Model Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="spiwrap_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="spiwrap_map.map" label="Map Log File" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
<toc-item title="Design Information" target="Design Information" />
<toc-item title="Design Summary" target="Design Summary" />
</view>
<view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
<view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spiwrap_preroute.twr" label="Post-Map Static Timing Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Timing Report Description" target="Device,package,speed:" />
<toc-item title="Informational Messages" target="INFO:" />
<toc-item title="Warning Messages" target="WARNING:" />
<toc-item title="Timing Constraints" target="Timing constraint:" />
<toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
<toc-item title="Data Sheet Report" target="Data Sheet report:" />
<toc-item title="Timing Summary" target="Timing summary:" />
<toc-item title="Trace Settings" target="Trace Settings:" />
</view>
<view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/spiwrap_map.nlf" label="Post-Map Simulation Model Report" />
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spiwrap_map.psr" label="Physical Synthesis Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="spiwrap_pad.txt" label="Pad Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="spiwrap.unroutes" label="Unroutes Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spiwrap_preroute.tsi" label="Post-Map Constraints Interaction Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spiwrap.grf" label="Guide Results Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spiwrap.dly" label="Asynchronous Delay Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spiwrap.clk_rgn" label="Clock Region Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spiwrap.tsi" label="Post-Place and Route Constraints Interaction Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="spiwrap_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
<view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/spiwrap_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="spiwrap_sta.nlf" label="Primetime Netlist Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="spiwrap.ibs" label="IBIS Model" >
<toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
<toc-item title="Component" target="Component " />
</view>
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spiwrap.lck" label="Back-annotate Pin Report" >
<toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
<toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
</view>
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spiwrap.lpc" label="Locked Pin Constraints" >
<toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
<toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
</view>
<view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/spiwrap_timesim.nlf" label="Post-Fit Simulation Model Report" />
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
</viewgroup>
</body>
</report-views>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/iseconfig/spiloop.xreport deleted 100644 → 0
View file @ 6bc46422
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2012-03-13T14:31:01</DateModified>
<ModuleName>spiloop</ModuleName>
<SummaryTimeStamp>2012-03-07T21:27:48</SummaryTimeStamp>
<SavedFilePath>C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/iseconfig/spiloop.xreport</SavedFilePath>
<ImplementationReportsDirectory>C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav\</ImplementationReportsDirectory>
<DateInitialized>2012-03-07T21:28:58</DateInitialized>
<EnableMessageFiltering>false</EnableMessageFiltering>
</header>
<body>
<viewgroup label="Design Overview" >
<view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="spiifc_summary.html" label="Summary" >
<toc-item title="Design Overview" target="Design Overview" />
<toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
<toc-item title="Performance Summary" target="Performance Summary" />
<toc-item title="Failing Constraints" target="Failing Constraints" />
<toc-item title="Detailed Reports" target="Detailed Reports" />
</view>
<view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="spiifc_envsettings.html" label="System Settings" />
<view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="spiifc_map.xrpt" label="IOB Properties" />
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="spiifc_map.xrpt" label="Control Set Information" />
<view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="spiifc_map.xrpt" label="Module Level Utilization" />
<view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="spiifc.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
<view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="spiifc_par.xrpt" label="Pinout Report" />
<view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="spiifc_par.xrpt" label="Clock Report" />
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="spiifc.twx" label="Static Timing" />
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="spiifc_html/fit/report.htm" label="CPLD Fitter Report" />
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="spiifc_html/tim/report.htm" label="CPLD Timing Report" />
</viewgroup>
<viewgroup label="XPS Errors and Warnings" >
<view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" />
<view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" />
<view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" />
</viewgroup>
<viewgroup label="XPS Reports" >
<view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" />
<view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
<view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
<view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="spiifc.log" label="System Log File" />
</viewgroup>
<viewgroup label="Errors and Warnings" >
<view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
<view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" />
<view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" />
<view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" />
<view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" />
<view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" />
<view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" />
<view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" />
<view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" />
<view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages" />
<view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" />
</viewgroup>
<viewgroup label="Detailed Reports" >
<view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="spiifc.syr" label="Synthesis Report" >
<toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
<toc-item title="Synthesis Options Summary" target=" Synthesis Options Summary " />
<toc-item title="HDL Compilation" target=" HDL Compilation " />
<toc-item title="Design Hierarchy Analysis" target=" Design Hierarchy Analysis " />
<toc-item title="HDL Analysis" target=" HDL Analysis " />
<toc-item title="HDL Parsing" target=" HDL Parsing " />
<toc-item title="HDL Elaboration" target=" HDL Elaboration " />
<toc-item title="HDL Synthesis" target=" HDL Synthesis " />
<toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" />
<toc-item title="Advanced HDL Synthesis" target=" Advanced HDL Synthesis " searchDir="Backward" />
<toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" />
<toc-item title="Low Level Synthesis" target=" Low Level Synthesis " />
<toc-item title="Partition Report" target=" Partition Report " />
<toc-item title="Final Report" target=" Final Report " />
<toc-item title="Design Summary" target=" Design Summary " />
<toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" />
<toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" />
<toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" />
<toc-item title="Timing Report" target="Timing Report" subItemLevel="1" />
<toc-item title="Clock Information" target="Clock Information" subItemLevel="2" />
<toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" />
<toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" />
<toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
<toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
</view>
<view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="spiifc.srr" label="Synplify Report" />
<view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="spiifc.prec_log" label="Precision Report" />
<view inputState="Synthesized" program="ngdbuild" type="Report" file="spiifc.bld" label="Translation Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Command Line" target="Command Line:" />
<toc-item title="Partition Status" target="Partition Implementation Status" />
<toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
</view>
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="spiifc_map.mrp" label="Map Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
<toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
<toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
<toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" />
<toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" />
<toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" />
<toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" />
<toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" />
<toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" />
<toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" />
<toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" />
<toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" />
<toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
<toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="spiifc.par" label="Place and Route Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Device Utilization" target="Device Utilization Summary:" />
<toc-item title="Router Information" target="Starting Router" />
<toc-item title="Partition Status" target="Partition Implementation Status" />
<toc-item title="Clock Report" target="Generating Clock Report" />
<toc-item title="Timing Results" target="Timing Score:" />
<toc-item title="Final Summary" target="Peak Memory Usage:" />
</view>
<view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="spiifc.twr" label="Post-PAR Static Timing Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Timing Report Description" target="Device,package,speed:" />
<toc-item title="Informational Messages" target="INFO:" />
<toc-item title="Warning Messages" target="WARNING:" />
<toc-item title="Timing Constraints" target="Timing constraint:" />
<toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
<toc-item title="Data Sheet Report" target="Data Sheet report:" />
<toc-item title="Timing Summary" target="Timing summary:" />
<toc-item title="Trace Settings" target="Trace Settings:" />
</view>
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="spiifc.rpt" label="CPLD Fitter Report (Text)" >
<toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
<toc-item title="Resources Summary" target="** Mapped Resource Summary **" />
<toc-item title="Pin Resources" target="** Pin Resources **" />
<toc-item title="Global Resources" target="** Global Control Resources **" />
</view>
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="spiifc.tim" label="CPLD Timing Report (Text)" >
<toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
<toc-item title="Performance Summary" target="Performance Summary:" />
</view>
<view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="spiifc.pwr" label="Power Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Power summary" target="Power summary" />
<toc-item title="Thermal summary" target="Thermal summary" />
</view>
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="spiifc.bgn" label="Bitgen Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
<toc-item title="Final Summary" target="DRC detected" />
</view>
</viewgroup>
<viewgroup label="Secondary Reports" >
<view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
<view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/spiifc_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/spiifc_translate.nlf" label="Post-Translate Simulation Model Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="spiifc_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="spiifc_map.map" label="Map Log File" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
<toc-item title="Design Information" target="Design Information" />
<toc-item title="Design Summary" target="Design Summary" />
</view>
<view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
<view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spiifc_preroute.twr" label="Post-Map Static Timing Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Timing Report Description" target="Device,package,speed:" />
<toc-item title="Informational Messages" target="INFO:" />
<toc-item title="Warning Messages" target="WARNING:" />
<toc-item title="Timing Constraints" target="Timing constraint:" />
<toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
<toc-item title="Data Sheet Report" target="Data Sheet report:" />
<toc-item title="Timing Summary" target="Timing summary:" />
<toc-item title="Trace Settings" target="Trace Settings:" />
</view>
<view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/spiifc_map.nlf" label="Post-Map Simulation Model Report" />
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spiifc_map.psr" label="Physical Synthesis Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="spiifc_pad.txt" label="Pad Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="spiifc.unroutes" label="Unroutes Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spiifc_preroute.tsi" label="Post-Map Constraints Interaction Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spiifc.grf" label="Guide Results Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spiifc.dly" label="Asynchronous Delay Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spiifc.clk_rgn" label="Clock Region Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spiifc.tsi" label="Post-Place and Route Constraints Interaction Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="spiifc_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
<view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/spiifc_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="spiifc_sta.nlf" label="Primetime Netlist Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="spiifc.ibs" label="IBIS Model" >
<toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
<toc-item title="Component" target="Component " />
</view>
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spiifc.lck" label="Back-annotate Pin Report" >
<toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
<toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
</view>
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spiifc.lpc" label="Locked Pin Constraints" >
<toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
<toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
</view>
<view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/spiifc_timesim.nlf" label="Post-Fit Simulation Model Report" />
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
</viewgroup>
</body>
</report-views>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/iseconfig/spiwrap.xreport deleted 100644 → 0
View file @ 6bc46422
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2012-03-07T18:05:09</DateModified>
<ModuleName>spiloop</ModuleName>
<SummaryTimeStamp>2012-03-07T17:56:22</SummaryTimeStamp>
<SavedFilePath>C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/iseconfig/spiwrap.xreport</SavedFilePath>
<ImplementationReportsDirectory>C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav\</ImplementationReportsDirectory>
<DateInitialized>2012-03-07T18:05:09</DateInitialized>
<EnableMessageFiltering>false</EnableMessageFiltering>
</header>
<body>
<viewgroup label="Design Overview" >
<view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="spiifc_summary.html" label="Summary" >
<toc-item title="Design Overview" target="Design Overview" />
<toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
<toc-item title="Performance Summary" target="Performance Summary" />
<toc-item title="Failing Constraints" target="Failing Constraints" />
<toc-item title="Detailed Reports" target="Detailed Reports" />
</view>
<view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="spiifc_envsettings.html" label="System Settings" />
<view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="spiifc_map.xrpt" label="IOB Properties" />
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="spiifc_map.xrpt" label="Control Set Information" />
<view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="spiifc_map.xrpt" label="Module Level Utilization" />
<view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="spiifc.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
<view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="spiifc_par.xrpt" label="Pinout Report" />
<view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="spiifc_par.xrpt" label="Clock Report" />
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="spiifc.twx" label="Static Timing" />
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="spiifc_html/fit/report.htm" label="CPLD Fitter Report" />
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="spiifc_html/tim/report.htm" label="CPLD Timing Report" />
</viewgroup>
<viewgroup label="XPS Errors and Warnings" >
<view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" />
<view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" />
<view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" />
</viewgroup>
<viewgroup label="XPS Reports" >
<view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" />
<view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
<view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
<view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="spiifc.log" label="System Log File" />
</viewgroup>
<viewgroup label="Errors and Warnings" >
<view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
<view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" />
<view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" />
<view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" />
<view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" />
<view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" />
<view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" />
<view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" />
<view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" />
<view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages" />
<view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" />
</viewgroup>
<viewgroup label="Detailed Reports" >
<view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="spiifc.syr" label="Synthesis Report" >
<toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
<toc-item title="Synthesis Options Summary" target=" Synthesis Options Summary " />
<toc-item title="HDL Compilation" target=" HDL Compilation " />
<toc-item title="Design Hierarchy Analysis" target=" Design Hierarchy Analysis " />
<toc-item title="HDL Analysis" target=" HDL Analysis " />
<toc-item title="HDL Parsing" target=" HDL Parsing " />
<toc-item title="HDL Elaboration" target=" HDL Elaboration " />
<toc-item title="HDL Synthesis" target=" HDL Synthesis " />
<toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" />
<toc-item title="Advanced HDL Synthesis" target=" Advanced HDL Synthesis " searchDir="Backward" />
<toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" />
<toc-item title="Low Level Synthesis" target=" Low Level Synthesis " />
<toc-item title="Partition Report" target=" Partition Report " />
<toc-item title="Final Report" target=" Final Report " />
<toc-item title="Design Summary" target=" Design Summary " />
<toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" />
<toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" />
<toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" />
<toc-item title="Timing Report" target="Timing Report" subItemLevel="1" />
<toc-item title="Clock Information" target="Clock Information" subItemLevel="2" />
<toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" />
<toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" />
<toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
<toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
</view>
<view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="spiifc.srr" label="Synplify Report" />
<view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="spiifc.prec_log" label="Precision Report" />
<view inputState="Synthesized" program="ngdbuild" type="Report" file="spiifc.bld" label="Translation Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Command Line" target="Command Line:" />
<toc-item title="Partition Status" target="Partition Implementation Status" />
<toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
</view>
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="spiifc_map.mrp" label="Map Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
<toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
<toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
<toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" />
<toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" />
<toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" />
<toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" />
<toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" />
<toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" />
<toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" />
<toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" />
<toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" />
<toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
<toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="spiifc.par" label="Place and Route Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Device Utilization" target="Device Utilization Summary:" />
<toc-item title="Router Information" target="Starting Router" />
<toc-item title="Partition Status" target="Partition Implementation Status" />
<toc-item title="Clock Report" target="Generating Clock Report" />
<toc-item title="Timing Results" target="Timing Score:" />
<toc-item title="Final Summary" target="Peak Memory Usage:" />
</view>
<view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="spiifc.twr" label="Post-PAR Static Timing Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Timing Report Description" target="Device,package,speed:" />
<toc-item title="Informational Messages" target="INFO:" />
<toc-item title="Warning Messages" target="WARNING:" />
<toc-item title="Timing Constraints" target="Timing constraint:" />
<toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
<toc-item title="Data Sheet Report" target="Data Sheet report:" />
<toc-item title="Timing Summary" target="Timing summary:" />
<toc-item title="Trace Settings" target="Trace Settings:" />
</view>
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="spiifc.rpt" label="CPLD Fitter Report (Text)" >
<toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
<toc-item title="Resources Summary" target="** Mapped Resource Summary **" />
<toc-item title="Pin Resources" target="** Pin Resources **" />
<toc-item title="Global Resources" target="** Global Control Resources **" />
</view>
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="spiifc.tim" label="CPLD Timing Report (Text)" >
<toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
<toc-item title="Performance Summary" target="Performance Summary:" />
</view>
<view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="spiifc.pwr" label="Power Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Power summary" target="Power summary" />
<toc-item title="Thermal summary" target="Thermal summary" />
</view>
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="spiifc.bgn" label="Bitgen Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
<toc-item title="Final Summary" target="DRC detected" />
</view>
</viewgroup>
<viewgroup label="Secondary Reports" >
<view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
<view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/spiifc_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/spiifc_translate.nlf" label="Post-Translate Simulation Model Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="spiifc_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="spiifc_map.map" label="Map Log File" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
<toc-item title="Design Information" target="Design Information" />
<toc-item title="Design Summary" target="Design Summary" />
</view>
<view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
<view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spiifc_preroute.twr" label="Post-Map Static Timing Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
<toc-item title="Timing Report Description" target="Device,package,speed:" />
<toc-item title="Informational Messages" target="INFO:" />
<toc-item title="Warning Messages" target="WARNING:" />
<toc-item title="Timing Constraints" target="Timing constraint:" />
<toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
<toc-item title="Data Sheet Report" target="Data Sheet report:" />
<toc-item title="Timing Summary" target="Timing summary:" />
<toc-item title="Trace Settings" target="Trace Settings:" />
</view>
<view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/spiifc_map.nlf" label="Post-Map Simulation Model Report" />
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spiifc_map.psr" label="Physical Synthesis Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="spiifc_pad.txt" label="Pad Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="spiifc.unroutes" label="Unroutes Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spiifc_preroute.tsi" label="Post-Map Constraints Interaction Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spiifc.grf" label="Guide Results Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spiifc.dly" label="Asynchronous Delay Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spiifc.clk_rgn" label="Clock Region Report" />
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spiifc.tsi" label="Post-Place and Route Constraints Interaction Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
</view>
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="spiifc_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
<view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/spiifc_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="spiifc_sta.nlf" label="Primetime Netlist Report" >
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
</view>
<view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="spiifc.ibs" label="IBIS Model" >
<toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
<toc-item title="Component" target="Component " />
</view>
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spiifc.lck" label="Back-annotate Pin Report" >
<toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
<toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
</view>
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="spiifc.lpc" label="Locked Pin Constraints" >
<toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
<toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
</view>
<view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/spiifc_timesim.nlf" label="Post-Fit Simulation Model Report" />
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
</viewgroup>
</body>
</report-views>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc.gise
View file @ 05b98f2c
......@@ -27,6 +27,11 @@
<file xil_pn:fileType="FILE_NCD" xil_pn:name="spiwrap_guide.ncd" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
<transforms xmlns="http://www.xilinx.com/XMLSchema">
<transform xil_pn:end_ts="1331743852" xil_pn:in_ck="241267088593728842" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1331743852">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
</transforms>
</generated_project>
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/spiifc.xise
View file @ 05b98f2c
......@@ -17,104 +17,104 @@
<files>
<file xil_pn:name="../../hdl/vhdl/spiifc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="../../hdl/verilog/user_logic.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/proc_common_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
<library xil_pn:name="proc_common_v3_00_a"/>
</file>
<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/ipif_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
<library xil_pn:name="proc_common_v3_00_a"/>
</file>
<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_muxcy.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
<library xil_pn:name="proc_common_v3_00_a"/>
</file>
<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/or_gate128.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
<library xil_pn:name="proc_common_v3_00_a"/>
</file>
<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/family_support.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
<library xil_pn:name="proc_common_v3_00_a"/>
</file>
<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/pselect_f.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
<library xil_pn:name="proc_common_v3_00_a"/>
</file>
<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/proc_common_v3_00_a/hdl/vhdl/counter_f.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
<library xil_pn:name="proc_common_v3_00_a"/>
</file>
<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/flex_addr_cntr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
<library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
</file>
<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/addr_reg_cntr_brst_flex.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
<library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
</file>
<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plb_address_decoder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
<library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
</file>
<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/burst_support.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
<library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
</file>
<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/wr_buffer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
<library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
</file>
<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/be_reset_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
<library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
</file>
<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plb_slave_attachment.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
<library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
</file>
<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/data_mirror_128.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
<library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
</file>
<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/plbv46_slave_burst_v1_01_a/hdl/vhdl/plbv46_slave_burst.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
<library xil_pn:name="plbv46_slave_burst_v1_01_a"/>
</file>
<file xil_pn:name="C:/Xilinx/13.2/ISE_DS/EDK/hw/XilinxProcessorIPLib/pcores/interrupt_control_v2_01_a/hdl/vhdl/interrupt_control.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
<library xil_pn:name="interrupt_control_v2_01_a"/>
</file>
<file xil_pn:name="ipcore_dir/buffermem.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="../../../../../../src/spi_base/spiifc.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="../../../../../../src/spi_base/spiwrap.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
......@@ -135,11 +135,11 @@
</file>
<file xil_pn:name="ipcore_dir/spiloopmem.xco" xil_pn:type="FILE_COREGEN">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../../../src/spi_base/spiloop.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../../../ucf/atlys/spiloop.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
......@@ -269,9 +269,9 @@
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Module|spiloop" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../../../../../../src/spi_base/spiloop.v" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/spiloop" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|spiifc|IMP" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="../../hdl/vhdl/spiifc.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/spiifc" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -335,7 +335,7 @@
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="spiloop" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="spiifc" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
......@@ -349,10 +349,10 @@
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="spiloop_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="spiloop_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="spiloop_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="spiloop_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="spiifc_map.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="spiifc_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="spiifc_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="spiifc_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
......
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/user_logic.cmd_log deleted 100644 → 0
View file @ 6bc46422
xst -intstyle ise -ifn "C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/user_logic.xst" -ofn "C:/Users/mjlyons/workspace/vSPI/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/user_logic.syr"
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/user_logic.ngc deleted 100644 → 0
View file @ 6bc46422
This source diff could not be displayed because it is too large. You can view the blob instead.
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/user_logic.prj deleted 100644 → 0
View file @ 6bc46422
verilog work "../../../../../../src/spi_base/spiifc.v"
verilog work "ipcore_dir/buffermem.v"
verilog work "../../hdl/verilog/user_logic.v"
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/user_logic.syr deleted 100644 → 0
View file @ 6bc46422
Release 13.2 - xst O.61xd (nt64)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.27 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.28 secs
--> Reading design: user_logic.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Parsing
3) HDL Elaboration
4) HDL Synthesis
4.1) HDL Synthesis Report
5) Advanced HDL Synthesis
5.1) Advanced HDL Synthesis Report
6) Low Level Synthesis
7) Partition Report
8) Design Summary
8.1) Primitive and Black Box Usage
8.2) Device utilization summary
8.3) Partition Resource Summary
8.4) Timing Report
8.4.1) Clock Information
8.4.2) Asynchronous Control Signals Information
8.4.3) Timing Summary
8.4.4) Timing Details
8.4.5) Cross Clock Domains Report
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "user_logic.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "user_logic"
Output Format : NGC
Target Device : xc6slx45-2-csg324
---- Source Options
Top Module Name : user_logic
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : LUT
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Shift Register Extraction : YES
ROM Style : Auto
Resource Sharing : YES
Asynchronous To Synchronous : NO
Shift Register Minimum Size : 2
Use DSP Block : Auto
Automatic Register Balancing : No
---- Target Options
LUT Combining : Auto
Reduce Control Sets : Auto
Add IO Buffers : YES
Global Maximum Fanout : 100000
Add Generic Clock Buffer(BUFG) : 16
Register Duplication : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Auto
Use Synchronous Set : Auto
Use Synchronous Reset : Auto
Pack IO Registers into IOBs : Auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Power Reduction : NO
Keep Hierarchy : No
Netlist Hierarchy : As_Optimized
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : Maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
DSP48 Utilization Ratio : 100
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
---- Other Options
Cores Search Directories : {"ipcore_dir" }
=========================================================================
=========================================================================
* HDL Parsing *
=========================================================================
Analyzing Verilog file \"C:\Users\mjlyons\workspace\vSPI\src\spi_base\spiifc.v\" into library work
Parsing module <spiifc>.
Analyzing Verilog file \"C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav\ipcore_dir\buffermem.v\" into library work
Parsing module <buffermem>.
Analyzing Verilog file \"C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\hdl\verilog\user_logic.v\" into library work
Parsing module <user_logic>.
=========================================================================
* HDL Elaboration *
=========================================================================
WARNING:HDLCompiler:1016 - "C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\hdl\verilog\user_logic.v" Line 196: Port douta is not connected to this instance
WARNING:HDLCompiler:1016 - "C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\hdl\verilog\user_logic.v" Line 212: Port dina is not connected to this instance
WARNING:HDLCompiler:1016 - "C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\hdl\verilog\user_logic.v" Line 228: Port debug_out is not connected to this instance
Elaborating module <user_logic>.
Elaborating module <buffermem>.
WARNING:HDLCompiler:1499 - "C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\devl\projnav\ipcore_dir\buffermem.v" Line 39: Empty module <buffermem> remains a black box.
Elaborating module <spiifc>.
WARNING:HDLCompiler:413 - "C:\Users\mjlyons\workspace\vSPI\src\spi_base\spiifc.v" Line 123: Result of 32-bit expression is truncated to fit in 1-bit target.
WARNING:HDLCompiler:413 - "C:\Users\mjlyons\workspace\vSPI\src\spi_base\spiifc.v" Line 124: Result of 32-bit expression is truncated to fit in 12-bit target.
WARNING:HDLCompiler:1127 - "C:\Users\mjlyons\workspace\vSPI\src\spi_base\spiifc.v" Line 145: Assignment to ssTurnOnReg ignored, since the identifier is never used
WARNING:HDLCompiler:413 - "C:\Users\mjlyons\workspace\vSPI\src\spi_base\spiifc.v" Line 190: Result of 13-bit expression is truncated to fit in 12-bit target.
WARNING:HDLCompiler:413 - "C:\Users\mjlyons\workspace\vSPI\src\spi_base\spiifc.v" Line 192: Result of 32-bit expression is truncated to fit in 3-bit target.
WARNING:HDLCompiler:413 - "C:\Users\mjlyons\workspace\vSPI\src\spi_base\spiifc.v" Line 218: Result of 13-bit expression is truncated to fit in 12-bit target.
WARNING:HDLCompiler:1127 - "C:\Users\mjlyons\workspace\vSPI\src\spi_base\spiifc.v" Line 164: Assignment to cmd ignored, since the identifier is never used
WARNING:HDLCompiler:552 - "C:\Users\mjlyons\workspace\vSPI\projnav\xps\pcores\spiifc_v1_00_a\hdl\verilog\user_logic.v" Line 212: Input port dina[7] is not connected on this instance
=========================================================================
* HDL Synthesis *
=========================================================================
Synthesizing Unit <user_logic>.
Related source file is "c:/users/mjlyons/workspace/vspi/projnav/xps/pcores/spiifc_v1_00_a/hdl/verilog/user_logic.v".
C_SLV_AWIDTH = 32
C_SLV_DWIDTH = 32
C_NUM_REG = 16
C_NUM_MEM = 2
C_NUM_INTR = 1
WARNING:Xst:647 - Input <Bus2IP_Addr<0:19>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Bus2IP_Addr<30:31>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Bus2IP_BurstLength<0:8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Bus2IP_Burst> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "c:/users/mjlyons/workspace/vspi/projnav/xps/pcores/spiifc_v1_00_a/hdl/verilog/user_logic.v" line 196: Output port <douta> of the instance <mosiMem> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/users/mjlyons/workspace/vspi/projnav/xps/pcores/spiifc_v1_00_a/hdl/verilog/user_logic.v" line 228: Output port <debug_out> of the instance <spi> is unconnected or connected to loadless signal.
Found 1-bit register for signal <slv_reg0<0>>.
Found 1-bit register for signal <slv_reg0<1>>.
Found 1-bit register for signal <slv_reg0<2>>.
Found 1-bit register for signal <slv_reg0<3>>.
Found 1-bit register for signal <slv_reg0<4>>.
Found 1-bit register for signal <slv_reg0<5>>.
Found 1-bit register for signal <slv_reg0<6>>.
Found 1-bit register for signal <slv_reg0<7>>.
Found 1-bit register for signal <slv_reg0<8>>.
Found 1-bit register for signal <slv_reg0<9>>.
Found 1-bit register for signal <slv_reg0<10>>.
Found 1-bit register for signal <slv_reg0<11>>.
Found 1-bit register for signal <slv_reg0<12>>.
Found 1-bit register for signal <slv_reg0<13>>.
Found 1-bit register for signal <slv_reg0<14>>.
Found 1-bit register for signal <slv_reg0<15>>.
Found 1-bit register for signal <slv_reg0<16>>.
Found 1-bit register for signal <slv_reg0<17>>.
Found 1-bit register for signal <slv_reg0<18>>.
Found 1-bit register for signal <slv_reg0<19>>.
Found 1-bit register for signal <slv_reg0<20>>.
Found 1-bit register for signal <slv_reg0<21>>.
Found 1-bit register for signal <slv_reg0<22>>.
Found 1-bit register for signal <slv_reg0<23>>.
Found 1-bit register for signal <slv_reg0<24>>.
Found 1-bit register for signal <slv_reg0<25>>.
Found 1-bit register for signal <slv_reg0<26>>.
Found 1-bit register for signal <slv_reg0<27>>.
Found 1-bit register for signal <slv_reg0<28>>.
Found 1-bit register for signal <slv_reg0<29>>.
Found 1-bit register for signal <slv_reg0<30>>.
Found 1-bit register for signal <slv_reg0<31>>.
Found 1-bit register for signal <slv_reg1<0>>.
Found 1-bit register for signal <slv_reg1<1>>.
Found 1-bit register for signal <slv_reg1<2>>.
Found 1-bit register for signal <slv_reg1<3>>.
Found 1-bit register for signal <slv_reg1<4>>.
Found 1-bit register for signal <slv_reg1<5>>.
Found 1-bit register for signal <slv_reg1<6>>.
Found 1-bit register for signal <slv_reg1<7>>.
Found 1-bit register for signal <slv_reg1<8>>.
Found 1-bit register for signal <slv_reg1<9>>.
Found 1-bit register for signal <slv_reg1<10>>.
Found 1-bit register for signal <slv_reg1<11>>.
Found 1-bit register for signal <slv_reg1<12>>.
Found 1-bit register for signal <slv_reg1<13>>.
Found 1-bit register for signal <slv_reg1<14>>.
Found 1-bit register for signal <slv_reg1<15>>.
Found 1-bit register for signal <slv_reg1<16>>.
Found 1-bit register for signal <slv_reg1<17>>.
Found 1-bit register for signal <slv_reg1<18>>.
Found 1-bit register for signal <slv_reg1<19>>.
Found 1-bit register for signal <slv_reg1<20>>.
Found 1-bit register for signal <slv_reg1<21>>.
Found 1-bit register for signal <slv_reg1<22>>.
Found 1-bit register for signal <slv_reg1<23>>.
Found 1-bit register for signal <slv_reg1<24>>.
Found 1-bit register for signal <slv_reg1<25>>.
Found 1-bit register for signal <slv_reg1<26>>.
Found 1-bit register for signal <slv_reg1<27>>.
Found 1-bit register for signal <slv_reg1<28>>.
Found 1-bit register for signal <slv_reg1<29>>.
Found 1-bit register for signal <slv_reg1<30>>.
Found 1-bit register for signal <slv_reg1<31>>.
Found 1-bit register for signal <slv_reg2<0>>.
Found 1-bit register for signal <slv_reg2<1>>.
Found 1-bit register for signal <slv_reg2<2>>.
Found 1-bit register for signal <slv_reg2<3>>.
Found 1-bit register for signal <slv_reg2<4>>.
Found 1-bit register for signal <slv_reg2<5>>.
Found 1-bit register for signal <slv_reg2<6>>.
Found 1-bit register for signal <slv_reg2<7>>.
Found 1-bit register for signal <slv_reg2<8>>.
Found 1-bit register for signal <slv_reg2<9>>.
Found 1-bit register for signal <slv_reg2<10>>.
Found 1-bit register for signal <slv_reg2<11>>.
Found 1-bit register for signal <slv_reg2<12>>.
Found 1-bit register for signal <slv_reg2<13>>.
Found 1-bit register for signal <slv_reg2<14>>.
Found 1-bit register for signal <slv_reg2<15>>.
Found 1-bit register for signal <slv_reg2<16>>.
Found 1-bit register for signal <slv_reg2<17>>.
Found 1-bit register for signal <slv_reg2<18>>.
Found 1-bit register for signal <slv_reg2<19>>.
Found 1-bit register for signal <slv_reg2<20>>.
Found 1-bit register for signal <slv_reg2<21>>.
Found 1-bit register for signal <slv_reg2<22>>.
Found 1-bit register for signal <slv_reg2<23>>.
Found 1-bit register for signal <slv_reg2<24>>.
Found 1-bit register for signal <slv_reg2<25>>.
Found 1-bit register for signal <slv_reg2<26>>.
Found 1-bit register for signal <slv_reg2<27>>.
Found 1-bit register for signal <slv_reg2<28>>.
Found 1-bit register for signal <slv_reg2<29>>.
Found 1-bit register for signal <slv_reg2<30>>.
Found 1-bit register for signal <slv_reg2<31>>.
Found 1-bit register for signal <slv_reg3<0>>.
Found 1-bit register for signal <slv_reg3<1>>.
Found 1-bit register for signal <slv_reg3<2>>.
Found 1-bit register for signal <slv_reg3<3>>.
Found 1-bit register for signal <slv_reg3<4>>.
Found 1-bit register for signal <slv_reg3<5>>.
Found 1-bit register for signal <slv_reg3<6>>.
Found 1-bit register for signal <slv_reg3<7>>.
Found 1-bit register for signal <slv_reg3<8>>.
Found 1-bit register for signal <slv_reg3<9>>.
Found 1-bit register for signal <slv_reg3<10>>.
Found 1-bit register for signal <slv_reg3<11>>.
Found 1-bit register for signal <slv_reg3<12>>.
Found 1-bit register for signal <slv_reg3<13>>.
Found 1-bit register for signal <slv_reg3<14>>.
Found 1-bit register for signal <slv_reg3<15>>.
Found 1-bit register for signal <slv_reg3<16>>.
Found 1-bit register for signal <slv_reg3<17>>.
Found 1-bit register for signal <slv_reg3<18>>.
Found 1-bit register for signal <slv_reg3<19>>.
Found 1-bit register for signal <slv_reg3<20>>.
Found 1-bit register for signal <slv_reg3<21>>.
Found 1-bit register for signal <slv_reg3<22>>.
Found 1-bit register for signal <slv_reg3<23>>.
Found 1-bit register for signal <slv_reg3<24>>.
Found 1-bit register for signal <slv_reg3<25>>.
Found 1-bit register for signal <slv_reg3<26>>.
Found 1-bit register for signal <slv_reg3<27>>.
Found 1-bit register for signal <slv_reg3<28>>.
Found 1-bit register for signal <slv_reg3<29>>.
Found 1-bit register for signal <slv_reg3<30>>.
Found 1-bit register for signal <slv_reg3<31>>.
Found 1-bit register for signal <slv_reg4<0>>.
Found 1-bit register for signal <slv_reg4<1>>.
Found 1-bit register for signal <slv_reg4<2>>.
Found 1-bit register for signal <slv_reg4<3>>.
Found 1-bit register for signal <slv_reg4<4>>.
Found 1-bit register for signal <slv_reg4<5>>.
Found 1-bit register for signal <slv_reg4<6>>.
Found 1-bit register for signal <slv_reg4<7>>.
Found 1-bit register for signal <slv_reg4<8>>.
Found 1-bit register for signal <slv_reg4<9>>.
Found 1-bit register for signal <slv_reg4<10>>.
Found 1-bit register for signal <slv_reg4<11>>.
Found 1-bit register for signal <slv_reg4<12>>.
Found 1-bit register for signal <slv_reg4<13>>.
Found 1-bit register for signal <slv_reg4<14>>.
Found 1-bit register for signal <slv_reg4<15>>.
Found 1-bit register for signal <slv_reg4<16>>.
Found 1-bit register for signal <slv_reg4<17>>.
Found 1-bit register for signal <slv_reg4<18>>.
Found 1-bit register for signal <slv_reg4<19>>.
Found 1-bit register for signal <slv_reg4<20>>.
Found 1-bit register for signal <slv_reg4<21>>.
Found 1-bit register for signal <slv_reg4<22>>.
Found 1-bit register for signal <slv_reg4<23>>.
Found 1-bit register for signal <slv_reg4<24>>.
Found 1-bit register for signal <slv_reg4<25>>.
Found 1-bit register for signal <slv_reg4<26>>.
Found 1-bit register for signal <slv_reg4<27>>.
Found 1-bit register for signal <slv_reg4<28>>.
Found 1-bit register for signal <slv_reg4<29>>.
Found 1-bit register for signal <slv_reg4<30>>.
Found 1-bit register for signal <slv_reg4<31>>.
Found 1-bit register for signal <slv_reg5<0>>.
Found 1-bit register for signal <slv_reg5<1>>.
Found 1-bit register for signal <slv_reg5<2>>.
Found 1-bit register for signal <slv_reg5<3>>.
Found 1-bit register for signal <slv_reg5<4>>.
Found 1-bit register for signal <slv_reg5<5>>.
Found 1-bit register for signal <slv_reg5<6>>.
Found 1-bit register for signal <slv_reg5<7>>.
Found 1-bit register for signal <slv_reg5<8>>.
Found 1-bit register for signal <slv_reg5<9>>.
Found 1-bit register for signal <slv_reg5<10>>.
Found 1-bit register for signal <slv_reg5<11>>.
Found 1-bit register for signal <slv_reg5<12>>.
Found 1-bit register for signal <slv_reg5<13>>.
Found 1-bit register for signal <slv_reg5<14>>.
Found 1-bit register for signal <slv_reg5<15>>.
Found 1-bit register for signal <slv_reg5<16>>.
Found 1-bit register for signal <slv_reg5<17>>.
Found 1-bit register for signal <slv_reg5<18>>.
Found 1-bit register for signal <slv_reg5<19>>.
Found 1-bit register for signal <slv_reg5<20>>.
Found 1-bit register for signal <slv_reg5<21>>.
Found 1-bit register for signal <slv_reg5<22>>.
Found 1-bit register for signal <slv_reg5<23>>.
Found 1-bit register for signal <slv_reg5<24>>.
Found 1-bit register for signal <slv_reg5<25>>.
Found 1-bit register for signal <slv_reg5<26>>.
Found 1-bit register for signal <slv_reg5<27>>.
Found 1-bit register for signal <slv_reg5<28>>.
Found 1-bit register for signal <slv_reg5<29>>.
Found 1-bit register for signal <slv_reg5<30>>.
Found 1-bit register for signal <slv_reg5<31>>.
Found 1-bit register for signal <slv_reg6<0>>.
Found 1-bit register for signal <slv_reg6<1>>.
Found 1-bit register for signal <slv_reg6<2>>.
Found 1-bit register for signal <slv_reg6<3>>.
Found 1-bit register for signal <slv_reg6<4>>.
Found 1-bit register for signal <slv_reg6<5>>.
Found 1-bit register for signal <slv_reg6<6>>.
Found 1-bit register for signal <slv_reg6<7>>.
Found 1-bit register for signal <slv_reg6<8>>.
Found 1-bit register for signal <slv_reg6<9>>.
Found 1-bit register for signal <slv_reg6<10>>.
Found 1-bit register for signal <slv_reg6<11>>.
Found 1-bit register for signal <slv_reg6<12>>.
Found 1-bit register for signal <slv_reg6<13>>.
Found 1-bit register for signal <slv_reg6<14>>.
Found 1-bit register for signal <slv_reg6<15>>.
Found 1-bit register for signal <slv_reg6<16>>.
Found 1-bit register for signal <slv_reg6<17>>.
Found 1-bit register for signal <slv_reg6<18>>.
Found 1-bit register for signal <slv_reg6<19>>.
Found 1-bit register for signal <slv_reg6<20>>.
Found 1-bit register for signal <slv_reg6<21>>.
Found 1-bit register for signal <slv_reg6<22>>.
Found 1-bit register for signal <slv_reg6<23>>.
Found 1-bit register for signal <slv_reg6<24>>.
Found 1-bit register for signal <slv_reg6<25>>.
Found 1-bit register for signal <slv_reg6<26>>.
Found 1-bit register for signal <slv_reg6<27>>.
Found 1-bit register for signal <slv_reg6<28>>.
Found 1-bit register for signal <slv_reg6<29>>.
Found 1-bit register for signal <slv_reg6<30>>.
Found 1-bit register for signal <slv_reg6<31>>.
Found 1-bit register for signal <slv_reg7<0>>.
Found 1-bit register for signal <slv_reg7<1>>.
Found 1-bit register for signal <slv_reg7<2>>.
Found 1-bit register for signal <slv_reg7<3>>.
Found 1-bit register for signal <slv_reg7<4>>.
Found 1-bit register for signal <slv_reg7<5>>.
Found 1-bit register for signal <slv_reg7<6>>.
Found 1-bit register for signal <slv_reg7<7>>.
Found 1-bit register for signal <slv_reg7<8>>.
Found 1-bit register for signal <slv_reg7<9>>.
Found 1-bit register for signal <slv_reg7<10>>.
Found 1-bit register for signal <slv_reg7<11>>.
Found 1-bit register for signal <slv_reg7<12>>.
Found 1-bit register for signal <slv_reg7<13>>.
Found 1-bit register for signal <slv_reg7<14>>.
Found 1-bit register for signal <slv_reg7<15>>.
Found 1-bit register for signal <slv_reg7<16>>.
Found 1-bit register for signal <slv_reg7<17>>.
Found 1-bit register for signal <slv_reg7<18>>.
Found 1-bit register for signal <slv_reg7<19>>.
Found 1-bit register for signal <slv_reg7<20>>.
Found 1-bit register for signal <slv_reg7<21>>.
Found 1-bit register for signal <slv_reg7<22>>.
Found 1-bit register for signal <slv_reg7<23>>.
Found 1-bit register for signal <slv_reg7<24>>.
Found 1-bit register for signal <slv_reg7<25>>.
Found 1-bit register for signal <slv_reg7<26>>.
Found 1-bit register for signal <slv_reg7<27>>.
Found 1-bit register for signal <slv_reg7<28>>.
Found 1-bit register for signal <slv_reg7<29>>.
Found 1-bit register for signal <slv_reg7<30>>.
Found 1-bit register for signal <slv_reg7<31>>.
Found 1-bit register for signal <slv_reg8<0>>.
Found 1-bit register for signal <slv_reg8<1>>.
Found 1-bit register for signal <slv_reg8<2>>.
Found 1-bit register for signal <slv_reg8<3>>.
Found 1-bit register for signal <slv_reg8<4>>.
Found 1-bit register for signal <slv_reg8<5>>.
Found 1-bit register for signal <slv_reg8<6>>.
Found 1-bit register for signal <slv_reg8<7>>.
Found 1-bit register for signal <slv_reg8<8>>.
Found 1-bit register for signal <slv_reg8<9>>.
Found 1-bit register for signal <slv_reg8<10>>.
Found 1-bit register for signal <slv_reg8<11>>.
Found 1-bit register for signal <slv_reg8<12>>.
Found 1-bit register for signal <slv_reg8<13>>.
Found 1-bit register for signal <slv_reg8<14>>.
Found 1-bit register for signal <slv_reg8<15>>.
Found 1-bit register for signal <slv_reg8<16>>.
Found 1-bit register for signal <slv_reg8<17>>.
Found 1-bit register for signal <slv_reg8<18>>.
Found 1-bit register for signal <slv_reg8<19>>.
Found 1-bit register for signal <slv_reg8<20>>.
Found 1-bit register for signal <slv_reg8<21>>.
Found 1-bit register for signal <slv_reg8<22>>.
Found 1-bit register for signal <slv_reg8<23>>.
Found 1-bit register for signal <slv_reg8<24>>.
Found 1-bit register for signal <slv_reg8<25>>.
Found 1-bit register for signal <slv_reg8<26>>.
Found 1-bit register for signal <slv_reg8<27>>.
Found 1-bit register for signal <slv_reg8<28>>.
Found 1-bit register for signal <slv_reg8<29>>.
Found 1-bit register for signal <slv_reg8<30>>.
Found 1-bit register for signal <slv_reg8<31>>.
Found 1-bit register for signal <slv_reg9<0>>.
Found 1-bit register for signal <slv_reg9<1>>.
Found 1-bit register for signal <slv_reg9<2>>.
Found 1-bit register for signal <slv_reg9<3>>.
Found 1-bit register for signal <slv_reg9<4>>.
Found 1-bit register for signal <slv_reg9<5>>.
Found 1-bit register for signal <slv_reg9<6>>.
Found 1-bit register for signal <slv_reg9<7>>.
Found 1-bit register for signal <slv_reg9<8>>.
Found 1-bit register for signal <slv_reg9<9>>.
Found 1-bit register for signal <slv_reg9<10>>.
Found 1-bit register for signal <slv_reg9<11>>.
Found 1-bit register for signal <slv_reg9<12>>.
Found 1-bit register for signal <slv_reg9<13>>.
Found 1-bit register for signal <slv_reg9<14>>.
Found 1-bit register for signal <slv_reg9<15>>.
Found 1-bit register for signal <slv_reg9<16>>.
Found 1-bit register for signal <slv_reg9<17>>.
Found 1-bit register for signal <slv_reg9<18>>.
Found 1-bit register for signal <slv_reg9<19>>.
Found 1-bit register for signal <slv_reg9<20>>.
Found 1-bit register for signal <slv_reg9<21>>.
Found 1-bit register for signal <slv_reg9<22>>.
Found 1-bit register for signal <slv_reg9<23>>.
Found 1-bit register for signal <slv_reg9<24>>.
Found 1-bit register for signal <slv_reg9<25>>.
Found 1-bit register for signal <slv_reg9<26>>.
Found 1-bit register for signal <slv_reg9<27>>.
Found 1-bit register for signal <slv_reg9<28>>.
Found 1-bit register for signal <slv_reg9<29>>.
Found 1-bit register for signal <slv_reg9<30>>.
Found 1-bit register for signal <slv_reg9<31>>.
Found 1-bit register for signal <slv_reg10<0>>.
Found 1-bit register for signal <slv_reg10<1>>.
Found 1-bit register for signal <slv_reg10<2>>.
Found 1-bit register for signal <slv_reg10<3>>.
Found 1-bit register for signal <slv_reg10<4>>.
Found 1-bit register for signal <slv_reg10<5>>.
Found 1-bit register for signal <slv_reg10<6>>.
Found 1-bit register for signal <slv_reg10<7>>.
Found 1-bit register for signal <slv_reg10<8>>.
Found 1-bit register for signal <slv_reg10<9>>.
Found 1-bit register for signal <slv_reg10<10>>.
Found 1-bit register for signal <slv_reg10<11>>.
Found 1-bit register for signal <slv_reg10<12>>.
Found 1-bit register for signal <slv_reg10<13>>.
Found 1-bit register for signal <slv_reg10<14>>.
Found 1-bit register for signal <slv_reg10<15>>.
Found 1-bit register for signal <slv_reg10<16>>.
Found 1-bit register for signal <slv_reg10<17>>.
Found 1-bit register for signal <slv_reg10<18>>.
Found 1-bit register for signal <slv_reg10<19>>.
Found 1-bit register for signal <slv_reg10<20>>.
Found 1-bit register for signal <slv_reg10<21>>.
Found 1-bit register for signal <slv_reg10<22>>.
Found 1-bit register for signal <slv_reg10<23>>.
Found 1-bit register for signal <slv_reg10<24>>.
Found 1-bit register for signal <slv_reg10<25>>.
Found 1-bit register for signal <slv_reg10<26>>.
Found 1-bit register for signal <slv_reg10<27>>.
Found 1-bit register for signal <slv_reg10<28>>.
Found 1-bit register for signal <slv_reg10<29>>.
Found 1-bit register for signal <slv_reg10<30>>.
Found 1-bit register for signal <slv_reg10<31>>.
Found 1-bit register for signal <slv_reg11<0>>.
Found 1-bit register for signal <slv_reg11<1>>.
Found 1-bit register for signal <slv_reg11<2>>.
Found 1-bit register for signal <slv_reg11<3>>.
Found 1-bit register for signal <slv_reg11<4>>.
Found 1-bit register for signal <slv_reg11<5>>.
Found 1-bit register for signal <slv_reg11<6>>.
Found 1-bit register for signal <slv_reg11<7>>.
Found 1-bit register for signal <slv_reg11<8>>.
Found 1-bit register for signal <slv_reg11<9>>.
Found 1-bit register for signal <slv_reg11<10>>.
Found 1-bit register for signal <slv_reg11<11>>.
Found 1-bit register for signal <slv_reg11<12>>.
Found 1-bit register for signal <slv_reg11<13>>.
Found 1-bit register for signal <slv_reg11<14>>.
Found 1-bit register for signal <slv_reg11<15>>.
Found 1-bit register for signal <slv_reg11<16>>.
Found 1-bit register for signal <slv_reg11<17>>.
Found 1-bit register for signal <slv_reg11<18>>.
Found 1-bit register for signal <slv_reg11<19>>.
Found 1-bit register for signal <slv_reg11<20>>.
Found 1-bit register for signal <slv_reg11<21>>.
Found 1-bit register for signal <slv_reg11<22>>.
Found 1-bit register for signal <slv_reg11<23>>.
Found 1-bit register for signal <slv_reg11<24>>.
Found 1-bit register for signal <slv_reg11<25>>.
Found 1-bit register for signal <slv_reg11<26>>.
Found 1-bit register for signal <slv_reg11<27>>.
Found 1-bit register for signal <slv_reg11<28>>.
Found 1-bit register for signal <slv_reg11<29>>.
Found 1-bit register for signal <slv_reg11<30>>.
Found 1-bit register for signal <slv_reg11<31>>.
Found 1-bit register for signal <slv_reg12<0>>.
Found 1-bit register for signal <slv_reg12<1>>.
Found 1-bit register for signal <slv_reg12<2>>.
Found 1-bit register for signal <slv_reg12<3>>.
Found 1-bit register for signal <slv_reg12<4>>.
Found 1-bit register for signal <slv_reg12<5>>.
Found 1-bit register for signal <slv_reg12<6>>.
Found 1-bit register for signal <slv_reg12<7>>.
Found 1-bit register for signal <slv_reg12<8>>.
Found 1-bit register for signal <slv_reg12<9>>.
Found 1-bit register for signal <slv_reg12<10>>.
Found 1-bit register for signal <slv_reg12<11>>.
Found 1-bit register for signal <slv_reg12<12>>.
Found 1-bit register for signal <slv_reg12<13>>.
Found 1-bit register for signal <slv_reg12<14>>.
Found 1-bit register for signal <slv_reg12<15>>.
Found 1-bit register for signal <slv_reg12<16>>.
Found 1-bit register for signal <slv_reg12<17>>.
Found 1-bit register for signal <slv_reg12<18>>.
Found 1-bit register for signal <slv_reg12<19>>.
Found 1-bit register for signal <slv_reg12<20>>.
Found 1-bit register for signal <slv_reg12<21>>.
Found 1-bit register for signal <slv_reg12<22>>.
Found 1-bit register for signal <slv_reg12<23>>.
Found 1-bit register for signal <slv_reg12<24>>.
Found 1-bit register for signal <slv_reg12<25>>.
Found 1-bit register for signal <slv_reg12<26>>.
Found 1-bit register for signal <slv_reg12<27>>.
Found 1-bit register for signal <slv_reg12<28>>.
Found 1-bit register for signal <slv_reg12<29>>.
Found 1-bit register for signal <slv_reg12<30>>.
Found 1-bit register for signal <slv_reg12<31>>.
Found 1-bit register for signal <slv_reg13<0>>.
Found 1-bit register for signal <slv_reg13<1>>.
Found 1-bit register for signal <slv_reg13<2>>.
Found 1-bit register for signal <slv_reg13<3>>.
Found 1-bit register for signal <slv_reg13<4>>.
Found 1-bit register for signal <slv_reg13<5>>.
Found 1-bit register for signal <slv_reg13<6>>.
Found 1-bit register for signal <slv_reg13<7>>.
Found 1-bit register for signal <slv_reg13<8>>.
Found 1-bit register for signal <slv_reg13<9>>.
Found 1-bit register for signal <slv_reg13<10>>.
Found 1-bit register for signal <slv_reg13<11>>.
Found 1-bit register for signal <slv_reg13<12>>.
Found 1-bit register for signal <slv_reg13<13>>.
Found 1-bit register for signal <slv_reg13<14>>.
Found 1-bit register for signal <slv_reg13<15>>.
Found 1-bit register for signal <slv_reg13<16>>.
Found 1-bit register for signal <slv_reg13<17>>.
Found 1-bit register for signal <slv_reg13<18>>.
Found 1-bit register for signal <slv_reg13<19>>.
Found 1-bit register for signal <slv_reg13<20>>.
Found 1-bit register for signal <slv_reg13<21>>.
Found 1-bit register for signal <slv_reg13<22>>.
Found 1-bit register for signal <slv_reg13<23>>.
Found 1-bit register for signal <slv_reg13<24>>.
Found 1-bit register for signal <slv_reg13<25>>.
Found 1-bit register for signal <slv_reg13<26>>.
Found 1-bit register for signal <slv_reg13<27>>.
Found 1-bit register for signal <slv_reg13<28>>.
Found 1-bit register for signal <slv_reg13<29>>.
Found 1-bit register for signal <slv_reg13<30>>.
Found 1-bit register for signal <slv_reg13<31>>.
Found 1-bit register for signal <slv_reg14<0>>.
Found 1-bit register for signal <slv_reg14<1>>.
Found 1-bit register for signal <slv_reg14<2>>.
Found 1-bit register for signal <slv_reg14<3>>.
Found 1-bit register for signal <slv_reg14<4>>.
Found 1-bit register for signal <slv_reg14<5>>.
Found 1-bit register for signal <slv_reg14<6>>.
Found 1-bit register for signal <slv_reg14<7>>.
Found 1-bit register for signal <slv_reg14<8>>.
Found 1-bit register for signal <slv_reg14<9>>.
Found 1-bit register for signal <slv_reg14<10>>.
Found 1-bit register for signal <slv_reg14<11>>.
Found 1-bit register for signal <slv_reg14<12>>.
Found 1-bit register for signal <slv_reg14<13>>.
Found 1-bit register for signal <slv_reg14<14>>.
Found 1-bit register for signal <slv_reg14<15>>.
Found 1-bit register for signal <slv_reg14<16>>.
Found 1-bit register for signal <slv_reg14<17>>.
Found 1-bit register for signal <slv_reg14<18>>.
Found 1-bit register for signal <slv_reg14<19>>.
Found 1-bit register for signal <slv_reg14<20>>.
Found 1-bit register for signal <slv_reg14<21>>.
Found 1-bit register for signal <slv_reg14<22>>.
Found 1-bit register for signal <slv_reg14<23>>.
Found 1-bit register for signal <slv_reg14<24>>.
Found 1-bit register for signal <slv_reg14<25>>.
Found 1-bit register for signal <slv_reg14<26>>.
Found 1-bit register for signal <slv_reg14<27>>.
Found 1-bit register for signal <slv_reg14<28>>.
Found 1-bit register for signal <slv_reg14<29>>.
Found 1-bit register for signal <slv_reg14<30>>.
Found 1-bit register for signal <slv_reg14<31>>.
Found 1-bit register for signal <slv_reg15<0>>.
Found 1-bit register for signal <slv_reg15<1>>.
Found 1-bit register for signal <slv_reg15<2>>.
Found 1-bit register for signal <slv_reg15<3>>.
Found 1-bit register for signal <slv_reg15<4>>.
Found 1-bit register for signal <slv_reg15<5>>.
Found 1-bit register for signal <slv_reg15<6>>.
Found 1-bit register for signal <slv_reg15<7>>.
Found 1-bit register for signal <slv_reg15<8>>.
Found 1-bit register for signal <slv_reg15<9>>.
Found 1-bit register for signal <slv_reg15<10>>.
Found 1-bit register for signal <slv_reg15<11>>.
Found 1-bit register for signal <slv_reg15<12>>.
Found 1-bit register for signal <slv_reg15<13>>.
Found 1-bit register for signal <slv_reg15<14>>.
Found 1-bit register for signal <slv_reg15<15>>.
Found 1-bit register for signal <slv_reg15<16>>.
Found 1-bit register for signal <slv_reg15<17>>.
Found 1-bit register for signal <slv_reg15<18>>.
Found 1-bit register for signal <slv_reg15<19>>.
Found 1-bit register for signal <slv_reg15<20>>.
Found 1-bit register for signal <slv_reg15<21>>.
Found 1-bit register for signal <slv_reg15<22>>.
Found 1-bit register for signal <slv_reg15<23>>.
Found 1-bit register for signal <slv_reg15<24>>.
Found 1-bit register for signal <slv_reg15<25>>.
Found 1-bit register for signal <slv_reg15<26>>.
Found 1-bit register for signal <slv_reg15<27>>.
Found 1-bit register for signal <slv_reg15<28>>.
Found 1-bit register for signal <slv_reg15<29>>.
Found 1-bit register for signal <slv_reg15<30>>.
Found 1-bit register for signal <slv_reg15<31>>.
Found 2-bit register for signal <mem_read_prev>.
Summary:
inferred 514 D-type flip-flop(s).
inferred 530 Multiplexer(s).
Unit <user_logic> synthesized.
Synthesizing Unit <spiifc>.
Related source file is "c:/users/mjlyons/workspace/vspi/src/spi_base/spiifc.v".
AddrBits = 12
Found 1-bit register for signal <ssFastToggleReg>.
Found 1-bit register for signal <ssSlowToggle>.
Found 8-bit register for signal <rcByteReg>.
Found 1-bit register for signal <rcStarted>.
Found 3-bit register for signal <rcBitIndexReg>.
Found 8-bit register for signal <debug_reg>.
Found 8-bit register for signal <stateReg>.
Found 12-bit register for signal <rcMemAddrReg>.
Found 12-bit register for signal <txMemAddrReg>.
Found 3-bit register for signal <txBitAddr>.
Found 12-bit register for signal <rcMemAddrNext>.
Found 8-bit register for signal <rcMemDataReg>.
Found 1-bit register for signal <rcMemWEReg>.
Found 1-bit register for signal <ssPrev>.
Found 3-bit subtractor for signal <rcBitIndex[2]_GND_3_o_sub_17_OUT> created at line 184.
Found 12-bit adder for signal <txMemAddr[11]_GND_3_o_add_19_OUT> created at line 190.
Found 12-bit adder for signal <rcMemAddr[11]_GND_3_o_add_43_OUT> created at line 218.
Found 3-bit subtractor for signal <GND_3_o_GND_3_o_sub_22_OUT<2:0>> created at line 192.
Found 1-bit 8-to-1 multiplexer for signal <SPI_MISO> created at line 125.
Summary:
inferred 4 Adder/Subtractor(s).
inferred 79 D-type flip-flop(s).
inferred 28 Multiplexer(s).
Unit <spiifc> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# Adders/Subtractors : 4
12-bit adder : 2
3-bit subtractor : 2
# Registers : 31
1-bit register : 5
12-bit register : 3
2-bit register : 1
3-bit register : 2
32-bit register : 16
8-bit register : 4
# Multiplexers : 558
1-bit 2-to-1 multiplexer : 521
1-bit 8-to-1 multiplexer : 1
12-bit 2-to-1 multiplexer : 6
3-bit 2-to-1 multiplexer : 7
32-bit 2-to-1 multiplexer : 19
8-bit 2-to-1 multiplexer : 4
# Xors : 1
1-bit xor2 : 1
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
Reading core <ipcore_dir/buffermem.ngc>.
Loading core <buffermem> for timing and area information for instance <mosiMem>.
Loading core <buffermem> for timing and area information for instance <misoMem>.
WARNING:Xst:2677 - Node <rcByteReg_0> of sequential type is unconnected in block <spiifc>.
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# Adders/Subtractors : 4
12-bit adder : 2
3-bit subtractor : 2
# Registers : 592
Flip-Flops : 592
# Multiplexers : 557
1-bit 2-to-1 multiplexer : 520
1-bit 8-to-1 multiplexer : 1
12-bit 2-to-1 multiplexer : 6
3-bit 2-to-1 multiplexer : 7
32-bit 2-to-1 multiplexer : 19
8-bit 2-to-1 multiplexer : 4
# Xors : 1
1-bit xor2 : 1
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
Optimizing unit <user_logic> ...
Optimizing unit <spiifc> ...
WARNING:Xst:1710 - FF/Latch <stateReg_2> (without init value) has a constant value of 0 in block <spiifc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <stateReg_3> (without init value) has a constant value of 0 in block <spiifc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <stateReg_4> (without init value) has a constant value of 0 in block <spiifc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <stateReg_5> (without init value) has a constant value of 0 in block <spiifc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <stateReg_6> (without init value) has a constant value of 0 in block <spiifc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <stateReg_7> (without init value) has a constant value of 0 in block <spiifc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1710 - FF/Latch <stateReg_2> (without init value) has a constant value of 0 in block <spiifc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <stateReg_3> (without init value) has a constant value of 0 in block <spiifc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <stateReg_4> (without init value) has a constant value of 0 in block <spiifc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <stateReg_5> (without init value) has a constant value of 0 in block <spiifc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <stateReg_6> (without init value) has a constant value of 0 in block <spiifc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <stateReg_7> (without init value) has a constant value of 0 in block <spiifc>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <spi/debug_reg_7> of sequential type is unconnected in block <user_logic>.
WARNING:Xst:2677 - Node <spi/debug_reg_6> of sequential type is unconnected in block <user_logic>.
WARNING:Xst:2677 - Node <spi/debug_reg_5> of sequential type is unconnected in block <user_logic>.
WARNING:Xst:2677 - Node <spi/debug_reg_4> of sequential type is unconnected in block <user_logic>.
WARNING:Xst:2677 - Node <spi/debug_reg_3> of sequential type is unconnected in block <user_logic>.
WARNING:Xst:2677 - Node <spi/debug_reg_2> of sequential type is unconnected in block <user_logic>.
WARNING:Xst:2677 - Node <spi/debug_reg_1> of sequential type is unconnected in block <user_logic>.
WARNING:Xst:2677 - Node <spi/debug_reg_0> of sequential type is unconnected in block <user_logic>.
Mapping all equations...
Building and optimizing final netlist ...
PACKER Warning: Lut spi/Mmux_n010431 is driving XOR and other loads hence can not be packed with the XOR/Carry. This would result in an extra LUT for a feedthrough.
Found area constraint ratio of 100 (+ 5) on block user_logic, actual ratio is 5.
FlipFlop spi/rcByteReg_1 has been replicated 1 time(s)
Final Macro Processing ...
=========================================================================
Final Register Report
Macro Statistics
# Registers : 579
Flip-Flops : 579
=========================================================================
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Design Summary *
=========================================================================
Top Level Output File Name : user_logic.ngc
Primitive and Black Box Usage:
------------------------------
# BELS : 1131
# GND : 3
# INV : 3
# LUT1 : 10
# LUT2 : 21
# LUT3 : 12
# LUT4 : 530
# LUT5 : 122
# LUT6 : 382
# MUXCY : 22
# MUXF7 : 1
# VCC : 1
# XORCY : 24
# FlipFlops/Latches : 579
# FD : 16
# FDE : 37
# FDR : 515
# FDRE : 8
# FDSE : 3
# RAMS : 4
# RAMB16BWER : 4
# Clock Buffers : 2
# BUFGP : 2
# IO Buffers : 123
# IBUF : 86
# OBUF : 37
PACKER Warning: Lut spi/Mmux_n010431 is driving XOR and other loads hence can not be packed with the XOR/Carry. This would result in an extra LUT for a feedthrough.
Device utilization summary:
---------------------------
Selected Device : 6slx45csg324-2
Slice Logic Utilization:
Number of Slice Registers: 579 out of 54576 1%
Number of Slice LUTs: 1080 out of 27288 3%
Number used as Logic: 1080 out of 27288 3%
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 1097
Number with an unused Flip Flop: 518 out of 1097 47%
Number with an unused LUT: 17 out of 1097 1%
Number of fully used LUT-FF pairs: 562 out of 1097 51%
Number of unique control sets: 9
IO Utilization:
Number of IOs: 158
Number of bonded IOBs: 125 out of 218 57%
Specific Feature Utilization:
Number of Block RAM/FIFO: 4 out of 116 3%
Number using Block RAM only: 4
Number of BUFG/BUFGCTRLs: 2 out of 16 12%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=========================================================================
Timing Report
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
Bus2IP_Clk | BUFGP | 520 |
SPI_CLK | BUFGP | 63 |
-----------------------------------+------------------------+-------+
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -2
Minimum period: 6.130ns (Maximum Frequency: 163.132MHz)
Minimum input arrival time before clock: 9.060ns
Maximum output required time after clock: 8.612ns
Maximum combinational path delay: 15.761ns
Timing Details:
---------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'Bus2IP_Clk'
Clock period: 5.714ns (frequency: 175.009MHz)
Total number of paths / destination ports: 562 / 537
-------------------------------------------------------------------------
Delay: 5.714ns (Levels of Logic = 4)
Source: spi/ssPrev (FF)
Destination: misoMem/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram (RAM)
Source Clock: Bus2IP_Clk rising
Destination Clock: Bus2IP_Clk rising
Data Path: spi/ssPrev to misoMem/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 8 0.525 1.052 spi/ssPrev (spi/ssPrev)
LUT3:I1->O 9 0.250 1.204 spi/Mmux_ssFastToggle11 (spi/ssFastToggle)
LUT6:I3->O 12 0.235 1.069 spi/txMemAddrReset1 (spi/txMemAddrReset)
LUT2:I1->O 2 0.254 0.725 spi/Mmux_n010413 (misoMem_addra<11>)
begin scope: 'misoMem:addra<0>'
RAMB16BWER:ADDRA2 0.400 U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/s6_noinit.ram/TRUE_DP.PRIM18.ram
----------------------------------------
Total 5.714ns (1.664ns logic, 4.050ns route)
(29.1% logic, 70.9% route)
=========================================================================
Timing constraint: Default period analysis for Clock 'SPI_CLK'
Clock period: 6.130ns (frequency: 163.132MHz)
Total number of paths / destination ports: 2786 / 84
-------------------------------------------------------------------------
Delay: 6.130ns (Levels of Logic = 3)
Source: spi/ssSlowToggle (FF)
Destination: spi/txMemAddrReg_11 (FF)
Source Clock: SPI_CLK rising
Destination Clock: SPI_CLK rising
Data Path: spi/ssSlowToggle to spi/txMemAddrReg_11
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FD:C->Q 14 0.525 1.127 spi/ssSlowToggle (spi/ssSlowToggle)
LUT5:I4->O 6 0.254 1.104 spi/Mmux_state21 (spi/state<1>)
LUT6:I3->O 19 0.235 1.261 spi/Mmux_state[7]_state[7]_mux_55_OUT111 (spi/Mmux_state[7]_state[7]_mux_55_OUT11)
LUT6:I5->O 12 0.254 1.068 spi/_n0491_inv1 (spi/_n0491_inv)
FDE:CE 0.302 spi/txMemAddrReg_0
----------------------------------------
Total 6.130ns (1.570ns logic, 4.560ns route)
(25.6% logic, 74.4% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'Bus2IP_Clk'
Total number of paths / destination ports: 9953 / 1179
-------------------------------------------------------------------------
Offset: 9.060ns (Levels of Logic = 6)
Source: Bus2IP_WrCE<10> (PAD)
Destination: slv_reg5_31 (FF)
Destination Clock: Bus2IP_Clk rising
Data Path: Bus2IP_WrCE<10> to slv_reg5_31
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 68 1.328 2.391 Bus2IP_WrCE_10_IBUF (Bus2IP_WrCE_10_IBUF)
LUT6:I1->O 3 0.254 0.766 slv_reg_write_sel[0]_GND_1_o_equal_80_o<0>11 (slv_reg_write_sel[0]_GND_1_o_equal_80_o<0>1)
LUT4:I3->O 5 0.254 0.841 slv_reg_write_sel[0]_GND_1_o_equal_80_o<0>211 (slv_reg_write_sel[0]_GND_1_o_equal_80_o<0>21)
LUT5:I4->O 3 0.254 0.766 slv_reg_write_sel[0]_GND_1_o_equal_84_o<0>11 (slv_reg_write_sel[0]_GND_1_o_equal_84_o<0>1)
LUT4:I3->O 32 0.254 1.628 slv_reg_write_sel[0]_GND_1_o_equal_84_o<0>2 (slv_reg_write_sel[0]_GND_1_o_equal_84_o)
LUT4:I2->O 1 0.250 0.000 Mmux__n2030161 (_n2030<23>)
FDR:D 0.074 slv_reg5_23
----------------------------------------
Total 9.060ns (2.668ns logic, 6.392ns route)
(29.4% logic, 70.6% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'SPI_CLK'
Total number of paths / destination ports: 629 / 103
-------------------------------------------------------------------------
Offset: 8.484ns (Levels of Logic = 5)
Source: SPI_SS (PAD)
Destination: spi/txMemAddrReg_11 (FF)
Destination Clock: SPI_CLK rising
Data Path: SPI_SS to spi/txMemAddrReg_11
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 11 1.328 1.267 SPI_SS_IBUF (SPI_SS_IBUF)
LUT3:I0->O 9 0.235 1.431 spi/Mmux_ssFastToggle11 (spi/ssFastToggle)
LUT6:I0->O 2 0.254 0.834 spi/rcByteValid1_1 (spi/rcByteValid1)
LUT6:I4->O 19 0.250 1.261 spi/Mmux_state[7]_state[7]_mux_55_OUT111 (spi/Mmux_state[7]_state[7]_mux_55_OUT11)
LUT6:I5->O 12 0.254 1.068 spi/_n0491_inv1 (spi/_n0491_inv)
FDE:CE 0.302 spi/txMemAddrReg_0
----------------------------------------
Total 8.484ns (2.623ns logic, 5.861ns route)
(30.9% logic, 69.1% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'Bus2IP_Clk'
Total number of paths / destination ports: 650 / 34
-------------------------------------------------------------------------
Offset: 8.612ns (Levels of Logic = 5)
Source: slv_reg4_0 (FF)
Destination: IP2Bus_Data<0> (PAD)
Source Clock: Bus2IP_Clk rising
Data Path: slv_reg4_0 to IP2Bus_Data<0>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDR:C->Q 2 0.525 1.156 slv_reg4_0 (slv_reg4_0)
LUT5:I0->O 1 0.254 0.682 Mmux_IP2Bus_Data110 (Mmux_IP2Bus_Data1)
LUT6:I5->O 1 0.254 0.682 Mmux_IP2Bus_Data112 (Mmux_IP2Bus_Data12)
LUT6:I5->O 1 0.254 0.958 Mmux_IP2Bus_Data116 (Mmux_IP2Bus_Data16)
LUT6:I2->O 1 0.254 0.681 Mmux_IP2Bus_Data121 (IP2Bus_Data_0_OBUF)
OBUF:I->O 2.912 IP2Bus_Data_0_OBUF (IP2Bus_Data<0>)
----------------------------------------
Total 8.612ns (4.453ns logic, 4.159ns route)
(51.7% logic, 48.3% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'SPI_CLK'
Total number of paths / destination ports: 5 / 1
-------------------------------------------------------------------------
Offset: 5.953ns (Levels of Logic = 3)
Source: spi/txBitAddr_0 (FF)
Destination: SPI_MISO (PAD)
Source Clock: SPI_CLK rising
Data Path: spi/txBitAddr_0 to SPI_MISO
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDE:C->Q 9 0.525 1.406 spi/txBitAddr_0 (spi/txBitAddr_0)
LUT6:I1->O 1 0.254 0.000 spi/Mmux_SPI_MISO_3 (spi/Mmux_SPI_MISO_3)
MUXF7:I1->O 1 0.175 0.681 spi/Mmux_SPI_MISO_2_f7 (SPI_MISO_OBUF)
OBUF:I->O 2.912 SPI_MISO_OBUF (SPI_MISO)
----------------------------------------
Total 5.953ns (3.866ns logic, 2.087ns route)
(64.9% logic, 35.1% route)
=========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 4656 / 35
-------------------------------------------------------------------------
Delay: 15.761ns (Levels of Logic = 8)
Source: Bus2IP_RdCE<5> (PAD)
Destination: IP2Bus_Data<0> (PAD)
Data Path: Bus2IP_RdCE<5> to IP2Bus_Data<0>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 99 1.328 2.429 Bus2IP_RdCE_5_IBUF (Bus2IP_RdCE_5_IBUF)
LUT4:I1->O 33 0.235 1.537 slv_reg_read_sel[0]_GND_1_o_equal_129_o<0>21 (slv_reg_read_sel[0]_GND_1_o_equal_129_o<0>2)
LUT5:I4->O 35 0.254 1.846 slv_reg_read_sel[0]_GND_1_o_equal_136_o<0>11 (slv_reg_read_sel[0]_GND_1_o_equal_136_o<0>1)
LUT4:I0->O 32 0.254 1.950 slv_reg_read_sel[0]_GND_1_o_equal_140_o<0>11 (slv_reg_read_sel[0]_GND_1_o_equal_140_o<0>1)
LUT5:I0->O 1 0.254 0.682 Mmux_IP2Bus_Data119 (Mmux_IP2Bus_Data19)
LUT6:I5->O 1 0.254 0.910 Mmux_IP2Bus_Data120 (Mmux_IP2Bus_Data110)
LUT6:I3->O 1 0.235 0.681 Mmux_IP2Bus_Data121 (IP2Bus_Data_0_OBUF)
OBUF:I->O 2.912 IP2Bus_Data_0_OBUF (IP2Bus_Data<0>)
----------------------------------------
Total 15.761ns (5.726ns logic, 10.035ns route)
(36.3% logic, 63.7% route)
=========================================================================
Cross Clock Domains Report:
--------------------------
Clock to Setup on destination clock Bus2IP_Clk
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
Bus2IP_Clk | 5.714| | | |
SPI_CLK | 5.667| | | |
---------------+---------+---------+---------+---------+
Clock to Setup on destination clock SPI_CLK
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
Bus2IP_Clk | 7.481| | | |
SPI_CLK | 6.130| | | |
---------------+---------+---------+---------+---------+
=========================================================================
Total REAL time to Xst completion: 24.00 secs
Total CPU time to Xst completion: 23.64 secs
-->
Total memory usage is 255080 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 37 ( 0 filtered)
Number of infos : 2 ( 0 filtered)
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/user_logic.xst deleted 100644 → 0
View file @ 6bc46422
set -tmpdir "xst/projnav.tmp"
set -xsthdpdir "xst"
run
-ifn user_logic.prj
-ifmt mixed
-ofn user_logic
-ofmt NGC
-p xc6slx45-2-csg324
-top user_logic
-opt_mode Speed
-opt_level 1
-power NO
-iuc NO
-keep_hierarchy No
-netlist_hierarchy As_Optimized
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-sd {"ipcore_dir" }
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case Maintain
-slice_utilization_ratio 100
-bram_utilization_ratio 100
-dsp_utilization_ratio 100
-lc Auto
-reduce_control_sets Auto
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-fsm_style LUT
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-shreg_extract YES
-rom_style Auto
-auto_bram_packing NO
-resource_sharing YES
-async_to_sync NO
-shreg_min_size 2
-use_dsp48 Auto
-iobuf YES
-max_fanout 100000
-bufg 16
-register_duplication YES
-register_balancing No
-optimize_primitives NO
-use_clock_enable Auto
-use_sync_set Auto
-use_sync_reset Auto
-iob Auto
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5
projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/user_logic_xst.xrpt deleted 100644 → 0
View file @ 6bc46422
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="nt64" product="ISE" version="13.2">
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Xst" timeStamp="Thu Mar 01 10:48:00 2012">
<section stringID="User_Env">
<table stringID="User_EnvVar">
<column stringID="variable"/>
<column stringID="value"/>
<row stringID="row" value="0">
<item stringID="variable" value="Path"/>
<item stringID="value" value="C:\Xilinx\13.2\ISE_DS\ISE\\lib\nt64;C:\Xilinx\13.2\ISE_DS\ISE\\bin\nt64;C:\Xilinx\13.2\ISE_DS\PlanAhead\bin;C:\Xilinx\13.2\ISE_DS\ISE\bin\nt64;C:\Xilinx\13.2\ISE_DS\ISE\lib\nt64;C:\Xilinx\13.2\ISE_DS\EDK\bin\nt64;C:\Xilinx\13.2\ISE_DS\EDK\lib\nt64;C:\Xilinx\13.2\ISE_DS\EDK\gnu\microblaze\nt64\bin;C:\Xilinx\13.2\ISE_DS\EDK\gnu\powerpc-eabi\nt64\bin;C:\Xilinx\13.2\ISE_DS\EDK\gnuwin\bin;C:\Xilinx\13.2\ISE_DS\common\bin\nt64;C:\Xilinx\13.2\ISE_DS\common\lib\nt64;C:\Program Files (x86)\Atmel\AVR Tools\AVR Toolchain\bin;C:\Windows\system32;C:\Windows;C:\Windows\System32\Wbem;C:\Windows\System32\WindowsPowerShell\v1.0\;C:\Program Files (x86)\Java\jdk1.6.0_26\bin;c:\python27;C:\Python27\Scripts;C:\Program Files\SlikSvn\bin\;C:\Program Files (x86)\GnuWin32\bin;C:\Program Files\Vim\vim73;c:\Program Files (x86)\Microsoft SQL Server\100\Tools\Binn\;c:\Program Files\Microsoft SQL Server\100\Tools\Binn\;c:\Program Files\Microsoft SQL Server\100\DTS\Binn\;c:\Program Files\TortoiseSVN\bin"/>
</row>
<row stringID="row" value="1">
<item stringID="variable" value="PATHEXT"/>
<item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC"/>
</row>
<row stringID="row" value="2">
<item stringID="variable" value="XILINX"/>
<item stringID="value" value="C:\Xilinx\13.2\ISE_DS\ISE\"/>
</row>
<row stringID="row" value="3">
<item stringID="variable" value="XILINX_DSP"/>
<item stringID="value" value="C:\Xilinx\13.2\ISE_DS\ISE"/>
</row>
<row stringID="row" value="4">
<item stringID="variable" value="XILINX_EDK"/>
<item stringID="value" value="C:\Xilinx\13.2\ISE_DS\EDK"/>
</row>
<row stringID="row" value="5">
<item stringID="variable" value="XILINX_FOR_ALTIUM_OVERRIDE"/>
<item stringID="value" value=" "/>
</row>
<row stringID="row" value="6">
<item stringID="variable" value="XILINX_PLANAHEAD"/>
<item stringID="value" value="C:\Xilinx\13.2\ISE_DS\PlanAhead"/>
</row>
</table>
<item stringID="User_EnvOs" value="OS Information">
<item stringID="User_EnvOsname" value="Microsoft Windows 7 , 64-bit"/>
<item stringID="User_EnvOsrelease" value="Service Pack 1 (build 7601)"/>
</item>
<item stringID="User_EnvHost" value="WIN-MEQROG0RPAS"/>
<table stringID="User_EnvCpu">
<column stringID="arch"/>
<column stringID="speed"/>
<row stringID="row" value="0">
<item stringID="arch" value="Intel(R) Core(TM) i5-2400S CPU @ 2.50GHz"/>
<item stringID="speed" value="2499 MHz"/>
</row>
</table>
</section>
<section stringID="XST_OPTION_SUMMARY">
<item DEFAULT="" label="-ifn" stringID="XST_IFN" value="user_logic.prj"/>
<item DEFAULT="Mixed" label="-ifmt" stringID="XST_IFMT" value="mixed"/>
<item DEFAULT="" label="-ofn" stringID="XST_OFN" value="user_logic"/>
<item DEFAULT="NGC" label="-ofmt" stringID="XST_OFMT" value="NGC"/>
<item DEFAULT="" label="-p" stringID="XST_P" value="xc6slx45-2-csg324"/>
<item DEFAULT="" label="-top" stringID="XST_TOP" value="user_logic"/>
<item DEFAULT="Speed" label="-opt_mode" stringID="XST_OPTMODE" value="Speed"/>
<item DEFAULT="1" label="-opt_level" stringID="XST_OPTLEVEL" value="1"/>
<item DEFAULT="No" label="-power" stringID="XST_POWER" value="NO"/>
<item DEFAULT="No" label="-iuc" stringID="XST_IUC" value="NO"/>
<item DEFAULT="No" label="-keep_hierarchy" stringID="XST_KEEPHIERARCHY" value="No"/>
<item DEFAULT="As_Optimized" label="-netlist_hierarchy" stringID="XST_NETLISTHIERARCHY" value="As_Optimized"/>
<item DEFAULT="No" label="-rtlview" stringID="XST_RTLVIEW" value="Yes"/>
<item DEFAULT="AllClockNets" label="-glob_opt" stringID="XST_GLOBOPT" value="AllClockNets"/>
<item DEFAULT="Yes" label="-read_cores" stringID="XST_READCORES" value="YES"/>
<item DEFAULT="" label="-sd" stringID="XST_SD" value="{&quot;ipcore_dir&quot; }"/>
<item DEFAULT="No" label="-write_timing_constraints" stringID="XST_WRITETIMINGCONSTRAINTS" value="NO"/>
<item DEFAULT="No" label="-cross_clock_analysis" stringID="XST_CROSSCLOCKANALYSIS" value="NO"/>
<item DEFAULT="/" stringID="XST_HIERARCHYSEPARATOR" value="/"/>
<item DEFAULT="&lt;>" label="-bus_delimiter" stringID="XST_BUSDELIMITER" value="&lt;>"/>
<item DEFAULT="Maintain" stringID="XST_CASE" value="Maintain"/>
<item DEFAULT="100" label="-slice_utilization_ratio" stringID="XST_SLICEUTILIZATIONRATIO" value="100"/>
<item DEFAULT="100" label="-bram_utilization_ratio" stringID="XST_BRAMUTILIZATIONRATIO" value="100"/>
<item DEFAULT="100" label="-dsp_utilization_ratio" stringID="XST_DSPUTILIZATIONRATIO" value="100"/>
<item DEFAULT="Auto" stringID="XST_LC" value="Auto"/>
<item DEFAULT="Auto" label="-reduce_control_sets" stringID="XST_REDUCECONTROLSETS" value="Auto"/>
<item DEFAULT="Yes" label="-fsm_extract" stringID="XST_FSMEXTRACT" value="YES"/>
<item DEFAULT="Auto" label="-fsm_encoding" stringID="XST_FSMENCODING" value="Auto"/>
<item DEFAULT="No" label="-safe_implementation" stringID="XST_SAFEIMPLEMENTATION" value="No"/>
<item DEFAULT="LUT" label="-fsm_style" stringID="XST_FSMSTYLE" value="LUT"/>
<item DEFAULT="Yes" label="-ram_extract" stringID="XST_RAMEXTRACT" value="Yes"/>
<item DEFAULT="Auto" label="-ram_style" stringID="XST_RAMSTYLE" value="Auto"/>
<item DEFAULT="Yes" label="-rom_extract" stringID="XST_ROMEXTRACT" value="Yes"/>
<item DEFAULT="Yes" label="-shreg_extract" stringID="XST_SHREGEXTRACT" value="YES"/>
<item DEFAULT="Auto" label="-rom_style" stringID="XST_ROMSTYLE" value="Auto"/>
<item DEFAULT="No" label="-auto_bram_packing" stringID="XST_AUTOBRAMPACKING" value="NO"/>
<item DEFAULT="Yes" label="-resource_sharing" stringID="XST_RESOURCESHARING" value="YES"/>
<item DEFAULT="No" label="-async_to_sync" stringID="XST_ASYNCTOSYNC" value="NO"/>
<item DEFAULT="2" stringID="XST_SHREGMINSIZE" value="2"/>
<item DEFAULT="Auto" label="-use_dsp48" stringID="XST_USEDSP48" value="Auto"/>
<item DEFAULT="Yes" label="-iobuf" stringID="XST_IOBUF" value="YES"/>
<item DEFAULT="100000" label="-max_fanout" stringID="XST_MAXFANOUT" value="100000"/>
<item DEFAULT="16" label="-bufg" stringID="XST_BUFG" value="16"/>
<item DEFAULT="Yes" label="-register_duplication" stringID="XST_REGISTERDUPLICATION" value="YES"/>
<item DEFAULT="No" label="-register_balancing" stringID="XST_REGISTERBALANCING" value="No"/>
<item DEFAULT="No" label="-optimize_primitives" stringID="XST_OPTIMIZEPRIMITIVES" value="NO"/>
<item DEFAULT="Auto" label="-use_clock_enable" stringID="XST_USECLOCKENABLE" value="Auto"/>
<item DEFAULT="Auto" label="-use_sync_set" stringID="XST_USESYNCSET" value="Auto"/>
<item DEFAULT="Auto" label="-use_sync_reset" stringID="XST_USESYNCRESET" value="Auto"/>
<item DEFAULT="Auto" label="-iob" stringID="XST_IOB" value="Auto"/>
<item DEFAULT="Yes" label="-equivalent_register_removal" stringID="XST_EQUIVALENTREGISTERREMOVAL" value="YES"/>
<item DEFAULT="0" label="-slice_utilization_ratio_maxmargin" stringID="XST_SLICEUTILIZATIONRATIOMAXMARGIN" value="5"/>
</section>
<section stringID="XST_HDL_SYNTHESIS_REPORT">
<item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="4">
<item dataType="int" stringID="XST_3BIT_SUBTRACTOR" value="2"/>
</item>
<item dataType="int" stringID="XST_REGISTERS" value="31">
<item dataType="int" stringID="XST_1BIT_REGISTER" value="5"/>
<item dataType="int" stringID="XST_2BIT_REGISTER" value="1"/>
<item dataType="int" stringID="XST_3BIT_REGISTER" value="2"/>
<item dataType="int" stringID="XST_32BIT_REGISTER" value="16"/>
<item dataType="int" stringID="XST_8BIT_REGISTER" value="4"/>
</item>
<item dataType="int" stringID="XST_MULTIPLEXERS" value="558">
<item dataType="int" stringID="XST_1BIT_2TO1_MULTIPLEXER" value="521"/>
<item dataType="int" stringID="XST_1BIT_8TO1_MULTIPLEXER" value="1"/>
<item dataType="int" stringID="XST_3BIT_2TO1_MULTIPLEXER" value="7"/>
<item dataType="int" stringID="XST_32BIT_2TO1_MULTIPLEXER" value="19"/>
<item dataType="int" stringID="XST_8BIT_2TO1_MULTIPLEXER" value="4"/>
</item>
<item dataType="int" stringID="XST_XORS" value="1">
<item dataType="int" stringID="XST_1BIT_XOR2" value="1"/>
</item>
</section>
<section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORT">
<item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="4">
<item dataType="int" stringID="XST_3BIT_SUBTRACTOR" value="2"/>
</item>
<item dataType="int" stringID="XST_REGISTERS" value="592">
<item dataType="int" stringID="XST_FLIPFLOPS" value="592"/>
</item>
<item dataType="int" stringID="XST_MULTIPLEXERS" value="557">
<item dataType="int" stringID="XST_1BIT_2TO1_MULTIPLEXER" value="520"/>
<item dataType="int" stringID="XST_1BIT_8TO1_MULTIPLEXER" value="1"/>
<item dataType="int" stringID="XST_3BIT_2TO1_MULTIPLEXER" value="7"/>
<item dataType="int" stringID="XST_32BIT_2TO1_MULTIPLEXER" value="19"/>
<item dataType="int" stringID="XST_8BIT_2TO1_MULTIPLEXER" value="4"/>
</item>
<item dataType="int" stringID="XST_XORS" value="1">
<item dataType="int" stringID="XST_1BIT_XOR2" value="1"/>
</item>
</section>
<section stringID="XST_FINAL_REGISTER_REPORT">
<item dataType="int" stringID="XST_REGISTERS" value="579">
<item dataType="int" stringID="XST_FLIPFLOPS" value="579"/>
</item>
</section>
<section stringID="XST_PARTITION_REPORT">
<section stringID="XST_PARTITION_IMPLEMENTATION_STATUS">
<section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
</section>
</section>
<section stringID="XST_DESIGN_SUMMARY">
<section stringID="XST_">
<item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="user_logic.ngc"/>
</section>
<section stringID="XST_PRIMITIVE_AND_BLACK_BOX_USAGE">
<item dataType="int" stringID="XST_BELS" value="1131">
<item dataType="int" stringID="XST_GND" value="3"/>
<item dataType="int" stringID="XST_INV" value="3"/>
<item dataType="int" stringID="XST_LUT1" value="10"/>
<item dataType="int" stringID="XST_LUT2" value="21"/>
<item dataType="int" stringID="XST_LUT3" value="12"/>
<item dataType="int" stringID="XST_LUT4" value="530"/>
<item dataType="int" stringID="XST_LUT5" value="122"/>
<item dataType="int" stringID="XST_LUT6" value="382"/>
<item dataType="int" stringID="XST_MUXCY" value="22"/>
<item dataType="int" stringID="XST_MUXF7" value="1"/>
<item dataType="int" stringID="XST_VCC" value="1"/>
<item dataType="int" stringID="XST_XORCY" value="24"/>
</item>
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="579">
<item dataType="int" stringID="XST_FD" value="16"/>
<item dataType="int" stringID="XST_FDE" value="37"/>
<item dataType="int" stringID="XST_FDR" value="515"/>
<item dataType="int" stringID="XST_FDRE" value="8"/>
<item dataType="int" stringID="XST_FDSE" value="3"/>
</item>
<item dataType="int" stringID="XST_RAMS" value="4">
<item dataType="int" stringID="XST_RAMB16BWER" value="4"/>
</item>
<item dataType="int" stringID="XST_CLOCK_BUFFERS" value="2">
<item dataType="int" stringID="XST_BUFGP" value="2"/>
</item>
<item dataType="int" stringID="XST_IO_BUFFERS" value="123">
<item dataType="int" stringID="XST_IBUF" value="86"/>
<item dataType="int" stringID="XST_OBUF" value="37"/>
</item>
</section>
</section>
<section stringID="XST_DEVICE_UTILIZATION_SUMMARY">
<item stringID="XST_SELECTED_DEVICE" value="6slx45csg324-2"/>
<item AVAILABLE="54576" dataType="int" label="Number of Slice Registers" stringID="XST_NUMBER_OF_SLICE_REGISTERS" value="579"/>
<item AVAILABLE="27288" dataType="int" label="Number of Slice LUTs" stringID="XST_NUMBER_OF_SLICE_LUTS" value="1080"/>
<item AVAILABLE="27288" dataType="int" label="Number used as Logic" stringID="XST_NUMBER_USED_AS_LOGIC" value="1080"/>
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="XST_NUMBER_OF_LUT_FLIP_FLOP_PAIRS_USED" value="1097"/>
<item AVAILABLE="1097" dataType="int" label="Number with an unused Flip Flop" stringID="XST_NUMBER_WITH_AN_UNUSED_FLIP_FLOP" value="518"/>
<item AVAILABLE="1097" dataType="int" label="Number with an unused LUT" stringID="XST_NUMBER_WITH_AN_UNUSED_LUT" value="17"/>
<item AVAILABLE="1097" dataType="int" label="Number of fully used LUT-FF pairs" stringID="XST_NUMBER_OF_FULLY_USED_LUTFF_PAIRS" value="562"/>
<item dataType="int" label="Number of unique control sets" stringID="XST_NUMBER_OF_UNIQUE_CONTROL_SETS" value="9"/>
<item dataType="int" label="Number of IOs" stringID="XST_NUMBER_OF_IOS" value="158"/>
<item AVAILABLE="218" dataType="int" label="Number of bonded IOBs" stringID="XST_NUMBER_OF_BONDED_IOBS" value="125"/>
<item AVAILABLE="116" dataType="int" label="Number of Block RAM/FIFO" stringID="XST_NUMBER_OF_BLOCK_RAMFIFO" value="4"/>
<item dataType="int" label="Number using Block RAM only" stringID="XST_NUMBER_USING_BLOCK_RAM_ONLY" value="4"/>
<item AVAILABLE="16" dataType="int" label="Number of BUFG/BUFGCTRLs" stringID="XST_NUMBER_OF_BUFGBUFGCTRLS" value="2"/>
</section>
<section stringID="XST_PARTITION_RESOURCE_SUMMARY">
<section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
</section>
<section stringID="XST_ERRORS_STATISTICS">
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="37"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="2"/>
</section>
</application>
</document>
projnav/xps/pcores/spiifc_v1_00_a/hdl/verilog/spiifc.v
View file @ 05b98f2c
......@@ -3,7 +3,7 @@
// Company:
// Engineer:
//
// Create Date: 19:24:33 10/18/2011
// Create Date: 16:46:12 03/02/2012
// Design Name:
// Module Name: spiifc
// Project Name:
......@@ -30,453 +30,259 @@ module spiifc(
rcMemAddr,
rcMemData,
rcMemWE,
regAddr,
regReadData,
regWriteEn,
regWriteData,
debug_out
);
//
// Parameters
//
parameter AddrBits = 12;
// Defines
`define CMD_READ_START 8'd1
`define CMD_READ_MORE 8'd2
`define CMD_WRITE_START 8'd3
`define STATE_GET_CMD 8'd0
`define STATE_READING 8'd1
`define STATE_WRITING 8'd2
//
// Input/Output defs
//
input Reset;
input SysClk;
input SPI_CLK;
output SPI_MISO;
input SPI_MOSI;
input SPI_SS;
output [AddrBits-1:0] txMemAddr;
input [7:0] txMemData;
output [AddrBits-1:0] rcMemAddr;
output [7:0] rcMemData;
output rcMemWE;
output [7:0] debug_out;
//
// Registers
//
reg [ 7: 0] debug_reg;
reg [ 7: 0] rcByteReg;
reg rcStarted;
reg [ 2: 0] rcBitIndexReg;
reg [11: 0] rcMemAddrReg;
reg [11: 0] rcMemAddrNext;
reg [ 7: 0] rcMemDataReg;
reg rcMemWEReg;
reg ssPrev;
reg ssFastToggleReg;
reg ssSlowToggle;
reg ssTurnOnReg;
reg ssTurnOnHandled;
reg [ 7: 0] cmd;
reg [ 7: 0] stateReg;
reg [11: 0] txMemAddrReg;
reg [ 2: 0] txBitAddr;
//
// Wires
//
wire rcByteValid;
wire [ 7: 0] rcByte;
wire rcStarting;
wire [ 2: 0] rcBitIndex;
wire ssTurnOn;
wire ssFastToggle;
wire [ 7: 0] state;
wire txMemAddrReset;
//
// Output assigns
//
assign debug_out = debug_reg;
assign rcMemAddr = rcMemAddrReg;
assign rcMemData = rcMemDataReg;
assign rcMemWE = rcMemWEReg;
assign txMemAddrReset = (rcByteValid && rcByte == `CMD_WRITE_START ? 1 : 0);
assign txMemAddr = (txMemAddrReset ? 0 : txMemAddrReg);
assign SPI_MISO = txMemData[txBitAddr];
assign ssFastToggle =
(ssPrev == 1 && SPI_SS == 0 ? ~ssFastToggleReg : ssFastToggleReg);
//
// Wire assigns
//
assign rcByteValid = rcStarted && rcBitIndex == 0;
assign rcByte = {rcByteReg[7:1], SPI_MOSI};
assign rcStarting = ssTurnOn;
assign rcBitIndex = (rcStarting ? 3'd7 : rcBitIndexReg);
assign ssTurnOn = ssSlowToggle ^ ssFastToggle;
assign state = (rcStarting ? `STATE_GET_CMD : stateReg);
initial begin
ssSlowToggle <= 0;
end
always @(posedge SysClk) begin
ssPrev <= SPI_SS;
if (Reset) begin
ssTurnOnReg <= 0;
ssFastToggleReg <= 0;
end else begin
if (ssPrev & (~SPI_SS)) begin
ssTurnOnReg <= 1;
ssFastToggleReg <= ~ssFastToggleReg;
end else if (ssTurnOnHandled) begin
ssTurnOnReg <= 0;
end
end
end
always @(posedge SPI_CLK) begin
ssSlowToggle <= ssFastToggle;
if (Reset) begin
// Resetting
rcByteReg <= 8'h00;
rcStarted <= 0;
rcBitIndexReg <= 3'd7;
ssTurnOnHandled <= 0;
debug_reg <= 8'hFF;
end else begin
// Not resetting
ssTurnOnHandled <= ssTurnOn;
stateReg <= state;
rcMemAddrReg <= rcMemAddrNext;
if (~SPI_SS) begin
rcByteReg[rcBitIndex] <= SPI_MOSI;
rcBitIndexReg <= rcBitIndex - 3'd1;
rcStarted <= 1;
// Update txBitAddr if writing out
if (`STATE_WRITING == state) begin
if (txBitAddr == 3'd1) begin
txMemAddrReg <= txMemAddr + 1;
end
txBitAddr <= txBitAddr - 1;
end
end
// We've just received a byte (well, currently receiving the last bit)
if (rcByteValid) begin
// For now, just display on LEDs
debug_reg <= rcByte;
if (`STATE_GET_CMD == state) begin
cmd <= rcByte; // Will take effect next cycle
if (`CMD_READ_START == rcByte) begin
rcMemAddrNext <= 0;
stateReg <= `STATE_READING;
end else if (`CMD_READ_MORE == rcByte) begin
stateReg <= `STATE_READING;
end else if (`CMD_WRITE_START == rcByte) begin
txBitAddr <= 3'd7;
stateReg <= `STATE_WRITING;
txMemAddrReg <= txMemAddr; // Keep at 0
end
end else if (`STATE_READING == state) begin
rcMemDataReg <= rcByte;
rcMemAddrNext <= rcMemAddr + 1;
rcMemWEReg <= 1;
// end else if (`STATE_WRITING == state) begin
// txBitAddr <= 3'd7;
// stateReg <= `STATE_WRITING;
end
end else begin
// Not a valid byte
rcMemWEReg <= 0;
end // valid/valid' byte
end // Reset/Reset'
end
/*
reg rcByte_valid;
wire rcClockBridgeEmpty;
wire readRcByte;
assign getRcByte = ~rcClockBridgeEmpty;
wire rcClockBridgeReadValid;
wire rcClockBridgeFull;
wire [7:0] rcByte;
clock_bridge recvClockBridge (
.rst(Reset), // input rst
.wr_clk(~SPI_CLK), // input wr_clk
.rd_clk(SysClk), // input rd_clk
.din(SPI_MOSI), // input [0 : 0] din
.wr_en(~SPI_SS), // input wr_en
.rd_en(getRcByte), // input rd_en
.dout(rcByte), // output [7 : 0] dout
.full(rcClockBridgeFull), // output full
.empty(rcClockBridgeEmpty), // output empty
.valid(rcClockBridgeReadValid) // output valid
);
//
// Parameters
//
parameter AddrBits = 12;
parameter RegAddrBits = 4;
//
// Defines
//
`define CMD_READ_START 8'd1
`define CMD_READ_MORE 8'd2
`define CMD_WRITE_START 8'd3
`define CMD_WRITE_MORE 8'd4
`define CMD_INTERRUPT 8'd5
`define CMD_REG_BASE 8'd128
`define CMD_REG_BIT 7
`define CMD_REG_WE_BIT 6
`define CMD_REG_ID_MASK 8'h3F
`define STATE_GET_CMD 8'd0
`define STATE_READING 8'd1
`define STATE_WRITING 8'd2
`define STATE_WRITE_INTR 8'd3
`define STATE_BUILD_WORD 8'd4
`define STATE_SEND_WORD 8'd5
//
// Input/Outputs
//
input Reset;
input SysClk;
input SPI_CLK;
output SPI_MISO; // outgoing (from respect of this module)
input SPI_MOSI; // incoming (from respect of this module)
input SPI_SS;
output [AddrBits-1:0] txMemAddr; // outgoing data
input [7:0] txMemData;
output [AddrBits-1:0] rcMemAddr; // incoming data
output [7:0] rcMemData;
output rcMemWE;
output [RegAddrBits-1:0] regAddr; // Register read address (combinational)
input [31:0] regReadData; // Result of register read
output regWriteEn; // Enable write to register, otherwise read
output [31:0] regWriteData; // Register write data
output [7:0] debug_out;
//
// Registers
//
reg SPI_CLK_reg; // Stabalized version of SPI_CLK
reg SPI_SS_reg; // Stabalized version of SPI_SS
reg SPI_MOSI_reg; // Stabalized version of SPI_MOSI
reg prev_spiClk; // Value of SPI_CLK during last SysClk cycle
reg prev_spiSS; // Value of SPI_SS during last SysClk cycle
reg [7:0] state_reg; // Register backing the 'state' wire
reg [7:0] rcByte_reg; // Register backing 'rcByte'
reg [2:0] rcBitIndex_reg; // Register backing 'rcBitIndex'
reg [AddrBits-1:0] rcMemAddr_reg; // Byte addr to write MOSI data to
reg [7:0] debug_reg; // register backing debug_out signal
reg [2:0] txBitIndex_reg; // Register backing txBitIndex
reg [AddrBits-1:0] txMemAddr_reg; // Register backing txAddr
reg [7:0] command; // Command being handled
reg [31:0] rcWord; // Incoming word being built
reg [1:0] rcWordByteId; // Which byte the in the rcWord to map to
reg [RegAddrBits-1:0] regAddr_reg; // Address of register to read/write to
//
// Wires
//
wire risingSpiClk; // Did the SPI_CLK rise since last SysClk cycle?
wire validSpiBit; // Are the SPI MOSI/MISO bits new and valid?
reg [7:0] state; // Current state in the module's state machine (always @* effectively wire)
wire rcByteValid; // rcByte is valid and new
wire [7:0] rcByte; // Byte received from master
wire [2:0] rcBitIndex; // Bit of rcByte to write to next
reg [2:0] txBitIndex; // bit of txByte to send to master next
reg [AddrBits-1:0] txMemAddr_oreg; // Wirereg piped to txMemAddr output
reg [7:0] regReadByte_oreg; // Which byte of the reg word we're reading out master
// Save buffered SPI inputs
always @(posedge SysClk) begin
rcByte_valid <= getRcByte;
SPI_CLK_reg <= SPI_CLK;
SPI_SS_reg <= SPI_SS;
SPI_MOSI_reg <= SPI_MOSI;
end
wire txCmdClkBridgeEmpty;
wire txCmdClkBridgeFull;
wire [7:0] txCmd;
wire txCmdValid;
assign txCmdValid = ~txCmdClkBridgeEmpty;
wire postTxCmd;
assign postTxCmd =
fifo_8bit_to_8bit txCmdClkBridge(
.rst(Reset), // input rst
.wr_clk(SysClk), // input wr_clk
.rd_clk(SPI_CLK), // input rd_clk
.din(din), // input [7 : 0] din
.wr_en(post), // input wr_en
.rd_en(txCmdValid), // input rd_en
.dout(txCmd), // output [7 : 0] dout
.full(txCmdClkBridgeFull), // output full
.empty(txCmdClkBridgeEmpty) // output empty
);
// Detect new valid bit
always @(posedge SysClk) begin
prev_spiClk <= SPI_CLK_reg;
end
assign risingSpiClk = SPI_CLK_reg & (~prev_spiClk);
assign validSpiBit = risingSpiClk & (~SPI_SS_reg);
// Detect new SPI packet (SS dropped low)
always @(posedge SysClk) begin
prev_spiSS <= SPI_SS_reg;
end
assign packetStart = prev_spiSS & (~SPI_SS_reg);
//
// TRANSMIT: FPGA TO PC
//
assign SPI_MISO = txMemData[bitIndex];
reg [2:0] bitIndex;
reg [AddrBits-1:0] byteAddr;
assign txMemAddr = byteAddr;
reg [7:0] debug_reg;
assign debug_out = debug_reg;
// Build incoming byte
always @(posedge SysClk) begin
if (validSpiBit) begin
rcByte_reg[rcBitIndex] <= SPI_MOSI_reg;
rcBitIndex_reg <= (rcBitIndex > 0 ? rcBitIndex - 1 : 7);
end else begin
rcBitIndex_reg <= rcBitIndex;
end
end
assign rcBitIndex = (Reset || packetStart ? 7 : rcBitIndex_reg);
assign rcByte = {rcByte_reg[7:1], SPI_MOSI_reg};
assign rcByteValid = (validSpiBit && rcBitIndex == 0 ? 1 : 0);
initial begin
debug_reg <= 8'h00;
//rcState <= 0;
// Incoming MOSI data buffer management
assign rcMemAddr = rcMemAddr_reg;
assign rcMemData = rcByte;
assign rcMemWE = (state == `STATE_READING && rcByteValid ? 1 : 0);
always @(posedge SysClk) begin
if (Reset || (`STATE_GET_CMD == state && rcByteValid)) begin
rcMemAddr_reg <= 0;
end else if (rcMemWE) begin
rcMemAddr_reg <= rcMemAddr + 1;
end else begin
rcMemAddr_reg <= rcMemAddr;
end
end
//
// Clocked logic
//
always @(posedge SPI_CLK) begin
if (Reset) begin
bitIndex <= 3'd0;
byteAddr <= 0;
end else if (SPI_SS == 1'b0) begin
bitIndex <= bitIndex - 3'd1;
if (bitIndex == 3'd1) begin
byteAddr <= byteAddr + 1;
end
// Outgoing MISO data buffer management
always @(*) begin
if (Reset || (state == `STATE_GET_CMD && rcByteValid &&
(rcByte == `CMD_WRITE_START ||
rcByte[`CMD_REG_BIT:`CMD_REG_WE_BIT] == 2'b11)
)) begin
txBitIndex <= 3'd7;
txMemAddr_oreg <= 0;
end else begin
txBitIndex <= txBitIndex_reg;
//txMemAddr_oreg <= txMemAddr_reg;
if ((state == `STATE_WRITING || state == `STATE_SEND_WORD) &&
validSpiBit && txBitIndex == 0) begin
txMemAddr_oreg <= txMemAddr_reg + 1;
end else begin
txMemAddr_oreg <= txMemAddr_reg;
end
end
//
// RECEIVE: PC TO FPGA
//
// Detect start of receive
reg ss_prev;
wire ss_negedge;
always @(posedge SysClk) begin
ss_prev <= SPI_SS;
end
always @(posedge SysClk) begin
if (validSpiBit && (state == `STATE_WRITING || state == `STATE_SEND_WORD)) begin
txBitIndex_reg <= (txBitIndex == 0 ? 7 : txBitIndex - 1);
end else begin
txBitIndex_reg <= txBitIndex;
end
assign ss_negedge = (ss_prev == 1'b1 && SPI_SS == 1'b0 ? 1'b1 : 1'b0);
`define RC_MODE_GET_STATUS 8'd0
`define RC_MODE_GET_BUFFER 8'd1
`define RC_MODE_PUT_BUFFER 8'd2
reg [7:0] rcMode;
`define RC_STATE_CMD 8'd0
`define RC_STATE_SIZE 8'd1
`define RC_STATE_PAYLOAD 8'd2
reg [7:0] rcState;
reg [31:0] rcByteCount;
reg [31:0] rcByteSize;
reg [7:0] rcMemData_reg;
reg [AddrBits-1:0] rcMemAddr_reg;
reg rcMemWE_reg;
assign rcMemData = rcMemData_reg;
assign rcMemAddr = rcMemAddr_reg;
assign rcMemWE = rcMemWE_reg;
always @(posedge SysClk) begin
// // About to receive
// if (ss_negedge) begin
// rcBitIndex <= 3'd7;
// rcState <= `RC_STATE_CMD;
//
// debug_reg[0] <= 1;
// end
//
// // Receiving
// if (receiving) begin
// rcByte[rcBitIndex] <= SPI_MOSI;
// rcBitIndex <= rcBitIndex - 3'd1;
// end
// rcByte_valid <= (receiving && rcBitIndex == 3'd0 ? 1'b1 : 1'b0);
// Handle the complete incoming byte
if (rcByte_valid) begin
debug_reg[7:4] <= rcByte[3:0];
// First byte: the command
if (`RC_STATE_CMD == rcState || ss_negedge) begin
// Disable writing to the read buffer (will be left on if the prev
// cycle was writing to it)
rcMemWE_reg <= 1'b0;
txMemAddr_reg <= txMemAddr;
// if (state == `STATE_WRITING && validSpiBit && txBitIndex == 0) begin
// txMemAddr_reg <= txMemAddr + 1;
// end else begin
// txMemAddr_reg <= txMemAddr;
// end
end
assign txMemAddr = txMemAddr_oreg;
assign SPI_MISO = (state == `STATE_SEND_WORD ? regReadByte_oreg[txBitIndex] : txMemData[txBitIndex]);
debug_reg[0] <= 1;
// State machine
always @(*) begin
if (Reset || packetStart) begin
state <= `STATE_GET_CMD;
// Handled in state_reg logic, should be latched, not immediate.
// end else if (state_reg == `STATE_GET_CMD && rcByteValid) begin
// state <= rcByte;
end else begin
state <= state_reg;
end
end
always @(posedge SysClk) begin
if (`STATE_GET_CMD == state && rcByteValid) begin
if (`CMD_READ_START == rcByte) begin
state_reg <= `STATE_READING;
end else if (`CMD_READ_MORE == rcByte) begin
state_reg <= `STATE_READING;
end else if (`CMD_WRITE_START == rcByte) begin
state_reg <= `STATE_WRITING;
end else if (`CMD_WRITE_MORE == rcByte) begin
state_reg <= `STATE_WRITING;
end else if (rcByte[`CMD_REG_BIT] != 0) begin
// Register access
rcWordByteId <= 0;
command <= `CMD_REG_BASE; // Write reg Read reg
state_reg <= (rcByte[`CMD_REG_WE_BIT] ? `STATE_BUILD_WORD : `STATE_SEND_WORD);
end else if (`CMD_INTERRUPT == rcByte) begin
// TODO: NYI
end
end else if (`STATE_BUILD_WORD == state && rcByteValid) begin
if (0 == rcWordByteId) begin
rcWord[31:24] <= rcByte;
rcWordByteId <= 1;
end else if (1 == rcWordByteId) begin
rcWord[23:16] <= rcByte;
rcWordByteId <= 2;
end else if (2 == rcWordByteId) begin
rcWord[15:8] <= rcByte;
rcWordByteId <= 3;
end else if (3 == rcWordByteId) begin
rcWord[7:0] <= rcByte;
state_reg <= `STATE_GET_CMD;
end
end else if (`STATE_SEND_WORD == state && rcByteValid) begin
rcWordByteId <= rcWordByteId + 1;
state_reg <= (rcWordByteId == 3 ? `STATE_GET_CMD : `STATE_SEND_WORD);
// Decode the SPI command
case (rcByte)
`RC_MODE_GET_STATUS: begin end // no status yet
`RC_MODE_GET_BUFFER: begin rcMode <= `RC_MODE_GET_BUFFER; rcState <= `RC_STATE_SIZE; end
`RC_MODE_PUT_BUFFER: begin rcMode <= `RC_MODE_PUT_BUFFER; rcState <= `RC_STATE_SIZE; end
endcase
// Initialize counters
rcByteCount <= 32'd0;
rcByteSize <= 32'd0;
end
// Record size (in bytes) of payload
if (`RC_STATE_SIZE == rcState) begin
debug_reg[1] <= 1;
case (rcByteCount)
32'd0: begin rcByteSize[31:24] <= rcByte; rcByteCount <= 32'd1; end
32'd1: begin rcByteSize[23:16] <= rcByte; rcByteCount <= 32'd2; end
32'd2: begin rcByteSize[15: 8] <= rcByte; rcByteCount <= 32'd3; end
32'd3: begin
rcByteSize[ 7: 0] <= rcByte;
rcByteCount <= 32'd0;
rcState <= `RC_STATE_PAYLOAD;
rcByteCount <= 32'd0;
if (`RC_MODE_GET_BUFFER == rcMode) begin
// TODO: want reset tx byte addr here probably
end
end
endcase
end
// The payload
if (rcState == `RC_STATE_PAYLOAD) begin
debug_reg[2] <= 1;
case (rcMode)
`RC_MODE_GET_BUFFER: begin
// IGNORE EVERYTHING SO STUFF CAN BE READ OUT
end
`RC_MODE_PUT_BUFFER: begin
//debug_reg[4] <= 1;
rcMemWE_reg <= 1'b1;
rcMemData_reg <= rcByte;
rcMemAddr_reg <= rcByteCount[AddrBits-1:0];
end
endcase
end else begin
state_reg <= state;
end
end
if (rcByteCount == rcByteSize - 1) begin
rcState <= `RC_STATE_CMD;
//debug_reg[5] <= 1;
end else begin
rcByteCount <= rcByteCount + 32'd1;
end
end
end
else begin // not valid byte
if (ss_negedge) begin
rcState <= `RC_STATE_CMD;
end
end
// Register logic
assign regAddr = (`STATE_GET_CMD == state && rcByteValid && rcByte[`CMD_REG_BIT] ? (rcByte & `CMD_REG_ID_MASK) : regAddr_reg);
assign regWriteEn = (`STATE_BUILD_WORD == state && rcByteValid && 3 == rcWordByteId ? 1 : 0);
assign regWriteData = {rcWord[31:8], rcByte};
always @(posedge SysClk) begin
regAddr_reg <= regAddr;
end
always @(*) begin
case (rcWordByteId)
0: regReadByte_oreg <= regReadData[31:24];
1: regReadByte_oreg <= regReadData[23:16];
2: regReadByte_oreg <= regReadData[15:8];
3: regReadByte_oreg <= regReadData[7:0];
endcase
end
// Debugging
always @(posedge SysClk) begin
if (rcByteValid) begin
debug_reg <= rcByte;
end
//reg [7:0] rcByteReg;
//wire [7:0] rcByte;
//assign rcByte = {rcByteReg[7:1], (SPI_SS == 1'b0 && bitIndex ==
end
assign debug_out = debug_reg;
// //
// // Receive (GPU to SPI)
// //
// reg SPI_SS_prev_cycle;
//
// // This is the register backing rcByteId. It is always one cycle
// // behind the true value of rcByteId, which we have to do a little
// // work to get instantaneously correct using wire logic.
// reg [31:0] rcByteIdPrev;
// wire [31:0] rcByteId;
// assign rcByteId = (SPI_SS_prev_cycle == 1 && SPI_SS == 0 ? 32'd0 : 32'd1 + rcByteIdPrev);
//
// // 1 if we're receiving from GPC, 0 if not.
// wire isRecv;
// assign isRecv = ~SPI_SS;
//
// // Bits to Byte aggregator
// reg [2:0] rcBitId;
// reg [7:0] rcByte;
//
//
// reg [31:0] rcSizeBytes;
//
// always @(posedge SPI_CLK) begin
// if (1 == isRecv) begin
// case (rcByteId)
// 0: rcSizeBytes[ 7: 0] <=
// end
//
// // Update registers for next cycle
// SPI_SS_prev_cycle <= SPI_SS;
// rcByteId <= rcByteIdPrev;
// end
*/
endmodule
scripts/pre-xilinx-checkin.sh 0 → 100644
View file @ 05b98f2c
#!/bin/sh
#
# pre-xilinx-checkin.sh
#
# Michael J. Lyons, 2012
#
# Deletes temporary files left over, even after xilinx tools do a 'clean'
#
VSPI_ROOT=..
RM="rm -f"
$RM $VSPI_ROOT/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/iseconfig/*.xreport
$RM $VSPI_ROOT/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/*.html
$RM $VSPI_ROOT/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/webtalk_impact.xml
$RM $VSPI_ROOT/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/*.xrpt
$RM $VSPI_ROOT/projnav/xps/pcores/spiifc_v1_00_a/devl/projnav/*.xreport
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment