Skip to content

G
grabor
Commit 45999dcd authored by Upi Tamminen's avatar Upi Tamminen
Browse files
Options

Add project files

parent 60dcc6cc
Show whitespace changes
Inline Side-by-side
Showing with 16962 additions and 0 deletions
COPYRIGHT 0 → 100644
View file @ 45999dcd
Copyright (c) 2013 Upi Tamminen
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions
are met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. The names of the author(s) may not be used to endorse or promote
products derived from this software without specific prior written
permission.
THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR
IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
SUCH DAMAGE.
LPC1758_59_67_68_69_rom.ld 0 → 100644
View file @ 45999dcd
/******************************************************************************
* author: Freddie Chopin, http://www.freddiechopin.info/
* file: LPC1758_59_67_68_69_rom.ld
* last change: 2012-04-07
*
* chip: LPC1758 / LPC1759 / LPC1767 / LPC1768 / LPC1769
* compiler: arm-none-eabi-gcc (GNU Tools for ARM Embedded Processors) 4.6.2
* 20110921 (release) [ARM/embedded-4_6-branch revision 182083]
*
* description:
* Linker script for LPC1758, LPC1759, LPC1767, LPC1768 and LPC1769 chips (512kB
* Flash, 32kB SRAM, 16kB AHB SRAM0 and 16kB AHB SRAM1). Only main block of SRAM
* (32kB) is used.
******************************************************************************/
SEARCH_DIR(.);
/*
+=============================================================================+
| format configurations
+=============================================================================+
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm");
OUTPUT_ARCH(arm);
/*
+=============================================================================+
| stacks sizes
+=============================================================================+
*/
/* Handler mode (core exceptions / interrupts) can use only main stack */
/* Thread mode can use main stack (default) or process stack - selected in CONTROL special register */
__main_stack_size = 1024;
__process_stack_size = 1024;
PROVIDE(__main_stack_size = __main_stack_size);
PROVIDE(__process_stack_size = __process_stack_size);
/*
+=============================================================================+
| available memories definitions
+=============================================================================+
*/
MEMORY
{
rom (rx) : org = 0x00000000, len = 512k
ram (rwx) : org = 0x10000000, len = 32k
ahb_sram0 (rwx) : org = 0x2007C000, len = 16k
ahb_sram1 (rwx) : org = 0x20080000, len = 16k
}
__rom_start = ORIGIN(rom);
__rom_size = LENGTH(rom);
__rom_end = __rom_start + __rom_size;
__ram_start = ORIGIN(ram);
__ram_size = LENGTH(ram);
__ram_end = __ram_start + __ram_size;
__ahb_sram0_start = ORIGIN(ahb_sram0);
__ahb_sram0_size = LENGTH(ahb_sram0);
__ahb_sram0_end = __ahb_sram0_start + __ahb_sram0_size;
__ahb_sram1_start = ORIGIN(ahb_sram1);
__ahb_sram1_size = LENGTH(ahb_sram1);
__ahb_sram1_end = __ahb_sram1_start + __ahb_sram1_size;
PROVIDE(__rom_start = __rom_start);
PROVIDE(__rom_size = __rom_size);
PROVIDE(__rom_end = __rom_end);
PROVIDE(__ram_start = __ram_start);
PROVIDE(__ram_size = __ram_size);
PROVIDE(__ram_end = __ram_end);
PROVIDE(__ahb_sram0_start = __ahb_sram0_start);
PROVIDE(__ahb_sram0_size = __ahb_sram0_size);
PROVIDE(__ahb_sram0_end = __ahb_sram0_end);
PROVIDE(__ahb_sram1_start = __ahb_sram1_start);
PROVIDE(__ahb_sram1_size = __ahb_sram1_size);
PROVIDE(__ahb_sram1_end = __ahb_sram1_end);
/*
+=============================================================================+
| entry point
+=============================================================================+
*/
ENTRY(Reset_Handler);
/*
+=============================================================================+
| put data in sections
+=============================================================================+
*/
SECTIONS
{
.text :
{
. = ALIGN(4);
__text_start = .;
PROVIDE(__text_start = __text_start);
. = ALIGN(4);
KEEP(*(.vectors));
. = ALIGN(4);
*(.text .text.* .gnu.linkonce.t.*);
. = ALIGN(4);
*(.glue_7t .glue_7);
. = ALIGN(4);
*(.rodata .rodata.* .gnu.linkonce.r.*);
. = ALIGN(4);
*(.ARM.extab* .gnu.linkonce.armextab.*); /* exception unwinding information */
. = ALIGN(4);
*(.gcc_except_table); /* information used for stack unwinding during exception */
. = ALIGN(4);
*(.eh_frame_hdr); /* additional information about .ex_frame section */
. = ALIGN(4);
*(.eh_frame); /* information used for stack unwinding during exception */
. = ALIGN(4);
KEEP(*(.init));
. = ALIGN(4);
__preinit_array_start = .;
KEEP(*(.preinit_array));
. = ALIGN(4);
__preinit_array_end = .;
__init_array_start = .;
KEEP(*(SORT(.init_array.*)));
. = ALIGN(4);
KEEP(*(.init_array));
. = ALIGN(4);
__init_array_end = .;
KEEP(*(.fini));
. = ALIGN(4);
__fini_array_start = .;
KEEP(*(.fini_array));
. = ALIGN(4);
KEEP(*(SORT(.fini_array.*)));
. = ALIGN(4);
__fini_array_end = .;
. = ALIGN(4);
__text_end = .;
PROVIDE(__text_end = __text_end);
} > rom AT > rom
. = ALIGN(4);
__exidx_start = .;
PROVIDE(__exidx_start = __exidx_start);
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*);
} > rom AT > rom /* index entries for section unwinding */
. = ALIGN(4);
__exidx_end = .;
PROVIDE(__exidx_end = __exidx_end);
.data :
{
. = ALIGN(4);
__data_init_start = LOADADDR (.data);
PROVIDE(__data_init_start = __data_init_start);
__data_start = .;
PROVIDE(__data_start = __data_start);
. = ALIGN(4);
*(.data .data.* .gnu.linkonce.d.*)
. = ALIGN(4);
__data_end = .;
PROVIDE(__data_end = __data_end);
} > ram AT > rom
.bss :
{
. = ALIGN(4);
__bss_start = .;
PROVIDE(__bss_start = __bss_start);
. = ALIGN(4);
*(.bss .bss.* .gnu.linkonce.b.*)
. = ALIGN(4);
*(COMMON);
. = ALIGN(4);
__bss_end = .;
PROVIDE(__bss_end = __bss_end);
} > ram AT > ram
.stack :
{
. = ALIGN(8);
__stack_start = .;
PROVIDE(__stack_start = __stack_start);
. = ALIGN(8);
__main_stack_start = .;
PROVIDE(__main_stack_start = __main_stack_start);
. += __main_stack_size;
. = ALIGN(8);
__main_stack_end = .;
PROVIDE(__main_stack_end = __main_stack_end);
. = ALIGN(8);
__process_stack_start = .;
PROVIDE(__process_stack_start = __process_stack_start);
. += __process_stack_size;
. = ALIGN(8);
__process_stack_end = .;
PROVIDE(__process_stack_end = __process_stack_end);
. = ALIGN(8);
__stack_end = .;
PROVIDE(__stack_end = __stack_end);
} > ram AT > ram
. = ALIGN(4);
__heap_start = .;
PROVIDE(__heap_start = __heap_start);
. = ALIGN(4);
__heap_end = __ram_end;
PROVIDE(__heap_end = __heap_end);
.stab 0 (NOLOAD) : { *(.stab) }
.stabstr 0 (NOLOAD) : { *(.stabstr) }
/* DWARF debug sections.
* Symbols in the DWARF debugging sections are relative to the beginning
* of the section so we begin them at 0. */
/* DWARF 1 */
.debug 0 : { *(.debug) }
.line 0 : { *(.line) }
/* GNU DWARF 1 extensions */
.debug_srcinfo 0 : { *(.debug_srcinfo) }
.debug_sfnames 0 : { *(.debug_sfnames) }
/* DWARF 1.1 and DWARF 2 */
.debug_aranges 0 : { *(.debug_aranges) }
.debug_pubnames 0 : { *(.debug_pubnames) }
/* DWARF 2 */
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
.debug_abbrev 0 : { *(.debug_abbrev) }
.debug_line 0 : { *(.debug_line) }
.debug_frame 0 : { *(.debug_frame) }
.debug_str 0 : { *(.debug_str) }
.debug_loc 0 : { *(.debug_loc) }
.debug_macinfo 0 : { *(.debug_macinfo) }
/* SGI/MIPS DWARF 2 extensions */
.debug_weaknames 0 : { *(.debug_weaknames) }
.debug_funcnames 0 : { *(.debug_funcnames) }
.debug_typenames 0 : { *(.debug_typenames) }
.debug_varnames 0 : { *(.debug_varnames) }
.note.gnu.arm.ident 0 : { KEEP(*(.note.gnu.arm.ident)) }
.ARM.attributes 0 : { KEEP(*(.ARM.attributes)) }
/DISCARD/ : { *(.note.GNU-stack) }
}
PROVIDE(__text_size = __text_end - __text_start);
PROVIDE(__exidx_size = __exidx_end - __exidx_start);
PROVIDE(__data_size = __data_end - __data_start);
PROVIDE(__bss_size = __bss_end - __bss_start);
PROVIDE(__stack_size = __stack_end - __stack_start);
PROVIDE(__heap_size = __heap_end - __heap_start);
/******************************************************************************
* END OF FILE
******************************************************************************/
Makefile 0 → 100644
View file @ 45999dcd
#=============================================================================#
# ARM makefile
#
# author: Freddie Chopin, http://www.freddiechopin.info/
# last change: 2012-04-07
#
# this makefile is based strongly on many examples found in the network
#
# Adopted for the grabor project by Upi Tamminen
#=============================================================================#
#=============================================================================#
# toolchain configuration
#=============================================================================#
TOOLCHAIN = arm-none-eabi-
CXX = $(TOOLCHAIN)g++
CC = $(TOOLCHAIN)gcc
AS = $(TOOLCHAIN)gcc -x assembler-with-cpp
OBJCOPY = $(TOOLCHAIN)objcopy
OBJDUMP = $(TOOLCHAIN)objdump
SIZE = $(TOOLCHAIN)size
RM = rm -f
#=============================================================================#
# project configuration
#=============================================================================#
# project name
PROJECT = grabor
# core type
CORE = cortex-m3
# linker script
LD_SCRIPT = LPC1758_59_67_68_69_rom.ld
# output folder (absolute or relative path, leave empty for in-tree compilation)
OUT_DIR = out
# lwIP
DIR_LWIP = lwip-1.4.1/src
# global definitions for C++, C and ASM (e.g. "symbol_with_value=0xDEAD symbol_without_value")
GLOBAL_DEFS =
# C++ definitions
CXX_DEFS =
# C definitions
C_DEFS =
# ASM definitions
AS_DEFS =
# include directories (absolute or relative paths to additional folders with
# headers, current folder is always included)
INC_DIRS = inc
INC_DIRS += $(DIR_LWIP)/include $(DIR_LWIP)/include/ipv4
# library directories (absolute or relative paths to additional folders with
# libraries)
LIB_DIRS =
# libraries (additional libraries for linking, e.g. "-lm -lsome_name" to link
# math library libm.a and libsome_name.a)
LIBS =
# additional directories with source files (absolute or relative paths to
# folders with source files, current folder is always included)
SRCS_DIRS = src
SRCS_DIRS += $(DIR_LWIP)/core/ $(DIR_LWIP)/core/ipv4/ $(DIR_LWIP)/netif/
SRCS_DIRS += $(DIR_LWIP)/api/
# extension of C++ files
CXX_EXT = cpp
# wildcard for C++ source files (all files with CXX_EXT extension found in
# current folder and SRCS_DIRS folders will be compiled and linked)
CXX_SRCS = $(wildcard $(patsubst %, %/*.$(CXX_EXT), . $(SRCS_DIRS)))
# extension of C files
C_EXT = c
# wildcard for C source files (all files with C_EXT extension found in current
# folder and SRCS_DIRS folders will be compiled and linked)
#C_SRCS = $(wildcard $(patsubst %, %/*.$(C_EXT), . $(SRCS_DIRS)))
C_SRCS =
C_SRCS += cpu.c
C_SRCS += dma.c
C_SRCS += gpio.c
C_SRCS += i2c.c
C_SRCS += led.c
C_SRCS += main.c
C_SRCS += spi.c
C_SRCS += tvp7002.c
C_SRCS += uart0.c
C_SRCS += vectors.c
C_SRCS += utils.c
C_SRCS += cpld.c
C_SRCS += tprintf.c
C_SRCS += enc28j60.c
C_SRCS += enc28j60if.c
C_SRCS += httpd.c
# lwip (the full paths are actually ignored here, since this Makefile is funny)
C_SRCS += $(LWIPDIR)/core/init.c
C_SRCS += $(LWIPDIR)/core/mem.c
C_SRCS += $(LWIPDIR)/core/memp.c
C_SRCS += $(LWIPDIR)/core/netif.c
C_SRCS += $(LWIPDIR)/core/tcp.c
C_SRCS += $(LWIPDIR)/core/stats.c
C_SRCS += $(LWIPDIR)/core/tcp_out.c
C_SRCS += $(LWIPDIR)/core/tcp_in.c
C_SRCS += $(LWIPDIR)/core/pbuf.c
C_SRCS += $(LWIPDIR)/core/timers.c
C_SRCS += $(LWIPDIR)/core/def.c
C_SRCS += $(LWIPDIR)/core/raw.c
C_SRCS += $(LWIPDIR)/core/udp.c
C_SRCS += $(LWIPDIR)/core/ipv4/ip.c
C_SRCS += $(LWIPDIR)/core/ipv4/inet_chksum.c
C_SRCS += $(LWIPDIR)/core/ipv4/ip_addr.c
C_SRCS += $(LWIPDIR)/core/ipv4/ip_frag.c
C_SRCS += $(LWIPDIR)/core/ipv4/icmp.c
C_SRCS += $(LWIPDIR)/netif/ethernetif.c
C_SRCS += $(LWIPDIR)/netif/etharp.c
C_SRCS += $(LWIPDIR)/api/err.c
# extension of ASM files
AS_EXT = S
# wildcard for ASM source files (all files with AS_EXT extension found in
# current folder and SRCS_DIRS folders will be compiled and linked)
AS_SRCS = $(wildcard $(patsubst %, %/*.$(AS_EXT), . $(SRCS_DIRS)))
# optimization flags ("-O0" - no optimization, "-O1" - optimize, "-O2" -
# optimize even more, "-Os" - optimize for size or "-O3" - optimize yet more)
OPTIMIZATION = -Os
# set to 1 to optimize size by removing unused code and data during link phase
REMOVE_UNUSED = 1
# set to 1 to compile and link additional code required for C++
USES_CXX = 0
# define warning options here
CXX_WARNINGS = -Wall -Wextra
C_WARNINGS = -Wall -Wstrict-prototypes -Wextra
# C++ language standard ("c++98", "gnu++98" - default, "c++0x", "gnu++0x")
CXX_STD = gnu++98
# C language standard ("c89" / "iso9899:1990", "iso9899:199409",
# "c99" / "iso9899:1999", "gnu89" - default, "gnu99")
C_STD = gnu89
#=============================================================================#
# set the VPATH according to SRCS_DIRS
#=============================================================================#
VPATH = $(SRCS_DIRS)
#=============================================================================#
# when using output folder, append trailing slash to its name
#=============================================================================#
ifeq ($(strip $(OUT_DIR)), )
OUT_DIR_F =
else
OUT_DIR_F = $(strip $(OUT_DIR))/
endif
#=============================================================================#
# various compilation flags
#=============================================================================#
# core flags
CORE_FLAGS = -mcpu=$(CORE) -mthumb
# flags for C++ compiler
CXX_FLAGS = -std=$(CXX_STD) -g -ggdb3 -fno-rtti -fno-exceptions -fverbose-asm -Wa,-ahlms=$(OUT_DIR_F)$(notdir $(<:.$(CXX_EXT)=.lst))
# flags for C compiler
C_FLAGS = -std=$(C_STD) -g -ggdb3 -fverbose-asm -Wa,-ahlms=$(OUT_DIR_F)$(notdir $(<:.$(C_EXT)=.lst))
# flags for assembler
AS_FLAGS = -g -ggdb3 -Wa,-amhls=$(OUT_DIR_F)$(notdir $(<:.$(AS_EXT)=.lst))
# flags for linker
LD_FLAGS = -T$(LD_SCRIPT) -g -Wl,-Map=$(OUT_DIR_F)$(PROJECT).map,--cref,--no-warn-mismatch
# process option for removing unused code
ifeq ($(REMOVE_UNUSED), 1)
LD_FLAGS += -Wl,--gc-sections
OPTIMIZATION += -ffunction-sections -fdata-sections
endif
# if __USES_CXX is defined for ASM then code for global/static constructors /
# destructors is compiled; if -nostartfiles option for linker is added then C++
# initialization / finalization code is not linked
ifeq ($(USES_CXX), 1)
AS_DEFS += __USES_CXX
else
LD_FLAGS += -nostartfiles
endif
#=============================================================================#
# do some formatting
#=============================================================================#
CXX_OBJS = $(addprefix $(OUT_DIR_F), $(notdir $(CXX_SRCS:.$(CXX_EXT)=.o)))
C_OBJS = $(addprefix $(OUT_DIR_F), $(notdir $(C_SRCS:.$(C_EXT)=.o)))
AS_OBJS = $(addprefix $(OUT_DIR_F), $(notdir $(AS_SRCS:.$(AS_EXT)=.o)))
OBJS = $(AS_OBJS) $(C_OBJS) $(CXX_OBJS) $(USER_OBJS)
DEPS = $(OBJS:.o=.d)
INC_DIRS_F = -I. $(patsubst %, -I%, $(INC_DIRS))
LIB_DIRS_F = $(patsubst %, -L%, $(LIB_DIRS))
GLOBAL_DEFS_F = $(patsubst %, -D%, $(GLOBAL_DEFS))
CXX_DEFS_F = $(patsubst %, -D%, $(CXX_DEFS))
C_DEFS_F = $(patsubst %, -D%, $(C_DEFS))
AS_DEFS_F = $(patsubst %, -D%, $(AS_DEFS))
ELF = $(OUT_DIR_F)$(PROJECT).elf
HEX = $(OUT_DIR_F)$(PROJECT).hex
BIN = $(OUT_DIR_F)$(PROJECT).bin
LSS = $(OUT_DIR_F)$(PROJECT).lss
DMP = $(OUT_DIR_F)$(PROJECT).dmp
# format final flags for tools, request dependancies for C++, C and asm
CXX_FLAGS_F = $(CORE_FLAGS) $(OPTIMIZATION) $(CXX_WARNINGS) $(CXX_FLAGS) $(GLOBAL_DEFS_F) $(CXX_DEFS_F) -MD -MP -MF $(OUT_DIR_F)$(@F:.o=.d) $(INC_DIRS_F)
C_FLAGS_F = $(CORE_FLAGS) $(OPTIMIZATION) $(C_WARNINGS) $(C_FLAGS) $(GLOBAL_DEFS_F) $(C_DEFS_F) -MD -MP -MF $(OUT_DIR_F)$(@F:.o=.d) $(INC_DIRS_F)
AS_FLAGS_F = $(CORE_FLAGS) $(AS_FLAGS) $(GLOBAL_DEFS_F) $(AS_DEFS_F) -MD -MP -MF $(OUT_DIR_F)$(@F:.o=.d) $(INC_DIRS_F)
LD_FLAGS_F = $(CORE_FLAGS) $(LD_FLAGS) $(LIB_DIRS_F)
#contents of output directory
GENERATED = $(wildcard $(patsubst %, $(OUT_DIR_F)*.%, bin d dmp elf hex lss lst map o))
#=============================================================================#
# make all
#=============================================================================#
all : make_output_dir $(ELF) $(LSS) $(DMP) $(HEX) $(BIN) print_size
# make object files dependent on Makefile
$(OBJS) : Makefile
# make .elf file dependent on linker script
$(ELF) : $(LD_SCRIPT)
#-----------------------------------------------------------------------------#
# linking - objects -> elf
#-----------------------------------------------------------------------------#
$(ELF) : $(OBJS)
@echo 'Linking target: $(ELF)'
$(CXX) $(LD_FLAGS_F) $(OBJS) $(LIBS) -o $@
@echo ' '
#-----------------------------------------------------------------------------#
# compiling - C++ source -> objects
#-----------------------------------------------------------------------------#
$(OUT_DIR_F)%.o : %.$(CXX_EXT)
@echo 'Compiling file: $<'
$(CXX) -c $(CXX_FLAGS_F) $< -o $@
@echo ' '
#-----------------------------------------------------------------------------#
# compiling - C source -> objects
#-----------------------------------------------------------------------------#
$(OUT_DIR_F)%.o : %.$(C_EXT)
@echo 'Compiling file: $<'
$(CC) -c $(C_FLAGS_F) $< -o $@
@echo ' '
#-----------------------------------------------------------------------------#
# assembling - ASM source -> objects
#-----------------------------------------------------------------------------#
$(OUT_DIR_F)%.o : %.$(AS_EXT)
@echo 'Assembling file: $<'
$(AS) -c $(AS_FLAGS_F) $< -o $@
@echo ' '
#-----------------------------------------------------------------------------#
# memory images - elf -> hex, elf -> bin
#-----------------------------------------------------------------------------#
$(HEX) : $(ELF)
@echo 'Creating IHEX image: $(HEX)'
$(OBJCOPY) -O ihex $< $@
@echo ' '
$(BIN) : $(ELF)
@echo 'Creating binary image: $(BIN)'
$(OBJCOPY) -O binary $< $@
@echo ' '
#-----------------------------------------------------------------------------#
# memory dump - elf -> dmp
#-----------------------------------------------------------------------------#
$(DMP) : $(ELF)
@echo 'Creating memory dump: $(DMP)'
$(OBJDUMP) -x --syms $< > $@
@echo ' '
#-----------------------------------------------------------------------------#
# extended listing - elf -> lss
#-----------------------------------------------------------------------------#
$(LSS) : $(ELF)
@echo 'Creating extended listing: $(LSS)'
$(OBJDUMP) -S $< > $@
@echo ' '
#-----------------------------------------------------------------------------#
# print the size of the objects and the .elf file
#-----------------------------------------------------------------------------#
print_size :
@echo 'Size of modules:'
$(SIZE) -B -t --common $(OBJS) $(USER_OBJS)
@echo ' '
@echo 'Size of target .elf file:'
$(SIZE) -B $(ELF)
@echo ' '
#-----------------------------------------------------------------------------#
# create the desired output directory
#-----------------------------------------------------------------------------#
make_output_dir :
$(shell mkdir $(OUT_DIR_F) 2>/dev/null)
#=============================================================================#
# make clean
#=============================================================================#
clean:
ifeq ($(strip $(OUT_DIR_F)), )
@echo 'Removing all generated output files'
else
@echo 'Removing all generated output files from output directory: $(OUT_DIR_F)'
endif
ifneq ($(strip $(GENERATED)), )
$(RM) $(GENERATED)
else
@echo 'Nothing to remove...'
endif
#=============================================================================#
# global exports
#=============================================================================#
.PHONY: all clean dependents
.SECONDARY:
# include dependancy files
-include $(DEPS)
hdr/hdr_bitband.h 0 → 100644
View file @ 45999dcd
/** \file hdr_bitband.h
* \brief Header for bit-banding
* \author Freddie Chopin, http://www.freddiechopin.info/
* \date 2012-04-06
*/
/******************************************************************************
* chip: ARMv7-M(E) (Cortex-M3 / Cortex-M4)
* compiler: arm-none-eabi-gcc (GNU Tools for ARM Embedded Processors) 4.6.2
* 20110921 (release) [ARM/embedded-4_6-branch revision 182083]
******************************************************************************/
#ifndef HDR_BITBAND_H_
#define HDR_BITBAND_H_
/*
+=============================================================================+
| global definitions
+=============================================================================+
*/
#define BITBAND_SRAM_REF 0x20000000
#define BITBAND_SRAM_BASE 0x22000000
#define BITBAND_PERIPH_REF 0x40000000
#define BITBAND_PERIPH_BASE 0x42000000
/*
+=============================================================================+
| strange variables
+=============================================================================+
*/
#define bitband_t *(volatile unsigned long*)
/*
+=============================================================================+
| macros
+=============================================================================+
*/
#define BITBAND_SRAM(address, bit) (BITBAND_SRAM_BASE + (((unsigned long)address) - BITBAND_SRAM_REF) * 32 + (bit) * 4)
#define BITBAND_PERIPH(address, bit) (BITBAND_PERIPH_BASE + (((unsigned long)address) - BITBAND_PERIPH_REF) * 32 + (bit) * 4)
#define BITBAND(address, bit) ( \
(((unsigned long)address) >= 0x20000000) && (((unsigned long)address) <= 0x200FFFFF) ? BITBAND_SRAM(address, bit) : \
(((unsigned long)address) >= 0x40000000) && (((unsigned long)address) <= 0x400FFFFF) ? BITBAND_PERIPH(address, bit) : \
0 /* fail */ \
)
/******************************************************************************
* END OF FILE
******************************************************************************/
#endif /* HDR_BITBAND_H_ */
hdr/hdr_gpio.h 0 → 100644
View file @ 45999dcd
/** \file hdr_gpio.h
* \brief Header with definition of bits in GPIO control registers
* \author Freddie Chopin, http://www.freddiechopin.info/
* \date 2012-04-07
*/
/******************************************************************************
* chip: LPC175x / LPC176x
* compiler: arm-none-eabi-gcc (GNU Tools for ARM Embedded Processors) 4.6.2
* 20110921 (release) [ARM/embedded-4_6-branch revision 182083]
******************************************************************************/
#ifndef HDR_GPIO_H_
#define HDR_GPIO_H_
#include "hdr/hdr_bitband.h"
/*
+=============================================================================+
| global definitions
+=============================================================================+
*/
#define LPC_GPIO_FIODIR_IN_value 0
#define LPC_GPIO_FIODIR_OUT_value 1
#define LPC_GPIO_FIODIR_mask 1
/*
+-----------------------------------------------------------------------------+
| FIODIR - GPIO port Direction register
+-----------------------------------------------------------------------------+
*/
#define LPC_GPIO_FIODIR_DIR0_bit 0
#define LPC_GPIO_FIODIR_DIR1_bit 1
#define LPC_GPIO_FIODIR_DIR2_bit 2
#define LPC_GPIO_FIODIR_DIR3_bit 3
#define LPC_GPIO_FIODIR_DIR4_bit 4
#define LPC_GPIO_FIODIR_DIR5_bit 5
#define LPC_GPIO_FIODIR_DIR6_bit 6
#define LPC_GPIO_FIODIR_DIR7_bit 7
#define LPC_GPIO_FIODIR_DIR8_bit 8
#define LPC_GPIO_FIODIR_DIR9_bit 9
#define LPC_GPIO_FIODIR_DIR10_bit 10
#define LPC_GPIO_FIODIR_DIR11_bit 11
#define LPC_GPIO_FIODIR_DIR12_bit 12
#define LPC_GPIO_FIODIR_DIR13_bit 13
#define LPC_GPIO_FIODIR_DIR14_bit 14
#define LPC_GPIO_FIODIR_DIR15_bit 15
#define LPC_GPIO_FIODIR_DIR16_bit 16
#define LPC_GPIO_FIODIR_DIR17_bit 17
#define LPC_GPIO_FIODIR_DIR18_bit 18
#define LPC_GPIO_FIODIR_DIR19_bit 19
#define LPC_GPIO_FIODIR_DIR20_bit 20
#define LPC_GPIO_FIODIR_DIR21_bit 21
#define LPC_GPIO_FIODIR_DIR22_bit 22
#define LPC_GPIO_FIODIR_DIR23_bit 23
#define LPC_GPIO_FIODIR_DIR24_bit 24
#define LPC_GPIO_FIODIR_DIR25_bit 25
#define LPC_GPIO_FIODIR_DIR26_bit 26
#define LPC_GPIO_FIODIR_DIR27_bit 27
#define LPC_GPIO_FIODIR_DIR28_bit 28
#define LPC_GPIO_FIODIR_DIR29_bit 29
#define LPC_GPIO_FIODIR_DIR30_bit 30
#define LPC_GPIO_FIODIR_DIR31_bit 31
#define LPC_GPIO_FIODIR_DIR0 (1 << LPC_GPIO_FIODIR_DIR0_bit)
#define LPC_GPIO_FIODIR_DIR1 (1 << LPC_GPIO_FIODIR_DIR1_bit)
#define LPC_GPIO_FIODIR_DIR2 (1 << LPC_GPIO_FIODIR_DIR2_bit)
#define LPC_GPIO_FIODIR_DIR3 (1 << LPC_GPIO_FIODIR_DIR3_bit)
#define LPC_GPIO_FIODIR_DIR4 (1 << LPC_GPIO_FIODIR_DIR4_bit)
#define LPC_GPIO_FIODIR_DIR5 (1 << LPC_GPIO_FIODIR_DIR5_bit)
#define LPC_GPIO_FIODIR_DIR6 (1 << LPC_GPIO_FIODIR_DIR6_bit)
#define LPC_GPIO_FIODIR_DIR7 (1 << LPC_GPIO_FIODIR_DIR7_bit)
#define LPC_GPIO_FIODIR_DIR8 (1 << LPC_GPIO_FIODIR_DIR8_bit)
#define LPC_GPIO_FIODIR_DIR9 (1 << LPC_GPIO_FIODIR_DIR9_bit)
#define LPC_GPIO_FIODIR_DIR10 (1 << LPC_GPIO_FIODIR_DIR10_bit)
#define LPC_GPIO_FIODIR_DIR11 (1 << LPC_GPIO_FIODIR_DIR11_bit)
#define LPC_GPIO_FIODIR_DIR12 (1 << LPC_GPIO_FIODIR_DIR12_bit)
#define LPC_GPIO_FIODIR_DIR13 (1 << LPC_GPIO_FIODIR_DIR13_bit)
#define LPC_GPIO_FIODIR_DIR14 (1 << LPC_GPIO_FIODIR_DIR14_bit)
#define LPC_GPIO_FIODIR_DIR15 (1 << LPC_GPIO_FIODIR_DIR15_bit)
#define LPC_GPIO_FIODIR_DIR16 (1 << LPC_GPIO_FIODIR_DIR16_bit)
#define LPC_GPIO_FIODIR_DIR17 (1 << LPC_GPIO_FIODIR_DIR17_bit)
#define LPC_GPIO_FIODIR_DIR18 (1 << LPC_GPIO_FIODIR_DIR18_bit)
#define LPC_GPIO_FIODIR_DIR19 (1 << LPC_GPIO_FIODIR_DIR19_bit)
#define LPC_GPIO_FIODIR_DIR20 (1 << LPC_GPIO_FIODIR_DIR20_bit)
#define LPC_GPIO_FIODIR_DIR21 (1 << LPC_GPIO_FIODIR_DIR21_bit)
#define LPC_GPIO_FIODIR_DIR22 (1 << LPC_GPIO_FIODIR_DIR22_bit)
#define LPC_GPIO_FIODIR_DIR23 (1 << LPC_GPIO_FIODIR_DIR23_bit)
#define LPC_GPIO_FIODIR_DIR24 (1 << LPC_GPIO_FIODIR_DIR24_bit)
#define LPC_GPIO_FIODIR_DIR25 (1 << LPC_GPIO_FIODIR_DIR25_bit)
#define LPC_GPIO_FIODIR_DIR26 (1 << LPC_GPIO_FIODIR_DIR26_bit)
#define LPC_GPIO_FIODIR_DIR27 (1 << LPC_GPIO_FIODIR_DIR27_bit)
#define LPC_GPIO_FIODIR_DIR28 (1 << LPC_GPIO_FIODIR_DIR28_bit)
#define LPC_GPIO_FIODIR_DIR29 (1 << LPC_GPIO_FIODIR_DIR29_bit)
#define LPC_GPIO_FIODIR_DIR30 (1 << LPC_GPIO_FIODIR_DIR30_bit)
#define LPC_GPIO_FIODIR_DIR31 (1 << LPC_GPIO_FIODIR_DIR31_bit)
#define LPC_GPIO0_FIODIR_DIR0_bb bitband_t BITBAND(&LPC_GPIO0->FIODIR, LPC_GPIO_FIODIR_DIR0_bit)
#define LPC_GPIO0_FIODIR_DIR1_bb bitband_t BITBAND(&LPC_GPIO0->FIODIR, LPC_GPIO_FIODIR_DIR1_bit)
#define LPC_GPIO0_FIODIR_DIR2_bb bitband_t BITBAND(&LPC_GPIO0->FIODIR, LPC_GPIO_FIODIR_DIR2_bit)
#define LPC_GPIO0_FIODIR_DIR3_bb bitband_t BITBAND(&LPC_GPIO0->FIODIR, LPC_GPIO_FIODIR_DIR3_bit)
#define LPC_GPIO0_FIODIR_DIR4_bb bitband_t BITBAND(&LPC_GPIO0->FIODIR, LPC_GPIO_FIODIR_DIR4_bit)
#define LPC_GPIO0_FIODIR_DIR5_bb bitband_t BITBAND(&LPC_GPIO0->FIODIR, LPC_GPIO_FIODIR_DIR5_bit)
#define LPC_GPIO0_FIODIR_DIR6_bb bitband_t BITBAND(&LPC_GPIO0->FIODIR, LPC_GPIO_FIODIR_DIR6_bit)
#define LPC_GPIO0_FIODIR_DIR7_bb bitband_t BITBAND(&LPC_GPIO0->FIODIR, LPC_GPIO_FIODIR_DIR7_bit)
#define LPC_GPIO0_FIODIR_DIR8_bb bitband_t BITBAND(&LPC_GPIO0->FIODIR, LPC_GPIO_FIODIR_DIR8_bit)
#define LPC_GPIO0_FIODIR_DIR9_bb bitband_t BITBAND(&LPC_GPIO0->FIODIR, LPC_GPIO_FIODIR_DIR9_bit)
#define LPC_GPIO0_FIODIR_DIR10_bb bitband_t BITBAND(&LPC_GPIO0->FIODIR, LPC_GPIO_FIODIR_DIR10_bit)
#define LPC_GPIO0_FIODIR_DIR11_bb bitband_t BITBAND(&LPC_GPIO0->FIODIR, LPC_GPIO_FIODIR_DIR11_bit)
#define LPC_GPIO0_FIODIR_DIR15_bb bitband_t BITBAND(&LPC_GPIO0->FIODIR, LPC_GPIO_FIODIR_DIR15_bit)
#define LPC_GPIO0_FIODIR_DIR16_bb bitband_t BITBAND(&LPC_GPIO0->FIODIR, LPC_GPIO_FIODIR_DIR16_bit)
#define LPC_GPIO0_FIODIR_DIR17_bb bitband_t BITBAND(&LPC_GPIO0->FIODIR, LPC_GPIO_FIODIR_DIR17_bit)
#define LPC_GPIO0_FIODIR_DIR18_bb bitband_t BITBAND(&LPC_GPIO0->FIODIR, LPC_GPIO_FIODIR_DIR18_bit)
#define LPC_GPIO0_FIODIR_DIR19_bb bitband_t BITBAND(&LPC_GPIO0->FIODIR, LPC_GPIO_FIODIR_DIR19_bit)
#define LPC_GPIO0_FIODIR_DIR20_bb bitband_t BITBAND(&LPC_GPIO0->FIODIR, LPC_GPIO_FIODIR_DIR20_bit)
#define LPC_GPIO0_FIODIR_DIR21_bb bitband_t BITBAND(&LPC_GPIO0->FIODIR, LPC_GPIO_FIODIR_DIR21_bit)
#define LPC_GPIO0_FIODIR_DIR22_bb bitband_t BITBAND(&LPC_GPIO0->FIODIR, LPC_GPIO_FIODIR_DIR22_bit)
#define LPC_GPIO0_FIODIR_DIR23_bb bitband_t BITBAND(&LPC_GPIO0->FIODIR, LPC_GPIO_FIODIR_DIR23_bit)
#define LPC_GPIO0_FIODIR_DIR24_bb bitband_t BITBAND(&LPC_GPIO0->FIODIR, LPC_GPIO_FIODIR_DIR24_bit)
#define LPC_GPIO0_FIODIR_DIR25_bb bitband_t BITBAND(&LPC_GPIO0->FIODIR, LPC_GPIO_FIODIR_DIR25_bit)
#define LPC_GPIO0_FIODIR_DIR26_bb bitband_t BITBAND(&LPC_GPIO0->FIODIR, LPC_GPIO_FIODIR_DIR26_bit)
#define LPC_GPIO0_FIODIR_DIR27_bb bitband_t BITBAND(&LPC_GPIO0->FIODIR, LPC_GPIO_FIODIR_DIR27_bit)
#define LPC_GPIO0_FIODIR_DIR28_bb bitband_t BITBAND(&LPC_GPIO0->FIODIR, LPC_GPIO_FIODIR_DIR28_bit)
#define LPC_GPIO0_FIODIR_DIR29_bb bitband_t BITBAND(&LPC_GPIO0->FIODIR, LPC_GPIO_FIODIR_DIR29_bit)
#define LPC_GPIO0_FIODIR_DIR30_bb bitband_t BITBAND(&LPC_GPIO0->FIODIR, LPC_GPIO_FIODIR_DIR30_bit)
#define LPC_GPIO1_FIODIR_DIR0_bb bitband_t BITBAND(&LPC_GPIO1->FIODIR, LPC_GPIO_FIODIR_DIR0_bit)
#define LPC_GPIO1_FIODIR_DIR1_bb bitband_t BITBAND(&LPC_GPIO1->FIODIR, LPC_GPIO_FIODIR_DIR1_bit)
#define LPC_GPIO1_FIODIR_DIR4_bb bitband_t BITBAND(&LPC_GPIO1->FIODIR, LPC_GPIO_FIODIR_DIR4_bit)
#define LPC_GPIO1_FIODIR_DIR8_bb bitband_t BITBAND(&LPC_GPIO1->FIODIR, LPC_GPIO_FIODIR_DIR8_bit)
#define LPC_GPIO1_FIODIR_DIR9_bb bitband_t BITBAND(&LPC_GPIO1->FIODIR, LPC_GPIO_FIODIR_DIR9_bit)
#define LPC_GPIO1_FIODIR_DIR10_bb bitband_t BITBAND(&LPC_GPIO1->FIODIR, LPC_GPIO_FIODIR_DIR10_bit)
#define LPC_GPIO1_FIODIR_DIR14_bb bitband_t BITBAND(&LPC_GPIO1->FIODIR, LPC_GPIO_FIODIR_DIR14_bit)
#define LPC_GPIO1_FIODIR_DIR15_bb bitband_t BITBAND(&LPC_GPIO1->FIODIR, LPC_GPIO_FIODIR_DIR15_bit)
#define LPC_GPIO1_FIODIR_DIR16_bb bitband_t BITBAND(&LPC_GPIO1->FIODIR, LPC_GPIO_FIODIR_DIR16_bit)
#define LPC_GPIO1_FIODIR_DIR17_bb bitband_t BITBAND(&LPC_GPIO1->FIODIR, LPC_GPIO_FIODIR_DIR17_bit)
#define LPC_GPIO1_FIODIR_DIR18_bb bitband_t BITBAND(&LPC_GPIO1->FIODIR, LPC_GPIO_FIODIR_DIR18_bit)
#define LPC_GPIO1_FIODIR_DIR19_bb bitband_t BITBAND(&LPC_GPIO1->FIODIR, LPC_GPIO_FIODIR_DIR19_bit)
#define LPC_GPIO1_FIODIR_DIR20_bb bitband_t BITBAND(&LPC_GPIO1->FIODIR, LPC_GPIO_FIODIR_DIR20_bit)
#define LPC_GPIO1_FIODIR_DIR21_bb bitband_t BITBAND(&LPC_GPIO1->FIODIR, LPC_GPIO_FIODIR_DIR21_bit)
#define LPC_GPIO1_FIODIR_DIR22_bb bitband_t BITBAND(&LPC_GPIO1->FIODIR, LPC_GPIO_FIODIR_DIR22_bit)
#define LPC_GPIO1_FIODIR_DIR23_bb bitband_t BITBAND(&LPC_GPIO1->FIODIR, LPC_GPIO_FIODIR_DIR23_bit)
#define LPC_GPIO1_FIODIR_DIR24_bb bitband_t BITBAND(&LPC_GPIO1->FIODIR, LPC_GPIO_FIODIR_DIR24_bit)
#define LPC_GPIO1_FIODIR_DIR25_bb bitband_t BITBAND(&LPC_GPIO1->FIODIR, LPC_GPIO_FIODIR_DIR25_bit)
#define LPC_GPIO1_FIODIR_DIR26_bb bitband_t BITBAND(&LPC_GPIO1->FIODIR, LPC_GPIO_FIODIR_DIR26_bit)
#define LPC_GPIO1_FIODIR_DIR27_bb bitband_t BITBAND(&LPC_GPIO1->FIODIR, LPC_GPIO_FIODIR_DIR27_bit)
#define LPC_GPIO1_FIODIR_DIR28_bb bitband_t BITBAND(&LPC_GPIO1->FIODIR, LPC_GPIO_FIODIR_DIR28_bit)
#define LPC_GPIO1_FIODIR_DIR29_bb bitband_t BITBAND(&LPC_GPIO1->FIODIR, LPC_GPIO_FIODIR_DIR29_bit)
#define LPC_GPIO1_FIODIR_DIR30_bb bitband_t BITBAND(&LPC_GPIO1->FIODIR, LPC_GPIO_FIODIR_DIR30_bit)
#define LPC_GPIO1_FIODIR_DIR31_bb bitband_t BITBAND(&LPC_GPIO1->FIODIR, LPC_GPIO_FIODIR_DIR31_bit)
#define LPC_GPIO2_FIODIR_DIR0_bb bitband_t BITBAND(&LPC_GPIO2->FIODIR, LPC_GPIO_FIODIR_DIR0_bit)
#define LPC_GPIO2_FIODIR_DIR1_bb bitband_t BITBAND(&LPC_GPIO2->FIODIR, LPC_GPIO_FIODIR_DIR1_bit)
#define LPC_GPIO2_FIODIR_DIR2_bb bitband_t BITBAND(&LPC_GPIO2->FIODIR, LPC_GPIO_FIODIR_DIR2_bit)
#define LPC_GPIO2_FIODIR_DIR3_bb bitband_t BITBAND(&LPC_GPIO2->FIODIR, LPC_GPIO_FIODIR_DIR3_bit)
#define LPC_GPIO2_FIODIR_DIR4_bb bitband_t BITBAND(&LPC_GPIO2->FIODIR, LPC_GPIO_FIODIR_DIR4_bit)
#define LPC_GPIO2_FIODIR_DIR5_bb bitband_t BITBAND(&LPC_GPIO2->FIODIR, LPC_GPIO_FIODIR_DIR5_bit)
#define LPC_GPIO2_FIODIR_DIR6_bb bitband_t BITBAND(&LPC_GPIO2->FIODIR, LPC_GPIO_FIODIR_DIR6_bit)
#define LPC_GPIO2_FIODIR_DIR7_bb bitband_t BITBAND(&LPC_GPIO2->FIODIR, LPC_GPIO_FIODIR_DIR7_bit)
#define LPC_GPIO2_FIODIR_DIR8_bb bitband_t BITBAND(&LPC_GPIO2->FIODIR, LPC_GPIO_FIODIR_DIR8_bit)
#define LPC_GPIO2_FIODIR_DIR9_bb bitband_t BITBAND(&LPC_GPIO2->FIODIR, LPC_GPIO_FIODIR_DIR9_bit)
#define LPC_GPIO2_FIODIR_DIR10_bb bitband_t BITBAND(&LPC_GPIO2->FIODIR, LPC_GPIO_FIODIR_DIR10_bit)
#define LPC_GPIO2_FIODIR_DIR11_bb bitband_t BITBAND(&LPC_GPIO2->FIODIR, LPC_GPIO_FIODIR_DIR11_bit)
#define LPC_GPIO2_FIODIR_DIR12_bb bitband_t BITBAND(&LPC_GPIO2->FIODIR, LPC_GPIO_FIODIR_DIR12_bit)
#define LPC_GPIO2_FIODIR_DIR13_bb bitband_t BITBAND(&LPC_GPIO2->FIODIR, LPC_GPIO_FIODIR_DIR13_bit)
#define LPC_GPIO3_FIODIR_DIR25_bb bitband_t BITBAND(&LPC_GPIO3->FIODIR, LPC_GPIO_FIODIR_DIR25_bit)
#define LPC_GPIO3_FIODIR_DIR26_bb bitband_t BITBAND(&LPC_GPIO3->FIODIR, LPC_GPIO_FIODIR_DIR26_bit)
#define LPC_GPIO4_FIODIR_DIR28_bb bitband_t BITBAND(&LPC_GPIO4->FIODIR, LPC_GPIO_FIODIR_DIR28_bit)
#define LPC_GPIO4_FIODIR_DIR29_bb bitband_t BITBAND(&LPC_GPIO4->FIODIR, LPC_GPIO_FIODIR_DIR29_bit)
/*
+-----------------------------------------------------------------------------+
| FIOSET - GPIO port output Set register
+-----------------------------------------------------------------------------+
*/
#define LPC_GPIO_FIOSET_SET0_bit 0
#define LPC_GPIO_FIOSET_SET1_bit 1
#define LPC_GPIO_FIOSET_SET2_bit 2
#define LPC_GPIO_FIOSET_SET3_bit 3
#define LPC_GPIO_FIOSET_SET4_bit 4
#define LPC_GPIO_FIOSET_SET5_bit 5
#define LPC_GPIO_FIOSET_SET6_bit 6
#define LPC_GPIO_FIOSET_SET7_bit 7
#define LPC_GPIO_FIOSET_SET8_bit 8
#define LPC_GPIO_FIOSET_SET9_bit 9
#define LPC_GPIO_FIOSET_SET10_bit 10
#define LPC_GPIO_FIOSET_SET11_bit 11
#define LPC_GPIO_FIOSET_SET12_bit 12
#define LPC_GPIO_FIOSET_SET13_bit 13
#define LPC_GPIO_FIOSET_SET14_bit 14
#define LPC_GPIO_FIOSET_SET15_bit 15
#define LPC_GPIO_FIOSET_SET16_bit 16
#define LPC_GPIO_FIOSET_SET17_bit 17
#define LPC_GPIO_FIOSET_SET18_bit 18
#define LPC_GPIO_FIOSET_SET19_bit 19
#define LPC_GPIO_FIOSET_SET20_bit 20
#define LPC_GPIO_FIOSET_SET21_bit 21
#define LPC_GPIO_FIOSET_SET22_bit 22
#define LPC_GPIO_FIOSET_SET23_bit 23
#define LPC_GPIO_FIOSET_SET24_bit 24
#define LPC_GPIO_FIOSET_SET25_bit 25
#define LPC_GPIO_FIOSET_SET26_bit 26
#define LPC_GPIO_FIOSET_SET27_bit 27
#define LPC_GPIO_FIOSET_SET28_bit 28
#define LPC_GPIO_FIOSET_SET29_bit 29
#define LPC_GPIO_FIOSET_SET30_bit 30
#define LPC_GPIO_FIOSET_SET31_bit 31
#define LPC_GPIO_FIOSET_SET0 (1 << LPC_GPIO_FIOSET_SET0_bit)
#define LPC_GPIO_FIOSET_SET1 (1 << LPC_GPIO_FIOSET_SET1_bit)
#define LPC_GPIO_FIOSET_SET2 (1 << LPC_GPIO_FIOSET_SET2_bit)
#define LPC_GPIO_FIOSET_SET3 (1 << LPC_GPIO_FIOSET_SET3_bit)
#define LPC_GPIO_FIOSET_SET4 (1 << LPC_GPIO_FIOSET_SET4_bit)
#define LPC_GPIO_FIOSET_SET5 (1 << LPC_GPIO_FIOSET_SET5_bit)
#define LPC_GPIO_FIOSET_SET6 (1 << LPC_GPIO_FIOSET_SET6_bit)
#define LPC_GPIO_FIOSET_SET7 (1 << LPC_GPIO_FIOSET_SET7_bit)
#define LPC_GPIO_FIOSET_SET8 (1 << LPC_GPIO_FIOSET_SET8_bit)
#define LPC_GPIO_FIOSET_SET9 (1 << LPC_GPIO_FIOSET_SET9_bit)
#define LPC_GPIO_FIOSET_SET10 (1 << LPC_GPIO_FIOSET_SET10_bit)
#define LPC_GPIO_FIOSET_SET11 (1 << LPC_GPIO_FIOSET_SET11_bit)
#define LPC_GPIO_FIOSET_SET12 (1 << LPC_GPIO_FIOSET_SET12_bit)
#define LPC_GPIO_FIOSET_SET13 (1 << LPC_GPIO_FIOSET_SET13_bit)
#define LPC_GPIO_FIOSET_SET14 (1 << LPC_GPIO_FIOSET_SET14_bit)
#define LPC_GPIO_FIOSET_SET15 (1 << LPC_GPIO_FIOSET_SET15_bit)
#define LPC_GPIO_FIOSET_SET16 (1 << LPC_GPIO_FIOSET_SET16_bit)
#define LPC_GPIO_FIOSET_SET17 (1 << LPC_GPIO_FIOSET_SET17_bit)
#define LPC_GPIO_FIOSET_SET18 (1 << LPC_GPIO_FIOSET_SET18_bit)
#define LPC_GPIO_FIOSET_SET19 (1 << LPC_GPIO_FIOSET_SET19_bit)
#define LPC_GPIO_FIOSET_SET20 (1 << LPC_GPIO_FIOSET_SET20_bit)
#define LPC_GPIO_FIOSET_SET21 (1 << LPC_GPIO_FIOSET_SET21_bit)
#define LPC_GPIO_FIOSET_SET22 (1 << LPC_GPIO_FIOSET_SET22_bit)
#define LPC_GPIO_FIOSET_SET23 (1 << LPC_GPIO_FIOSET_SET23_bit)
#define LPC_GPIO_FIOSET_SET24 (1 << LPC_GPIO_FIOSET_SET24_bit)
#define LPC_GPIO_FIOSET_SET25 (1 << LPC_GPIO_FIOSET_SET25_bit)
#define LPC_GPIO_FIOSET_SET26 (1 << LPC_GPIO_FIOSET_SET26_bit)
#define LPC_GPIO_FIOSET_SET27 (1 << LPC_GPIO_FIOSET_SET27_bit)
#define LPC_GPIO_FIOSET_SET28 (1 << LPC_GPIO_FIOSET_SET28_bit)
#define LPC_GPIO_FIOSET_SET29 (1 << LPC_GPIO_FIOSET_SET29_bit)
#define LPC_GPIO_FIOSET_SET30 (1 << LPC_GPIO_FIOSET_SET30_bit)
#define LPC_GPIO_FIOSET_SET31 (1 << LPC_GPIO_FIOSET_SET31_bit)
#define LPC_GPIO0_FIOSET_SET0_bb bitband_t BITBAND(&LPC_GPIO0->FIOSET, LPC_GPIO_FIOSET_SET0_bit)
#define LPC_GPIO0_FIOSET_SET1_bb bitband_t BITBAND(&LPC_GPIO0->FIOSET, LPC_GPIO_FIOSET_SET1_bit)
#define LPC_GPIO0_FIOSET_SET2_bb bitband_t BITBAND(&LPC_GPIO0->FIOSET, LPC_GPIO_FIOSET_SET2_bit)
#define LPC_GPIO0_FIOSET_SET3_bb bitband_t BITBAND(&LPC_GPIO0->FIOSET, LPC_GPIO_FIOSET_SET3_bit)
#define LPC_GPIO0_FIOSET_SET4_bb bitband_t BITBAND(&LPC_GPIO0->FIOSET, LPC_GPIO_FIOSET_SET4_bit)
#define LPC_GPIO0_FIOSET_SET5_bb bitband_t BITBAND(&LPC_GPIO0->FIOSET, LPC_GPIO_FIOSET_SET5_bit)
#define LPC_GPIO0_FIOSET_SET6_bb bitband_t BITBAND(&LPC_GPIO0->FIOSET, LPC_GPIO_FIOSET_SET6_bit)
#define LPC_GPIO0_FIOSET_SET7_bb bitband_t BITBAND(&LPC_GPIO0->FIOSET, LPC_GPIO_FIOSET_SET7_bit)
#define LPC_GPIO0_FIOSET_SET8_bb bitband_t BITBAND(&LPC_GPIO0->FIOSET, LPC_GPIO_FIOSET_SET8_bit)
#define LPC_GPIO0_FIOSET_SET9_bb bitband_t BITBAND(&LPC_GPIO0->FIOSET, LPC_GPIO_FIOSET_SET9_bit)
#define LPC_GPIO0_FIOSET_SET10_bb bitband_t BITBAND(&LPC_GPIO0->FIOSET, LPC_GPIO_FIOSET_SET10_bit)
#define LPC_GPIO0_FIOSET_SET11_bb bitband_t BITBAND(&LPC_GPIO0->FIOSET, LPC_GPIO_FIOSET_SET11_bit)
#define LPC_GPIO0_FIOSET_SET15_bb bitband_t BITBAND(&LPC_GPIO0->FIOSET, LPC_GPIO_FIOSET_SET15_bit)
#define LPC_GPIO0_FIOSET_SET16_bb bitband_t BITBAND(&LPC_GPIO0->FIOSET, LPC_GPIO_FIOSET_SET16_bit)
#define LPC_GPIO0_FIOSET_SET17_bb bitband_t BITBAND(&LPC_GPIO0->FIOSET, LPC_GPIO_FIOSET_SET17_bit)
#define LPC_GPIO0_FIOSET_SET18_bb bitband_t BITBAND(&LPC_GPIO0->FIOSET, LPC_GPIO_FIOSET_SET18_bit)
#define LPC_GPIO0_FIOSET_SET19_bb bitband_t BITBAND(&LPC_GPIO0->FIOSET, LPC_GPIO_FIOSET_SET19_bit)
#define LPC_GPIO0_FIOSET_SET20_bb bitband_t BITBAND(&LPC_GPIO0->FIOSET, LPC_GPIO_FIOSET_SET20_bit)
#define LPC_GPIO0_FIOSET_SET21_bb bitband_t BITBAND(&LPC_GPIO0->FIOSET, LPC_GPIO_FIOSET_SET21_bit)
#define LPC_GPIO0_FIOSET_SET22_bb bitband_t BITBAND(&LPC_GPIO0->FIOSET, LPC_GPIO_FIOSET_SET22_bit)
#define LPC_GPIO0_FIOSET_SET23_bb bitband_t BITBAND(&LPC_GPIO0->FIOSET, LPC_GPIO_FIOSET_SET23_bit)
#define LPC_GPIO0_FIOSET_SET24_bb bitband_t BITBAND(&LPC_GPIO0->FIOSET, LPC_GPIO_FIOSET_SET24_bit)
#define LPC_GPIO0_FIOSET_SET25_bb bitband_t BITBAND(&LPC_GPIO0->FIOSET, LPC_GPIO_FIOSET_SET25_bit)
#define LPC_GPIO0_FIOSET_SET26_bb bitband_t BITBAND(&LPC_GPIO0->FIOSET, LPC_GPIO_FIOSET_SET26_bit)
#define LPC_GPIO0_FIOSET_SET27_bb bitband_t BITBAND(&LPC_GPIO0->FIOSET, LPC_GPIO_FIOSET_SET27_bit)
#define LPC_GPIO0_FIOSET_SET28_bb bitband_t BITBAND(&LPC_GPIO0->FIOSET, LPC_GPIO_FIOSET_SET28_bit)
#define LPC_GPIO0_FIOSET_SET29_bb bitband_t BITBAND(&LPC_GPIO0->FIOSET, LPC_GPIO_FIOSET_SET29_bit)
#define LPC_GPIO0_FIOSET_SET30_bb bitband_t BITBAND(&LPC_GPIO0->FIOSET, LPC_GPIO_FIOSET_SET30_bit)
#define LPC_GPIO1_FIOSET_SET0_bb bitband_t BITBAND(&LPC_GPIO1->FIOSET, LPC_GPIO_FIOSET_SET0_bit)
#define LPC_GPIO1_FIOSET_SET1_bb bitband_t BITBAND(&LPC_GPIO1->FIOSET, LPC_GPIO_FIOSET_SET1_bit)
#define LPC_GPIO1_FIOSET_SET4_bb bitband_t BITBAND(&LPC_GPIO1->FIOSET, LPC_GPIO_FIOSET_SET4_bit)
#define LPC_GPIO1_FIOSET_SET8_bb bitband_t BITBAND(&LPC_GPIO1->FIOSET, LPC_GPIO_FIOSET_SET8_bit)
#define LPC_GPIO1_FIOSET_SET9_bb bitband_t BITBAND(&LPC_GPIO1->FIOSET, LPC_GPIO_FIOSET_SET9_bit)
#define LPC_GPIO1_FIOSET_SET10_bb bitband_t BITBAND(&LPC_GPIO1->FIOSET, LPC_GPIO_FIOSET_SET10_bit)
#define LPC_GPIO1_FIOSET_SET14_bb bitband_t BITBAND(&LPC_GPIO1->FIOSET, LPC_GPIO_FIOSET_SET14_bit)
#define LPC_GPIO1_FIOSET_SET15_bb bitband_t BITBAND(&LPC_GPIO1->FIOSET, LPC_GPIO_FIOSET_SET15_bit)
#define LPC_GPIO1_FIOSET_SET16_bb bitband_t BITBAND(&LPC_GPIO1->FIOSET, LPC_GPIO_FIOSET_SET16_bit)
#define LPC_GPIO1_FIOSET_SET17_bb bitband_t BITBAND(&LPC_GPIO1->FIOSET, LPC_GPIO_FIOSET_SET17_bit)
#define LPC_GPIO1_FIOSET_SET18_bb bitband_t BITBAND(&LPC_GPIO1->FIOSET, LPC_GPIO_FIOSET_SET18_bit)
#define LPC_GPIO1_FIOSET_SET19_bb bitband_t BITBAND(&LPC_GPIO1->FIOSET, LPC_GPIO_FIOSET_SET19_bit)
#define LPC_GPIO1_FIOSET_SET20_bb bitband_t BITBAND(&LPC_GPIO1->FIOSET, LPC_GPIO_FIOSET_SET20_bit)
#define LPC_GPIO1_FIOSET_SET21_bb bitband_t BITBAND(&LPC_GPIO1->FIOSET, LPC_GPIO_FIOSET_SET21_bit)
#define LPC_GPIO1_FIOSET_SET22_bb bitband_t BITBAND(&LPC_GPIO1->FIOSET, LPC_GPIO_FIOSET_SET22_bit)
#define LPC_GPIO1_FIOSET_SET23_bb bitband_t BITBAND(&LPC_GPIO1->FIOSET, LPC_GPIO_FIOSET_SET23_bit)
#define LPC_GPIO1_FIOSET_SET24_bb bitband_t BITBAND(&LPC_GPIO1->FIOSET, LPC_GPIO_FIOSET_SET24_bit)
#define LPC_GPIO1_FIOSET_SET25_bb bitband_t BITBAND(&LPC_GPIO1->FIOSET, LPC_GPIO_FIOSET_SET25_bit)
#define LPC_GPIO1_FIOSET_SET26_bb bitband_t BITBAND(&LPC_GPIO1->FIOSET, LPC_GPIO_FIOSET_SET26_bit)
#define LPC_GPIO1_FIOSET_SET27_bb bitband_t BITBAND(&LPC_GPIO1->FIOSET, LPC_GPIO_FIOSET_SET27_bit)
#define LPC_GPIO1_FIOSET_SET28_bb bitband_t BITBAND(&LPC_GPIO1->FIOSET, LPC_GPIO_FIOSET_SET28_bit)
#define LPC_GPIO1_FIOSET_SET29_bb bitband_t BITBAND(&LPC_GPIO1->FIOSET, LPC_GPIO_FIOSET_SET29_bit)
#define LPC_GPIO1_FIOSET_SET30_bb bitband_t BITBAND(&LPC_GPIO1->FIOSET, LPC_GPIO_FIOSET_SET30_bit)
#define LPC_GPIO1_FIOSET_SET31_bb bitband_t BITBAND(&LPC_GPIO1->FIOSET, LPC_GPIO_FIOSET_SET31_bit)
#define LPC_GPIO2_FIOSET_SET0_bb bitband_t BITBAND(&LPC_GPIO2->FIOSET, LPC_GPIO_FIOSET_SET0_bit)
#define LPC_GPIO2_FIOSET_SET1_bb bitband_t BITBAND(&LPC_GPIO2->FIOSET, LPC_GPIO_FIOSET_SET1_bit)
#define LPC_GPIO2_FIOSET_SET2_bb bitband_t BITBAND(&LPC_GPIO2->FIOSET, LPC_GPIO_FIOSET_SET2_bit)
#define LPC_GPIO2_FIOSET_SET3_bb bitband_t BITBAND(&LPC_GPIO2->FIOSET, LPC_GPIO_FIOSET_SET3_bit)
#define LPC_GPIO2_FIOSET_SET4_bb bitband_t BITBAND(&LPC_GPIO2->FIOSET, LPC_GPIO_FIOSET_SET4_bit)
#define LPC_GPIO2_FIOSET_SET5_bb bitband_t BITBAND(&LPC_GPIO2->FIOSET, LPC_GPIO_FIOSET_SET5_bit)
#define LPC_GPIO2_FIOSET_SET6_bb bitband_t BITBAND(&LPC_GPIO2->FIOSET, LPC_GPIO_FIOSET_SET6_bit)
#define LPC_GPIO2_FIOSET_SET7_bb bitband_t BITBAND(&LPC_GPIO2->FIOSET, LPC_GPIO_FIOSET_SET7_bit)
#define LPC_GPIO2_FIOSET_SET8_bb bitband_t BITBAND(&LPC_GPIO2->FIOSET, LPC_GPIO_FIOSET_SET8_bit)
#define LPC_GPIO2_FIOSET_SET9_bb bitband_t BITBAND(&LPC_GPIO2->FIOSET, LPC_GPIO_FIOSET_SET9_bit)
#define LPC_GPIO2_FIOSET_SET10_bb bitband_t BITBAND(&LPC_GPIO2->FIOSET, LPC_GPIO_FIOSET_SET10_bit)
#define LPC_GPIO2_FIOSET_SET11_bb bitband_t BITBAND(&LPC_GPIO2->FIOSET, LPC_GPIO_FIOSET_SET11_bit)
#define LPC_GPIO2_FIOSET_SET12_bb bitband_t BITBAND(&LPC_GPIO2->FIOSET, LPC_GPIO_FIOSET_SET12_bit)
#define LPC_GPIO2_FIOSET_SET13_bb bitband_t BITBAND(&LPC_GPIO2->FIOSET, LPC_GPIO_FIOSET_SET13_bit)
#define LPC_GPIO3_FIOSET_SET25_bb bitband_t BITBAND(&LPC_GPIO3->FIOSET, LPC_GPIO_FIOSET_SET25_bit)
#define LPC_GPIO3_FIOSET_SET26_bb bitband_t BITBAND(&LPC_GPIO3->FIOSET, LPC_GPIO_FIOSET_SET26_bit)
#define LPC_GPIO4_FIOSET_SET28_bb bitband_t BITBAND(&LPC_GPIO4->FIOSET, LPC_GPIO_FIOSET_SET28_bit)
#define LPC_GPIO4_FIOSET_SET29_bb bitband_t BITBAND(&LPC_GPIO4->FIOSET, LPC_GPIO_FIOSET_SET29_bit)
/*
+-----------------------------------------------------------------------------+
| FIOCLR - GPIO port output Clear register
+-----------------------------------------------------------------------------+
*/
#define LPC_GPIO_FIOCLR_CLR0_bit 0
#define LPC_GPIO_FIOCLR_CLR1_bit 1
#define LPC_GPIO_FIOCLR_CLR2_bit 2
#define LPC_GPIO_FIOCLR_CLR3_bit 3
#define LPC_GPIO_FIOCLR_CLR4_bit 4
#define LPC_GPIO_FIOCLR_CLR5_bit 5
#define LPC_GPIO_FIOCLR_CLR6_bit 6
#define LPC_GPIO_FIOCLR_CLR7_bit 7
#define LPC_GPIO_FIOCLR_CLR8_bit 8
#define LPC_GPIO_FIOCLR_CLR9_bit 9
#define LPC_GPIO_FIOCLR_CLR10_bit 10
#define LPC_GPIO_FIOCLR_CLR11_bit 11
#define LPC_GPIO_FIOCLR_CLR12_bit 12
#define LPC_GPIO_FIOCLR_CLR13_bit 13
#define LPC_GPIO_FIOCLR_CLR14_bit 14
#define LPC_GPIO_FIOCLR_CLR15_bit 15
#define LPC_GPIO_FIOCLR_CLR16_bit 16
#define LPC_GPIO_FIOCLR_CLR17_bit 17
#define LPC_GPIO_FIOCLR_CLR18_bit 18
#define LPC_GPIO_FIOCLR_CLR19_bit 19
#define LPC_GPIO_FIOCLR_CLR20_bit 20
#define LPC_GPIO_FIOCLR_CLR21_bit 21
#define LPC_GPIO_FIOCLR_CLR22_bit 22
#define LPC_GPIO_FIOCLR_CLR23_bit 23
#define LPC_GPIO_FIOCLR_CLR24_bit 24
#define LPC_GPIO_FIOCLR_CLR25_bit 25
#define LPC_GPIO_FIOCLR_CLR26_bit 26
#define LPC_GPIO_FIOCLR_CLR27_bit 27
#define LPC_GPIO_FIOCLR_CLR28_bit 28
#define LPC_GPIO_FIOCLR_CLR29_bit 29
#define LPC_GPIO_FIOCLR_CLR30_bit 30
#define LPC_GPIO_FIOCLR_CLR31_bit 31
#define LPC_GPIO_FIOCLR_CLR0 (1 << LPC_GPIO_FIOCLR_CLR0_bit)
#define LPC_GPIO_FIOCLR_CLR1 (1 << LPC_GPIO_FIOCLR_CLR1_bit)
#define LPC_GPIO_FIOCLR_CLR2 (1 << LPC_GPIO_FIOCLR_CLR2_bit)
#define LPC_GPIO_FIOCLR_CLR3 (1 << LPC_GPIO_FIOCLR_CLR3_bit)
#define LPC_GPIO_FIOCLR_CLR4 (1 << LPC_GPIO_FIOCLR_CLR4_bit)
#define LPC_GPIO_FIOCLR_CLR5 (1 << LPC_GPIO_FIOCLR_CLR5_bit)
#define LPC_GPIO_FIOCLR_CLR6 (1 << LPC_GPIO_FIOCLR_CLR6_bit)
#define LPC_GPIO_FIOCLR_CLR7 (1 << LPC_GPIO_FIOCLR_CLR7_bit)
#define LPC_GPIO_FIOCLR_CLR8 (1 << LPC_GPIO_FIOCLR_CLR8_bit)
#define LPC_GPIO_FIOCLR_CLR9 (1 << LPC_GPIO_FIOCLR_CLR9_bit)
#define LPC_GPIO_FIOCLR_CLR10 (1 << LPC_GPIO_FIOCLR_CLR10_bit)
#define LPC_GPIO_FIOCLR_CLR11 (1 << LPC_GPIO_FIOCLR_CLR11_bit)
#define LPC_GPIO_FIOCLR_CLR12 (1 << LPC_GPIO_FIOCLR_CLR12_bit)
#define LPC_GPIO_FIOCLR_CLR13 (1 << LPC_GPIO_FIOCLR_CLR13_bit)
#define LPC_GPIO_FIOCLR_CLR14 (1 << LPC_GPIO_FIOCLR_CLR14_bit)
#define LPC_GPIO_FIOCLR_CLR15 (1 << LPC_GPIO_FIOCLR_CLR15_bit)
#define LPC_GPIO_FIOCLR_CLR16 (1 << LPC_GPIO_FIOCLR_CLR16_bit)
#define LPC_GPIO_FIOCLR_CLR17 (1 << LPC_GPIO_FIOCLR_CLR17_bit)
#define LPC_GPIO_FIOCLR_CLR18 (1 << LPC_GPIO_FIOCLR_CLR18_bit)
#define LPC_GPIO_FIOCLR_CLR19 (1 << LPC_GPIO_FIOCLR_CLR19_bit)
#define LPC_GPIO_FIOCLR_CLR20 (1 << LPC_GPIO_FIOCLR_CLR20_bit)
#define LPC_GPIO_FIOCLR_CLR21 (1 << LPC_GPIO_FIOCLR_CLR21_bit)
#define LPC_GPIO_FIOCLR_CLR22 (1 << LPC_GPIO_FIOCLR_CLR22_bit)
#define LPC_GPIO_FIOCLR_CLR23 (1 << LPC_GPIO_FIOCLR_CLR23_bit)
#define LPC_GPIO_FIOCLR_CLR24 (1 << LPC_GPIO_FIOCLR_CLR24_bit)
#define LPC_GPIO_FIOCLR_CLR25 (1 << LPC_GPIO_FIOCLR_CLR25_bit)
#define LPC_GPIO_FIOCLR_CLR26 (1 << LPC_GPIO_FIOCLR_CLR26_bit)
#define LPC_GPIO_FIOCLR_CLR27 (1 << LPC_GPIO_FIOCLR_CLR27_bit)
#define LPC_GPIO_FIOCLR_CLR28 (1 << LPC_GPIO_FIOCLR_CLR28_bit)
#define LPC_GPIO_FIOCLR_CLR29 (1 << LPC_GPIO_FIOCLR_CLR29_bit)
#define LPC_GPIO_FIOCLR_CLR30 (1 << LPC_GPIO_FIOCLR_CLR30_bit)
#define LPC_GPIO_FIOCLR_CLR31 (1 << LPC_GPIO_FIOCLR_CLR31_bit)
#define LPC_GPIO0_FIOCLR_CLR0_bb bitband_t BITBAND(&LPC_GPIO0->FIOCLR, LPC_GPIO_FIOCLR_CLR0_bit)
#define LPC_GPIO0_FIOCLR_CLR1_bb bitband_t BITBAND(&LPC_GPIO0->FIOCLR, LPC_GPIO_FIOCLR_CLR1_bit)
#define LPC_GPIO0_FIOCLR_CLR2_bb bitband_t BITBAND(&LPC_GPIO0->FIOCLR, LPC_GPIO_FIOCLR_CLR2_bit)
#define LPC_GPIO0_FIOCLR_CLR3_bb bitband_t BITBAND(&LPC_GPIO0->FIOCLR, LPC_GPIO_FIOCLR_CLR3_bit)
#define LPC_GPIO0_FIOCLR_CLR4_bb bitband_t BITBAND(&LPC_GPIO0->FIOCLR, LPC_GPIO_FIOCLR_CLR4_bit)
#define LPC_GPIO0_FIOCLR_CLR5_bb bitband_t BITBAND(&LPC_GPIO0->FIOCLR, LPC_GPIO_FIOCLR_CLR5_bit)
#define LPC_GPIO0_FIOCLR_CLR6_bb bitband_t BITBAND(&LPC_GPIO0->FIOCLR, LPC_GPIO_FIOCLR_CLR6_bit)
#define LPC_GPIO0_FIOCLR_CLR7_bb bitband_t BITBAND(&LPC_GPIO0->FIOCLR, LPC_GPIO_FIOCLR_CLR7_bit)
#define LPC_GPIO0_FIOCLR_CLR8_bb bitband_t BITBAND(&LPC_GPIO0->FIOCLR, LPC_GPIO_FIOCLR_CLR8_bit)
#define LPC_GPIO0_FIOCLR_CLR9_bb bitband_t BITBAND(&LPC_GPIO0->FIOCLR, LPC_GPIO_FIOCLR_CLR9_bit)
#define LPC_GPIO0_FIOCLR_CLR10_bb bitband_t BITBAND(&LPC_GPIO0->FIOCLR, LPC_GPIO_FIOCLR_CLR10_bit)
#define LPC_GPIO0_FIOCLR_CLR11_bb bitband_t BITBAND(&LPC_GPIO0->FIOCLR, LPC_GPIO_FIOCLR_CLR11_bit)
#define LPC_GPIO0_FIOCLR_CLR15_bb bitband_t BITBAND(&LPC_GPIO0->FIOCLR, LPC_GPIO_FIOCLR_CLR15_bit)
#define LPC_GPIO0_FIOCLR_CLR16_bb bitband_t BITBAND(&LPC_GPIO0->FIOCLR, LPC_GPIO_FIOCLR_CLR16_bit)
#define LPC_GPIO0_FIOCLR_CLR17_bb bitband_t BITBAND(&LPC_GPIO0->FIOCLR, LPC_GPIO_FIOCLR_CLR17_bit)
#define LPC_GPIO0_FIOCLR_CLR18_bb bitband_t BITBAND(&LPC_GPIO0->FIOCLR, LPC_GPIO_FIOCLR_CLR18_bit)
#define LPC_GPIO0_FIOCLR_CLR19_bb bitband_t BITBAND(&LPC_GPIO0->FIOCLR, LPC_GPIO_FIOCLR_CLR19_bit)
#define LPC_GPIO0_FIOCLR_CLR20_bb bitband_t BITBAND(&LPC_GPIO0->FIOCLR, LPC_GPIO_FIOCLR_CLR20_bit)
#define LPC_GPIO0_FIOCLR_CLR21_bb bitband_t BITBAND(&LPC_GPIO0->FIOCLR, LPC_GPIO_FIOCLR_CLR21_bit)
#define LPC_GPIO0_FIOCLR_CLR22_bb bitband_t BITBAND(&LPC_GPIO0->FIOCLR, LPC_GPIO_FIOCLR_CLR22_bit)
#define LPC_GPIO0_FIOCLR_CLR23_bb bitband_t BITBAND(&LPC_GPIO0->FIOCLR, LPC_GPIO_FIOCLR_CLR23_bit)
#define LPC_GPIO0_FIOCLR_CLR24_bb bitband_t BITBAND(&LPC_GPIO0->FIOCLR, LPC_GPIO_FIOCLR_CLR24_bit)
#define LPC_GPIO0_FIOCLR_CLR25_bb bitband_t BITBAND(&LPC_GPIO0->FIOCLR, LPC_GPIO_FIOCLR_CLR25_bit)
#define LPC_GPIO0_FIOCLR_CLR26_bb bitband_t BITBAND(&LPC_GPIO0->FIOCLR, LPC_GPIO_FIOCLR_CLR26_bit)
#define LPC_GPIO0_FIOCLR_CLR27_bb bitband_t BITBAND(&LPC_GPIO0->FIOCLR, LPC_GPIO_FIOCLR_CLR27_bit)
#define LPC_GPIO0_FIOCLR_CLR28_bb bitband_t BITBAND(&LPC_GPIO0->FIOCLR, LPC_GPIO_FIOCLR_CLR28_bit)
#define LPC_GPIO0_FIOCLR_CLR29_bb bitband_t BITBAND(&LPC_GPIO0->FIOCLR, LPC_GPIO_FIOCLR_CLR29_bit)
#define LPC_GPIO0_FIOCLR_CLR30_bb bitband_t BITBAND(&LPC_GPIO0->FIOCLR, LPC_GPIO_FIOCLR_CLR30_bit)
#define LPC_GPIO1_FIOCLR_CLR0_bb bitband_t BITBAND(&LPC_GPIO1->FIOCLR, LPC_GPIO_FIOCLR_CLR0_bit)
#define LPC_GPIO1_FIOCLR_CLR1_bb bitband_t BITBAND(&LPC_GPIO1->FIOCLR, LPC_GPIO_FIOCLR_CLR1_bit)
#define LPC_GPIO1_FIOCLR_CLR4_bb bitband_t BITBAND(&LPC_GPIO1->FIOCLR, LPC_GPIO_FIOCLR_CLR4_bit)
#define LPC_GPIO1_FIOCLR_CLR8_bb bitband_t BITBAND(&LPC_GPIO1->FIOCLR, LPC_GPIO_FIOCLR_CLR8_bit)
#define LPC_GPIO1_FIOCLR_CLR9_bb bitband_t BITBAND(&LPC_GPIO1->FIOCLR, LPC_GPIO_FIOCLR_CLR9_bit)
#define LPC_GPIO1_FIOCLR_CLR10_bb bitband_t BITBAND(&LPC_GPIO1->FIOCLR, LPC_GPIO_FIOCLR_CLR10_bit)
#define LPC_GPIO1_FIOCLR_CLR14_bb bitband_t BITBAND(&LPC_GPIO1->FIOCLR, LPC_GPIO_FIOCLR_CLR14_bit)
#define LPC_GPIO1_FIOCLR_CLR15_bb bitband_t BITBAND(&LPC_GPIO1->FIOCLR, LPC_GPIO_FIOCLR_CLR15_bit)
#define LPC_GPIO1_FIOCLR_CLR16_bb bitband_t BITBAND(&LPC_GPIO1->FIOCLR, LPC_GPIO_FIOCLR_CLR16_bit)
#define LPC_GPIO1_FIOCLR_CLR17_bb bitband_t BITBAND(&LPC_GPIO1->FIOCLR, LPC_GPIO_FIOCLR_CLR17_bit)
#define LPC_GPIO1_FIOCLR_CLR18_bb bitband_t BITBAND(&LPC_GPIO1->FIOCLR, LPC_GPIO_FIOCLR_CLR18_bit)
#define LPC_GPIO1_FIOCLR_CLR19_bb bitband_t BITBAND(&LPC_GPIO1->FIOCLR, LPC_GPIO_FIOCLR_CLR19_bit)
#define LPC_GPIO1_FIOCLR_CLR20_bb bitband_t BITBAND(&LPC_GPIO1->FIOCLR, LPC_GPIO_FIOCLR_CLR20_bit)
#define LPC_GPIO1_FIOCLR_CLR21_bb bitband_t BITBAND(&LPC_GPIO1->FIOCLR, LPC_GPIO_FIOCLR_CLR21_bit)
#define LPC_GPIO1_FIOCLR_CLR22_bb bitband_t BITBAND(&LPC_GPIO1->FIOCLR, LPC_GPIO_FIOCLR_CLR22_bit)
#define LPC_GPIO1_FIOCLR_CLR23_bb bitband_t BITBAND(&LPC_GPIO1->FIOCLR, LPC_GPIO_FIOCLR_CLR23_bit)
#define LPC_GPIO1_FIOCLR_CLR24_bb bitband_t BITBAND(&LPC_GPIO1->FIOCLR, LPC_GPIO_FIOCLR_CLR24_bit)
#define LPC_GPIO1_FIOCLR_CLR25_bb bitband_t BITBAND(&LPC_GPIO1->FIOCLR, LPC_GPIO_FIOCLR_CLR25_bit)
#define LPC_GPIO1_FIOCLR_CLR26_bb bitband_t BITBAND(&LPC_GPIO1->FIOCLR, LPC_GPIO_FIOCLR_CLR26_bit)
#define LPC_GPIO1_FIOCLR_CLR27_bb bitband_t BITBAND(&LPC_GPIO1->FIOCLR, LPC_GPIO_FIOCLR_CLR27_bit)
#define LPC_GPIO1_FIOCLR_CLR28_bb bitband_t BITBAND(&LPC_GPIO1->FIOCLR, LPC_GPIO_FIOCLR_CLR28_bit)
#define LPC_GPIO1_FIOCLR_CLR29_bb bitband_t BITBAND(&LPC_GPIO1->FIOCLR, LPC_GPIO_FIOCLR_CLR29_bit)
#define LPC_GPIO1_FIOCLR_CLR30_bb bitband_t BITBAND(&LPC_GPIO1->FIOCLR, LPC_GPIO_FIOCLR_CLR30_bit)
#define LPC_GPIO1_FIOCLR_CLR31_bb bitband_t BITBAND(&LPC_GPIO1->FIOCLR, LPC_GPIO_FIOCLR_CLR31_bit)
#define LPC_GPIO2_FIOCLR_CLR0_bb bitband_t BITBAND(&LPC_GPIO2->FIOCLR, LPC_GPIO_FIOCLR_CLR0_bit)
#define LPC_GPIO2_FIOCLR_CLR1_bb bitband_t BITBAND(&LPC_GPIO2->FIOCLR, LPC_GPIO_FIOCLR_CLR1_bit)
#define LPC_GPIO2_FIOCLR_CLR2_bb bitband_t BITBAND(&LPC_GPIO2->FIOCLR, LPC_GPIO_FIOCLR_CLR2_bit)
#define LPC_GPIO2_FIOCLR_CLR3_bb bitband_t BITBAND(&LPC_GPIO2->FIOCLR, LPC_GPIO_FIOCLR_CLR3_bit)
#define LPC_GPIO2_FIOCLR_CLR4_bb bitband_t BITBAND(&LPC_GPIO2->FIOCLR, LPC_GPIO_FIOCLR_CLR4_bit)
#define LPC_GPIO2_FIOCLR_CLR5_bb bitband_t BITBAND(&LPC_GPIO2->FIOCLR, LPC_GPIO_FIOCLR_CLR5_bit)
#define LPC_GPIO2_FIOCLR_CLR6_bb bitband_t BITBAND(&LPC_GPIO2->FIOCLR, LPC_GPIO_FIOCLR_CLR6_bit)
#define LPC_GPIO2_FIOCLR_CLR7_bb bitband_t BITBAND(&LPC_GPIO2->FIOCLR, LPC_GPIO_FIOCLR_CLR7_bit)
#define LPC_GPIO2_FIOCLR_CLR8_bb bitband_t BITBAND(&LPC_GPIO2->FIOCLR, LPC_GPIO_FIOCLR_CLR8_bit)
#define LPC_GPIO2_FIOCLR_CLR9_bb bitband_t BITBAND(&LPC_GPIO2->FIOCLR, LPC_GPIO_FIOCLR_CLR9_bit)
#define LPC_GPIO2_FIOCLR_CLR10_bb bitband_t BITBAND(&LPC_GPIO2->FIOCLR, LPC_GPIO_FIOCLR_CLR10_bit)
#define LPC_GPIO2_FIOCLR_CLR11_bb bitband_t BITBAND(&LPC_GPIO2->FIOCLR, LPC_GPIO_FIOCLR_CLR11_bit)
#define LPC_GPIO2_FIOCLR_CLR12_bb bitband_t BITBAND(&LPC_GPIO2->FIOCLR, LPC_GPIO_FIOCLR_CLR12_bit)
#define LPC_GPIO2_FIOCLR_CLR13_bb bitband_t BITBAND(&LPC_GPIO2->FIOCLR, LPC_GPIO_FIOCLR_CLR13_bit)
#define LPC_GPIO3_FIOCLR_CLR25_bb bitband_t BITBAND(&LPC_GPIO3->FIOCLR, LPC_GPIO_FIOCLR_CLR25_bit)
#define LPC_GPIO3_FIOCLR_CLR26_bb bitband_t BITBAND(&LPC_GPIO3->FIOCLR, LPC_GPIO_FIOCLR_CLR26_bit)
#define LPC_GPIO4_FIOCLR_CLR28_bb bitband_t BITBAND(&LPC_GPIO4->FIOCLR, LPC_GPIO_FIOCLR_CLR28_bit)
#define LPC_GPIO4_FIOCLR_CLR29_bb bitband_t BITBAND(&LPC_GPIO4->FIOCLR, LPC_GPIO_FIOCLR_CLR29_bit)
/*
+-----------------------------------------------------------------------------+
| FIOPIN - GPIO port Pin value register
+-----------------------------------------------------------------------------+
*/
#define LPC_GPIO_FIOPIN_PIN0_bit 0
#define LPC_GPIO_FIOPIN_PIN1_bit 1
#define LPC_GPIO_FIOPIN_PIN2_bit 2
#define LPC_GPIO_FIOPIN_PIN3_bit 3
#define LPC_GPIO_FIOPIN_PIN4_bit 4
#define LPC_GPIO_FIOPIN_PIN5_bit 5
#define LPC_GPIO_FIOPIN_PIN6_bit 6
#define LPC_GPIO_FIOPIN_PIN7_bit 7
#define LPC_GPIO_FIOPIN_PIN8_bit 8
#define LPC_GPIO_FIOPIN_PIN9_bit 9
#define LPC_GPIO_FIOPIN_PIN10_bit 10
#define LPC_GPIO_FIOPIN_PIN11_bit 11
#define LPC_GPIO_FIOPIN_PIN12_bit 12
#define LPC_GPIO_FIOPIN_PIN13_bit 13
#define LPC_GPIO_FIOPIN_PIN14_bit 14
#define LPC_GPIO_FIOPIN_PIN15_bit 15
#define LPC_GPIO_FIOPIN_PIN16_bit 16
#define LPC_GPIO_FIOPIN_PIN17_bit 17
#define LPC_GPIO_FIOPIN_PIN18_bit 18
#define LPC_GPIO_FIOPIN_PIN19_bit 19
#define LPC_GPIO_FIOPIN_PIN20_bit 20
#define LPC_GPIO_FIOPIN_PIN21_bit 21
#define LPC_GPIO_FIOPIN_PIN22_bit 22
#define LPC_GPIO_FIOPIN_PIN23_bit 23
#define LPC_GPIO_FIOPIN_PIN24_bit 24
#define LPC_GPIO_FIOPIN_PIN25_bit 25
#define LPC_GPIO_FIOPIN_PIN26_bit 26
#define LPC_GPIO_FIOPIN_PIN27_bit 27
#define LPC_GPIO_FIOPIN_PIN28_bit 28
#define LPC_GPIO_FIOPIN_PIN29_bit 29
#define LPC_GPIO_FIOPIN_PIN30_bit 30
#define LPC_GPIO_FIOPIN_PIN31_bit 31
#define LPC_GPIO_FIOPIN_PIN0 (1 << LPC_GPIO_FIOPIN_PIN0_bit)
#define LPC_GPIO_FIOPIN_PIN1 (1 << LPC_GPIO_FIOPIN_PIN1_bit)
#define LPC_GPIO_FIOPIN_PIN2 (1 << LPC_GPIO_FIOPIN_PIN2_bit)
#define LPC_GPIO_FIOPIN_PIN3 (1 << LPC_GPIO_FIOPIN_PIN3_bit)
#define LPC_GPIO_FIOPIN_PIN4 (1 << LPC_GPIO_FIOPIN_PIN4_bit)
#define LPC_GPIO_FIOPIN_PIN5 (1 << LPC_GPIO_FIOPIN_PIN5_bit)
#define LPC_GPIO_FIOPIN_PIN6 (1 << LPC_GPIO_FIOPIN_PIN6_bit)
#define LPC_GPIO_FIOPIN_PIN7 (1 << LPC_GPIO_FIOPIN_PIN7_bit)
#define LPC_GPIO_FIOPIN_PIN8 (1 << LPC_GPIO_FIOPIN_PIN8_bit)
#define LPC_GPIO_FIOPIN_PIN9 (1 << LPC_GPIO_FIOPIN_PIN9_bit)
#define LPC_GPIO_FIOPIN_PIN10 (1 << LPC_GPIO_FIOPIN_PIN10_bit)
#define LPC_GPIO_FIOPIN_PIN11 (1 << LPC_GPIO_FIOPIN_PIN11_bit)
#define LPC_GPIO_FIOPIN_PIN12 (1 << LPC_GPIO_FIOPIN_PIN12_bit)
#define LPC_GPIO_FIOPIN_PIN13 (1 << LPC_GPIO_FIOPIN_PIN13_bit)
#define LPC_GPIO_FIOPIN_PIN14 (1 << LPC_GPIO_FIOPIN_PIN14_bit)
#define LPC_GPIO_FIOPIN_PIN15 (1 << LPC_GPIO_FIOPIN_PIN15_bit)
#define LPC_GPIO_FIOPIN_PIN16 (1 << LPC_GPIO_FIOPIN_PIN16_bit)
#define LPC_GPIO_FIOPIN_PIN17 (1 << LPC_GPIO_FIOPIN_PIN17_bit)
#define LPC_GPIO_FIOPIN_PIN18 (1 << LPC_GPIO_FIOPIN_PIN18_bit)
#define LPC_GPIO_FIOPIN_PIN19 (1 << LPC_GPIO_FIOPIN_PIN19_bit)
#define LPC_GPIO_FIOPIN_PIN20 (1 << LPC_GPIO_FIOPIN_PIN20_bit)
#define LPC_GPIO_FIOPIN_PIN21 (1 << LPC_GPIO_FIOPIN_PIN21_bit)
#define LPC_GPIO_FIOPIN_PIN22 (1 << LPC_GPIO_FIOPIN_PIN22_bit)
#define LPC_GPIO_FIOPIN_PIN23 (1 << LPC_GPIO_FIOPIN_PIN23_bit)
#define LPC_GPIO_FIOPIN_PIN24 (1 << LPC_GPIO_FIOPIN_PIN24_bit)
#define LPC_GPIO_FIOPIN_PIN25 (1 << LPC_GPIO_FIOPIN_PIN25_bit)
#define LPC_GPIO_FIOPIN_PIN26 (1 << LPC_GPIO_FIOPIN_PIN26_bit)
#define LPC_GPIO_FIOPIN_PIN27 (1 << LPC_GPIO_FIOPIN_PIN27_bit)
#define LPC_GPIO_FIOPIN_PIN28 (1 << LPC_GPIO_FIOPIN_PIN28_bit)
#define LPC_GPIO_FIOPIN_PIN29 (1 << LPC_GPIO_FIOPIN_PIN29_bit)
#define LPC_GPIO_FIOPIN_PIN30 (1 << LPC_GPIO_FIOPIN_PIN30_bit)
#define LPC_GPIO_FIOPIN_PIN31 (1 << LPC_GPIO_FIOPIN_PIN31_bit)
#define LPC_GPIO0_FIOPIN_PIN0_bb bitband_t BITBAND(&LPC_GPIO0->FIOPIN, LPC_GPIO_FIOPIN_PIN0_bit)
#define LPC_GPIO0_FIOPIN_PIN1_bb bitband_t BITBAND(&LPC_GPIO0->FIOPIN, LPC_GPIO_FIOPIN_PIN1_bit)
#define LPC_GPIO0_FIOPIN_PIN2_bb bitband_t BITBAND(&LPC_GPIO0->FIOPIN, LPC_GPIO_FIOPIN_PIN2_bit)
#define LPC_GPIO0_FIOPIN_PIN3_bb bitband_t BITBAND(&LPC_GPIO0->FIOPIN, LPC_GPIO_FIOPIN_PIN3_bit)
#define LPC_GPIO0_FIOPIN_PIN4_bb bitband_t BITBAND(&LPC_GPIO0->FIOPIN, LPC_GPIO_FIOPIN_PIN4_bit)
#define LPC_GPIO0_FIOPIN_PIN5_bb bitband_t BITBAND(&LPC_GPIO0->FIOPIN, LPC_GPIO_FIOPIN_PIN5_bit)
#define LPC_GPIO0_FIOPIN_PIN6_bb bitband_t BITBAND(&LPC_GPIO0->FIOPIN, LPC_GPIO_FIOPIN_PIN6_bit)
#define LPC_GPIO0_FIOPIN_PIN7_bb bitband_t BITBAND(&LPC_GPIO0->FIOPIN, LPC_GPIO_FIOPIN_PIN7_bit)
#define LPC_GPIO0_FIOPIN_PIN8_bb bitband_t BITBAND(&LPC_GPIO0->FIOPIN, LPC_GPIO_FIOPIN_PIN8_bit)
#define LPC_GPIO0_FIOPIN_PIN9_bb bitband_t BITBAND(&LPC_GPIO0->FIOPIN, LPC_GPIO_FIOPIN_PIN9_bit)
#define LPC_GPIO0_FIOPIN_PIN10_bb bitband_t BITBAND(&LPC_GPIO0->FIOPIN, LPC_GPIO_FIOPIN_PIN10_bit)
#define LPC_GPIO0_FIOPIN_PIN11_bb bitband_t BITBAND(&LPC_GPIO0->FIOPIN, LPC_GPIO_FIOPIN_PIN11_bit)
#define LPC_GPIO0_FIOPIN_PIN15_bb bitband_t BITBAND(&LPC_GPIO0->FIOPIN, LPC_GPIO_FIOPIN_PIN15_bit)
#define LPC_GPIO0_FIOPIN_PIN16_bb bitband_t BITBAND(&LPC_GPIO0->FIOPIN, LPC_GPIO_FIOPIN_PIN16_bit)
#define LPC_GPIO0_FIOPIN_PIN17_bb bitband_t BITBAND(&LPC_GPIO0->FIOPIN, LPC_GPIO_FIOPIN_PIN17_bit)
#define LPC_GPIO0_FIOPIN_PIN18_bb bitband_t BITBAND(&LPC_GPIO0->FIOPIN, LPC_GPIO_FIOPIN_PIN18_bit)
#define LPC_GPIO0_FIOPIN_PIN19_bb bitband_t BITBAND(&LPC_GPIO0->FIOPIN, LPC_GPIO_FIOPIN_PIN19_bit)
#define LPC_GPIO0_FIOPIN_PIN20_bb bitband_t BITBAND(&LPC_GPIO0->FIOPIN, LPC_GPIO_FIOPIN_PIN20_bit)
#define LPC_GPIO0_FIOPIN_PIN21_bb bitband_t BITBAND(&LPC_GPIO0->FIOPIN, LPC_GPIO_FIOPIN_PIN21_bit)
#define LPC_GPIO0_FIOPIN_PIN22_bb bitband_t BITBAND(&LPC_GPIO0->FIOPIN, LPC_GPIO_FIOPIN_PIN22_bit)
#define LPC_GPIO0_FIOPIN_PIN23_bb bitband_t BITBAND(&LPC_GPIO0->FIOPIN, LPC_GPIO_FIOPIN_PIN23_bit)
#define LPC_GPIO0_FIOPIN_PIN24_bb bitband_t BITBAND(&LPC_GPIO0->FIOPIN, LPC_GPIO_FIOPIN_PIN24_bit)
#define LPC_GPIO0_FIOPIN_PIN25_bb bitband_t BITBAND(&LPC_GPIO0->FIOPIN, LPC_GPIO_FIOPIN_PIN25_bit)
#define LPC_GPIO0_FIOPIN_PIN26_bb bitband_t BITBAND(&LPC_GPIO0->FIOPIN, LPC_GPIO_FIOPIN_PIN26_bit)
#define LPC_GPIO0_FIOPIN_PIN27_bb bitband_t BITBAND(&LPC_GPIO0->FIOPIN, LPC_GPIO_FIOPIN_PIN27_bit)
#define LPC_GPIO0_FIOPIN_PIN28_bb bitband_t BITBAND(&LPC_GPIO0->FIOPIN, LPC_GPIO_FIOPIN_PIN28_bit)
#define LPC_GPIO0_FIOPIN_PIN29_bb bitband_t BITBAND(&LPC_GPIO0->FIOPIN, LPC_GPIO_FIOPIN_PIN29_bit)
#define LPC_GPIO0_FIOPIN_PIN30_bb bitband_t BITBAND(&LPC_GPIO0->FIOPIN, LPC_GPIO_FIOPIN_PIN30_bit)
#define LPC_GPIO1_FIOPIN_PIN0_bb bitband_t BITBAND(&LPC_GPIO1->FIOPIN, LPC_GPIO_FIOPIN_PIN0_bit)
#define LPC_GPIO1_FIOPIN_PIN1_bb bitband_t BITBAND(&LPC_GPIO1->FIOPIN, LPC_GPIO_FIOPIN_PIN1_bit)
#define LPC_GPIO1_FIOPIN_PIN4_bb bitband_t BITBAND(&LPC_GPIO1->FIOPIN, LPC_GPIO_FIOPIN_PIN4_bit)
#define LPC_GPIO1_FIOPIN_PIN8_bb bitband_t BITBAND(&LPC_GPIO1->FIOPIN, LPC_GPIO_FIOPIN_PIN8_bit)
#define LPC_GPIO1_FIOPIN_PIN9_bb bitband_t BITBAND(&LPC_GPIO1->FIOPIN, LPC_GPIO_FIOPIN_PIN9_bit)
#define LPC_GPIO1_FIOPIN_PIN10_bb bitband_t BITBAND(&LPC_GPIO1->FIOPIN, LPC_GPIO_FIOPIN_PIN10_bit)
#define LPC_GPIO1_FIOPIN_PIN14_bb bitband_t BITBAND(&LPC_GPIO1->FIOPIN, LPC_GPIO_FIOPIN_PIN14_bit)
#define LPC_GPIO1_FIOPIN_PIN15_bb bitband_t BITBAND(&LPC_GPIO1->FIOPIN, LPC_GPIO_FIOPIN_PIN15_bit)
#define LPC_GPIO1_FIOPIN_PIN16_bb bitband_t BITBAND(&LPC_GPIO1->FIOPIN, LPC_GPIO_FIOPIN_PIN16_bit)
#define LPC_GPIO1_FIOPIN_PIN17_bb bitband_t BITBAND(&LPC_GPIO1->FIOPIN, LPC_GPIO_FIOPIN_PIN17_bit)
#define LPC_GPIO1_FIOPIN_PIN18_bb bitband_t BITBAND(&LPC_GPIO1->FIOPIN, LPC_GPIO_FIOPIN_PIN18_bit)
#define LPC_GPIO1_FIOPIN_PIN19_bb bitband_t BITBAND(&LPC_GPIO1->FIOPIN, LPC_GPIO_FIOPIN_PIN19_bit)
#define LPC_GPIO1_FIOPIN_PIN20_bb bitband_t BITBAND(&LPC_GPIO1->FIOPIN, LPC_GPIO_FIOPIN_PIN20_bit)
#define LPC_GPIO1_FIOPIN_PIN21_bb bitband_t BITBAND(&LPC_GPIO1->FIOPIN, LPC_GPIO_FIOPIN_PIN21_bit)
#define LPC_GPIO1_FIOPIN_PIN22_bb bitband_t BITBAND(&LPC_GPIO1->FIOPIN, LPC_GPIO_FIOPIN_PIN22_bit)
#define LPC_GPIO1_FIOPIN_PIN23_bb bitband_t BITBAND(&LPC_GPIO1->FIOPIN, LPC_GPIO_FIOPIN_PIN23_bit)
#define LPC_GPIO1_FIOPIN_PIN24_bb bitband_t BITBAND(&LPC_GPIO1->FIOPIN, LPC_GPIO_FIOPIN_PIN24_bit)
#define LPC_GPIO1_FIOPIN_PIN25_bb bitband_t BITBAND(&LPC_GPIO1->FIOPIN, LPC_GPIO_FIOPIN_PIN25_bit)
#define LPC_GPIO1_FIOPIN_PIN26_bb bitband_t BITBAND(&LPC_GPIO1->FIOPIN, LPC_GPIO_FIOPIN_PIN26_bit)
#define LPC_GPIO1_FIOPIN_PIN27_bb bitband_t BITBAND(&LPC_GPIO1->FIOPIN, LPC_GPIO_FIOPIN_PIN27_bit)
#define LPC_GPIO1_FIOPIN_PIN28_bb bitband_t BITBAND(&LPC_GPIO1->FIOPIN, LPC_GPIO_FIOPIN_PIN28_bit)
#define LPC_GPIO1_FIOPIN_PIN29_bb bitband_t BITBAND(&LPC_GPIO1->FIOPIN, LPC_GPIO_FIOPIN_PIN29_bit)
#define LPC_GPIO1_FIOPIN_PIN30_bb bitband_t BITBAND(&LPC_GPIO1->FIOPIN, LPC_GPIO_FIOPIN_PIN30_bit)
#define LPC_GPIO1_FIOPIN_PIN31_bb bitband_t BITBAND(&LPC_GPIO1->FIOPIN, LPC_GPIO_FIOPIN_PIN31_bit)
#define LPC_GPIO2_FIOPIN_PIN0_bb bitband_t BITBAND(&LPC_GPIO2->FIOPIN, LPC_GPIO_FIOPIN_PIN0_bit)
#define LPC_GPIO2_FIOPIN_PIN1_bb bitband_t BITBAND(&LPC_GPIO2->FIOPIN, LPC_GPIO_FIOPIN_PIN1_bit)
#define LPC_GPIO2_FIOPIN_PIN2_bb bitband_t BITBAND(&LPC_GPIO2->FIOPIN, LPC_GPIO_FIOPIN_PIN2_bit)
#define LPC_GPIO2_FIOPIN_PIN3_bb bitband_t BITBAND(&LPC_GPIO2->FIOPIN, LPC_GPIO_FIOPIN_PIN3_bit)
#define LPC_GPIO2_FIOPIN_PIN4_bb bitband_t BITBAND(&LPC_GPIO2->FIOPIN, LPC_GPIO_FIOPIN_PIN4_bit)
#define LPC_GPIO2_FIOPIN_PIN5_bb bitband_t BITBAND(&LPC_GPIO2->FIOPIN, LPC_GPIO_FIOPIN_PIN5_bit)
#define LPC_GPIO2_FIOPIN_PIN6_bb bitband_t BITBAND(&LPC_GPIO2->FIOPIN, LPC_GPIO_FIOPIN_PIN6_bit)
#define LPC_GPIO2_FIOPIN_PIN7_bb bitband_t BITBAND(&LPC_GPIO2->FIOPIN, LPC_GPIO_FIOPIN_PIN7_bit)
#define LPC_GPIO2_FIOPIN_PIN8_bb bitband_t BITBAND(&LPC_GPIO2->FIOPIN, LPC_GPIO_FIOPIN_PIN8_bit)
#define LPC_GPIO2_FIOPIN_PIN9_bb bitband_t BITBAND(&LPC_GPIO2->FIOPIN, LPC_GPIO_FIOPIN_PIN9_bit)
#define LPC_GPIO2_FIOPIN_PIN10_bb bitband_t BITBAND(&LPC_GPIO2->FIOPIN, LPC_GPIO_FIOPIN_PIN10_bit)
#define LPC_GPIO2_FIOPIN_PIN11_bb bitband_t BITBAND(&LPC_GPIO2->FIOPIN, LPC_GPIO_FIOPIN_PIN11_bit)
#define LPC_GPIO2_FIOPIN_PIN12_bb bitband_t BITBAND(&LPC_GPIO2->FIOPIN, LPC_GPIO_FIOPIN_PIN12_bit)
#define LPC_GPIO2_FIOPIN_PIN13_bb bitband_t BITBAND(&LPC_GPIO2->FIOPIN, LPC_GPIO_FIOPIN_PIN13_bit)
#define LPC_GPIO3_FIOPIN_PIN25_bb bitband_t BITBAND(&LPC_GPIO3->FIOPIN, LPC_GPIO_FIOPIN_PIN25_bit)
#define LPC_GPIO3_FIOPIN_PIN26_bb bitband_t BITBAND(&LPC_GPIO3->FIOPIN, LPC_GPIO_FIOPIN_PIN26_bit)
#define LPC_GPIO4_FIOPIN_PIN28_bb bitband_t BITBAND(&LPC_GPIO4->FIOPIN, LPC_GPIO_FIOPIN_PIN28_bit)
#define LPC_GPIO4_FIOPIN_PIN29_bb bitband_t BITBAND(&LPC_GPIO4->FIOPIN, LPC_GPIO_FIOPIN_PIN29_bit)
/*
+-----------------------------------------------------------------------------+
| FIOMASK - Fast GPIO port Mask register
+-----------------------------------------------------------------------------+
*/
#define LPC_GPIO_FIOMASK_MASK0_bit 0
#define LPC_GPIO_FIOMASK_MASK1_bit 1
#define LPC_GPIO_FIOMASK_MASK2_bit 2
#define LPC_GPIO_FIOMASK_MASK3_bit 3
#define LPC_GPIO_FIOMASK_MASK4_bit 4
#define LPC_GPIO_FIOMASK_MASK5_bit 5
#define LPC_GPIO_FIOMASK_MASK6_bit 6
#define LPC_GPIO_FIOMASK_MASK7_bit 7
#define LPC_GPIO_FIOMASK_MASK8_bit 8
#define LPC_GPIO_FIOMASK_MASK9_bit 9
#define LPC_GPIO_FIOMASK_MASK10_bit 10
#define LPC_GPIO_FIOMASK_MASK11_bit 11
#define LPC_GPIO_FIOMASK_MASK12_bit 12
#define LPC_GPIO_FIOMASK_MASK13_bit 13
#define LPC_GPIO_FIOMASK_MASK14_bit 14
#define LPC_GPIO_FIOMASK_MASK15_bit 15
#define LPC_GPIO_FIOMASK_MASK16_bit 16
#define LPC_GPIO_FIOMASK_MASK17_bit 17
#define LPC_GPIO_FIOMASK_MASK18_bit 18
#define LPC_GPIO_FIOMASK_MASK19_bit 19
#define LPC_GPIO_FIOMASK_MASK20_bit 20
#define LPC_GPIO_FIOMASK_MASK21_bit 21
#define LPC_GPIO_FIOMASK_MASK22_bit 22
#define LPC_GPIO_FIOMASK_MASK23_bit 23
#define LPC_GPIO_FIOMASK_MASK24_bit 24
#define LPC_GPIO_FIOMASK_MASK25_bit 25
#define LPC_GPIO_FIOMASK_MASK26_bit 26
#define LPC_GPIO_FIOMASK_MASK27_bit 27
#define LPC_GPIO_FIOMASK_MASK28_bit 28
#define LPC_GPIO_FIOMASK_MASK29_bit 29
#define LPC_GPIO_FIOMASK_MASK30_bit 30
#define LPC_GPIO_FIOMASK_MASK31_bit 31
#define LPC_GPIO_FIOMASK_MASK0 (1 << LPC_GPIO_FIOMASK_MASK0_bit)
#define LPC_GPIO_FIOMASK_MASK1 (1 << LPC_GPIO_FIOMASK_MASK1_bit)
#define LPC_GPIO_FIOMASK_MASK2 (1 << LPC_GPIO_FIOMASK_MASK2_bit)
#define LPC_GPIO_FIOMASK_MASK3 (1 << LPC_GPIO_FIOMASK_MASK3_bit)
#define LPC_GPIO_FIOMASK_MASK4 (1 << LPC_GPIO_FIOMASK_MASK4_bit)
#define LPC_GPIO_FIOMASK_MASK5 (1 << LPC_GPIO_FIOMASK_MASK5_bit)
#define LPC_GPIO_FIOMASK_MASK6 (1 << LPC_GPIO_FIOMASK_MASK6_bit)
#define LPC_GPIO_FIOMASK_MASK7 (1 << LPC_GPIO_FIOMASK_MASK7_bit)
#define LPC_GPIO_FIOMASK_MASK8 (1 << LPC_GPIO_FIOMASK_MASK8_bit)
#define LPC_GPIO_FIOMASK_MASK9 (1 << LPC_GPIO_FIOMASK_MASK9_bit)
#define LPC_GPIO_FIOMASK_MASK10 (1 << LPC_GPIO_FIOMASK_MASK10_bit)
#define LPC_GPIO_FIOMASK_MASK11 (1 << LPC_GPIO_FIOMASK_MASK11_bit)
#define LPC_GPIO_FIOMASK_MASK12 (1 << LPC_GPIO_FIOMASK_MASK12_bit)
#define LPC_GPIO_FIOMASK_MASK13 (1 << LPC_GPIO_FIOMASK_MASK13_bit)
#define LPC_GPIO_FIOMASK_MASK14 (1 << LPC_GPIO_FIOMASK_MASK14_bit)
#define LPC_GPIO_FIOMASK_MASK15 (1 << LPC_GPIO_FIOMASK_MASK15_bit)
#define LPC_GPIO_FIOMASK_MASK16 (1 << LPC_GPIO_FIOMASK_MASK16_bit)
#define LPC_GPIO_FIOMASK_MASK17 (1 << LPC_GPIO_FIOMASK_MASK17_bit)
#define LPC_GPIO_FIOMASK_MASK18 (1 << LPC_GPIO_FIOMASK_MASK18_bit)
#define LPC_GPIO_FIOMASK_MASK19 (1 << LPC_GPIO_FIOMASK_MASK19_bit)
#define LPC_GPIO_FIOMASK_MASK20 (1 << LPC_GPIO_FIOMASK_MASK20_bit)
#define LPC_GPIO_FIOMASK_MASK21 (1 << LPC_GPIO_FIOMASK_MASK21_bit)
#define LPC_GPIO_FIOMASK_MASK22 (1 << LPC_GPIO_FIOMASK_MASK22_bit)
#define LPC_GPIO_FIOMASK_MASK23 (1 << LPC_GPIO_FIOMASK_MASK23_bit)
#define LPC_GPIO_FIOMASK_MASK24 (1 << LPC_GPIO_FIOMASK_MASK24_bit)
#define LPC_GPIO_FIOMASK_MASK25 (1 << LPC_GPIO_FIOMASK_MASK25_bit)
#define LPC_GPIO_FIOMASK_MASK26 (1 << LPC_GPIO_FIOMASK_MASK26_bit)
#define LPC_GPIO_FIOMASK_MASK27 (1 << LPC_GPIO_FIOMASK_MASK27_bit)
#define LPC_GPIO_FIOMASK_MASK28 (1 << LPC_GPIO_FIOMASK_MASK28_bit)
#define LPC_GPIO_FIOMASK_MASK29 (1 << LPC_GPIO_FIOMASK_MASK29_bit)
#define LPC_GPIO_FIOMASK_MASK30 (1 << LPC_GPIO_FIOMASK_MASK30_bit)
#define LPC_GPIO_FIOMASK_MASK31 (1 << LPC_GPIO_FIOMASK_MASK31_bit)
#define LPC_GPIO0_FIOMASK_MASK0_bb bitband_t BITBAND(&LPC_GPIO0->FIOMASK, LPC_GPIO_FIOMASK_MASK0_bit)
#define LPC_GPIO0_FIOMASK_MASK1_bb bitband_t BITBAND(&LPC_GPIO0->FIOMASK, LPC_GPIO_FIOMASK_MASK1_bit)
#define LPC_GPIO0_FIOMASK_MASK2_bb bitband_t BITBAND(&LPC_GPIO0->FIOMASK, LPC_GPIO_FIOMASK_MASK2_bit)
#define LPC_GPIO0_FIOMASK_MASK3_bb bitband_t BITBAND(&LPC_GPIO0->FIOMASK, LPC_GPIO_FIOMASK_MASK3_bit)
#define LPC_GPIO0_FIOMASK_MASK4_bb bitband_t BITBAND(&LPC_GPIO0->FIOMASK, LPC_GPIO_FIOMASK_MASK4_bit)
#define LPC_GPIO0_FIOMASK_MASK5_bb bitband_t BITBAND(&LPC_GPIO0->FIOMASK, LPC_GPIO_FIOMASK_MASK5_bit)
#define LPC_GPIO0_FIOMASK_MASK6_bb bitband_t BITBAND(&LPC_GPIO0->FIOMASK, LPC_GPIO_FIOMASK_MASK6_bit)
#define LPC_GPIO0_FIOMASK_MASK7_bb bitband_t BITBAND(&LPC_GPIO0->FIOMASK, LPC_GPIO_FIOMASK_MASK7_bit)
#define LPC_GPIO0_FIOMASK_MASK8_bb bitband_t BITBAND(&LPC_GPIO0->FIOMASK, LPC_GPIO_FIOMASK_MASK8_bit)
#define LPC_GPIO0_FIOMASK_MASK9_bb bitband_t BITBAND(&LPC_GPIO0->FIOMASK, LPC_GPIO_FIOMASK_MASK9_bit)
#define LPC_GPIO0_FIOMASK_MASK10_bb bitband_t BITBAND(&LPC_GPIO0->FIOMASK, LPC_GPIO_FIOMASK_MASK10_bit)
#define LPC_GPIO0_FIOMASK_MASK11_bb bitband_t BITBAND(&LPC_GPIO0->FIOMASK, LPC_GPIO_FIOMASK_MASK11_bit)
#define LPC_GPIO0_FIOMASK_MASK15_bb bitband_t BITBAND(&LPC_GPIO0->FIOMASK, LPC_GPIO_FIOMASK_MASK15_bit)
#define LPC_GPIO0_FIOMASK_MASK16_bb bitband_t BITBAND(&LPC_GPIO0->FIOMASK, LPC_GPIO_FIOMASK_MASK16_bit)
#define LPC_GPIO0_FIOMASK_MASK17_bb bitband_t BITBAND(&LPC_GPIO0->FIOMASK, LPC_GPIO_FIOMASK_MASK17_bit)
#define LPC_GPIO0_FIOMASK_MASK18_bb bitband_t BITBAND(&LPC_GPIO0->FIOMASK, LPC_GPIO_FIOMASK_MASK18_bit)
#define LPC_GPIO0_FIOMASK_MASK19_bb bitband_t BITBAND(&LPC_GPIO0->FIOMASK, LPC_GPIO_FIOMASK_MASK19_bit)
#define LPC_GPIO0_FIOMASK_MASK20_bb bitband_t BITBAND(&LPC_GPIO0->FIOMASK, LPC_GPIO_FIOMASK_MASK20_bit)
#define LPC_GPIO0_FIOMASK_MASK21_bb bitband_t BITBAND(&LPC_GPIO0->FIOMASK, LPC_GPIO_FIOMASK_MASK21_bit)
#define LPC_GPIO0_FIOMASK_MASK22_bb bitband_t BITBAND(&LPC_GPIO0->FIOMASK, LPC_GPIO_FIOMASK_MASK22_bit)
#define LPC_GPIO0_FIOMASK_MASK23_bb bitband_t BITBAND(&LPC_GPIO0->FIOMASK, LPC_GPIO_FIOMASK_MASK23_bit)
#define LPC_GPIO0_FIOMASK_MASK24_bb bitband_t BITBAND(&LPC_GPIO0->FIOMASK, LPC_GPIO_FIOMASK_MASK24_bit)
#define LPC_GPIO0_FIOMASK_MASK25_bb bitband_t BITBAND(&LPC_GPIO0->FIOMASK, LPC_GPIO_FIOMASK_MASK25_bit)
#define LPC_GPIO0_FIOMASK_MASK26_bb bitband_t BITBAND(&LPC_GPIO0->FIOMASK, LPC_GPIO_FIOMASK_MASK26_bit)
#define LPC_GPIO0_FIOMASK_MASK27_bb bitband_t BITBAND(&LPC_GPIO0->FIOMASK, LPC_GPIO_FIOMASK_MASK27_bit)
#define LPC_GPIO0_FIOMASK_MASK28_bb bitband_t BITBAND(&LPC_GPIO0->FIOMASK, LPC_GPIO_FIOMASK_MASK28_bit)
#define LPC_GPIO0_FIOMASK_MASK29_bb bitband_t BITBAND(&LPC_GPIO0->FIOMASK, LPC_GPIO_FIOMASK_MASK29_bit)
#define LPC_GPIO0_FIOMASK_MASK30_bb bitband_t BITBAND(&LPC_GPIO0->FIOMASK, LPC_GPIO_FIOMASK_MASK30_bit)
#define LPC_GPIO1_FIOMASK_MASK0_bb bitband_t BITBAND(&LPC_GPIO1->FIOMASK, LPC_GPIO_FIOMASK_MASK0_bit)
#define LPC_GPIO1_FIOMASK_MASK1_bb bitband_t BITBAND(&LPC_GPIO1->FIOMASK, LPC_GPIO_FIOMASK_MASK1_bit)
#define LPC_GPIO1_FIOMASK_MASK4_bb bitband_t BITBAND(&LPC_GPIO1->FIOMASK, LPC_GPIO_FIOMASK_MASK4_bit)
#define LPC_GPIO1_FIOMASK_MASK8_bb bitband_t BITBAND(&LPC_GPIO1->FIOMASK, LPC_GPIO_FIOMASK_MASK8_bit)
#define LPC_GPIO1_FIOMASK_MASK9_bb bitband_t BITBAND(&LPC_GPIO1->FIOMASK, LPC_GPIO_FIOMASK_MASK9_bit)
#define LPC_GPIO1_FIOMASK_MASK10_bb bitband_t BITBAND(&LPC_GPIO1->FIOMASK, LPC_GPIO_FIOMASK_MASK10_bit)
#define LPC_GPIO1_FIOMASK_MASK14_bb bitband_t BITBAND(&LPC_GPIO1->FIOMASK, LPC_GPIO_FIOMASK_MASK14_bit)
#define LPC_GPIO1_FIOMASK_MASK15_bb bitband_t BITBAND(&LPC_GPIO1->FIOMASK, LPC_GPIO_FIOMASK_MASK15_bit)
#define LPC_GPIO1_FIOMASK_MASK16_bb bitband_t BITBAND(&LPC_GPIO1->FIOMASK, LPC_GPIO_FIOMASK_MASK16_bit)
#define LPC_GPIO1_FIOMASK_MASK17_bb bitband_t BITBAND(&LPC_GPIO1->FIOMASK, LPC_GPIO_FIOMASK_MASK17_bit)
#define LPC_GPIO1_FIOMASK_MASK18_bb bitband_t BITBAND(&LPC_GPIO1->FIOMASK, LPC_GPIO_FIOMASK_MASK18_bit)
#define LPC_GPIO1_FIOMASK_MASK19_bb bitband_t BITBAND(&LPC_GPIO1->FIOMASK, LPC_GPIO_FIOMASK_MASK19_bit)
#define LPC_GPIO1_FIOMASK_MASK20_bb bitband_t BITBAND(&LPC_GPIO1->FIOMASK, LPC_GPIO_FIOMASK_MASK20_bit)
#define LPC_GPIO1_FIOMASK_MASK21_bb bitband_t BITBAND(&LPC_GPIO1->FIOMASK, LPC_GPIO_FIOMASK_MASK21_bit)
#define LPC_GPIO1_FIOMASK_MASK22_bb bitband_t BITBAND(&LPC_GPIO1->FIOMASK, LPC_GPIO_FIOMASK_MASK22_bit)
#define LPC_GPIO1_FIOMASK_MASK23_bb bitband_t BITBAND(&LPC_GPIO1->FIOMASK, LPC_GPIO_FIOMASK_MASK23_bit)
#define LPC_GPIO1_FIOMASK_MASK24_bb bitband_t BITBAND(&LPC_GPIO1->FIOMASK, LPC_GPIO_FIOMASK_MASK24_bit)
#define LPC_GPIO1_FIOMASK_MASK25_bb bitband_t BITBAND(&LPC_GPIO1->FIOMASK, LPC_GPIO_FIOMASK_MASK25_bit)
#define LPC_GPIO1_FIOMASK_MASK26_bb bitband_t BITBAND(&LPC_GPIO1->FIOMASK, LPC_GPIO_FIOMASK_MASK26_bit)
#define LPC_GPIO1_FIOMASK_MASK27_bb bitband_t BITBAND(&LPC_GPIO1->FIOMASK, LPC_GPIO_FIOMASK_MASK27_bit)
#define LPC_GPIO1_FIOMASK_MASK28_bb bitband_t BITBAND(&LPC_GPIO1->FIOMASK, LPC_GPIO_FIOMASK_MASK28_bit)
#define LPC_GPIO1_FIOMASK_MASK29_bb bitband_t BITBAND(&LPC_GPIO1->FIOMASK, LPC_GPIO_FIOMASK_MASK29_bit)
#define LPC_GPIO1_FIOMASK_MASK30_bb bitband_t BITBAND(&LPC_GPIO1->FIOMASK, LPC_GPIO_FIOMASK_MASK30_bit)
#define LPC_GPIO1_FIOMASK_MASK31_bb bitband_t BITBAND(&LPC_GPIO1->FIOMASK, LPC_GPIO_FIOMASK_MASK31_bit)
#define LPC_GPIO2_FIOMASK_MASK0_bb bitband_t BITBAND(&LPC_GPIO2->FIOMASK, LPC_GPIO_FIOMASK_MASK0_bit)
#define LPC_GPIO2_FIOMASK_MASK1_bb bitband_t BITBAND(&LPC_GPIO2->FIOMASK, LPC_GPIO_FIOMASK_MASK1_bit)
#define LPC_GPIO2_FIOMASK_MASK2_bb bitband_t BITBAND(&LPC_GPIO2->FIOMASK, LPC_GPIO_FIOMASK_MASK2_bit)
#define LPC_GPIO2_FIOMASK_MASK3_bb bitband_t BITBAND(&LPC_GPIO2->FIOMASK, LPC_GPIO_FIOMASK_MASK3_bit)
#define LPC_GPIO2_FIOMASK_MASK4_bb bitband_t BITBAND(&LPC_GPIO2->FIOMASK, LPC_GPIO_FIOMASK_MASK4_bit)
#define LPC_GPIO2_FIOMASK_MASK5_bb bitband_t BITBAND(&LPC_GPIO2->FIOMASK, LPC_GPIO_FIOMASK_MASK5_bit)
#define LPC_GPIO2_FIOMASK_MASK6_bb bitband_t BITBAND(&LPC_GPIO2->FIOMASK, LPC_GPIO_FIOMASK_MASK6_bit)
#define LPC_GPIO2_FIOMASK_MASK7_bb bitband_t BITBAND(&LPC_GPIO2->FIOMASK, LPC_GPIO_FIOMASK_MASK7_bit)
#define LPC_GPIO2_FIOMASK_MASK8_bb bitband_t BITBAND(&LPC_GPIO2->FIOMASK, LPC_GPIO_FIOMASK_MASK8_bit)
#define LPC_GPIO2_FIOMASK_MASK9_bb bitband_t BITBAND(&LPC_GPIO2->FIOMASK, LPC_GPIO_FIOMASK_MASK9_bit)
#define LPC_GPIO2_FIOMASK_MASK10_bb bitband_t BITBAND(&LPC_GPIO2->FIOMASK, LPC_GPIO_FIOMASK_MASK10_bit)
#define LPC_GPIO2_FIOMASK_MASK11_bb bitband_t BITBAND(&LPC_GPIO2->FIOMASK, LPC_GPIO_FIOMASK_MASK11_bit)
#define LPC_GPIO2_FIOMASK_MASK12_bb bitband_t BITBAND(&LPC_GPIO2->FIOMASK, LPC_GPIO_FIOMASK_MASK12_bit)
#define LPC_GPIO2_FIOMASK_MASK13_bb bitband_t BITBAND(&LPC_GPIO2->FIOMASK, LPC_GPIO_FIOMASK_MASK13_bit)
#define LPC_GPIO3_FIOMASK_MASK25_bb bitband_t BITBAND(&LPC_GPIO3->FIOMASK, LPC_GPIO_FIOMASK_MASK25_bit)
#define LPC_GPIO3_FIOMASK_MASK26_bb bitband_t BITBAND(&LPC_GPIO3->FIOMASK, LPC_GPIO_FIOMASK_MASK26_bit)
#define LPC_GPIO4_FIOMASK_MASK28_bb bitband_t BITBAND(&LPC_GPIO4->FIOMASK, LPC_GPIO_FIOMASK_MASK28_bit)
#define LPC_GPIO4_FIOMASK_MASK29_bb bitband_t BITBAND(&LPC_GPIO4->FIOMASK, LPC_GPIO_FIOMASK_MASK29_bit)
/******************************************************************************
* END OF FILE
******************************************************************************/
#endif /* HDR_GPIO_H_ */
hdr/hdr_pincon.h 0 → 100644
View file @ 45999dcd
This source diff could not be displayed because it is too large. You can view the blob instead.
hdr/hdr_sc.h 0 → 100644
View file @ 45999dcd
This source diff could not be displayed because it is too large. You can view the blob instead.
hdr/hdr_special_registers.h 0 → 100644
View file @ 45999dcd
/** \file hdr_special_registers.h
* \brief Header with definition of bits in special registers in ARMv7-M(E) core
* \author Freddie Chopin, http://www.freddiechopin.info/
* \date 2012-03-18
*/
/******************************************************************************
* chip: ARMv7-M(E) (Cortex-M3 / Cortex-M4)
* compiler: arm-none-eabi-gcc (GNU Tools for ARM Embedded Processors) 4.6.2
* 20110921 (release) [ARM/embedded-4_6-branch revision 182083]
******************************************************************************/
#ifndef HDR_SPECIAL_REGISTERS_H_
#define HDR_SPECIAL_REGISTERS_H_
/*
+-----------------------------------------------------------------------------+
| PRIMASK - Register to mask out configurable exceptions
+-----------------------------------------------------------------------------+
*/
#define PRIMASK_MASK_EXCEPTIONS_bit 0
#define PRIMASK_MASK_EXCEPTIONS (1 << PRIMASK_MASK_EXCEPTIONS_bit)
/*
+-----------------------------------------------------------------------------+
| FAULTMASK - Register to raise priority to the HardFault level
+-----------------------------------------------------------------------------+
*/
#define FAULTMASK_MASK_EXCEPTIONS_bit 0
#define FAULTMASK_MASK_EXCEPTIONS (1 << FAULTMASK_MASK_EXCEPTIONS_bit)
/*
+-----------------------------------------------------------------------------+
| CONTROL - The special-purpose control register
+-----------------------------------------------------------------------------+
*/
#define CONTROL_THREAD_UNPRIVILEGED_bit 0
#define CONTROL_ALTERNATE_STACK_bit 1
#define CONTROL_THREAD_UNPRIVILEGED (1 << CONTROL_THREAD_UNPRIVILEGED_bit)
#define CONTROL_ALTERNATE_STACK (1 << CONTROL_ALTERNATE_STACK_bit)
/******************************************************************************
* END OF FILE
******************************************************************************/
#endif /* HDR_SPECIAL_REGISTERS_H_ */
inc/LPC17xx.h 0 → 100644
View file @ 45999dcd
/**************************************************************************//**
* @file LPC17xx.h
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
* NXP LPC17xx Device Series
* @version: V1.09
* @date: 17. March 2010
*
* @note
* Copyright (C) 2009 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __LPC17xx_H__
#define __LPC17xx_H__
/*
* ==========================================================================
* ---------- Interrupt Number Definition -----------------------------------
* ==========================================================================
*/
typedef enum IRQn
{
/****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
/****** LPC17xx Specific Interrupt Numbers *******************************************************/
WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
UART0_IRQn = 5, /*!< UART0 Interrupt */
UART1_IRQn = 6, /*!< UART1 Interrupt */
UART2_IRQn = 7, /*!< UART2 Interrupt */
UART3_IRQn = 8, /*!< UART3 Interrupt */
PWM1_IRQn = 9, /*!< PWM1 Interrupt */
I2C0_IRQn = 10, /*!< I2C0 Interrupt */
I2C1_IRQn = 11, /*!< I2C1 Interrupt */
I2C2_IRQn = 12, /*!< I2C2 Interrupt */
SPI_IRQn = 13, /*!< SPI Interrupt */
SSP0_IRQn = 14, /*!< SSP0 Interrupt */
SSP1_IRQn = 15, /*!< SSP1 Interrupt */
PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
ADC_IRQn = 22, /*!< A/D Converter Interrupt */
BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
USB_IRQn = 24, /*!< USB Interrupt */
CAN_IRQn = 25, /*!< CAN Interrupt */
DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
I2S_IRQn = 27, /*!< I2S Interrupt */
ENET_IRQn = 28, /*!< Ethernet Interrupt */
RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */
MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
USBActivity_IRQn = 33, /* USB Activity interrupt */
CANActivity_IRQn = 34, /* CAN Activity interrupt */
} IRQn_Type;
/*
* ==========================================================================
* ----------- Processor and Core Peripheral Section ------------------------
* ==========================================================================
*/
/* Configuration of the Cortex-M3 Processor and Core Peripherals */
#define __MPU_PRESENT 1 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
#include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
#include "system_LPC17xx.h" /* System Header */
/******************************************************************************/
/* Device Specific Peripheral registers structures */
/******************************************************************************/
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/*------------- System Control (SC) ------------------------------------------*/
typedef struct
{
__IO uint32_t FLASHCFG; /* Flash Accelerator Module */
uint32_t RESERVED0[31];
__IO uint32_t PLL0CON; /* Clocking and Power Control */
__IO uint32_t PLL0CFG;
__I uint32_t PLL0STAT;
__O uint32_t PLL0FEED;
uint32_t RESERVED1[4];
__IO uint32_t PLL1CON;
__IO uint32_t PLL1CFG;
__I uint32_t PLL1STAT;
__O uint32_t PLL1FEED;
uint32_t RESERVED2[4];
__IO uint32_t PCON;
__IO uint32_t PCONP;
uint32_t RESERVED3[15];
__IO uint32_t CCLKCFG;
__IO uint32_t USBCLKCFG;
__IO uint32_t CLKSRCSEL;
__IO uint32_t CANSLEEPCLR;
__IO uint32_t CANWAKEFLAGS;
uint32_t RESERVED4[10];
__IO uint32_t EXTINT; /* External Interrupts */
uint32_t RESERVED5;
__IO uint32_t EXTMODE;
__IO uint32_t EXTPOLAR;
uint32_t RESERVED6[12];
__IO uint32_t RSID; /* Reset */
uint32_t RESERVED7[7];
__IO uint32_t SCS; /* Syscon Miscellaneous Registers */
__IO uint32_t IRCTRIM; /* Clock Dividers */
__IO uint32_t PCLKSEL0;
__IO uint32_t PCLKSEL1;
uint32_t RESERVED8[4];
__IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
__IO uint32_t DMAREQSEL;
__IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
} LPC_SC_TypeDef;
/*------------- Pin Connect Block (PINCON) -----------------------------------*/
typedef struct
{
__IO uint32_t PINSEL0;
__IO uint32_t PINSEL1;
__IO uint32_t PINSEL2;
__IO uint32_t PINSEL3;
__IO uint32_t PINSEL4;
__IO uint32_t PINSEL5;
__IO uint32_t PINSEL6;
__IO uint32_t PINSEL7;
__IO uint32_t PINSEL8;
__IO uint32_t PINSEL9;
__IO uint32_t PINSEL10;
uint32_t RESERVED0[5];
__IO uint32_t PINMODE0;
__IO uint32_t PINMODE1;
__IO uint32_t PINMODE2;
__IO uint32_t PINMODE3;
__IO uint32_t PINMODE4;
__IO uint32_t PINMODE5;
__IO uint32_t PINMODE6;
__IO uint32_t PINMODE7;
__IO uint32_t PINMODE8;
__IO uint32_t PINMODE9;
__IO uint32_t PINMODE_OD0;
__IO uint32_t PINMODE_OD1;
__IO uint32_t PINMODE_OD2;
__IO uint32_t PINMODE_OD3;
__IO uint32_t PINMODE_OD4;
__IO uint32_t I2CPADCFG;
} LPC_PINCON_TypeDef;
/*------------- General Purpose Input/Output (GPIO) --------------------------*/
typedef struct
{
union {
__IO uint32_t FIODIR;
struct {
__IO uint16_t FIODIRL;
__IO uint16_t FIODIRH;
};
struct {
__IO uint8_t FIODIR0;
__IO uint8_t FIODIR1;
__IO uint8_t FIODIR2;
__IO uint8_t FIODIR3;
};
};
uint32_t RESERVED0[3];
union {
__IO uint32_t FIOMASK;
struct {
__IO uint16_t FIOMASKL;
__IO uint16_t FIOMASKH;
};
struct {
__IO uint8_t FIOMASK0;
__IO uint8_t FIOMASK1;
__IO uint8_t FIOMASK2;
__IO uint8_t FIOMASK3;
};
};
union {
__IO uint32_t FIOPIN;
struct {
__IO uint16_t FIOPINL;
__IO uint16_t FIOPINH;
};
struct {
__IO uint8_t FIOPIN0;
__IO uint8_t FIOPIN1;
__IO uint8_t FIOPIN2;
__IO uint8_t FIOPIN3;
};
};
union {
__IO uint32_t FIOSET;
struct {
__IO uint16_t FIOSETL;
__IO uint16_t FIOSETH;
};
struct {
__IO uint8_t FIOSET0;
__IO uint8_t FIOSET1;
__IO uint8_t FIOSET2;
__IO uint8_t FIOSET3;
};
};
union {
__O uint32_t FIOCLR;
struct {
__O uint16_t FIOCLRL;
__O uint16_t FIOCLRH;
};
struct {
__O uint8_t FIOCLR0;
__O uint8_t FIOCLR1;
__O uint8_t FIOCLR2;
__O uint8_t FIOCLR3;
};
};
} LPC_GPIO_TypeDef;
typedef struct
{
__I uint32_t IntStatus;
__I uint32_t IO0IntStatR;
__I uint32_t IO0IntStatF;
__O uint32_t IO0IntClr;
__IO uint32_t IO0IntEnR;
__IO uint32_t IO0IntEnF;
uint32_t RESERVED0[3];
__I uint32_t IO2IntStatR;
__I uint32_t IO2IntStatF;
__O uint32_t IO2IntClr;
__IO uint32_t IO2IntEnR;
__IO uint32_t IO2IntEnF;
} LPC_GPIOINT_TypeDef;
/*------------- Timer (TIM) --------------------------------------------------*/
typedef struct
{
__IO uint32_t IR;
__IO uint32_t TCR;
__IO uint32_t TC;
__IO uint32_t PR;
__IO uint32_t PC;
__IO uint32_t MCR;
__IO uint32_t MR0;
__IO uint32_t MR1;
__IO uint32_t MR2;
__IO uint32_t MR3;
__IO uint32_t CCR;
__I uint32_t CR0;
__I uint32_t CR1;
uint32_t RESERVED0[2];
__IO uint32_t EMR;
uint32_t RESERVED1[12];
__IO uint32_t CTCR;
} LPC_TIM_TypeDef;
/*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
typedef struct
{
__IO uint32_t IR;
__IO uint32_t TCR;
__IO uint32_t TC;
__IO uint32_t PR;
__IO uint32_t PC;
__IO uint32_t MCR;
__IO uint32_t MR0;
__IO uint32_t MR1;
__IO uint32_t MR2;
__IO uint32_t MR3;
__IO uint32_t CCR;
__I uint32_t CR0;
__I uint32_t CR1;
__I uint32_t CR2;
__I uint32_t CR3;
uint32_t RESERVED0;
__IO uint32_t MR4;
__IO uint32_t MR5;
__IO uint32_t MR6;
__IO uint32_t PCR;
__IO uint32_t LER;
uint32_t RESERVED1[7];
__IO uint32_t CTCR;
} LPC_PWM_TypeDef;
/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
typedef struct
{
union {
__I uint8_t RBR;
__O uint8_t THR;
__IO uint8_t DLL;
uint32_t RESERVED0;
};
union {
__IO uint8_t DLM;
__IO uint32_t IER;
};
union {
__I uint32_t IIR;
__O uint8_t FCR;
};
__IO uint8_t LCR;
uint8_t RESERVED1[7];
__I uint8_t LSR;
uint8_t RESERVED2[7];
__IO uint8_t SCR;
uint8_t RESERVED3[3];
__IO uint32_t ACR;
__IO uint8_t ICR;
uint8_t RESERVED4[3];
__IO uint8_t FDR;
uint8_t RESERVED5[7];
__IO uint8_t TER;
uint8_t RESERVED6[39];
__IO uint32_t FIFOLVL;
} LPC_UART_TypeDef;
typedef struct
{
union {
__I uint8_t RBR;
__O uint8_t THR;
__IO uint8_t DLL;
uint32_t RESERVED0;
};
union {
__IO uint8_t DLM;
__IO uint32_t IER;
};
union {
__I uint32_t IIR;
__O uint8_t FCR;
};
__IO uint8_t LCR;
uint8_t RESERVED1[7];
__I uint8_t LSR;
uint8_t RESERVED2[7];
__IO uint8_t SCR;
uint8_t RESERVED3[3];
__IO uint32_t ACR;
__IO uint8_t ICR;
uint8_t RESERVED4[3];
__IO uint8_t FDR;
uint8_t RESERVED5[7];
__IO uint8_t TER;
uint8_t RESERVED6[39];
__IO uint32_t FIFOLVL;
} LPC_UART0_TypeDef;
typedef struct
{
union {
__I uint8_t RBR;
__O uint8_t THR;
__IO uint8_t DLL;
uint32_t RESERVED0;
};
union {
__IO uint8_t DLM;
__IO uint32_t IER;
};
union {
__I uint32_t IIR;
__O uint8_t FCR;
};
__IO uint8_t LCR;
uint8_t RESERVED1[3];
__IO uint8_t MCR;
uint8_t RESERVED2[3];
__I uint8_t LSR;
uint8_t RESERVED3[3];
__I uint8_t MSR;
uint8_t RESERVED4[3];
__IO uint8_t SCR;
uint8_t RESERVED5[3];
__IO uint32_t ACR;
uint32_t RESERVED6;
__IO uint32_t FDR;
uint32_t RESERVED7;
__IO uint8_t TER;
uint8_t RESERVED8[27];
__IO uint8_t RS485CTRL;
uint8_t RESERVED9[3];
__IO uint8_t ADRMATCH;
uint8_t RESERVED10[3];
__IO uint8_t RS485DLY;
uint8_t RESERVED11[3];
__IO uint32_t FIFOLVL;
} LPC_UART1_TypeDef;
/*------------- Serial Peripheral Interface (SPI) ----------------------------*/
typedef struct
{
__IO uint32_t SPCR;
__I uint32_t SPSR;
__IO uint32_t SPDR;
__IO uint32_t SPCCR;
uint32_t RESERVED0[3];
__IO uint32_t SPINT;
} LPC_SPI_TypeDef;
/*------------- Synchronous Serial Communication (SSP) -----------------------*/
typedef struct
{
__IO uint32_t CR0;
__IO uint32_t CR1;
__IO uint32_t DR;
__I uint32_t SR;
__IO uint32_t CPSR;
__IO uint32_t IMSC;
__IO uint32_t RIS;
__IO uint32_t MIS;
__IO uint32_t ICR;
__IO uint32_t DMACR;
} LPC_SSP_TypeDef;
/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
typedef struct
{
__IO uint32_t I2CONSET;
__I uint32_t I2STAT;
__IO uint32_t I2DAT;
__IO uint32_t I2ADR0;
__IO uint32_t I2SCLH;
__IO uint32_t I2SCLL;
__O uint32_t I2CONCLR;
__IO uint32_t MMCTRL;
__IO uint32_t I2ADR1;
__IO uint32_t I2ADR2;
__IO uint32_t I2ADR3;
__I uint32_t I2DATA_BUFFER;
__IO uint32_t I2MASK0;
__IO uint32_t I2MASK1;
__IO uint32_t I2MASK2;
__IO uint32_t I2MASK3;
} LPC_I2C_TypeDef;
/*------------- Inter IC Sound (I2S) -----------------------------------------*/
typedef struct
{
__IO uint32_t I2SDAO;
__IO uint32_t I2SDAI;
__O uint32_t I2STXFIFO;
__I uint32_t I2SRXFIFO;
__I uint32_t I2SSTATE;
__IO uint32_t I2SDMA1;
__IO uint32_t I2SDMA2;
__IO uint32_t I2SIRQ;
__IO uint32_t I2STXRATE;
__IO uint32_t I2SRXRATE;
__IO uint32_t I2STXBITRATE;
__IO uint32_t I2SRXBITRATE;
__IO uint32_t I2STXMODE;
__IO uint32_t I2SRXMODE;
} LPC_I2S_TypeDef;
/*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
typedef struct
{
__IO uint32_t RICOMPVAL;
__IO uint32_t RIMASK;
__IO uint8_t RICTRL;
uint8_t RESERVED0[3];
__IO uint32_t RICOUNTER;
} LPC_RIT_TypeDef;
/*------------- Real-Time Clock (RTC) ----------------------------------------*/
typedef struct
{
__IO uint8_t ILR;
uint8_t RESERVED0[7];
__IO uint8_t CCR;
uint8_t RESERVED1[3];
__IO uint8_t CIIR;
uint8_t RESERVED2[3];
__IO uint8_t AMR;
uint8_t RESERVED3[3];
__I uint32_t CTIME0;
__I uint32_t CTIME1;
__I uint32_t CTIME2;
__IO uint8_t SEC;
uint8_t RESERVED4[3];
__IO uint8_t MIN;
uint8_t RESERVED5[3];
__IO uint8_t HOUR;
uint8_t RESERVED6[3];
__IO uint8_t DOM;
uint8_t RESERVED7[3];
__IO uint8_t DOW;
uint8_t RESERVED8[3];
__IO uint16_t DOY;
uint16_t RESERVED9;
__IO uint8_t MONTH;
uint8_t RESERVED10[3];
__IO uint16_t YEAR;
uint16_t RESERVED11;
__IO uint32_t CALIBRATION;
__IO uint32_t GPREG0;
__IO uint32_t GPREG1;
__IO uint32_t GPREG2;
__IO uint32_t GPREG3;
__IO uint32_t GPREG4;
__IO uint8_t RTC_AUXEN;
uint8_t RESERVED12[3];
__IO uint8_t RTC_AUX;
uint8_t RESERVED13[3];
__IO uint8_t ALSEC;
uint8_t RESERVED14[3];
__IO uint8_t ALMIN;
uint8_t RESERVED15[3];
__IO uint8_t ALHOUR;
uint8_t RESERVED16[3];
__IO uint8_t ALDOM;
uint8_t RESERVED17[3];
__IO uint8_t ALDOW;
uint8_t RESERVED18[3];
__IO uint16_t ALDOY;
uint16_t RESERVED19;
__IO uint8_t ALMON;
uint8_t RESERVED20[3];
__IO uint16_t ALYEAR;
uint16_t RESERVED21;
} LPC_RTC_TypeDef;
/*------------- Watchdog Timer (WDT) -----------------------------------------*/
typedef struct
{
__IO uint8_t WDMOD;
uint8_t RESERVED0[3];
__IO uint32_t WDTC;
__O uint8_t WDFEED;
uint8_t RESERVED1[3];
__I uint32_t WDTV;
__IO uint32_t WDCLKSEL;
} LPC_WDT_TypeDef;
/*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
typedef struct
{
__IO uint32_t ADCR;
__IO uint32_t ADGDR;
uint32_t RESERVED0;
__IO uint32_t ADINTEN;
__I uint32_t ADDR0;
__I uint32_t ADDR1;
__I uint32_t ADDR2;
__I uint32_t ADDR3;
__I uint32_t ADDR4;
__I uint32_t ADDR5;
__I uint32_t ADDR6;
__I uint32_t ADDR7;
__I uint32_t ADSTAT;
__IO uint32_t ADTRM;
} LPC_ADC_TypeDef;
/*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
typedef struct
{
__IO uint32_t DACR;
__IO uint32_t DACCTRL;
__IO uint16_t DACCNTVAL;
} LPC_DAC_TypeDef;
/*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
typedef struct
{
__I uint32_t MCCON;
__O uint32_t MCCON_SET;
__O uint32_t MCCON_CLR;
__I uint32_t MCCAPCON;
__O uint32_t MCCAPCON_SET;
__O uint32_t MCCAPCON_CLR;
__IO uint32_t MCTIM0;
__IO uint32_t MCTIM1;
__IO uint32_t MCTIM2;
__IO uint32_t MCPER0;
__IO uint32_t MCPER1;
__IO uint32_t MCPER2;
__IO uint32_t MCPW0;
__IO uint32_t MCPW1;
__IO uint32_t MCPW2;
__IO uint32_t MCDEADTIME;
__IO uint32_t MCCCP;
__IO uint32_t MCCR0;
__IO uint32_t MCCR1;
__IO uint32_t MCCR2;
__I uint32_t MCINTEN;
__O uint32_t MCINTEN_SET;
__O uint32_t MCINTEN_CLR;
__I uint32_t MCCNTCON;
__O uint32_t MCCNTCON_SET;
__O uint32_t MCCNTCON_CLR;
__I uint32_t MCINTFLAG;
__O uint32_t MCINTFLAG_SET;
__O uint32_t MCINTFLAG_CLR;
__O uint32_t MCCAP_CLR;
} LPC_MCPWM_TypeDef;
/*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
typedef struct
{
__O uint32_t QEICON;
__I uint32_t QEISTAT;
__IO uint32_t QEICONF;
__I uint32_t QEIPOS;
__IO uint32_t QEIMAXPOS;
__IO uint32_t CMPOS0;
__IO uint32_t CMPOS1;
__IO uint32_t CMPOS2;
__I uint32_t INXCNT;
__IO uint32_t INXCMP;
__IO uint32_t QEILOAD;
__I uint32_t QEITIME;
__I uint32_t QEIVEL;
__I uint32_t QEICAP;
__IO uint32_t VELCOMP;
__IO uint32_t FILTER;
uint32_t RESERVED0[998];
__O uint32_t QEIIEC;
__O uint32_t QEIIES;
__I uint32_t QEIINTSTAT;
__I uint32_t QEIIE;
__O uint32_t QEICLR;
__O uint32_t QEISET;
} LPC_QEI_TypeDef;
/*------------- Controller Area Network (CAN) --------------------------------*/
typedef struct
{
__IO uint32_t mask[512]; /* ID Masks */
} LPC_CANAF_RAM_TypeDef;
typedef struct /* Acceptance Filter Registers */
{
__IO uint32_t AFMR;
__IO uint32_t SFF_sa;
__IO uint32_t SFF_GRP_sa;
__IO uint32_t EFF_sa;
__IO uint32_t EFF_GRP_sa;
__IO uint32_t ENDofTable;
__I uint32_t LUTerrAd;
__I uint32_t LUTerr;
__IO uint32_t FCANIE;
__IO uint32_t FCANIC0;
__IO uint32_t FCANIC1;
} LPC_CANAF_TypeDef;
typedef struct /* Central Registers */
{
__I uint32_t CANTxSR;
__I uint32_t CANRxSR;
__I uint32_t CANMSR;
} LPC_CANCR_TypeDef;
typedef struct /* Controller Registers */
{
__IO uint32_t MOD;
__O uint32_t CMR;
__IO uint32_t GSR;
__I uint32_t ICR;
__IO uint32_t IER;
__IO uint32_t BTR;
__IO uint32_t EWL;
__I uint32_t SR;
__IO uint32_t RFS;
__IO uint32_t RID;
__IO uint32_t RDA;
__IO uint32_t RDB;
__IO uint32_t TFI1;
__IO uint32_t TID1;
__IO uint32_t TDA1;
__IO uint32_t TDB1;
__IO uint32_t TFI2;
__IO uint32_t TID2;
__IO uint32_t TDA2;
__IO uint32_t TDB2;
__IO uint32_t TFI3;
__IO uint32_t TID3;
__IO uint32_t TDA3;
__IO uint32_t TDB3;
} LPC_CAN_TypeDef;
/*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
typedef struct /* Common Registers */
{
__I uint32_t DMACIntStat;
__I uint32_t DMACIntTCStat;
__O uint32_t DMACIntTCClear;
__I uint32_t DMACIntErrStat;
__O uint32_t DMACIntErrClr;
__I uint32_t DMACRawIntTCStat;
__I uint32_t DMACRawIntErrStat;
__I uint32_t DMACEnbldChns;
__IO uint32_t DMACSoftBReq;
__IO uint32_t DMACSoftSReq;
__IO uint32_t DMACSoftLBReq;
__IO uint32_t DMACSoftLSReq;
__IO uint32_t DMACConfig;
__IO uint32_t DMACSync;
} LPC_GPDMA_TypeDef;
typedef struct /* Channel Registers */
{
__IO uint32_t DMACCSrcAddr;
__IO uint32_t DMACCDestAddr;
__IO uint32_t DMACCLLI;
__IO uint32_t DMACCControl;
__IO uint32_t DMACCConfig;
} LPC_GPDMACH_TypeDef;
/*------------- Universal Serial Bus (USB) -----------------------------------*/
typedef struct
{
__I uint32_t HcRevision; /* USB Host Registers */
__IO uint32_t HcControl;
__IO uint32_t HcCommandStatus;
__IO uint32_t HcInterruptStatus;
__IO uint32_t HcInterruptEnable;
__IO uint32_t HcInterruptDisable;
__IO uint32_t HcHCCA;
__I uint32_t HcPeriodCurrentED;
__IO uint32_t HcControlHeadED;
__IO uint32_t HcControlCurrentED;
__IO uint32_t HcBulkHeadED;
__IO uint32_t HcBulkCurrentED;
__I uint32_t HcDoneHead;
__IO uint32_t HcFmInterval;
__I uint32_t HcFmRemaining;
__I uint32_t HcFmNumber;
__IO uint32_t HcPeriodicStart;
__IO uint32_t HcLSTreshold;
__IO uint32_t HcRhDescriptorA;
__IO uint32_t HcRhDescriptorB;
__IO uint32_t HcRhStatus;
__IO uint32_t HcRhPortStatus1;
__IO uint32_t HcRhPortStatus2;
uint32_t RESERVED0[40];
__I uint32_t Module_ID;
__I uint32_t OTGIntSt; /* USB On-The-Go Registers */
__IO uint32_t OTGIntEn;
__O uint32_t OTGIntSet;
__O uint32_t OTGIntClr;
__IO uint32_t OTGStCtrl;
__IO uint32_t OTGTmr;
uint32_t RESERVED1[58];
__I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
__IO uint32_t USBDevIntEn;
__O uint32_t USBDevIntClr;
__O uint32_t USBDevIntSet;
__O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
__I uint32_t USBCmdData;
__I uint32_t USBRxData; /* USB Device Transfer Registers */
__O uint32_t USBTxData;
__I uint32_t USBRxPLen;
__O uint32_t USBTxPLen;
__IO uint32_t USBCtrl;
__O uint32_t USBDevIntPri;
__I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
__IO uint32_t USBEpIntEn;
__O uint32_t USBEpIntClr;
__O uint32_t USBEpIntSet;
__O uint32_t USBEpIntPri;
__IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
__O uint32_t USBEpInd;
__IO uint32_t USBMaxPSize;
__I uint32_t USBDMARSt; /* USB Device DMA Registers */
__O uint32_t USBDMARClr;
__O uint32_t USBDMARSet;
uint32_t RESERVED2[9];
__IO uint32_t USBUDCAH;
__I uint32_t USBEpDMASt;
__O uint32_t USBEpDMAEn;
__O uint32_t USBEpDMADis;
__I uint32_t USBDMAIntSt;
__IO uint32_t USBDMAIntEn;
uint32_t RESERVED3[2];
__I uint32_t USBEoTIntSt;
__O uint32_t USBEoTIntClr;
__O uint32_t USBEoTIntSet;
__I uint32_t USBNDDRIntSt;
__O uint32_t USBNDDRIntClr;
__O uint32_t USBNDDRIntSet;
__I uint32_t USBSysErrIntSt;
__O uint32_t USBSysErrIntClr;
__O uint32_t USBSysErrIntSet;
uint32_t RESERVED4[15];
union {
__I uint32_t I2C_RX; /* USB OTG I2C Registers */
__O uint32_t I2C_TX;
};
__I uint32_t I2C_STS;
__IO uint32_t I2C_CTL;
__IO uint32_t I2C_CLKHI;
__O uint32_t I2C_CLKLO;
uint32_t RESERVED5[824];
union {
__IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
__IO uint32_t OTGClkCtrl;
};
union {
__I uint32_t USBClkSt;
__I uint32_t OTGClkSt;
};
} LPC_USB_TypeDef;
/*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
typedef struct
{
__IO uint32_t MAC1; /* MAC Registers */
__IO uint32_t MAC2;
__IO uint32_t IPGT;
__IO uint32_t IPGR;
__IO uint32_t CLRT;
__IO uint32_t MAXF;
__IO uint32_t SUPP;
__IO uint32_t TEST;
__IO uint32_t MCFG;
__IO uint32_t MCMD;
__IO uint32_t MADR;
__O uint32_t MWTD;
__I uint32_t MRDD;
__I uint32_t MIND;
uint32_t RESERVED0[2];
__IO uint32_t SA0;
__IO uint32_t SA1;
__IO uint32_t SA2;
uint32_t RESERVED1[45];
__IO uint32_t Command; /* Control Registers */
__I uint32_t Status;
__IO uint32_t RxDescriptor;
__IO uint32_t RxStatus;
__IO uint32_t RxDescriptorNumber;
__I uint32_t RxProduceIndex;
__IO uint32_t RxConsumeIndex;
__IO uint32_t TxDescriptor;
__IO uint32_t TxStatus;
__IO uint32_t TxDescriptorNumber;
__IO uint32_t TxProduceIndex;
__I uint32_t TxConsumeIndex;
uint32_t RESERVED2[10];
__I uint32_t TSV0;
__I uint32_t TSV1;
__I uint32_t RSV;
uint32_t RESERVED3[3];
__IO uint32_t FlowControlCounter;
__I uint32_t FlowControlStatus;
uint32_t RESERVED4[34];
__IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
__IO uint32_t RxFilterWoLStatus;
__IO uint32_t RxFilterWoLClear;
uint32_t RESERVED5;
__IO uint32_t HashFilterL;
__IO uint32_t HashFilterH;
uint32_t RESERVED6[882];
__I uint32_t IntStatus; /* Module Control Registers */
__IO uint32_t IntEnable;
__O uint32_t IntClear;
__O uint32_t IntSet;
uint32_t RESERVED7;
__IO uint32_t PowerDown;
uint32_t RESERVED8;
__IO uint32_t Module_ID;
} LPC_EMAC_TypeDef;
#if defined ( __CC_ARM )
#pragma no_anon_unions
#endif
/******************************************************************************/
/* Peripheral memory map */
/******************************************************************************/
/* Base addresses */
#define LPC_FLASH_BASE (0x00000000UL)
#define LPC_RAM_BASE (0x10000000UL)
#define LPC_GPIO_BASE (0x2009C000UL)
#define LPC_APB0_BASE (0x40000000UL)
#define LPC_APB1_BASE (0x40080000UL)
#define LPC_AHB_BASE (0x50000000UL)
#define LPC_CM3_BASE (0xE0000000UL)
/* APB0 peripherals */
#define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
#define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
#define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
#define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
#define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
#define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
#define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
#define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000)
#define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
#define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
#define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000)
#define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
#define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
#define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
#define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
#define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
#define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
#define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
#define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
/* APB1 peripherals */
#define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
#define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
#define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
#define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
#define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
#define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
#define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
#define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
#define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000)
#define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
#define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
#define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
/* AHB peripherals */
#define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000)
#define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000)
#define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100)
#define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120)
#define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140)
#define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160)
#define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180)
#define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0)
#define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0)
#define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0)
#define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
/* GPIOs */
#define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000)
#define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020)
#define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040)
#define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060)
#define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080)
/******************************************************************************/
/* Peripheral declaration */
/******************************************************************************/
#define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
#define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
#define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
#define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
#define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
#define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
#define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
#define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
#define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
#define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
#define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
#define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE )
#define LPC_UART0 ((LPC_UART0_TypeDef *) LPC_UART0_BASE )
#define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
#define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
#define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
#define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
#define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
#define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
#define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
#define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
#define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE )
#define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
#define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
#define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE )
#define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
#define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
#define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
#define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
#define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
#define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
#define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
#define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
#define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
#define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
#define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
#define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
#define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
#define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
#define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
#define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
#define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
#define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
#define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
#define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
#define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
#define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
#endif // __LPC17xx_H__
inc/arch/cc.h 0 → 100644
View file @ 45999dcd
#ifndef __ARCH_CC_H__
#define __ARCH_CC_H__
#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include <string.h>
#include <sys/time.h>
#define BYTE_ORDER LITTLE_ENDIAN
typedef uint8_t u8_t;
typedef int8_t s8_t;
typedef uint16_t u16_t;
typedef int16_t s16_t;
typedef uint32_t u32_t;
typedef int32_t s32_t;
typedef uintptr_t mem_ptr_t;
#define LWIP_ERR_T int
/* Define (sn)printf formatters for these lwIP types */
#define U16_F "u"
#define S16_F "i"
#define X16_F "x"
#define U32_F "n"
#define S32_F "l"
#define X32_F "x"
/* Compiler hints for packing structures */
#define PACK_STRUCT_FIELD(x) x
#define PACK_STRUCT_STRUCT __attribute__((packed))
#define PACK_STRUCT_BEGIN
#define PACK_STRUCT_END
/* Plaform specific diagnostic output */
#define LWIP_PLATFORM_DIAG(x) {tprintf x;}
#define LWIP_PLATFORM_ASSERT(x) do {tprintf("Assertion \"%s\" failed at line %d in %s\n", \
x, __LINE__, __FILE__); while (1);} while(0)
#endif /* __ARCH_CC_H__ */
inc/arch/perf.h 0 → 100644
View file @ 45999dcd
/*
* Author: Adam Dunkels <adam@sics.se>
*
*/
#ifndef __LWIP_ARCH_PERF_H__
#define __LWIP_ARCH_PERF_H__
#define PERF_START
#define PERF_STOP(x)
#endif /* __LWIP_ARCH_PERF_H__ */
inc/config.h 0 → 100644
View file @ 45999dcd
/** \file config.h
* \brief Basic configuration of the project
* \author Freddie Chopin, http://www.freddiechopin.info/
* \date 2012-04-06
*/
/******************************************************************************
* project: lpc1769_blink_led
* chip: LPC1769
* compiler: arm-none-eabi-gcc (GNU Tools for ARM Embedded Processors) 4.6.2
* 20110921 (release) [ARM/embedded-4_6-branch revision 182083]
******************************************************************************/
#ifndef CONFIG_H_
#define CONFIG_H_
#include "hdr/hdr_bitband.h"
/*
+=============================================================================+
| global definitions
+=============================================================================+
*/
#define CRYSTAL 12000000ul ///< quartz crystal resonator which is connected to the chip
#define FREQUENCY 100000000ul ///< desired target frequency of the core
#define LED_GPIO LPC_GPIO0 ///< GPIO port to which the LED is connected
#define LED_pin 22 ///< pin number of the LED
#define LED (1 << LED_pin)
#define LED_FIOPIN LED_GPIO->FIOPIN ///< output register for the LED
#define LED_bb bitband_t BITBAND(&LED_FIOPIN, LED_pin) ///< bit-band "variable" to directly handle the pin
/*
+=============================================================================+
| strange variables
+=============================================================================+
*/
/*
+=============================================================================+
| global variables
+=============================================================================+
*/
/*
+=============================================================================+
| global functions' declarations
+=============================================================================+
*/
/******************************************************************************
* END OF FILE
******************************************************************************/
#endif /* CONFIG_H_ */
inc/core_cm3.h 0 → 100644
View file @ 45999dcd
/**************************************************************************//**
* @file core_cm3.h
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
* @version V2.01
* @date 06. December 2010
*
* @note
* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#endif
#ifdef __cplusplus
extern "C" {
#endif
#ifndef __CORE_CM3_H_GENERIC
#define __CORE_CM3_H_GENERIC
/** \mainpage CMSIS Cortex-M3
This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.
It consists of:
- Cortex-M Core Register Definitions
- Cortex-M functions
- Cortex-M instructions
The CMSIS Cortex-M3 Core Peripheral Access Layer contains C and assembly functions that ease
access to the Cortex-M Core
*/
/** \defgroup CMSIS_LintCinfiguration CMSIS Lint Configuration
List of Lint messages which will be suppressed and not shown:
- not yet checked
.
Note: To re-enable a Message, insert a space before 'lint' *
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/** \defgroup CMSIS_core_definitions CMSIS Core Definitions
This file defines all structures and symbols for CMSIS core:
- CMSIS version number
- Cortex-M core
- Cortex-M core Revision Number
@{
*/
/* CMSIS CM3 definitions */
#define __CM3_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */
#define __CM3_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
#define __CORTEX_M (0x03) /*!< Cortex core */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#endif
#include <stdint.h> /*!< standard types definitions */
#include "core_cmInstr.h" /*!< Core Instruction Access */
#include "core_cmFunc.h" /*!< Core Function Access */
#endif /* __CORE_CM3_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM3_H_DEPENDANT
#define __CORE_CM3_H_DEPENDANT
/* IO definitions (access restrictions to peripheral registers) */
#ifdef __cplusplus
#define __I volatile /*!< defines 'read only' permissions */
#else
#define __I volatile const /*!< defines 'read only' permissions */
#endif
#define __O volatile /*!< defines 'write only' permissions */
#define __IO volatile /*!< defines 'read / write' permissions */
/*@} end of group CMSIS_core_definitions */
/*******************************************************************************
* Register Abstraction
******************************************************************************/
/** \defgroup CMSIS_core_register CMSIS Core Register
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
- Core Debug Register
- Core MPU Register
*/
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CORE CMSIS Core
Type definitions for the Cortex-M Core Registers
@{
*/
/** \brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
#if (__CORTEX_M != 0x04)
uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
#else
uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
#endif
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/** \brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
#if (__CORTEX_M != 0x04)
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
#else
uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
#endif
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/** \brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/*@} end of group CMSIS_CORE */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_NVIC CMSIS NVIC
Type definitions for the Cortex-M NVIC Registers
@{
*/
/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[24];
__IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[24];
__IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[24];
__IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[24];
__IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
uint32_t RESERVED4[56];
__IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
uint32_t RESERVED5[644];
__O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SCB CMSIS SCB
Type definitions for the Cortex-M System Control Block Registers
@{
*/
/** \brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPU ID Base Register */
__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control State Register */
__IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
__IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt / Reset Control Register */
__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
__IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
__IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
__IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) Hard Fault Status Register */
__IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
__IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) Mem Manage Address Register */
__IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) Bus Fault Address Register */
__IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
__I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
__I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
__I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
__I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
__I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) ISA Feature Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
/* SCB Configurable Fault Status Registers Definitions */
#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
/* SCB Hard Fault Status Registers Definitions */
#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
/* SCB Debug Fault Status Register Definitions */
#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
/*@} end of group CMSIS_SCB */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SysTick CMSIS SysTick
Type definitions for the Cortex-M System Timer Registers
@{
*/
/** \brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_ITM CMSIS ITM
Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM)
@{
*/
/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
*/
typedef struct
{
__O union
{
__O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
__O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
__O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
} PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
uint32_t RESERVED0[864];
__IO uint32_t TER; /*!< Offset: (R/W) ITM Trace Enable Register */
uint32_t RESERVED1[15];
__IO uint32_t TPR; /*!< Offset: (R/W) ITM Trace Privilege Register */
uint32_t RESERVED2[15];
__IO uint32_t TCR; /*!< Offset: (R/W) ITM Trace Control Register */
uint32_t RESERVED3[29];
__IO uint32_t IWR; /*!< Offset: (R/W) ITM Integration Write Register */
__IO uint32_t IRR; /*!< Offset: (R/W) ITM Integration Read Register */
__IO uint32_t IMCR; /*!< Offset: (R/W) ITM Integration Mode Control Register */
uint32_t RESERVED4[43];
__IO uint32_t LAR; /*!< Offset: (R/W) ITM Lock Access Register */
__IO uint32_t LSR; /*!< Offset: (R/W) ITM Lock Status Register */
uint32_t RESERVED5[6];
__I uint32_t PID4; /*!< Offset: (R/ ) ITM Peripheral Identification Register #4 */
__I uint32_t PID5; /*!< Offset: (R/ ) ITM Peripheral Identification Register #5 */
__I uint32_t PID6; /*!< Offset: (R/ ) ITM Peripheral Identification Register #6 */
__I uint32_t PID7; /*!< Offset: (R/ ) ITM Peripheral Identification Register #7 */
__I uint32_t PID0; /*!< Offset: (R/ ) ITM Peripheral Identification Register #0 */
__I uint32_t PID1; /*!< Offset: (R/ ) ITM Peripheral Identification Register #1 */
__I uint32_t PID2; /*!< Offset: (R/ ) ITM Peripheral Identification Register #2 */
__I uint32_t PID3; /*!< Offset: (R/ ) ITM Peripheral Identification Register #3 */
__I uint32_t CID0; /*!< Offset: (R/ ) ITM Component Identification Register #0 */
__I uint32_t CID1; /*!< Offset: (R/ ) ITM Component Identification Register #1 */
__I uint32_t CID2; /*!< Offset: (R/ ) ITM Component Identification Register #2 */
__I uint32_t CID3; /*!< Offset: (R/ ) ITM Component Identification Register #3 */
} ITM_Type;
/* ITM Trace Privilege Register Definitions */
#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
/* ITM Trace Control Register Definitions */
#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
#define ITM_TCR_ATBID_Pos 16 /*!< ITM TCR: ATBID Position */
#define ITM_TCR_ATBID_Msk (0x7FUL << ITM_TCR_ATBID_Pos) /*!< ITM TCR: ATBID Mask */
#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
/* ITM Integration Write Register Definitions */
#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
/* ITM Integration Read Register Definitions */
#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
/* ITM Integration Mode Control Register Definitions */
#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
/* ITM Lock Status Register Definitions */
#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
/*@}*/ /* end of group CMSIS_ITM */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_InterruptType CMSIS Interrupt Type
Type definitions for the Cortex-M Interrupt Type Register
@{
*/
/** \brief Structure type to access the Interrupt Type Register.
*/
typedef struct
{
uint32_t RESERVED0;
__I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Control Type Register */
#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
__IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
#else
uint32_t RESERVED1;
#endif
} InterruptType_Type;
/* Interrupt Controller Type Register Definitions */
#define IntType_ICTR_INTLINESNUM_Pos 0 /*!< InterruptType ICTR: INTLINESNUM Position */
#define IntType_ICTR_INTLINESNUM_Msk (0x1FUL << IntType_ICTR_INTLINESNUM_Pos) /*!< InterruptType ICTR: INTLINESNUM Mask */
/* Auxiliary Control Register Definitions */
#define IntType_ACTLR_DISFOLD_Pos 2 /*!< InterruptType ACTLR: DISFOLD Position */
#define IntType_ACTLR_DISFOLD_Msk (1UL << IntType_ACTLR_DISFOLD_Pos) /*!< InterruptType ACTLR: DISFOLD Mask */
#define IntType_ACTLR_DISDEFWBUF_Pos 1 /*!< InterruptType ACTLR: DISDEFWBUF Position */
#define IntType_ACTLR_DISDEFWBUF_Msk (1UL << IntType_ACTLR_DISDEFWBUF_Pos) /*!< InterruptType ACTLR: DISDEFWBUF Mask */
#define IntType_ACTLR_DISMCYCINT_Pos 0 /*!< InterruptType ACTLR: DISMCYCINT Position */
#define IntType_ACTLR_DISMCYCINT_Msk (1UL << IntType_ACTLR_DISMCYCINT_Pos) /*!< InterruptType ACTLR: DISMCYCINT Mask */
/*@}*/ /* end of group CMSIS_InterruptType */
#if (__MPU_PRESENT == 1)
/** \ingroup CMSIS_core_register
\defgroup CMSIS_MPU CMSIS MPU
Type definitions for the Cortex-M Memory Protection Unit (MPU)
@{
*/
/** \brief Structure type to access the Memory Protection Unit (MPU).
*/
typedef struct
{
__I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
__IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
__IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
__IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
__IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
__IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
__IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
__IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
__IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
__IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
__IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
} MPU_Type;
/* MPU Type Register */
#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
/* MPU Control Register */
#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
/* MPU Region Number Register */
#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
/* MPU Region Base Address Register */
#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
/* MPU Region Attribute and Size Register */
#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: XN Position */
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: XN Mask */
#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: AP Position */
#define MPU_RASR_AP_Msk (7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: AP Mask */
#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: TEX Position */
#define MPU_RASR_TEX_Msk (7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: TEX Mask */
#define MPU_RASR_S_Pos 18 /*!< MPU RASR: Shareable bit Position */
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: Shareable bit Mask */
#define MPU_RASR_C_Pos 17 /*!< MPU RASR: Cacheable bit Position */
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: Cacheable bit Mask */
#define MPU_RASR_B_Pos 16 /*!< MPU RASR: Bufferable bit Position */
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: Bufferable bit Mask */
#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
#define MPU_RASR_ENA_Pos 0 /*!< MPU RASR: Region enable bit Position */
#define MPU_RASR_ENA_Msk (0x1UL << MPU_RASR_ENA_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
/*@} end of group CMSIS_MPU */
#endif
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug CMSIS Core Debug
Type definitions for the Cortex-M Core Debug Registers
@{
*/
/** \brief Structure type to access the Core Debug Register (CoreDebug).
*/
typedef struct
{
__IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
__O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
__IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
__IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
} CoreDebug_Type;
/* Debug Halting Control and Status Register */
#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
/* Debug Core Register Selector Register */
#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
/* Debug Exception and Monitor Control Register */
#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
/*@} end of group CMSIS_CoreDebug */
/** \ingroup CMSIS_core_register
@{
*/
/* Memory mapping of Cortex-M3 Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define InterruptType ((InterruptType_Type *) SCS_BASE) /*!< Interrupt Type Register */
#define SCB ((SCB_Type *) SCB_BASE) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE) /*!< NVIC configuration struct */
#define ITM ((ITM_Type *) ITM_BASE) /*!< ITM configuration struct */
#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
#if (__MPU_PRESENT == 1)
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
#define MPU ((MPU_Type*) MPU_BASE) /*!< Memory Protection Unit */
#endif
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
******************************************************************************/
/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Debug Functions
- Core Register Access Functions
*/
/* ########################## NVIC functions #################################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions
@{
*/
/** \brief Set Priority Grouping
This function sets the priority grouping field using the required unlock sequence.
The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
Only values from 0..7 are used.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field
*/
static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
reg_value = SCB->AIRCR; /* read old register configuration */
reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
reg_value = (reg_value |
(0x5FA << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << 8)); /* Insert write key and priorty group */
SCB->AIRCR = reg_value;
}
/** \brief Get Priority Grouping
This function gets the priority grouping from NVIC Interrupt Controller.
Priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
\return Priority grouping field
*/
static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
{
return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
}
/** \brief Enable External Interrupt
This function enables a device specific interupt in the NVIC interrupt controller.
The interrupt number cannot be a negative value.
\param [in] IRQn Number of the external interrupt to enable
*/
static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
}
/** \brief Disable External Interrupt
This function disables a device specific interupt in the NVIC interrupt controller.
The interrupt number cannot be a negative value.
\param [in] IRQn Number of the external interrupt to disable
*/
static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
}
/** \brief Get Pending Interrupt
This function reads the pending register in the NVIC and returns the pending bit
for the specified interrupt.
\param [in] IRQn Number of the interrupt for get pending
\return 0 Interrupt status is not pending
\return 1 Interrupt status is pending
*/
static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
}
/** \brief Set Pending Interrupt
This function sets the pending bit for the specified interrupt.
The interrupt number cannot be a negative value.
\param [in] IRQn Number of the interrupt for set pending
*/
static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
}
/** \brief Clear Pending Interrupt
This function clears the pending bit for the specified interrupt.
The interrupt number cannot be a negative value.
\param [in] IRQn Number of the interrupt for clear pending
*/
static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
}
/** \brief Get Active Interrupt
This function reads the active register in NVIC and returns the active bit.
\param [in] IRQn Number of the interrupt for get active
\return 0 Interrupt status is not active
\return 1 Interrupt status is active
*/
static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
{
return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
}
/** \brief Set Interrupt Priority
This function sets the priority for the specified interrupt. The interrupt
number can be positive to specify an external (device specific)
interrupt, or negative to specify an internal (core) interrupt.
Note: The priority cannot be set for every core interrupt.
\param [in] IRQn Number of the interrupt for set priority
\param [in] priority Priority to set
*/
static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if(IRQn < 0) {
SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
else {
NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
}
/** \brief Get Interrupt Priority
This function reads the priority for the specified interrupt. The interrupt
number can be positive to specify an external (device specific)
interrupt, or negative to specify an internal (core) interrupt.
The returned priority value is automatically aligned to the implemented
priority bits of the microcontroller.
\param [in] IRQn Number of the interrupt for get priority
\return Interrupt Priority
*/
static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if(IRQn < 0) {
return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
else {
return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
}
/** \brief Encode Priority
This function encodes the priority for an interrupt with the given priority group,
preemptive priority value and sub priority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
The returned priority value can be used for NVIC_SetPriority(...) function
\param [in] PriorityGroup Used priority group
\param [in] PreemptPriority Preemptive priority value (starting from 0)
\param [in] SubPriority Sub priority value (starting from 0)
\return Encoded priority for the interrupt
*/
static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
return (
((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
((SubPriority & ((1 << (SubPriorityBits )) - 1)))
);
}
/** \brief Decode Priority
This function decodes an interrupt priority value with the given priority group to
preemptive priority value and sub priority value.
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
The priority value can be retrieved with NVIC_GetPriority(...) function
\param [in] Priority Priority value
\param [in] PriorityGroup Used priority group
\param [out] pPreemptPriority Preemptive priority value (starting from 0)
\param [out] pSubPriority Sub priority value (starting from 0)
*/
static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
*pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
*pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
}
/** \brief System Reset
This function initiate a system reset request to reset the MCU.
*/
static __INLINE void NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
(SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
__DSB(); /* Ensure completion of memory access */
while(1); /* wait until reset */
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions
@{
*/
#if (__Vendor_SysTickConfig == 0)
/** \brief System Tick Configuration
This function initialises the system tick timer and its interrupt and start the system tick timer.
Counter is in free running mode to generate periodical interrupts.
\param [in] ticks Number of ticks between two interrupts
\return 0 Function succeeded
\return 1 Function failed
*/
static __INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
/* ##################################### Debug In/Output function ########################################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions
@{
*/
extern volatile int32_t ITM_RxBuffer; /*!< external variable to receive characters */
#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */
/** \brief ITM Send Character
This function transmits a character via the ITM channel 0.
It just returns when no debugger is connected that has booked the output.
It is blocking when a debugger is connected, but the previous character send is not transmitted.
\param [in] ch Character to transmit
\return Character to transmit
*/
static __INLINE uint32_t ITM_SendChar (uint32_t ch)
{
if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk) && /* Trace enabled */
(ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
(ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
{
while (ITM->PORT[0].u32 == 0);
ITM->PORT[0].u8 = (uint8_t) ch;
}
return (ch);
}
/** \brief ITM Receive Character
This function inputs a character via external variable ITM_RxBuffer.
It just returns when no debugger is connected that has booked the output.
It is blocking when a debugger is connected, but the previous character send is not transmitted.
\return Received character
\return -1 No character received
*/
static __INLINE int32_t ITM_ReceiveChar (void) {
int32_t ch = -1; /* no character available */
if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
ch = ITM_RxBuffer;
ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
}
return (ch);
}
/** \brief ITM Check Character
This function checks external variable ITM_RxBuffer whether a character is available or not.
It returns '1' if a character is available and '0' if no character is available.
\return 0 No character available
\return 1 Character available
*/
static __INLINE int32_t ITM_CheckChar (void) {
if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
return (0); /* no character available */
} else {
return (1); /* character available */
}
}
/*@} end of CMSIS_core_DebugFunctions */
#endif /* __CORE_CM3_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */
#ifdef __cplusplus
}
#endif
/*lint -restore */
inc/core_cmFunc.h 0 → 100644
View file @ 45999dcd
/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V2.01
* @date 06. December 2010
*
* @note
* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __CORE_CMFUNC_H__
#define __CORE_CMFUNC_H__
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
/* ARM armcc specific functions */
/* intrinsic void __enable_irq(); */
/* intrinsic void __disable_irq(); */
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
#if (__ARMCC_VERSION < 400000)
extern uint32_t __get_CONTROL(void);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
#endif /* __ARMCC_VERSION */
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
#if (__ARMCC_VERSION < 400000)
extern void __set_CONTROL(uint32_t control);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
#endif /* __ARMCC_VERSION */
/** \brief Get ISPR Register
This function returns the content of the ISPR Register.
\return ISPR Register value
*/
#if (__ARMCC_VERSION < 400000)
extern uint32_t __get_IPSR(void);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
#endif /* __ARMCC_VERSION */
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
#if (__ARMCC_VERSION < 400000)
extern uint32_t __get_APSR(void);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
#endif /* __ARMCC_VERSION */
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
#if (__ARMCC_VERSION < 400000)
extern uint32_t __get_xPSR(void);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
#endif /* __ARMCC_VERSION */
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
#if (__ARMCC_VERSION < 400000)
extern uint32_t __get_PSP(void);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
#endif /* __ARMCC_VERSION */
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
#if (__ARMCC_VERSION < 400000)
extern void __set_PSP(uint32_t topOfProcStack);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
#endif /* __ARMCC_VERSION */
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
#if (__ARMCC_VERSION < 400000)
extern uint32_t __get_MSP(void);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
#endif /* __ARMCC_VERSION */
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
#if (__ARMCC_VERSION < 400000)
extern void __set_MSP(uint32_t topOfMainStack);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
#endif /* __ARMCC_VERSION */
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
#if (__ARMCC_VERSION < 400000)
extern uint32_t __get_PRIMASK(void);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
#endif /* __ARMCC_VERSION */
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
#if (__ARMCC_VERSION < 400000)
extern void __set_PRIMASK(uint32_t priMask);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#endif /* __ARMCC_VERSION */
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
#if (__ARMCC_VERSION < 400000)
extern uint32_t __get_BASEPRI(void);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
#endif /* __ARMCC_VERSION */
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
#if (__ARMCC_VERSION < 400000)
extern void __set_BASEPRI(uint32_t basePri);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xff);
}
#endif /* __ARMCC_VERSION */
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
#if (__ARMCC_VERSION < 400000)
extern uint32_t __get_FAULTMASK(void);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
#endif /* __ARMCC_VERSION */
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
#if (__ARMCC_VERSION < 400000)
extern void __set_FAULTMASK(uint32_t faultMask);
#else /* (__ARMCC_VERSION >= 400000) */
static __INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & 1);
}
#endif /* __ARMCC_VERSION */
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
static __INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1)
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
static __INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1)
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
/* IAR iccarm specific functions */
#if defined (__ICCARM__)
#include <intrinsics.h> /* IAR Intrinsics */
#endif
#pragma diag_suppress=Pe940
/** \brief Enable IRQ Interrupts
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_irq __enable_interrupt
/** \brief Disable IRQ Interrupts
This function disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_irq __disable_interrupt
/* intrinsic unsigned long __get_CONTROL( void ); (see intrinsic.h) */
/* intrinsic void __set_CONTROL( unsigned long ); (see intrinsic.h) */
/** \brief Get ISPR Register
This function returns the content of the ISPR Register.
\return ISPR Register value
*/
static uint32_t __get_IPSR(void)
{
__ASM("mrs r0, ipsr");
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
static uint32_t __get_APSR(void)
{
__ASM("mrs r0, apsr");
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
static uint32_t __get_xPSR(void)
{
__ASM("mrs r0, psr"); // assembler does not know "xpsr"
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
static uint32_t __get_PSP(void)
{
__ASM("mrs r0, psp");
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
static void __set_PSP(uint32_t topOfProcStack)
{
__ASM("msr psp, r0");
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
static uint32_t __get_MSP(void)
{
__ASM("mrs r0, msp");
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
static void __set_MSP(uint32_t topOfMainStack)
{
__ASM("msr msp, r0");
}
/* intrinsic unsigned long __get_PRIMASK( void ); (see intrinsic.h) */
/* intrinsic void __set_PRIMASK( unsigned long ); (see intrinsic.h) */
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
static __INLINE void __enable_fault_irq(void)
{
__ASM ("cpsie f");
}
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
static __INLINE void __disable_fault_irq(void)
{
__ASM ("cpsid f");
}
/* intrinsic unsigned long __get_BASEPRI( void ); (see intrinsic.h) */
/* intrinsic void __set_BASEPRI( unsigned long ); (see intrinsic.h) */
/* intrinsic unsigned long __get_FAULTMASK( void ); (see intrinsic.h) */
/* intrinsic void __set_FAULTMASK(unsigned long); (see intrinsic.h) */
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
static uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1)
__ASM("vmrs r0, fpscr");
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
static void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1)
__ASM("vmsr fpscr, r0");
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#pragma diag_default=Pe940
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief Enable IRQ Interrupts
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)
{
__ASM volatile ("cpsie i");
}
/** \brief Disable IRQ Interrupts
This function disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i");
}
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)
{
uint32_t result;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) );
}
/** \brief Get ISPR Register
This function returns the content of the ISPR Register.
\return ISPR Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
return(result);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
return(result);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
return(result);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
return(result);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
return(result);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return(result);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) );
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)
{
__ASM volatile ("cpsie f");
}
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void)
{
__ASM volatile ("cpsid f");
}
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
return(result);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) );
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1)
uint32_t result;
__ASM volatile ("MRS %0, fpscr" : "=r" (result) );
return(result);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1)
__ASM volatile ("MSR fpscr, %0" : : "r" (fpscr) );
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H__ */
inc/core_cmInstr.h 0 → 100644
View file @ 45999dcd
/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V2.01
* @date 06. December 2010
*
* @note
* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __CORE_CMINSTR_H__
#define __CORE_CMINSTR_H__
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
/* ARM armcc specific functions */
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
#define __WFI __wfi
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
#define __ISB() __isb(0xF)
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() __dsb(0xF)
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() __dmb(0xF)
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
#if (__ARMCC_VERSION < 400677)
extern uint32_t __REV16(uint32_t value);
#else /* (__ARMCC_VERSION >= 400677) */
static __INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
#if (__ARMCC_VERSION < 400677)
extern int32_t __REVSH(int32_t value);
#else /* (__ARMCC_VERSION >= 400677) */
static __INLINE __ASM int32_t __REVSH(int32_t value)
{
revsh r0, r0
bx lr
}
#endif /* __ARMCC_VERSION */
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __RBIT __rbit
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXB(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXH(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXW(value, ptr) __strex(value, ptr)
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
#if (__ARMCC_VERSION < 400000)
extern void __CLREX(void);
#else /* (__ARMCC_VERSION >= 400000) */
#define __CLREX __clrex
#endif /* __ARMCC_VERSION */
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#endif /* (__CORTEX_M >= 0x03) */
#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
/* IAR iccarm specific functions */
#include <intrinsics.h> /* IAR Intrinsics */
#pragma diag_suppress=Pe940
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __no_operation
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
static __INLINE void __WFI(void)
{
__ASM ("wfi");
}
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
static __INLINE void __WFE(void)
{
__ASM ("wfe");
}
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
static __INLINE void __SEV(void)
{
__ASM ("sev");
}
/* intrinsic void __ISB(void) (see intrinsics.h) */
/* intrinsic void __DSB(void) (see intrinsics.h) */
/* intrinsic void __DMB(void) (see intrinsics.h) */
/* intrinsic uint32_t __REV(uint32_t value) (see intrinsics.h) */
/* intrinsic __SSAT (see intrinsics.h) */
/* intrinsic __USAT (see intrinsics.h) */
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
static uint32_t __REV16(uint32_t value)
{
__ASM("rev16 r0, r0");
}
/* intrinsic uint32_t __REVSH(uint32_t value) (see intrinsics.h */
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
static uint32_t __RBIT(uint32_t value)
{
__ASM("rbit r0, r0");
}
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
static uint8_t __LDREXB(volatile uint8_t *addr)
{
__ASM("ldrexb r0, [r0]");
}
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
static uint16_t __LDREXH(volatile uint16_t *addr)
{
__ASM("ldrexh r0, [r0]");
}
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
/* intrinsic unsigned long __LDREX(unsigned long *) (see intrinsics.h) */
static uint32_t __LDREXW(volatile uint32_t *addr)
{
__ASM("ldrex r0, [r0]");
}
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
static uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
__ASM("strexb r0, r0, [r1]");
}
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
static uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
__ASM("strexh r0, r0, [r1]");
}
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
/* intrinsic unsigned long __STREX(unsigned long, unsigned long) (see intrinsics.h )*/
static uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
__ASM("strex r0, r0, [r1]");
}
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
static __INLINE void __CLREX(void)
{
__ASM ("clrex");
}
/* intrinsic unsigned char __CLZ( unsigned long ) (see intrinsics.h) */
#endif /* (__CORTEX_M >= 0x03) */
#pragma diag_default=Pe940
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
__attribute__( ( always_inline ) ) static __INLINE void __NOP(void)
{
__ASM volatile ("nop");
}
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) static __INLINE void __WFI(void)
{
__ASM volatile ("wfi");
}
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) static __INLINE void __WFE(void)
{
__ASM volatile ("wfe");
}
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
__attribute__( ( always_inline ) ) static __INLINE void __SEV(void)
{
__ASM volatile ("sev");
}
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
__attribute__( ( always_inline ) ) static __INLINE void __ISB(void)
{
__ASM volatile ("isb");
}
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__attribute__( ( always_inline ) ) static __INLINE void __DSB(void)
{
__ASM volatile ("dsb");
}
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__attribute__( ( always_inline ) ) static __INLINE void __DMB(void)
{
__ASM volatile ("dmb");
}
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value)
{
uint32_t result;
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr)
{
uint8_t result;
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr)
{
uint16_t result;
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
uint32_t result;
__ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
uint32_t result;
__ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)
{
__ASM volatile ("clrex");
}
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value)
{
uint8_t result;
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
#endif /* (__CORTEX_M >= 0x03) */
#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
#endif /* __CORE_CMINSTR_H__ */
inc/cpld.h 0 → 100644
View file @ 45999dcd
/* Copyright (C) 2013 Upi Tamminen
* See the COPYRIGHT file for more information */
#ifndef __CPLD_H
#define __CPLD_H
void cpld_capture(void);
void cpld_xfr(void);
#endif
/* vim: set sw=4 et: */
inc/cpu.h 0 → 100644
View file @ 45999dcd
/* Copyright (C) 2013 Upi Tamminen
* See the COPYRIGHT file for more information */
#ifndef __CPU_H
#define __CPU_H
#include <stdint.h>
void flash_latency(uint32_t frequency);
void pll0_feed(void);
uint32_t pll0_start(uint32_t crystal, uint32_t frequency);
void system_init(void);
#endif
inc/dma.h 0 → 100644
View file @ 45999dcd
/* Copyright (C) 2013 Upi Tamminen
* See the COPYRIGHT file for more information */
#ifndef __DMA_H
#define __DMA_H
void dma_init(uint8_t *buf, uint16_t len);
void dma_start(uint8_t *buf, uint16_t len);
void dma_transfer(uint8_t *buf);
void dma_test(uint8_t *buf);
void dma_showdebug(void);
#endif
/* vim: set sw=4 et: */
inc/enc28j60.h 0 → 100644
View file @ 45999dcd
/* Copyright (C) 2013 Upi Tamminen
* See the COPYRIGHT file for more information */
#ifndef __ENC28J60_H
#define __ENC28J60_H
#include <stdint.h>
void enc_init(const uint8_t *mac);
uint8_t enc_test(void);
uint8_t enc_action(void);
void enc_send_packet(const uint8_t *buf, uint16_t count);
void enc_send_packet_begin(uint16_t count);
void enc_send_packet_end(uint16_t count);
uint16_t enc_receive_packet_begin(void);
void enc_receive_packet(uint8_t *buf, uint16_t len);
void enc_receive_packet_end(void);
void enc_get_mac_addr(uint8_t *mac_addr);
uint8_t enc_revid(void);
#endif
/* vim: set sw=4 et: */
inc/enc28j60if.h 0 → 100644
View file @ 45999dcd
/* Copyright (C) 2013 Upi Tamminen
* See the COPYRIGHT file for more information */
#ifndef __ENC28J60IF_H
#define __ENC28J60IF_H
#include <stdint.h>
void ethernet_init(void);
void ethernet_action(void);
#endif
/* vim: set sw=4 et: */
inc/enc28j60reg.h 0 → 100644
View file @ 45999dcd
/*
* This is from
* https://github.com/xpgdk/stellaris-enc28j60-booster
* Thank you, author
*/
#ifndef _ENC28J60_REG_H
#define _ENC28J60_REG_H
#define ANY_BANK 4
#define ENC_BANK(REG) REG ## _BANK
#define ENC_ERDPTL 0x00
#define ENC_ERDPTL_BANK 0
#define ENC_ERDPTH 0x01
#define ENC_ERDPTH_BANK 0
#define ENC_EWRPTL 0x02
#define ENC_EWRPTL_BANK 0
#define ENC_EWRPTH 0x03
#define ENC_EWRPTH_BANK 0
#define ENC_ETXSTL 0x04
#define ENC_ETXSTL_BANK 0
#define ENC_ETXSTH 0x05
#define ENC_ETXSTH_BANK 0
#define ENC_ETXNDL 0x06
#define ENC_ETXNDL_BANK 0
#define ENC_ETXNDH 0x07
#define ENC_ETXNDH_BANK 0
#define ENC_ERXSTL 0x08
#define ENC_ERXSTL_BANK 0
#define ENC_ERXSTH 0x09
#define ENC_ERXSTH_BANK 0
#define ENC_ERXNDL 0x0A
#define ENC_ERXNDL_BANK 0
#define ENC_ERXNDH 0x0B
#define ENC_ERXNDH_BANK 0
#define ENC_ERXRDPTL 0x0C
#define ENC_ERXRDPTL_BANK 0
#define ENC_ERXRDPTH 0x0D
#define ENC_ERXRDPTH_BANK 0
#define ENC_ERXWRPTL 0x0E
#define ENC_ERXWRPTL_BANK 0
#define ENC_ERXWRPTH 0x0F
#define ENC_ERXWRPTH_BANK 0
#define ENC_ERXFCON 0x18
#define ENC_ERXFCON_BANK 1
#define ENC_ERXFCON_BCEN (1<<0)
#define ENC_ERXFCON_MCEN (1<<1)
#define ENC_ERXFCON_HTEN (1<<2)
#define ENC_ERXFCON_MPEN (1<<3)
#define ENC_ERXFCON_PMEN (1<<4)
#define ENC_ERXFCON_CRCEN (1<<5)
#define ENC_ERXFCON_ANDOR (1<<6)
#define ENC_ERXFCON_UCEN (1<<7)
#define ENC_EPKTCNT 0x19
#define ENC_EPKTCNT_BANK 1
#define ENC_MACON1 0x00
#define ENC_MACON1_MARXEN (1<<0)
#define ENC_MACON1_PASSALL (1<<1)
#define ENC_MACON1_RXPAUS (1<<2)
#define ENC_MACON1_TXPAUS (1<<3)
#define ENC_MACON1_BANK 2
#define ENC_MACON3 0x02
#define ENC_MACON3_FULDPX (1<<0)
#define ENC_MACON3_FRMLNEN (1<<1)
#define ENC_MACON3_HFRMEN (1<<2)
#define ENC_MACON3_PHDREN (1<<3)
#define ENC_MACON3_TXRCEN (1<<4)
#define ENC_MACON3_PADCFG_MASK 0x07
#define ENC_MACON3_PADCFG_SHIFT 5
#define ENC_MACON3_BANK 2
#define ENC_MACON4 0x03
#define ENC_MACON4_NOBKOFF (1<<4)
#define ENC_MACON4_BPEN (1<<5)
#define ENC_MACON4_DEFER (1<<6)
#define ENC_MACON4_BANK 2
#define ENC_MABBIPG 0x04
#define ENC_MABBIPG_BANK 2
#define ENC_MAIPGL 0x06
#define ENC_MAIPGL_BANK 2
#define ENC_MAIPGH 0x07
#define ENC_MAIPGH_BANK 2
#define ENC_MACLCON1 0x08
#define ENC_MACLCON1_BANK 2
#define ENC_MICMD 0x12
#define ENC_MICMD_BANK 2
#define ENC_MIREGADR 0x14
#define ENC_MIREGADR_BANK 2
#define ENC_MIWRL 0x16
#define ENC_MIWRL_BANK 2
#define ENC_MIWRH 0x17
#define ENC_MIWRH_BANK 2
#define ENC_MIRDL 0x18
#define ENC_MIRDL_BANK 2
#define ENC_MIRDH 0x19
#define ENC_MIRDH_BANK 2
#define ENC_MAMXFLL 0x0A
#define ENC_MAMXFLL_BANK 2
#define ENC_MAMXFLH 0x0B
#define ENC_MAMXFLH_BANK 2
#define ENC_MAADR5 0x00
#define ENC_MAADR5_BANK 3
#define ENC_MAADR6 0x01
#define ENC_MAADR6_BANK 3
#define ENC_MAADR3 0x02
#define ENC_MAADR3_BANK 3
#define ENC_MAADR4 0x03
#define ENC_MAADR4_BANK 3
#define ENC_MAADR1 0x04
#define ENC_MAADR1_BANK 3
#define ENC_MAADR2 0x05
#define ENC_MAADR2_BANK 3
#define ENC_MISTAT 0x0A
#define ENC_MISTAT_BUSY (1<<0)
#define ENC_MISTAT_SCAN (1<<1)
#define ENC_MISTAT_NVALID (1<<2)
#define ENC_MISTAT_BANK 3
#define ENC_EREVID 0x12
#define ENC_EREVID_BANK 3
/* Common registers */
#define ENC_ECON1 0x1F
#define ENC_ECON1_BSEL_MASK 0x03
#define ENC_ECON1_BSEL_SHIFT 0
#define ENC_ECON1_RXEN (1<<2)
#define ENC_ECON1_TXRTS (1<<3)
#define ENC_ECON1_CSUMEN (1<<4)
#define ENC_ECON1_DMAST (1<<5)
#define ENC_ECON1_RXRST (1<<6)
#define ENC_ECON1_TXRST (1<<7)
#define ENC_ECON1_BANK ANY_BANK
#define ENC_ECON2 0x1E
#define ENC_ECON2_VRPS (1<<3)
#define ENC_ECON2_PWSRV (1<<5)
#define ENC_ECON2_PKTDEC (1<<6)
#define ENC_ECON2_AUTOINC (1<<7)
#define ENC_ECON2_BANK ANY_BANK
#define ENC_ESTAT 0x1D
#define ENC_ESTAT_CLKRDY (1<<0)
#define ENC_ESTAT_TXABRT (1<<1)
#define ENC_ESTAT_RXBUSY (1<<2)
#define ENC_ESTAT_LATECOL (1<<4)
#define ENC_ESTAT_BUFFER (1<<6)
#define ENC_ESTAT_INT (1<<7)
#define ENC_ESTAT_BANK ANY_BANK
#define ENC_EIR 0x1C
#define ENC_EIR_RXERIF (1<<0)
#define ENC_EIR_TXERIF (1<<1)
#define ENC_EIR_TXIF (1<<3)
#define ENC_EIR_LINKIF (1<<4)
#define ENC_EIR_DMAIF (1<<5)
#define ENC_EIR_PKTIF (1<<6)
#define ENC_EIR_BANK ANY_BANK
#define ENC_EIE 0x1B
#define ENC_EIE_RXERIE (1<<0)
#define ENC_EIE_TXERIE (1<<1)
#define ENC_EIE_TXIE (1<<3)
#define ENC_EIE_LINKIE (1<<4)
#define ENC_EIE_DMAIE (1<<5)
#define ENC_EIE_PKTIE (1<<6)
#define ENC_EIE_INTIE (1<<7)
#define ENC_EIE_BANK ANY_BANK
/* PHY Registers */
#define ENC_PHSTAT1 0x01
#define ENC_PHSTAT2 0x11
#define ENC_PHSTAT2_DPXSTAT (1<<9)
#define ENC_PHCON1 0x00
#define ENC_PHCON_PDPXMD (1<<8)
/* ENC28J60 Transmit Status Vector */
#define TSV_TXBYTECNT 0
#define TSV_TXCOLLISIONCNT 16
#define TSV_TXCRCERROR 20
#define TSV_TXLENCHKERROR 21
#define TSV_TXLENOUTOFRANGE 22
#define TSV_TXDONE 23
#define TSV_TXMULTICAST 24
#define TSV_TXBROADCAST 25
#define TSV_TXPACKETDEFER 26
#define TSV_TXEXDEFER 27
#define TSV_TXEXCOLLISION 28
#define TSV_TXLATECOLLISION 29
#define TSV_TXGIANT 30
#define TSV_TXUNDERRUN 31
#define TSV_TOTBYTETXONWIRE 32
#define TSV_TXCONTROLFRAME 48
#define TSV_TXPAUSEFRAME 49
#define TSV_BACKPRESSUREAPP 50
#define TSV_TXVLANTAGFRAME 51
#define TSV_SIZE 7
#define TSV_BYTEOF(x) ((x) / 8)
#define TSV_BITMASK(x) (1 << ((x) % 8))
#define TSV_GETBIT(x, y) (((x)[TSV_BYTEOF(y)] & TSV_BITMASK(y)) ? 1 : 0)
#endif
inc/gpio.h 0 → 100644
View file @ 45999dcd
/** \file gpio.h
* \brief Header for gpio.c
* \details Header for gpio.c
* \author Freddie Chopin, http://www.freddiechopin.info/
* \date 2012-04-07
*/
/******************************************************************************
* chip: LPC175x / LPC176x
* compiler: arm-none-eabi-gcc (GNU Tools for ARM Embedded Processors) 4.6.2
* 20110921 (release) [ARM/embedded-4_6-branch revision 182083]
******************************************************************************/
#ifndef GPIO_H_
#define GPIO_H_
#include "inc/LPC17xx.h"
#include "hdr/hdr_pincon.h"
#include "hdr/hdr_gpio.h"
/*
+=============================================================================+
| global definitions
+=============================================================================+
*/
#define GPIO_COMBINE(sel, mode, mode_od, dir) ((sel) | ((mode) << 8) | ((mode_od) << 16) | ((dir) << 24))
// all possible configurations of GPIO
// input configurations
#define GPIO_IN_PULL_UP GPIO_COMBINE(LPC_PINCON_PINSELx_DEFAULT_value, LPC_PINCON_PINMODEx_PULL_UP_value, 0, LPC_GPIO_FIODIR_IN_value)
#define GPIO_IN_REPEATER GPIO_COMBINE(LPC_PINCON_PINSELx_DEFAULT_value, LPC_PINCON_PINMODEx_REPEATER_value, 0, LPC_GPIO_FIODIR_IN_value)
#define GPIO_IN_FLOATING GPIO_COMBINE(LPC_PINCON_PINSELx_DEFAULT_value, LPC_PINCON_PINMODEx_FLOATING_value, 0, LPC_GPIO_FIODIR_IN_value)
#define GPIO_IN_PULL_DOWN GPIO_COMBINE(LPC_PINCON_PINSELx_DEFAULT_value, LPC_PINCON_PINMODEx_PULL_DOWN_value, 0, LPC_GPIO_FIODIR_IN_value)
// output configurations
#define GPIO_OUT_PP GPIO_COMBINE(LPC_PINCON_PINSELx_DEFAULT_value, 0, LPC_PINCON_PINMODE_ODx_PP_value, LPC_GPIO_FIODIR_OUT_value)
#define GPIO_OUT_OD GPIO_COMBINE(LPC_PINCON_PINSELx_DEFAULT_value, LPC_PINCON_PINMODEx_FLOATING_value, LPC_PINCON_PINMODE_ODx_OD_value, LPC_GPIO_FIODIR_OUT_value)
#define GPIO_OUT_OD_PULL_UP GPIO_COMBINE(LPC_PINCON_PINSELx_DEFAULT_value, LPC_PINCON_PINMODEx_PULL_UP_value, LPC_PINCON_PINMODE_ODx_OD_value, LPC_GPIO_FIODIR_OUT_value)
#define GPIO_OUT_OD_REPEATER GPIO_COMBINE(LPC_PINCON_PINSELx_DEFAULT_value, LPC_PINCON_PINMODEx_REPEATER_value, LPC_PINCON_PINMODE_ODx_OD_value, LPC_GPIO_FIODIR_OUT_value)
#define GPIO_OUT_OD_PULL_DOWN GPIO_COMBINE(LPC_PINCON_PINSELx_DEFAULT_value, LPC_PINCON_PINMODEx_PULL_DOWN_value, LPC_PINCON_PINMODE_ODx_OD_value, LPC_GPIO_FIODIR_OUT_value)
// alternate function configurations
#define GPIO_ALT1_PP_PULL_UP GPIO_COMBINE(LPC_PINCON_PINSELx_ALT1_value, LPC_PINCON_PINMODEx_PULL_UP_value, LPC_PINCON_PINMODE_ODx_PP_value, 0)
#define GPIO_ALT1_PP_REPEATER GPIO_COMBINE(LPC_PINCON_PINSELx_ALT1_value, LPC_PINCON_PINMODEx_REPEATER_value, LPC_PINCON_PINMODE_ODx_PP_value, 0)
#define GPIO_ALT1_PP_FLOATING GPIO_COMBINE(LPC_PINCON_PINSELx_ALT1_value, LPC_PINCON_PINMODEx_FLOATING_value, LPC_PINCON_PINMODE_ODx_PP_value, 0)
#define GPIO_ALT1_PP_PULL_DOWN GPIO_COMBINE(LPC_PINCON_PINSELx_ALT1_value, LPC_PINCON_PINMODEx_PULL_DOWN_value, LPC_PINCON_PINMODE_ODx_PP_value, 0)
#define GPIO_ALT1_OD_PULL_UP GPIO_COMBINE(LPC_PINCON_PINSELx_ALT1_value, LPC_PINCON_PINMODEx_PULL_UP_value, LPC_PINCON_PINMODE_ODx_OD_value, 0)
#define GPIO_ALT1_OD_REPEATER GPIO_COMBINE(LPC_PINCON_PINSELx_ALT1_value, LPC_PINCON_PINMODEx_REPEATER_value, LPC_PINCON_PINMODE_ODx_OD_value, 0)
#define GPIO_ALT1_OD_FLOATING GPIO_COMBINE(LPC_PINCON_PINSELx_ALT1_value, LPC_PINCON_PINMODEx_FLOATING_value, LPC_PINCON_PINMODE_ODx_OD_value, 0)
#define GPIO_ALT1_OD_PULL_DOWN GPIO_COMBINE(LPC_PINCON_PINSELx_ALT1_value, LPC_PINCON_PINMODEx_PULL_DOWN_value, LPC_PINCON_PINMODE_ODx_OD_value, 0)
#define GPIO_ALT2_PP_PULL_UP GPIO_COMBINE(LPC_PINCON_PINSELx_ALT2_value, LPC_PINCON_PINMODEx_PULL_UP_value, LPC_PINCON_PINMODE_ODx_PP_value, 0)
#define GPIO_ALT2_PP_REPEATER GPIO_COMBINE(LPC_PINCON_PINSELx_ALT2_value, LPC_PINCON_PINMODEx_REPEATER_value, LPC_PINCON_PINMODE_ODx_PP_value, 0)
#define GPIO_ALT2_PP_FLOATING GPIO_COMBINE(LPC_PINCON_PINSELx_ALT2_value, LPC_PINCON_PINMODEx_FLOATING_value, LPC_PINCON_PINMODE_ODx_PP_value, 0)
#define GPIO_ALT2_PP_PULL_DOWN GPIO_COMBINE(LPC_PINCON_PINSELx_ALT2_value, LPC_PINCON_PINMODEx_PULL_DOWN_value, LPC_PINCON_PINMODE_ODx_PP_value, 0)
#define GPIO_ALT2_OD_PULL_UP GPIO_COMBINE(LPC_PINCON_PINSELx_ALT2_value, LPC_PINCON_PINMODEx_PULL_UP_value, LPC_PINCON_PINMODE_ODx_OD_value, 0)
#define GPIO_ALT2_OD_REPEATER GPIO_COMBINE(LPC_PINCON_PINSELx_ALT2_value, LPC_PINCON_PINMODEx_REPEATER_value, LPC_PINCON_PINMODE_ODx_OD_value, 0)
#define GPIO_ALT2_OD_FLOATING GPIO_COMBINE(LPC_PINCON_PINSELx_ALT2_value, LPC_PINCON_PINMODEx_FLOATING_value, LPC_PINCON_PINMODE_ODx_OD_value, 0)
#define GPIO_ALT2_OD_PULL_DOWN GPIO_COMBINE(LPC_PINCON_PINSELx_ALT2_value, LPC_PINCON_PINMODEx_PULL_DOWN_value, LPC_PINCON_PINMODE_ODx_OD_value, 0)
#define GPIO_ALT3_PP_PULL_UP GPIO_COMBINE(LPC_PINCON_PINSELx_ALT3_value, LPC_PINCON_PINMODEx_PULL_UP_value, LPC_PINCON_PINMODE_ODx_PP_value, 0)
#define GPIO_ALT3_PP_REPEATER GPIO_COMBINE(LPC_PINCON_PINSELx_ALT3_value, LPC_PINCON_PINMODEx_REPEATER_value, LPC_PINCON_PINMODE_ODx_PP_value, 0)
#define GPIO_ALT3_PP_FLOATING GPIO_COMBINE(LPC_PINCON_PINSELx_ALT3_value, LPC_PINCON_PINMODEx_FLOATING_value, LPC_PINCON_PINMODE_ODx_PP_value, 0)
#define GPIO_ALT3_PP_PULL_DOWN GPIO_COMBINE(LPC_PINCON_PINSELx_ALT3_value, LPC_PINCON_PINMODEx_PULL_DOWN_value, LPC_PINCON_PINMODE_ODx_PP_value, 0)
#define GPIO_ALT3_OD_PULL_UP GPIO_COMBINE(LPC_PINCON_PINSELx_ALT3_value, LPC_PINCON_PINMODEx_PULL_UP_value, LPC_PINCON_PINMODE_ODx_OD_value, 0)
#define GPIO_ALT3_OD_REPEATER GPIO_COMBINE(LPC_PINCON_PINSELx_ALT3_value, LPC_PINCON_PINMODEx_REPEATER_value, LPC_PINCON_PINMODE_ODx_OD_value, 0)
#define GPIO_ALT3_OD_FLOATING GPIO_COMBINE(LPC_PINCON_PINSELx_ALT3_value, LPC_PINCON_PINMODEx_FLOATING_value, LPC_PINCON_PINMODE_ODx_OD_value, 0)
#define GPIO_ALT3_OD_PULL_DOWN GPIO_COMBINE(LPC_PINCON_PINSELx_ALT3_value, LPC_PINCON_PINMODEx_PULL_DOWN_value, LPC_PINCON_PINMODE_ODx_OD_value, 0)
/*
+=============================================================================+
| strange variables
+=============================================================================+
*/
/*
+=============================================================================+
| global variables
+=============================================================================+
*/
/*
+=============================================================================+
| global functions' declarations
+=============================================================================+
*/
void gpio_pin_cfg(LPC_GPIO_TypeDef *gpio_ptr, uint32_t pin, uint32_t configuration);
/******************************************************************************
* END OF FILE
******************************************************************************/
#endif /* GPIO_H_ */
inc/httpd.h 0 → 100644
View file @ 45999dcd
/* Copyright (C) 2013 Upi Tamminen
* See the COPYRIGHT file for more information */
#ifndef __HTTPD_H__
#define __HTTPD_H__
void httpd_init(void);
#endif
inc/i2c.h 0 → 100644
View file @ 45999dcd
/*****************************************************************************
* i2c.h: Header file for NXP LPC11xx Family Microprocessors
*
* Copyright(C) 2006, NXP Semiconductor
* parts of this code are (C) 2010, MyVoice CAD/CAM Services
* All rights reserved.
*
* History
* 2006.07.19 ver 1.00 Preliminary version, first Release
* 2010.07.19 ver 1.10 Rob Jansen - MyVoice CAD/CAM Services
* Updated to reflect new code
* 2011.03.07 ver 1.210 Larry Viesse - Corrected Buffer Sizes to accommodate writing 32 data bytes (a full page)
*
******************************************************************************/
#ifndef __I2C_H
#define __I2C_H
// #include "type.h"
/*
* These are states returned by the I2CEngine:
*
* IDLE - is never returned but only used internally
* PENDING - is never returned but only used internally in the I2C functions
* ACK - The transaction finished and the slave returned ACK (on all bytes)
* NACK - The transaction is aborted since the slave returned a NACK
* SLA_NACK - The transaction is aborted since the slave returned a NACK on the SLA
* this can be intentional (e.g. an 24LC08 EEPROM states it is busy)
* or the slave is not available/accessible at all.
* ARB_LOSS - Arbitration loss during any part of the transaction.
* This could only happen in a multi master system or could also
* identify a hardware problem in the system.
*/
#define I2CSTATE_IDLE 0x000
#define I2CSTATE_PENDING 0x001
#define I2CSTATE_ACK 0x101
#define I2CSTATE_NACK 0x102
#define I2CSTATE_SLA_NACK 0x103
#define I2CSTATE_ARB_LOSS 0x104
#define FAST_MODE_PLUS 0
#define Master_Buffer_BUFSIZE 35
#define Slave_Buffer_BUFSIZE 32
#define MAX_TIMEOUT 0x00FFFFFF
#define I2CMASTER 0x01
#define I2CSLAVE 0x02
#define PCF8594_ADDR 0xA0
#define READ_WRITE 0x01
#define RD_BIT 0x01
#define I2CONSET_I2EN 0x00000040 /* I2C Control Set Register */
#define I2CONSET_AA 0x00000004
#define I2CONSET_SI 0x00000008
#define I2CONSET_STO 0x00000010
#define I2CONSET_STA 0x00000020
#define I2CONCLR_AAC 0x00000004 /* I2C Control clear Register */
#define I2CONCLR_SIC 0x00000008
#define I2CONCLR_STAC 0x00000020
#define I2CONCLR_I2ENC 0x00000040
#define I2DAT_I2C 0x00000000 /* I2C Data Reg */
#define I2ADR_I2C 0x00000000 /* I2C Slave Address Reg */
#define I2SCLH_SCLH 58 /* I2C SCL Duty Cycle High Reg */
#define I2SCLL_SCLL 57 /* I2C SCL Duty Cycle Low Reg */
#define I2SCLH_HS_SCLH 0x00000020 /* Fast Plus I2C SCL Duty Cycle High Reg */
#define I2SCLL_HS_SCLL 0x00000020 /* Fast Plus I2C SCL Duty Cycle Low Reg */
extern volatile uint8_t I2CMasterBuffer[Master_Buffer_BUFSIZE];
extern volatile uint8_t I2CSlaveBuffer[Slave_Buffer_BUFSIZE];
extern volatile uint32_t I2CReadLength, I2CWriteLength;
extern uint32_t I2CInit( uint32_t I2cMode );
extern uint32_t I2CEngine( void );
void i2c_showbuffers(void);
void i2c_clearbuffers(void);
#endif /* end __I2C_H */
/* vim: set et sw=4: */
inc/led.h 0 → 100644
View file @ 45999dcd
/* Copyright (C) 2013 Upi Tamminen
* See the COPYRIGHT file for more information */
#ifndef __LED_H
#define __LED_H
inline void led_init(void);
inline void led_on(void);
inline void led_off(void);
inline void led_toggle(void);
#endif
/* vim: set sw=4 et: */
inc/lwipopts.h 0 → 100644
View file @ 45999dcd
/* Copyright (C) 2013 Upi Tamminen
* See the COPYRIGHT file for more information */
#ifndef __LWIP_LWIOPTS_H__
#define __LWIP_LWIOPTS_H__
#include <sys/time.h>
#include "tprintf.h"
//#define LWIP_HTTPD_CGI 1
//#define LWIP_HTTPD_SSI 1
#define LWIP_DEBUG 1
//#define IP_DEBUG LWIP_DBG_ON
//#define ETHARP_DEBUG LWIP_DBG_ON
//#define NETIF_DEBUG LWIP_DBG_ON
//#define ICMP_DEBUG LWIP_DBG_ON
#define HTTPD_DEBUG LWIP_DBG_ON
#define MEM_DEBUG LWIP_DBG_ON
//#define PBUF_DEBUG LWIP_DBG_ON
//#define LWIP_STATS 1
//#define MEM_STATS 1
//#define LWIP_STATS_DISPLAY 1
/* Align memory on 4 byte boundery (32-bit) */
#define MEM_ALIGNMENT 4
/* No operating system present */
#define NO_SYS 1
//#define SYS_LIGHTWEIGHT_PROT 1
//#define MEM_SIZE 1600
/* Time in milliseconds to perform ARP processing */
#define ETHARP_TMR_INTERVAL 5000
#define LWIP_TIMEVAL_PRIVATE 0
#define LWIP_SOCKET 0
#define LWIP_NETCONN 0
#define LWIP_ARP 1
//#define MEMP_NUM_PBUF 1
//#define MEMP_NUM_RAW_PCB 1
//#define MEMP_NUM_UDP_PCB 1
//#define MEMP_NUM_TCP_PCB 1
//#define MEMP_NUM_TCP_PCB_LISTEN 0
//#define MEMP_NUM_TCP_SEG 8
//#define MEMP_NUM_NETBUF 0
//#define MEMP_NUM_NETCONN 2
//#define MEMP_NUM_API_MSG 0
//#define MEMP_NUM_TCPIP_MSG 0
#define PBUF_POOL_SIZE 4
//#define PBUF_POOL_BUFSIZE 64
//#define ARP_TABLE_SIZE 2
//#define IP_REASS_BUFSIZE 600
#define TCP_WND 4000
//#define TCP_QUEUE_OOSEQ 0
#define TCP_MSS 1460
#endif /* __LWIP_LWIOPTS_H__ */
inc/spi.h 0 → 100644
View file @ 45999dcd
/* Copyright (C) 2013 Upi Tamminen
* See the COPYRIGHT file for more information */
#ifndef __SPI_H
#define __SPI_H
void spi_init(void);
uint16_t spi_write(uint16_t data);
uint16_t spi_read(uint16_t data);
#endif
/* vim: set sw=4 et: */
inc/system_LPC17xx.h 0 → 100644
View file @ 45999dcd
/**************************************************************************//**
* @file system_LPC17xx.h
* @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File
* for the NXP LPC17xx Device Series
* @version V1.02
* @date 08. September 2009
*
* @note
* Copyright (C) 2009 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __SYSTEM_LPC17xx_H
#define __SYSTEM_LPC17xx_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_LPC17xx_H */
inc/tprintf.h 0 → 100644
View file @ 45999dcd
#ifndef __TPRINTF_H
#define __TPRINTF_H
void tprintf(char *format, ...);
#endif
inc/tvp7002.h 0 → 100644
View file @ 45999dcd
/* Copyright (C) 2013 Upi Tamminen
* See the COPYRIGHT file for more information */
#ifndef __TVP7002_H
#define __TVP7002_H
#include "i2c.h"
#define TVP7002_ADDR 0xB8
uint32_t tvp7002_set(uint8_t addr, uint8_t val);
uint8_t tvp7002_get(uint8_t addr);
void tvp7002_init(void);
void tvp7002_info(void);
#endif
/* vim: set et sw=4: */
inc/tvp7002_reg.h 0 → 100644
View file @ 45999dcd
/* Texas Instruments Triple 8-/10-BIT 165-/110-MSPS Video and Graphics
* Digitizer with Horizontal PLL registers
*
* Copyright (C) 2009 Texas Instruments Inc
* Author: Santiago Nunez-Corrales <santiago.nunez@ridgerun.com>
*
* This code is partially based upon the TVP5150 driver
* written by Mauro Carvalho Chehab (mchehab@infradead.org),
* the TVP514x driver written by Vaibhav Hiremath <hvaibhav@ti.com>
* and the TVP7002 driver in the TI LSP 2.10.00.14
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
/* Naming conventions
* ------------------
*
* FDBK: Feedback
* DIV: Divider
* CTL: Control
* SEL: Select
* IN: Input
* OUT: Output
* R: Red
* G: Green
* B: Blue
* OFF: Offset
* THRS: Threshold
* DGTL: Digital
* LVL: Level
* PWR: Power
* MVIS: Macrovision
* W: Width
* H: Height
* ALGN: Alignment
* CLK: Clocks
* TOL: Tolerance
* BWTH: Bandwidth
* COEF: Coefficient
* STAT: Status
* AUTO: Automatic
* FLD: Field
* L: Line
*/
#define TVP7002_CHIP_REV 0x00
#define TVP7002_HPLL_FDBK_DIV_MSBS 0x01
#define TVP7002_HPLL_FDBK_DIV_LSBS 0x02
#define TVP7002_HPLL_CRTL 0x03
#define TVP7002_HPLL_PHASE_SEL 0x04
#define TVP7002_CLAMP_START 0x05
#define TVP7002_CLAMP_W 0x06
#define TVP7002_HSYNC_OUT_W 0x07
#define TVP7002_B_FINE_GAIN 0x08
#define TVP7002_G_FINE_GAIN 0x09
#define TVP7002_R_FINE_GAIN 0x0a
#define TVP7002_B_FINE_OFF_MSBS 0x0b
#define TVP7002_G_FINE_OFF_MSBS 0x0c
#define TVP7002_R_FINE_OFF_MSBS 0x0d
#define TVP7002_SYNC_CTL_1 0x0e
#define TVP7002_HPLL_AND_CLAMP_CTL 0x0f
#define TVP7002_SYNC_ON_G_THRS 0x10
#define TVP7002_SYNC_SEPARATOR_THRS 0x11
#define TVP7002_HPLL_PRE_COAST 0x12
#define TVP7002_HPLL_POST_COAST 0x13
#define TVP7002_SYNC_DETECT_STAT 0x14
#define TVP7002_OUT_FORMATTER 0x15
#define TVP7002_MISC_CTL_1 0x16
#define TVP7002_MISC_CTL_2 0x17
#define TVP7002_MISC_CTL_3 0x18
#define TVP7002_IN_MUX_SEL_1 0x19
#define TVP7002_IN_MUX_SEL_2 0x1a
#define TVP7002_B_AND_G_COARSE_GAIN 0x1b
#define TVP7002_R_COARSE_GAIN 0x1c
#define TVP7002_FINE_OFF_LSBS 0x1d
#define TVP7002_B_COARSE_OFF 0x1e
#define TVP7002_G_COARSE_OFF 0x1f
#define TVP7002_R_COARSE_OFF 0x20
#define TVP7002_HSOUT_OUT_START 0x21
#define TVP7002_MISC_CTL_4 0x22
#define TVP7002_B_DGTL_ALC_OUT_LSBS 0x23
#define TVP7002_G_DGTL_ALC_OUT_LSBS 0x24
#define TVP7002_R_DGTL_ALC_OUT_LSBS 0x25
#define TVP7002_AUTO_LVL_CTL_ENABLE 0x26
#define TVP7002_DGTL_ALC_OUT_MSBS 0x27
#define TVP7002_AUTO_LVL_CTL_FILTER 0x28
/* Reserved 0x29*/
#define TVP7002_FINE_CLAMP_CTL 0x2a
#define TVP7002_PWR_CTL 0x2b
#define TVP7002_ADC_SETUP 0x2c
#define TVP7002_COARSE_CLAMP_CTL 0x2d
#define TVP7002_SOG_CLAMP 0x2e
#define TVP7002_RGB_COARSE_CLAMP_CTL 0x2f
#define TVP7002_SOG_COARSE_CLAMP_CTL 0x30
#define TVP7002_ALC_PLACEMENT 0x31
/* Reserved 0x32 */
/* Reserved 0x33 */
#define TVP7002_MVIS_STRIPPER_W 0x34
#define TVP7002_VSYNC_ALGN 0x35
#define TVP7002_SYNC_BYPASS 0x36
#define TVP7002_L_FRAME_STAT_LSBS 0x37
#define TVP7002_L_FRAME_STAT_MSBS 0x38
#define TVP7002_CLK_L_STAT_LSBS 0x39
#define TVP7002_CLK_L_STAT_MSBS 0x3a
#define TVP7002_HSYNC_W 0x3b
#define TVP7002_VSYNC_W 0x3c
#define TVP7002_L_LENGTH_TOL 0x3d
/* Reserved 0x3e */
#define TVP7002_VIDEO_BWTH_CTL 0x3f
#define TVP7002_AVID_START_PIXEL_LSBS 0x40
#define TVP7002_AVID_START_PIXEL_MSBS 0x41
#define TVP7002_AVID_STOP_PIXEL_LSBS 0x42
#define TVP7002_AVID_STOP_PIXEL_MSBS 0x43
#define TVP7002_VBLK_F_0_START_L_OFF 0x44
#define TVP7002_VBLK_F_1_START_L_OFF 0x45
#define TVP7002_VBLK_F_0_DURATION 0x46
#define TVP7002_VBLK_F_1_DURATION 0x47
#define TVP7002_FBIT_F_0_START_L_OFF 0x48
#define TVP7002_FBIT_F_1_START_L_OFF 0x49
#define TVP7002_YUV_Y_G_COEF_LSBS 0x4a
#define TVP7002_YUV_Y_G_COEF_MSBS 0x4b
#define TVP7002_YUV_Y_B_COEF_LSBS 0x4c
#define TVP7002_YUV_Y_B_COEF_MSBS 0x4d
#define TVP7002_YUV_Y_R_COEF_LSBS 0x4e
#define TVP7002_YUV_Y_R_COEF_MSBS 0x4f
#define TVP7002_YUV_U_G_COEF_LSBS 0x50
#define TVP7002_YUV_U_G_COEF_MSBS 0x51
#define TVP7002_YUV_U_B_COEF_LSBS 0x52
#define TVP7002_YUV_U_B_COEF_MSBS 0x53
#define TVP7002_YUV_U_R_COEF_LSBS 0x54
#define TVP7002_YUV_U_R_COEF_MSBS 0x55
#define TVP7002_YUV_V_G_COEF_LSBS 0x56
#define TVP7002_YUV_V_G_COEF_MSBS 0x57
#define TVP7002_YUV_V_B_COEF_LSBS 0x58
#define TVP7002_YUV_V_B_COEF_MSBS 0x59
#define TVP7002_YUV_V_R_COEF_LSBS 0x5a
#define TVP7002_YUV_V_R_COEF_MSBS 0x5b
inc/uart0.h 0 → 100644
View file @ 45999dcd
//*****************************************************************************
// +--+
// | ++----+
// +-++ |
// | |
// +-+--+ |
// | +--+--+
// +----+ Copyright (c) 2009 Code Red Technologies Ltd.
//
// UART example header file
//
// Software License Agreement
//
// The software is owned by Code Red Technologies and/or its suppliers, and is
// protected under applicable copyright laws. All rights are reserved. Any
// use in violation of the foregoing restrictions may subject the user to criminal
// sanctions under applicable laws, as well as to civil liability for the breach
// of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// USE OF THIS SOFTWARE FOR COMMERCIAL DEVELOPMENT AND/OR EDUCATION IS SUBJECT
// TO A CURRENT END USER LICENSE AGREEMENT (COMMERCIAL OR EDUCATIONAL) WITH
// CODE RED TECHNOLOGIES LTD.
//
//*****************************************************************************
#ifndef UART0_H_
#define UART0_H_
#include "inc/LPC17xx.h"
// ***********************
// Function to set up UART
void UART0_Init(int baudrate);
// ***********************
// Function to send character over UART
void UART0_Sendchar(char c);
// ***********************
// Function to get character from UART
char UART0_Getchar(void);
// ***********************
// Function to prints the string out over the UART
void UART0_PrintString(char *pcString);
void uprintf(char *fmt, ...);
#endif /*UART0_H_*/
inc/utils.h 0 → 100644
View file @ 45999dcd
/* Copyright (C) 2013 Upi Tamminen
* See the COPYRIGHT file for more information */
#ifndef __UTILS_H
#define __UTILS_H
__INLINE void delay_ms(uint32_t dlyTicks);
uint16_t hex2int(char *a, uint16_t len);
void split_args(char *buf, char *p1, char *p2);
#endif
/* vim: set sw=4 et: */
src/cpld.c 0 → 100644
View file @ 45999dcd
/* Copyright (C) 2013 Upi Tamminen
* See the COPYRIGHT file for more information */
#include "inc/LPC17xx.h"
#include "tprintf.h"
#include "utils.h"
extern uint8_t dmabuf[2048];
/* instruct the cpld to capture an image from tvp7002 to sram */
void cpld_capture(void)
{
tprintf("Saving...");
LPC_GPIO0->FIOSET |= (1<<16);
delay_ms(100);
LPC_GPIO0->FIOCLR |= (1<<16);
delay_ms(100);
tprintf(" done.\r\n");
}
/* transfer some data from sram via cpld */
void cpld_xfr(void)
{
uint16_t i;
LPC_GPIO0->FIOSET |= (1<<15);
for (i = 0; i < 2048; i ++) {
while (!(LPC_GPIO0->FIOPIN & (1<<17)));
dmabuf[i] = (uint8_t) LPC_GPIO2->FIOPIN;
while ((LPC_GPIO0->FIOPIN & (1<<17)));
}
LPC_GPIO0->FIOCLR |= (1<<15);
}
/* vim: set et sw=4: */
src/cpu.c 0 → 100644
View file @ 45999dcd
/* Based on the sample lpc1769 project by Freddie Chopin
* http://www.freddiechopin.info/ */
#include <stdint.h>
#include "inc/LPC17xx.h"
#include "config.h"
#include "hdr/hdr_sc.h"
#include "gpio.h"
void flash_latency(uint32_t frequency)
{
uint32_t wait_states;
wait_states = frequency / 20000000; // 1 CLK per 20MHz
if (wait_states > 5) // 5 CLKs is the highest reasonable value, works for up to 120MHz
wait_states = 5;
LPC_SC->FLASHCFG = ((wait_states - 1) << LPC_SC_FLASHCFG_FLASHTIM_bit) | LPC_SC_FLASHCFG_RESERVED_value; // set the latency
}
void pll0_feed(void)
{
LPC_SC->PLL0FEED = LPC_SC_PLL0FEED_FIRST;
LPC_SC->PLL0FEED = LPC_SC_PLL0FEED_SECOND;
}
uint32_t pll0_start(uint32_t crystal, uint32_t frequency)
{
uint32_t prediv, mul, corediv, fcco, core_frequency;
uint32_t best_prediv = 0, best_mul = 0, best_corediv = 0, best_core_frequency = 0;
if (crystal > 20000000) // change OSCRANGE for crystals over 20MHz
LPC_SC_SCS_OSCRANGE_bb = 1;
LPC_SC_SCS_OSCEN_bb = 1; // enable main oscillator
flash_latency(frequency); // set flash latency
while (LPC_SC_SCS_OSCSTAT_bb == 0); // wait for main oscillator to start up
LPC_SC->CLKSRCSEL = LPC_SC_CLKSRCSEL_CLKSRC_MAIN; // set main oscillator as PLL0 clocksource
for (prediv = 1; prediv <= 32; prediv++) // NSEL0 in [1; 32]
for (mul = 6; mul <= 512; mul++) // MSEL0 in [5; 512]
{
fcco = 2 * mul * crystal / prediv; // calculate PLL output frequency
if ((fcco < 275000000) || (fcco > 550000000)) // skip invalid settings - fcco must be in [275M; 550M]
continue;
for (corediv = 1; corediv <= 256; corediv++) // CCLKSEL in [1; 256]
{
core_frequency = fcco / corediv; // calculate core frequency
if (core_frequency > frequency) // skip frequencies above desired value
continue;
if (core_frequency > best_core_frequency) // is this configuration better than previous one?
{
best_core_frequency = core_frequency; // yes - save values
best_prediv = prediv;
best_mul = mul;
best_corediv = corediv;
if (core_frequency == frequency) // is this configuration "perfect"?
break; // yes - skip further search
}
}
}
LPC_SC->PLL0CFG = ((best_prediv - 1) << LPC_SC_PLL0CFG_NSEL0_bit) | ((best_mul - 1) << LPC_SC_PLL0CFG_MSEL0_bit); // set NSEL0 and MSEL0
pll0_feed(); // validate change in PLL0CFG
LPC_SC_PLL0CON_PLLE0_bb = 1; // enable PLL0
pll0_feed(); // validate change in PLL0CON
LPC_SC->CCLKCFG = (best_corediv - 1) << LPC_SC_CCLKCFG_CCLKSEL_bit; // set core clock divider CCLKSEL
while (LPC_SC_PLL0STAT_PLOCK0_bb == 0); // wait for PLL0 lock
LPC_SC_PLL0CON_PLLC0_bb = 1; // connect PLL0 as clock source
pll0_feed(); // validate connection
return best_core_frequency;
}
void system_init(void)
{
LPC_SC->PCLKSEL0 = LPC_SC_PCLKSEL0_PCLK_WDT_DIV1 |LPC_SC_PCLKSEL0_PCLK_TIMER0_DIV1 |
LPC_SC_PCLKSEL0_PCLK_TIMER1_DIV1 | LPC_SC_PCLKSEL0_PCLK_UART0_DIV1 |
LPC_SC_PCLKSEL0_PCLK_UART1_DIV1 | LPC_SC_PCLKSEL0_PCLK_PWM1_DIV1 |
LPC_SC_PCLKSEL0_PCLK_I2C0_DIV1 | LPC_SC_PCLKSEL0_PCLK_SPI_DIV1 |
LPC_SC_PCLKSEL0_PCLK_SSP1_DIV1 | LPC_SC_PCLKSEL0_PCLK_DAC_DIV1 |
LPC_SC_PCLKSEL0_PCLK_ADC_DIV1 | LPC_SC_PCLKSEL0_PCLK_CAN1_DIV1 |
LPC_SC_PCLKSEL0_PCLK_CAN2_DIV1 | LPC_SC_PCLKSEL0_PCLK_ACF_DIV1;
LPC_SC->PCLKSEL1 = LPC_SC_PCLKSEL1_PCLK_QEI_DIV1 | LPC_SC_PCLKSEL1_PCLK_GPIOINT_DIV1 |
LPC_SC_PCLKSEL1_PCLK_PCB_DIV1 | LPC_SC_PCLKSEL1_PCLK_I2C1_DIV1 |
LPC_SC_PCLKSEL1_PCLK_SSP0_DIV1 | LPC_SC_PCLKSEL1_PCLK_TIMER2_DIV1 |
LPC_SC_PCLKSEL1_PCLK_TIMER3_DIV1 | LPC_SC_PCLKSEL1_PCLK_UART2_DIV1 |
LPC_SC_PCLKSEL1_PCLK_UART3_DIV1 | LPC_SC_PCLKSEL1_PCLK_I2C2_DIV1 |
LPC_SC_PCLKSEL1_PCLK_I2S_DIV1 | LPC_SC_PCLKSEL1_PCLK_RIT_DIV1 |
LPC_SC_PCLKSEL1_PCLK_SYSCON_DIV1 | LPC_SC_PCLKSEL1_PCLK_MC_DIV1;
}
src/dma.c 0 → 100644
View file @ 45999dcd
/* Copyright (C) 2013 Upi Tamminen
* See the COPYRIGHT file for more information
*
* This code is not used at the moment, but keep it around anyway */
#include <stdint.h>
#include "inc/LPC17xx.h"
#include "config.h"
#include "hdr/hdr_sc.h"
#include "tprintf.h"
#include "spi.h"
void dma_init(uint8_t *buf, uint16_t len)
{
LPC_SC->PCONP |= (1 << 29); // power up gpdma
LPC_PINCON->PINSEL4 &= ~0x7fff; // P2.0->P2.7 GPIO
LPC_GPIO2->FIODIR &= ~0xff; // P2.0->P2.7 input
LPC_GPDMACH0->DMACCConfig = 0; // stop ch0 dma
LPC_GPDMA->DMACConfig |= 1 << 0; // (table 557, pg 599)
LPC_GPDMA->DMACSync &= ~(1 << 10); // use MAT1.0 for Sync
// Timer1 Match Compare 0 as DMA request (table 558, pg 599)
LPC_SC->DMAREQSEL |= 1 << 2;
LPC_GPDMA->DMACIntErrClr |= 0xff; // (table 549, pg 596)
LPC_GPDMA->DMACIntTCClear |= 0xff; // (table 547, pg 595);
//LPC_GPDMACH0->DMACCDestAddr = (uint32_t) &dstdata[0];
LPC_GPDMACH0->DMACCDestAddr = (uint32_t) &buf[0];
//LPC_GPDMACH0->DMACCSrcAddr = (uint32_t) &srcdata[0];
LPC_GPDMACH0->DMACCSrcAddr = (uint32_t) &(LPC_GPIO2->FIOPIN);
// we are not using the linked list (table 562, pg 602)
LPC_GPDMACH0->DMACCLLI = 0;
LPC_GPDMACH0->DMACCControl = (len & 0xfff)
| (0 << 12) // source burst size (12 - 14) = 1
| (0 << 15) // destination burst size (15 - 17) = 1
| (0 << 18) // source width (18 - 20) = 8 bit
| (0 << 21) // destination width (21 - 23) = 8 bit
| (0 << 24) // source AHB select (24) = AHB 0
| (0 << 25) // destination AHB select (25) = AHB 0
| (0 << 26) // source increment (26) = no increment
| (1 << 27) // destination increment (27) = increment
| (0 << 28) // mode select (28) = access in user mode
| (0 << 29) // (29) = access not bufferable
| (0 << 30) // (30) = access not cacheable
| (1 << 31); // terminal count interrupt enabled
// 10 corresponds to MAT1.0 and it is selected as the source request
// peripheral (table 543, pg 592)
LPC_GPDMACH0->DMACCConfig = 1 // enable ch0
| (10 << 1) // source peripheral (1 - 5) = MAT1.0
| (0 << 6) // destination request peripheral (6 - 10) = none
| (2 << 11) // flow control (11 - 13) = per to mem
| (0 << 14) // (14) = mask out error interrupt
| (1 << 15) // (15) = mask out terminal count interrupt
| (0 << 16) // (16) = no locked transfers
| (0 << 18); // (27) = no HALT
}
void dma_start(uint8_t *buf, uint16_t len)
{
LPC_GPIO1->FIODIR &= ~(1 << 18); // 1.18 = input
LPC_PINCON->PINSEL3 |= (3 << 4); // 1.18 = CAP1.0
// setup timer1
LPC_SC->PCONP |= 1 << 2; // Power up
LPC_SC->PCLKSEL0 |= 0x01 << 4; // CCLK
LPC_TIM1->TCR = 0x00; // stop the timer
LPC_TIM1->MR0 = 1;
LPC_TIM1->MCR = 1 << 1; // reset on MR0
LPC_TIM1->IR |= 0xff; // Clear all timer interrupts if there are any
LPC_TIM1->TCR |=
(1 << 0) // counter enable
| (1 << 1); // counter reset
/* Counter Mode: TC is incremented on rising edges on the CAP
* input selected by bits 3:2. */
LPC_TIM1->CTCR |= (1 << 0);
LPC_TIM1->CTCR &= ~(3 << 2); // CAP1.0 for TIMER1
LPC_TIM1->CCR = 0; // capture on the rising edges on CAP1.0
dma_init(buf, len);
LPC_TIM1->TCR = 0x01; // start timer.
}
void dma_test_data(uint8_t *buf)
{
uint16_t d = 0;
uint16_t s = 0;
uint16_t fail = 0;
uint16_t success = 0;
uint32_t i;
for (i = 0; i < 2048; i ++) {
if (buf[i] != '\xaa') {
fail ++;
} else {
success ++;
}
}
//tprintf("d [%d] s [%d] fail [%d]\r\n", d, s, fail);
tprintf("success [%d] fail [%d]\r\n", success, fail);
}
void dma_test(uint8_t *buf)
{
uint16_t i;
for (i = 0; i < 2048; i ++) buf[i] = 'd';
dma_start(buf, 2048);
//spi_write(CMD_FOO);
while (!(LPC_GPDMA->DMACIntTCStat & 0x01));
dma_test_data(buf);
}
void dma_transfer(uint8_t *buf)
{
dma_start(buf, 2048);
//spi_write(CMD_FOO);
while (!(LPC_GPDMA->DMACIntTCStat & 0x01));
}
void dma_showdebug(void)
{
tprintf("LPC_TIM1->TC [%d]\r\n", LPC_TIM1->TC);
tprintf("LPC_GPDMACH0->DMACIntTCStat [%d]\r\n",
(LPC_GPDMA->DMACIntTCStat & 0x01));
}
/* vim: set sw=4 et: */
src/enc28j60.c 0 → 100644
View file @ 45999dcd
/* Copyright (C) 2013 Upi Tamminen
* See the COPYRIGHT file for more information */
#include <stdint.h>
#include "inc/LPC17xx.h"
#include "config.h"
#include "hdr/hdr_sc.h"
#include "utils.h"
#include "tprintf.h"
#include "spi.h"
#include "enc28j60.h"
#include "enc28j60reg.h"
#define TX_START (0x1FFF - 0x600)
#define RX_END (TX_START-1)
static uint8_t enc_current_bank;
static uint16_t enc_next_packet;
uint8_t enc_read(uint8_t data);
void enc_switch_bank(uint8_t new_bank);
void enc_wcr(uint8_t reg, uint8_t val);
void enc_reset(void);
uint8_t enc_read_reg(uint8_t reg, uint8_t bank);
/* Macros for accessing registers.
* These macros should be used instead of calling the functions directly.
* They simply pass the register's bank as an argument, so the caller
* doesn't have to deal with that.
*/
#define READ_REG(reg) enc_read_reg(reg, reg ## _BANK)
#define WRITE_REG(reg, value) enc_write_reg(reg, reg ## _BANK, value)
#define READ_MREG(reg) enc_read_mreg(reg, reg ## _BANK)
#define SET_REG_BITS(reg, mask) enc_set_bits(reg, reg ## _BANK, mask)
#define CLEAR_REG_BITS(reg, mask) enc_clear_bits(reg, reg ## _BANK, mask)
__INLINE void wait(void)
{
volatile uint32_t i;
/* tested at 100mhz using argument of 1 */
for (i = 0; i < 98; i ++);
}
__INLINE void delay_ssel(void)
{
volatile int i;
for (i = 0; i < 250; i ++); // if in doubt, increase me
}
__INLINE void ssel_enable(void)
{
//delay_ssel();
LPC_GPIO0->FIOCLR |= (1<<28);
//delay_ssel();
}
__INLINE void ssel_disable(void)
{
delay_ssel();
LPC_GPIO0->FIOSET |= (1<<28);
//delay_ssel();
}
uint8_t enc_write(uint8_t data)
{
uint8_t val;
ssel_enable();
val = spi_write(data);
ssel_disable();
return val;
}
void enc_reset(void)
{
LPC_GPIO0->FIOCLR |= (1<<7);
delay_ms(50);
LPC_GPIO0->FIOSET |= (1<<7);
delay_ms(50);
enc_write(0xff);
delay_ms(50);
}
/**
* Read Control Register (RCR)
*/
uint8_t enc_rcr(uint8_t reg)
{
uint8_t val;
ssel_enable();
spi_write(reg);
val = spi_write(0xFF);
ssel_disable();
return val;
}
/*
* Write control register
*/
void enc_wcr(uint8_t reg, uint8_t val)
{
ssel_enable();
spi_write(0x40 | reg);
spi_write(val);
ssel_disable();
}
/**
* Read Control Register for MAC an MII registers.
* Reading MAC and MII registers produces an initial dummy
* byte. Presumably because it takes longer to fetch the values
* of those registers.
*/
uint8_t enc_rcr_m(uint8_t reg)
{
uint8_t val;
ssel_enable();
spi_write(reg);
spi_write(0xFF);
val = spi_write(0xFF); // Dummy
ssel_disable();
return val;
}
/**
* Read Buffer Memory.
*/
void enc_rbm(uint8_t *buf, uint16_t count) {
int i;
ssel_enable();
spi_write(0x20 | 0x1A);
for (i = 0; i < count; i++) {
*buf = spi_write(0xFF);
buf++;
}
ssel_disable();
}
/**
* Write Buffer Memory.
*/
void enc_wbm(const uint8_t *buf, uint16_t count) {
int i;
ssel_enable();
spi_write(0x60 | 0x1A);
for (i = 0; i < count; i++) {
spi_write(*buf);
buf++;
}
ssel_disable();
}
/**
* Bit Field Set.
* Set the bits of argument 'mask' in the register 'reg'.
* Not valid for MAC and MII registers.
*/
void enc_bfs(uint8_t reg, uint8_t mask) {
ssel_enable();
spi_write(0x80 | reg);
spi_write(mask);
ssel_disable();
}
/**
* Bit Field Clear.
* Clear the bits of argument 'mask' in the register 'reg'.
* Not valid for MAC and MII registers.
*/
void enc_bfc(uint8_t reg, uint8_t mask) {
ssel_enable();
spi_write(0xA0 | reg);
spi_write(mask);
ssel_disable();
}
void enc_switch_bank(uint8_t new_bank)
{
uint8_t econ1;
if (new_bank == enc_current_bank || new_bank == ANY_BANK) {
return;
}
econ1 = enc_rcr(ENC_ECON1);
econ1 &= ~ENC_ECON1_BSEL_MASK;
econ1 |= (new_bank & ENC_ECON1_BSEL_MASK) << ENC_ECON1_BSEL_SHIFT;
enc_wcr(ENC_ECON1, econ1);
enc_current_bank = new_bank;
}
/**
* High level register read. Switches bank as appropriate.
*/
uint8_t enc_read_reg(uint8_t reg, uint8_t bank)
{
if (bank != enc_current_bank) {
enc_switch_bank(bank);
}
return enc_rcr(reg);
}
/**
* High level bit field set. Switches bank as appropriate.
*/
void enc_set_bits(uint8_t reg, uint8_t bank, uint8_t mask)
{
if (bank != enc_current_bank) {
enc_switch_bank(bank);
}
enc_bfs(reg, mask);
}
/**
* High level bit field clear. Switches bank as appropriate.
*/
void enc_clear_bits(uint8_t reg, uint8_t bank, uint8_t mask)
{
if (bank != enc_current_bank) {
enc_switch_bank(bank);
}
enc_bfc(reg, mask);
}
/**
* High level MAC/MII register read. Switches bank as appropriate.
*/
uint8_t enc_read_mreg(uint8_t reg, uint8_t bank)
{
if (bank != enc_current_bank) {
enc_switch_bank(bank);
}
return enc_rcr_m(reg);
}
/**
* High level register write. Switches bank as appropriate.
*/
void enc_write_reg(uint8_t reg, uint8_t bank, uint8_t value)
{
if (bank != enc_current_bank) {
enc_switch_bank(bank);
}
enc_wcr(reg, value);
}
/**
* Read value from PHY address.
* Reading procedure is described in ENC28J60 datasheet
* section 3.3.
*/
uint16_t enc_phy_read(uint8_t addr)
{
uint8_t stat;
uint8_t ret;
/*
1. Write the address of the PHY register to read
from into the MIREGADR register.*/
WRITE_REG(ENC_MIREGADR, addr);
/*2. Set the MICMD.MIIRD bit. The read operation
begins and the MISTAT.BUSY bit is set.*/
WRITE_REG(ENC_MICMD, 0x1);
/*3. Wait 10.24 .s. Poll the MISTAT.BUSY bit to be
certain that the operation is complete. While
busy, the host controller should not start any
MIISCAN operations or write to the MIWRH
register.
When the MAC has obtained the register
contents, the BUSY bit will clear itself.*/
/* Assuming that we are running at 1MHz, a single cycle is
* 1 us */
//MAP_SysCtlDelay(((MAP_SysCtlClockGet()/3)/1000));
wait();
do {
stat = READ_MREG(ENC_MISTAT);
} while (stat & ENC_MISTAT_BUSY);
/*4. Clear the MICMD.MIIRD bit.*/
WRITE_REG(ENC_MICMD, 0x00);
/*5. Read the desired data from the MIRDL and
MIRDH registers. The order that these bytes are
accessed is unimportant.
*/
ret = READ_MREG(ENC_MIRDL) & 0xFF;
ret |= READ_MREG(ENC_MIRDH) << 8;
return ret;
}
/**
* Write value to PHY address.
* Reading procedure is described in ENC28J60 datasheet
* section 3.3.
*/
void enc_phy_write(uint8_t addr, uint16_t value)
{
uint8_t stat;
WRITE_REG(ENC_MIREGADR, addr);
WRITE_REG(ENC_MIWRL, value & 0xFF);
WRITE_REG(ENC_MIWRH, value >> 8);
wait();
do {
stat = READ_MREG(ENC_MISTAT);
} while (stat & ENC_MISTAT_BUSY);
}
/**
* Set the memory area to use for receiving packets.
*/
void enc_set_rx_area(uint16_t start, uint16_t end)
{
WRITE_REG(ENC_ERXSTL, start & 0xFF);
WRITE_REG(ENC_ERXSTH, (start >> 8) & 0xFFF);
WRITE_REG(ENC_ERXNDL, end & 0xFF);
WRITE_REG(ENC_ERXNDH, (end >> 8) & 0xFFF);
WRITE_REG(ENC_ERXRDPTL, start & 0xFF);
WRITE_REG(ENC_ERXRDPTH, (start >> 8) & 0xFFF);
}
/**
* Set the MAC address.
*/
void enc_set_mac_addr(const uint8_t *mac_addr)
{
WRITE_REG(ENC_MAADR1, mac_addr[0]);
WRITE_REG(ENC_MAADR2, mac_addr[1]);
WRITE_REG(ENC_MAADR3, mac_addr[2]);
WRITE_REG(ENC_MAADR4, mac_addr[3]);
WRITE_REG(ENC_MAADR5, mac_addr[4]);
WRITE_REG(ENC_MAADR6, mac_addr[5]);
}
/**
* Read the MAC address.
*/
void enc_get_mac_addr(uint8_t *mac_addr)
{
mac_addr[0] = READ_REG(ENC_MAADR1);
mac_addr[0] = READ_REG(ENC_MAADR1);
mac_addr[1] = READ_REG(ENC_MAADR2);
mac_addr[2] = READ_REG(ENC_MAADR3);
mac_addr[3] = READ_REG(ENC_MAADR4);
mac_addr[4] = READ_REG(ENC_MAADR5);
mac_addr[5] = READ_REG(ENC_MAADR6);
}
void enc_init(const uint8_t *mac)
{
uint16_t phyreg;
enc_reset();
//while ((enc_read(0x1D) & ENC_ESTAT_CLKRDY) == 0);
enc_switch_bank(0);
//tprintf("Econ: 0x%x\r\n", READ_REG(ENC_ECON1));
//tprintf("REV: 0x%x\r\n", READ_REG(ENC_EREVID));
//SET_REG_BITS(ENC_ECON1, ENC_ECON1_TXRST | ENC_ECON1_RXRST);
SET_REG_BITS(ENC_ECON1, ENC_ECON1_TXRST);
CLEAR_REG_BITS(ENC_ECON1, ENC_ECON1_RXEN);
SET_REG_BITS(ENC_ECON2, ENC_ECON2_AUTOINC);
enc_set_rx_area(0x000, RX_END);
phyreg = enc_phy_read(ENC_PHSTAT2);
phyreg &= ~ENC_PHSTAT2_DPXSTAT;
enc_phy_write(ENC_PHSTAT2, phyreg);
phyreg = enc_phy_read(ENC_PHCON1);
phyreg &= ~ENC_PHCON_PDPXMD;
enc_phy_write(ENC_PHCON1, phyreg);
/* Setup receive filter to receive
* broadcast, multicast and unicast to the given MAC */
#if 1
tprintf("Setting MAC: [%x:%x:%x:%x:%x:%x]\n",
mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
#endif
enc_set_mac_addr(mac);
/* WRITE_REG(
ENC_ERXFCON,
ENC_ERXFCON_UCEN | ENC_ERXFCON_CRCEN | ENC_ERXFCON_BCEN |
ENC_ERXFCON_MCEN); */
WRITE_REG(
ENC_ERXFCON,
ENC_ERXFCON_UCEN | ENC_ERXFCON_CRCEN | ENC_ERXFCON_BCEN);
/* Initialize MAC */
WRITE_REG(ENC_MACON1,
ENC_MACON1_TXPAUS | ENC_MACON1_RXPAUS | ENC_MACON1_MARXEN);
WRITE_REG(
ENC_MACON3,
(0x1 << ENC_MACON3_PADCFG_SHIFT) | ENC_MACON3_TXRCEN |
/*ENC_MACON3_FULDPX |*/ENC_MACON3_FRMLNEN);
WRITE_REG(ENC_MAMXFLL, 1518 & 0xFF);
WRITE_REG(ENC_MAMXFLH, (1518 >> 8) & 0xFF);
WRITE_REG(ENC_MABBIPG, 0x12);
WRITE_REG(ENC_MAIPGL, 0x12);
WRITE_REG(ENC_MAIPGH, 0x0C);
SET_REG_BITS(ENC_EIE, ENC_EIE_INTIE | ENC_EIE_PKTIE);
CLEAR_REG_BITS(ENC_ECON1, ENC_ECON1_TXRST | ENC_ECON1_RXRST);
SET_REG_BITS(ENC_ECON1, ENC_ECON1_RXEN);
/* moved from send_start */
WRITE_REG(ENC_ETXSTL, TX_START & 0xFF);
WRITE_REG(ENC_ETXSTH, TX_START >> 8);
#if 1
uint8_t mc[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
enc_get_mac_addr(mc);
tprintf("Mac addr seems to be: [%x:%x:%x:%x:%x:%x]\n",
mc[0], mc[1], mc[2], mc[3], mc[4], mc[5]);
#endif
}
uint8_t enc_action(void)
{
uint8_t reg = READ_REG(ENC_EIR);
if (reg & ENC_EIR_PKTIF) {
if (READ_REG(ENC_EPKTCNT) > 0) {
return 1;
}
}
return 0;
}
void enc_print_status(uint8_t *status)
{
tprintf("STATUS BITS: \r\n");
tprintf(" ByteCount: %d, CollisionCount: %d, TotByteOnWire: %d\r\n",
status[0] | (status[1] << 8),
status[2] & 0x0f,
status[4] | (status[5] << 8));
tprintf(" TxDone: %d, CRCErr:%d, LenChkErr: %d, LenOutOfRange: %d\r\n",
TSV_GETBIT(status, TSV_TXDONE),
TSV_GETBIT(status, TSV_TXCRCERROR),
TSV_GETBIT(status, TSV_TXLENCHKERROR),
TSV_GETBIT(status, TSV_TXLENOUTOFRANGE));
tprintf(" Multicast: %d, Broadcast: %d, "
"PacketDefer: %d, ExDefer: %d\r\n",
TSV_GETBIT(status, TSV_TXMULTICAST),
TSV_GETBIT(status, TSV_TXBROADCAST),
TSV_GETBIT(status, TSV_TXPACKETDEFER),
TSV_GETBIT(status, TSV_TXEXDEFER));
tprintf(" ExCollision: %d, LateCollision: %d, "
"Giant: %d, Underrun: %d\r\n",
TSV_GETBIT(status, TSV_TXEXCOLLISION),
TSV_GETBIT(status, TSV_TXLATECOLLISION),
TSV_GETBIT(status, TSV_TXGIANT),
TSV_GETBIT(status, TSV_TXUNDERRUN));
tprintf(" ControlFrame: %d, PauseFrame: %d, "
"BackPressApp: %d, VLanTagFrame: %d\r\n",
TSV_GETBIT(status, TSV_TXCONTROLFRAME),
TSV_GETBIT(status, TSV_TXPAUSEFRAME),
TSV_GETBIT(status, TSV_BACKPRESSUREAPP),
TSV_GETBIT(status, TSV_TXVLANTAGFRAME));
}
void enc_send_packet_begin(uint16_t count)
{
uint8_t control;
uint16_t tx_end;
/*
if (count > 1000) {
tprintf("enc_send_packet_begin(%d)\r\n", count);
}
*/
/* Errata 12 */
SET_REG_BITS(ENC_ECON1, ENC_ECON1_TXRST);
CLEAR_REG_BITS(ENC_ECON1, ENC_ECON1_TXRST);
CLEAR_REG_BITS(ENC_EIR, ENC_EIR_TXIF);
/* moved to init */
/* WRITE_REG(ENC_ETXSTL, TX_START & 0xFF);
WRITE_REG(ENC_ETXSTH, TX_START >> 8); */
/*
tprintf("Setting EWRPT to [0x%x] (0x%x | 0x%x)\r\n",
TX_START, (TX_START & 0xFF), TX_START >> 8);
*/
WRITE_REG(ENC_EWRPTL, TX_START & 0xFF);
WRITE_REG(ENC_EWRPTH, TX_START >> 8);
tx_end = TX_START + count;
WRITE_REG(ENC_ETXNDL, tx_end & 0xFF);
WRITE_REG(ENC_ETXNDH, tx_end >> 8);
/*
tprintf("Write pointer start: [0x%x]\r\n",
READ_REG(ENC_EWRPTL) | (READ_REG(ENC_EWRPTH) << 8));
tprintf("End pointer: [0x%x]\r\n",
READ_REG(ENC_ETXNDL) | (READ_REG(ENC_ETXNDH) << 8));
*/
control = 0x00;
enc_wbm(&control, 1);
}
void enc_send_packet_end(uint16_t count)
{
uint8_t r;
uint8_t status[7];
//uint16_t transmit_count;
uint16_t tx_end;
tx_end = TX_START + count;
// tprintf("Done writing..\r\n");
/*
tprintf("Write pointer start: [0x%x]\r\n",
READ_REG(ENC_EWRPTL) | (READ_REG(ENC_EWRPTL) << 8));
tprintf("End pointer: [0x%x]\r\n",
READ_REG(ENC_ETXNDL) | (READ_REG(ENC_ETXNDH) << 8));
*/
//tprintf("enc_send_packet_end()\r\n");
/* Errata 12 */
/*
SET_REG_BITS(ENC_ECON1, ENC_ECON1_TXRST);
CLEAR_REG_BITS(ENC_ECON1, ENC_ECON1_TXRST);
CLEAR_REG_BITS(ENC_EIR, ENC_EIR_TXIF);
*/
SET_REG_BITS(ENC_ECON1, ENC_ECON1_TXRTS);
/* Busy wait for the transmission to complete */
while (1) {
r = READ_REG(ENC_ECON1);
if ((r & ENC_ECON1_TXRTS) == 0)
break;
}
/* Read status bits */
tx_end++;
WRITE_REG(ENC_ERDPTL, tx_end & 0xFF);
WRITE_REG(ENC_ERDPTH, tx_end >> 8);
enc_rbm(status, 7);
//transmit_count = status[0] | (status[1] << 8);
if (status[2] & 0x80) {
//tprintf("Transmit OK\n");
} else {
tprintf("Transmit NOT OK\n");
enc_print_status(status);
}
}
void enc_send_packet(const uint8_t *buf, uint16_t count)
{
//tprintf("enc_send_packet(..., %d)\r\n", count);
enc_wbm(buf, count);
}
uint16_t enc_receive_packet_begin(void)
{
/* Receive a single packet */
uint8_t header[6];
uint8_t *status = header + 2;
uint16_t data_count;
//tprintf("enc_receive_packet_begin()\r\n");
WRITE_REG(ENC_ERDPTL, enc_next_packet & 0xFF);
WRITE_REG(ENC_ERDPTH, (enc_next_packet >> 8) & 0xFF);
enc_rbm(header, 6);
/* Update next packet pointer */
enc_next_packet = header[0] | (header[1] << 8);
data_count = status[0] | (status[1] << 8);
if (!(status[2] & (1 << 7))) {
data_count = 0;
tprintf("Invalid!\r\n");
enc_print_status(status);
}
return data_count;
}
void enc_receive_packet(uint8_t *buf, uint16_t len)
{
//tprintf("enc_receive_packet(..., %d)\r\n", len);
enc_rbm(buf, len);
}
void enc_receive_packet_end(void)
{
uint16_t erxst;
//tprintf("enc_receive_packet_end()\r\n");
erxst = READ_REG(ENC_ERXSTL) | (READ_REG(ENC_ERXSTH) << 8);
/* Mark packet as read */
if (enc_next_packet == erxst) {
WRITE_REG(ENC_ERXRDPTL, READ_REG(ENC_ERXNDL));
WRITE_REG(ENC_ERXRDPTH, READ_REG(ENC_ERXNDH));
} else {
WRITE_REG(ENC_ERXRDPTL, (enc_next_packet-1) & 0xFF);
WRITE_REG(ENC_ERXRDPTH, ((enc_next_packet-1) >> 8) & 0xFF);
}
SET_REG_BITS(ENC_ECON2, ENC_ECON2_PKTDEC);
}
uint8_t enc_test(void)
{
uint8_t mc[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
uint8_t rev;
rev = READ_REG(ENC_EREVID);
enc_get_mac_addr(mc);
tprintf("REV: 0x%x, MAC: [%x:%x:%x:%x:%x:%x]\n",
rev, mc[0], mc[1], mc[2], mc[3], mc[4], mc[5]);
return 0;
}
uint8_t enc_revid(void)
{
return READ_REG(ENC_EREVID);
}
/* vim: set et sw=4: */
src/enc28j60if.c 0 → 100644
View file @ 45999dcd
/* Copyright (C) 2013 Upi Tamminen
* See the COPYRIGHT file for more information
*
* Based on the Ethernet Interface skeleton (ethernetif.c)
* which can be found in the lwip distribution in
* lwip-1.4.1/src/netif/ethernetif.c */
#include <stdint.h>
#include "inc/LPC17xx.h"
#include "config.h"
#include "hdr/hdr_sc.h"
#include "lwipopts.h"
#include "lwip/mem.h"
#include "lwip/memp.h"
#include "lwip/pbuf.h"
#include "lwip/udp.h"
#include "lwip/tcp.h"
#include "lwip/tcp_impl.h"
#include "lwip/stats.h"
#include "netif/etharp.h"
#include "enc28j60.h"
#include "httpd.h"
#define IFNAME0 'e'
#define IFNAME1 'n'
const uint8_t mac_addr[] = { 0x00, 0xC0, 0x033, 0x50, 0x48, 0x12 };
static struct ip_addr my_ipaddr_data;
static struct ip_addr my_netmask_data;
static struct ip_addr my_gw_data;
struct netif lwip_netif;
/**
* Helper struct to hold private data used to operate your ethernet interface.
* Keeping the ethernet address of the MAC in this struct is not necessary
* as it is already kept in the struct netif.
* But this is only an example, anyway...
*/
struct ethernetif {
struct eth_addr *ethaddr;
/* Add whatever per-interface state that is needed here. */
};
/**
* Should allocate a pbuf and transfer the bytes of the incoming
* packet from the interface into the pbuf.
*
* @param netif the lwip network interface structure for this ethernetif
* @return a pbuf filled with the received packet (including MAC header)
* NULL on memory error
*/
static struct pbuf * low_level_input(struct netif *netif)
{
struct pbuf *p, *q;
u16_t len;
LWIP_UNUSED_ARG(netif);
/* Obtain the size of the packet and put it into the "len"
variable. */
len = enc_receive_packet_begin();
if (!len) return NULL;
//tprintf("Received packet with len != NULL\r\n");
#if ETH_PAD_SIZE
len += ETH_PAD_SIZE; /* allow room for Ethernet padding */
#endif
/* We allocate a pbuf chain of pbufs from the pool. */
p = pbuf_alloc(PBUF_RAW, len, PBUF_POOL);
if (p != NULL) {
//tprintf("And p != NULL\r\n");
#if ETH_PAD_SIZE
pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */
#endif
/* We iterate over the pbuf chain until we have read the entire
* packet into the pbuf. */
for (q = p; q != NULL; q = q->next) {
//tprintf("Receiving data of %d bytes\r\n", q->len);
/* Read enough bytes to fill this pbuf in the chain. The
* available data in the pbuf is given by the q->len
* variable.
* This does not necessarily have to be a memcpy, you can also preallocate
* pbufs for a DMA-enabled MAC and after receiving truncate it to the
* actually received size. In this case, ensure the tot_len member of the
* pbuf is the sum of the chained pbuf len members.
*/
enc_receive_packet(q->payload, q->len);
}
//tprintf("done receiving packet :)\r\n");
enc_receive_packet_end();
#if ETH_PAD_SIZE
pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */
#endif
LINK_STATS_INC(link.recv);
} else {
tprintf("Ending packet!\r\n");
enc_receive_packet_end();
LINK_STATS_INC(link.memerr);
LINK_STATS_INC(link.drop);
}
return p;
}
/**
* This function should do the actual transmission of the packet. The packet is
* contained in the pbuf that is passed to the function. This pbuf
* might be chained.
*
* @param netif the lwip network interface structure for this ethernetif
* @param p the MAC packet to send (e.g. IP packet including MAC addresses and type)
* @return ERR_OK if the packet could be sent
* an err_t value if the packet couldn't be sent
*
* @note Returning ERR_MEM here if a DMA queue of your MAC is full can lead to
* strange results. You might consider waiting for space in the DMA queue
* to become availale since the stack doesn't retry to send a packet
* dropped because of memory failure (except for the TCP timers).
*/
static err_t low_level_output(struct netif *netif, struct pbuf *p)
{
struct pbuf *q;
LWIP_UNUSED_ARG(netif);
if (p->tot_len > 1530) {
tprintf("p->tot_len: %i\r\n", p->tot_len);
}
enc_send_packet_begin(p->tot_len);
#if ETH_PAD_SIZE
pbuf_header(p, -ETH_PAD_SIZE); /* drop the padding word */
#endif
for (q = p; q != NULL; q = q->next) {
/* Send the data from the pbuf to the interface, one pbuf at a
time. The size of the data in each pbuf is kept in the ->len
variable. */
enc_send_packet(q->payload, q->len);
}
enc_send_packet_end(p->tot_len);
#if ETH_PAD_SIZE
pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */
#endif
LINK_STATS_INC(link.xmit);
return ERR_OK;
}
/**
* In this function, the hardware should be initialized.
* Called from ethernetif_init().
*
* @param netif the already initialized lwip network interface structure
* for this ethernetif
*/
static void low_level_init(struct netif *netif)
{
/* set MAC hardware address length */
netif->hwaddr_len = ETHARP_HWADDR_LEN;
/* set MAC hardware address */
netif->hwaddr[0] = mac_addr[0];
netif->hwaddr[1] = mac_addr[1];
netif->hwaddr[2] = mac_addr[2];
netif->hwaddr[3] = mac_addr[3];
netif->hwaddr[4] = mac_addr[4];
netif->hwaddr[5] = mac_addr[5];
/* maximum transfer unit */
netif->mtu = 1500;
/* device capabilities */
/* don't set NETIF_FLAG_ETHARP if this device is not an ethernet one */
netif->flags =
NETIF_FLAG_BROADCAST |
NETIF_FLAG_ETHARP |
NETIF_FLAG_LINK_UP;
/* Do whatever else is needed to initialize interface. */
enc_init(mac_addr);
}
/**
* Should be called at the beginning of the program to set up the
* network interface. It calls the function low_level_init() to do the
* actual setup of the hardware.
*
* This function should be passed as a parameter to netif_add().
*
* @param netif the lwip network interface structure for this ethernetif
* @return ERR_OK if the loopif is initialized
* ERR_MEM if private data couldn't be allocated
* any other err_t on error
*/
err_t ethernetif_init(struct netif *netif)
{
struct ethernetif *ethernetif;
LWIP_ASSERT("netif != NULL", (netif != NULL));
ethernetif = mem_malloc(sizeof(struct ethernetif));
if (ethernetif == NULL) {
LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_init: out of memory\n"));
return ERR_MEM;
}
#if LWIP_NETIF_HOSTNAME
/* Initialize interface hostname */
netif->hostname = "lwip";
#endif /* LWIP_NETIF_HOSTNAME */
/*
* Initialize the snmp variables and counters inside the struct netif.
* The last argument should be replaced with your link speed, in units
* of bits per second.
*/
NETIF_INIT_SNMP(netif, snmp_ifType_ethernet_csmacd, LINK_SPEED_OF_YOUR_NETIF_IN_BPS);
netif->state = ethernetif;
netif->name[0] = IFNAME0;
netif->name[1] = IFNAME1;
/* We directly use etharp_output() here to save a function call.
* You can instead declare your own function an call etharp_output()
* from it if you have to do some checks before sending (e.g. if link
* is available...) */
netif->output = etharp_output;
netif->linkoutput = low_level_output;
ethernetif->ethaddr = (struct eth_addr *)&(netif->hwaddr[0]);
/* initialize the hardware */
low_level_init(netif);
return ERR_OK;
}
/**
* This function should be called when a packet is ready to be read
* from the interface. It uses the function low_level_input() that
* should handle the actual reception of bytes from the network
* interface. Then the type of the received packet is determined and
* the appropriate input function is called.
*
* @param netif the lwip network interface structure for this ethernetif
*/
static void ethernetif_input(struct netif *netif)
{
struct eth_hdr *ethhdr;
struct pbuf *p;
/* move received packet into a new pbuf */
p = low_level_input(netif);
/* no packet could be read, silently ignore this */
if (p == NULL) return;
/* points to packet payload, which starts with an Ethernet header */
ethhdr = p->payload;
//tprintf("We have packet: [0x%x]\r\n", htons(ethhdr->type));
switch (htons(ethhdr->type)) {
/* IP or ARP packet? */
case ETHTYPE_IP:
case ETHTYPE_ARP:
/* full packet send to tcpip_thread to process */
//tprintf("Passing to netif->input\r\n");
if (netif->input(p, netif) != ERR_OK) {
LWIP_DEBUGF(NETIF_DEBUG,
("ethernetif_input: IP input error\n"));
pbuf_free(p);
p = NULL;
}
break;
default:
pbuf_free(p);
p = NULL;
break;
}
}
/*
* init lwip & enc28j60
*/
void ethernet_init(void)
{
mem_init();
memp_init();
pbuf_init();
etharp_init();
ip_init();
udp_init();
tcp_init();
IP4_ADDR(&my_ipaddr_data, 192, 168, 88, 13);
IP4_ADDR(&my_netmask_data, 255, 255, 255, 0);
IP4_ADDR(&my_gw_data, 192, 168, 88, 147);
netif_add(&lwip_netif, &my_ipaddr_data, &my_netmask_data, &my_gw_data,
NULL, ethernetif_init, ethernet_input);
netif_set_default(&lwip_netif);
netif_set_up(&lwip_netif);
httpd_init();
}
__INLINE void ethernet_action(void)
{
while (enc_action()) {
ethernetif_input(&lwip_netif);
}
}
/* vim: set sw=4 et: */
src/gpio.c 0 → 100644
View file @ 45999dcd
/** \file gpio.c
* \brief GPIO driver.
* \details Function for configuring a GPIO pin
* \author Freddie Chopin, http://www.freddiechopin.info/
* \date 2012-04-07
*/
/******************************************************************************
* chip: LPC175x / LPC176x
* compiler: arm-none-eabi-gcc (GNU Tools for ARM Embedded Processors) 4.6.2
* 20110921 (release) [ARM/embedded-4_6-branch revision 182083]
*
* prefix: gpio_
*
* available global functions:
* void gpio_pin_cfg(LPC_GPIO_TypeDef *gpio_ptr, uint32_t pin, uint32_t configuration)
*
* available local functions:
*
* available interrupt handlers:
******************************************************************************/
/*
+=============================================================================+
| includes
+=============================================================================+
*/
#include <stdint.h>
#include "inc/LPC17xx.h"
#include "gpio.h"
/*
+=============================================================================+
| local definitions
+=============================================================================+
*/
#define GPIO_GET_SEL(combination) (((combination) >> 0) & 0xFF)
#define GPIO_GET_MODE(combination) (((combination) >> 8) & 0xFF)
#define GPIO_GET_MODE_OD(combination) (((combination) >> 16) & 0xFF)
#define GPIO_GET_DIR(combination) (((combination) >> 24) & 0xFF)
/*
+=============================================================================+
| module variables
+=============================================================================+
*/
/*
+=============================================================================+
| local functions' declarations
+=============================================================================+
*/
/*
+=============================================================================+
| global functions
+=============================================================================+
*/
/*------------------------------------------------------------------------*//**
* \brief Configures pin.
* \details Configures one pin in one port.
*
* \param [in] gpio_ptr points to the configuration structure of desired GPIO
* port
* \param [in] pin selects one pin, [0,31]
* \param [in] configuration is a combined value of PINSEL, PINMODE, PINMODE_OD,
* and FIODIR register bitfields, allowed values:
* {GPIO_IN_{PULL_UP, REPEATER, FLOATING, PULL_DOWN},
* GPIO_OUT_{PP, OD}, GPIO_OUT_OD_{PULL_UP, REPEATER, PULL_DOWN},
* GPIO_{ALT1, ALT2, ALT3}_{PP, OD}_{PULL_UP, REPEATER, FLOATING, PULL_DOWN}}
*//*-------------------------------------------------------------------------*/
void gpio_pin_cfg(LPC_GPIO_TypeDef *gpio_ptr, uint32_t pin, uint32_t configuration)
{
uint32_t gpio, sel, mode, mode_od, dir;
volatile uint32_t *pinsel, *pinmode, *pinmode_od;
// calculate the number of GPIO that should be configured
gpio = (((uint32_t)gpio_ptr) - LPC_GPIO_BASE) / (LPC_GPIO1_BASE - LPC_GPIO0_BASE);
// get address of appropriate PINSEL register
pinsel = &(&LPC_PINCON->PINSEL0)[gpio * 2 + pin / 16];
sel = *pinsel; // localize
sel &=~ (LPC_PINCON_PINSELx_mask << (pin * 2)); // clear current setting
sel |= (GPIO_GET_SEL(configuration) << (pin * 2)); // apply new setting
*pinsel = sel; // save back
// get address of appropriate PINMODE register
pinmode = &(&LPC_PINCON->PINMODE0)[gpio * 2 + pin / 16];
mode = *pinmode; // localize
mode &=~ (LPC_PINCON_PINMODEx_mask << (pin * 2)); // clear current setting
mode |= (GPIO_GET_MODE(configuration) << (pin * 2)); // apply new setting
*pinmode = mode; // save back
// get address of appropriate PINMODE_OD register
pinmode_od = &(&LPC_PINCON->PINMODE_OD0)[gpio];
mode_od = *pinmode_od; // localize
mode_od &=~ (LPC_PINCON_PINMODE_ODx_mask << pin); // clear current setting
mode_od |= (GPIO_GET_MODE_OD(configuration) << pin); // apply new setting
*pinmode_od = mode_od; // save back
dir = gpio_ptr->FIODIR; // localize
dir &=~ (LPC_GPIO_FIODIR_mask << pin); // clear current setting
dir |= (GPIO_GET_DIR(configuration) << pin); // apply new setting
gpio_ptr->FIODIR = dir; // save back
}
/*
+=============================================================================+
| local functions
+=============================================================================+
*/
/*
+=============================================================================+
| ISRs
+=============================================================================+
*/
/******************************************************************************
* END OF FILE
******************************************************************************/
src/httpd.c 0 → 100644
View file @ 45999dcd
/* Copyright (C) 2013 Upi Tamminen
* See the COPYRIGHT file for more information
*
* http://lwip.wikia.com/wiki/Raw/TCP
*
* This code is based on the tcpecho_raw from lwIP's contrib-1.4.1
*/
#include "lwip/opt.h"
#include "lwip/debug.h"
#include "lwip/stats.h"
#include "lwip/tcp.h"
#include "tprintf.h"
#include "uart0.h"
#include "cpld.h"
static const char http_response_200[] =
"HTTP/1.1 200 OK\r\n"
"Server: lp1768\r\n"
"Access-Control-Allow-Origin: *\r\n"
"Content-Type: text/html\r\n\r\n";
static const char http_response_404[] =
"HTTP/1.1 404 Not Found\r\n"
"Server: lp1768\r\n"
"Content-Type: text/html\r\n\r\n";
static const char page_root[] =
"<!DOCTYPE HTML PUBLIC \"-//W3C//DTD HTML 4.01 Transitional//EN" "http://www.w3.org/TR/html4/loose.dtd\">"
"<html>"
"<head>"
"<link rel=\"stylesheet\" type=\"text/css\" href=\"http://www.rpg.fi/grabor/grabor.css\" />"
"<script type=\"text/javascript\" src=\"http://www.rpg.fi/grabor/jquery-1.4.4-binary-ajax.js\"></script>"
"<script type=\"text/javascript\" src=\"http://www.rpg.fi/grabor/jdataview.js\"></script>"
"<script type=\"text/javascript\" src='http://www.rpg.fi/grabor/grabor_brd.js'></script>"
"</head>"
"<body>"
"<h1>Grabor</h1>"
"<div id=\"canvasblock\">"
"<canvas id='canvas' width=\"704\" height=\"516\">"
"Canvas not supported"
"</canvas>"
"</div>"
"</body>"
"</html>";
static const char page_404[] =
"<html>"
"<head>"
"<title>404 Not Found!</title>"
"</head>"
"<body>"
"<p>The page you requested is not here!</p>"
"</body>"
"</html>";
char buf[2048]; // this can be smaller, but 2048 is currently used by _test
#define DMABUF_SIZE 2048
extern uint8_t dmabuf[2048];
static struct tcp_pcb *httpd_pcb;
enum httpd_states {
ST_NONE = 0,
ST_ACCEPTED,
ST_READY, // ready to send data
ST_CLOSING,
ST_SENDING,
};
struct httpd_state {
u8_t state;
u8_t retries;
struct tcp_pcb *pcb;
u32_t bodycount;
u8_t (*handler)(struct tcp_pcb *, struct httpd_state *);
u32_t data_to_send;
u8_t *sendbuf;
u8_t *hdrbuf;
u16_t grabbufpos;
};
void httpd_init(void);
err_t httpd_accept(void *arg, struct tcp_pcb *newpcb, err_t err);
err_t httpd_recv(void *arg, struct tcp_pcb *tpcb, struct pbuf *p, err_t err);
err_t httpd_recv(void *arg, struct tcp_pcb *tpcb, struct pbuf *p, err_t err);
void httpd_error(void *arg, err_t err);
err_t httpd_poll(void *arg, struct tcp_pcb *tpcb);
static err_t httpd_sent(void *arg, struct tcp_pcb *tpcb, u16_t len);
//void httpd_send(struct tcp_pcb *tpcb, struct httpd_state *st);
u8_t httpd_send_test(struct tcp_pcb *tpcb, struct httpd_state *st);
u8_t httpd_send_grab(struct tcp_pcb *tpcb, struct httpd_state *st);
u8_t httpd_send_buf(struct tcp_pcb *tpcb, struct httpd_state *st);
void httpd_close(struct tcp_pcb *tpcb, struct httpd_state *st);
void httpd_init(void)
{
err_t err;
httpd_pcb = tcp_new();
if (httpd_pcb == NULL) {
LWIP_DEBUGF(HTTPD_DEBUG, ("Could not create PCB!\r\n"));
while (1);
}
err = tcp_bind(httpd_pcb, IP_ADDR_ANY, 80);
if (err != ERR_OK) {
LWIP_DEBUGF(HTTPD_DEBUG, ("Could not bind!\r\n"));
while (1);
}
httpd_pcb = tcp_listen(httpd_pcb);
tcp_accept(httpd_pcb, httpd_accept);
}
/*
* Connection arrives here
*/
err_t httpd_accept(void *arg, struct tcp_pcb *newpcb, err_t err)
{
struct httpd_state *st;
LWIP_UNUSED_ARG(arg);
LWIP_UNUSED_ARG(err);
LWIP_DEBUGF(HTTPD_DEBUG, ("httpd_accept()\r\n"));
/* Unless this pcb should have NORMAL priority, set its priority now.
When running out of pcbs, low priority pcbs can be aborted to create
new pcbs of higher priority. */
tcp_setprio(newpcb, TCP_PRIO_MIN);
st = (struct httpd_state *)mem_malloc(sizeof(struct httpd_state));
if (st == NULL) {
return ERR_MEM;
}
st->state = ST_ACCEPTED;
st->pcb = newpcb;
st->retries = 0;
st->bodycount = 0;
/* pass newly allocated es to our callbacks */
tcp_arg(newpcb, st);
tcp_recv(newpcb, httpd_recv);
tcp_err(newpcb, httpd_error);
tcp_poll(newpcb, httpd_poll, 4);
tcp_nagle_disable(newpcb);
return ERR_OK;
}
err_t httpd_recv(void *arg, struct tcp_pcb *tpcb, struct pbuf *p, err_t err)
{
struct httpd_state *st;
err_t ret_err;
u16_t i;
LWIP_ASSERT("arg != NULL", arg != NULL);
st = (struct httpd_state *) arg;
if (p == NULL) {
/* remote host closed connection */
LWIP_DEBUGF(HTTPD_DEBUG, ("Remote host closed connection.\r\n"));
st->state = ST_CLOSING;
httpd_close(tpcb, st);
ret_err = ERR_OK;
} else if (err != ERR_OK) {
/* cleanup, for unkown reason */
pbuf_free(p);
ret_err = err;
} else if (st->state == ST_ACCEPTED) {
/* first data chunk in p->payload */
st->state = ST_READY;
ret_err = ERR_OK;
memcpy(buf, p->payload, p->len);
buf[p->len - 1] = '\0';
/* LWIP_DEBUGF(HTTPD_DEBUG, (
"First chunk arrived: [%s] (%d)\r\n", buf, p->len)); */
st->handler = NULL;
st->data_to_send = 0;
if (p->len > 4 && strncmp(buf, "GET ", 4) == 0) {
//tprintf("Seems to be GET\r\n");
for (i = 4; i < p->len; i ++) {
if (buf[i] == ' ') {
buf[i] = '\0';
}
}
tprintf("Request: [%s]\r\n", buf + 4);
if (strcmp(buf + 4, "/") == 0) {
st->handler = &httpd_send_buf;
st->sendbuf = (u8_t *) page_root;
st->hdrbuf = (u8_t *) http_response_200;
st->data_to_send = sizeof(page_root) - 1;
tprintf("body1 | sizeof: %d strlen: %d\r\n",
sizeof(page_root), strlen((char *) page_root));
} else if (strcmp(buf + 4, "/test") == 0) {
st->hdrbuf = (u8_t *) http_response_200;
st->handler = &httpd_send_test;
st->data_to_send = 4000000000;
//st->data_to_send = 100000;
} else if (strcmp(buf + 4, "/grab") == 0) {
cpld_capture();
st->hdrbuf = (u8_t *) http_response_200;
st->handler = &httpd_send_grab;
st->data_to_send = 704*516;
st->grabbufpos = DMABUF_SIZE;
//st->data_to_send = 100000;
} else {
tprintf("Was no match [%s]\r\n", buf + 4);
st->handler = &httpd_send_buf;
st->hdrbuf = (u8_t *) http_response_404;
st->sendbuf = (u8_t *) page_404;
st->data_to_send = sizeof(page_404) - 1;
}
}
tcp_recved(tpcb, p->tot_len);
pbuf_free(p);
for (i = 0; i < 2048; i ++) buf[i] = 'a';
} else if (st->state == ST_READY) {
/* we are not really expecting another packet... */
memcpy((char *) buf, (char *) p->payload, p->len);
memcpy(buf, p->payload, p->len);
buf[p->len - 1] = '\0';
LWIP_DEBUGF(HTTPD_DEBUG, (
"Another chunk arrived: [%s] (%d)\r\n", buf, p->len));
tcp_recved(tpcb, p->tot_len);
pbuf_free(p);
ret_err = ERR_OK;
} else if (st->state == ST_CLOSING) {
/* odd case, remote side closing twice, trash data */
tcp_recved(tpcb, p->tot_len);
pbuf_free(p);
ret_err = ERR_OK;
} else {
/* unkown st->state, trash data */
tcp_recved(tpcb, p->tot_len);
pbuf_free(p);
ret_err = ERR_OK;
}
return ret_err;
}
void httpd_error(void *arg, err_t err)
{
struct httpd_state *st;
LWIP_UNUSED_ARG(err);
st = (struct httpd_state *) arg;
if (st != NULL) {
mem_free(st);
}
}
err_t httpd_poll(void *arg, struct tcp_pcb *tpcb)
{
struct httpd_state *st;
st = (struct httpd_state *) arg;
if (st == NULL) {
/* nothing to be done */
LWIP_DEBUGF(HTTPD_DEBUG, ("Aborting!\r\n"));
tcp_abort(tpcb);
return ERR_ABRT;
}
if (st->state == ST_CLOSING) {
httpd_close(tpcb, st);
}
if (st->state == ST_READY) {
st->state = ST_SENDING;
tcp_sent(tpcb, httpd_sent);
if (st->handler != NULL && (*st->handler)(tpcb, st)) {
tcp_output(tpcb);
}
}
return ERR_OK;
}
static err_t httpd_sent(void *arg, struct tcp_pcb *tpcb, u16_t len)
{
struct httpd_state *st;
LWIP_UNUSED_ARG(len);
LWIP_UNUSED_ARG(tpcb);
st = (struct httpd_state *) arg;
/* LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, (
"Data was sent! [%d]\r\n", len)); */
if (st == NULL) {
return ERR_OK;
}
st->state = ST_READY;
/*
if (st->handler != NULL) {
(*st->handler)(tpcb, st);
}
*/
return ERR_OK;
}
u8_t httpd_send_test(struct tcp_pcb *tpcb, struct httpd_state *st)
{
u8_t retval = 0;
err_t wr_err = ERR_OK;
u16_t len;
/* LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, (
"Okay, let's send some body [%d].\r\n", st->bodycount)); */
/* if (!tcp_nagle_disabled(tpcb)) {
tprintf("nagle is not disabled!\r\n");
} */
if (st->bodycount == 0) {
LWIP_DEBUGF(HTTPD_DEBUG, ("Sending headers..\r\n"));
wr_err = tcp_write(tpcb,
st->hdrbuf, strlen((char *) st->hdrbuf), 1);
retval = 1;
} else {
len = tcp_sndbuf(tpcb) - 1;
if (len > 2048) {
len = 2048;
//tprintf("len: [%d]\r\n", len);
}
if (len > st->data_to_send) {
len = st->data_to_send;
}
/* LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("sendbuf is [%d]\r\n", len)); */
/* LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, ("Sending body #%d\r\n", st->bodycount)); */
wr_err = tcp_write(tpcb, buf, len, 0);
if (wr_err == ERR_OK) {
st->data_to_send -= len;
/* LWIP_DEBUGF(HTTPD_DEBUG | LWIP_DBG_TRACE, (
"tcp_write says ERR_OK\r\n")); */
} else if (wr_err == ERR_MEM) {
LWIP_DEBUGF(HTTPD_DEBUG, ("tcp_write says ERR_MEM\r\n"));
} else {
LWIP_DEBUGF(HTTPD_DEBUG, ("tcp_write says fail!!\r\n"));
}
//tcp_output(tpcb);
retval = 1;
}
if (st->data_to_send == 0) {
LWIP_DEBUGF(HTTPD_DEBUG, ("Closing connection...\r\n"));
st->state = ST_CLOSING;
httpd_close(tpcb, st);
retval = 0;
}
st->bodycount ++;
return retval;
}
u8_t httpd_send_grab(struct tcp_pcb *tpcb, struct httpd_state *st)
{
u8_t retval = 0;
err_t wr_err = ERR_OK;
u16_t len;
if (st->bodycount == 0) {
LWIP_DEBUGF(HTTPD_DEBUG, ("Sending headers..\r\n"));
wr_err = tcp_write(tpcb,
st->hdrbuf, strlen((char *) st->hdrbuf), 1);
retval = 1;
} else {
if (st->grabbufpos == DMABUF_SIZE) {
//tprintf("Filling grabbuf...\r\n");
st->grabbufpos = 0;
cpld_xfr();
}
LWIP_ASSERT("st->grabbufpos > DMABUF_SIZE",
st->grabbufpos <= DMABUF_SIZE);
len = tcp_sndbuf(tpcb) - 1;
if (len > st->data_to_send) {
len = st->data_to_send;
}
if (len > (DMABUF_SIZE - st->grabbufpos)) {
len = (DMABUF_SIZE - st->grabbufpos);
}
//tprintf("Sending %d bytes of data!\r\n", len);
wr_err = tcp_write(tpcb, dmabuf + st->grabbufpos, len, 0);
if (wr_err == ERR_OK) {
st->data_to_send -= len;
st->grabbufpos += len;
} else if (wr_err == ERR_MEM) {
LWIP_DEBUGF(HTTPD_DEBUG, ("tcp_write says ERR_MEM\r\n"));
} else {
LWIP_DEBUGF(HTTPD_DEBUG, ("tcp_write says fail!!\r\n"));
}
retval = 1;
}
if (st->data_to_send == 0) {
LWIP_DEBUGF(HTTPD_DEBUG, ("Closing connection...\r\n"));
st->state = ST_CLOSING;
httpd_close(tpcb, st);
retval = 0;
}
st->bodycount ++;
return retval;
}
u8_t httpd_send_buf(struct tcp_pcb *tpcb, struct httpd_state *st)
{
u8_t retval = 0;
err_t wr_err = ERR_OK;
u16_t len;
if (st->bodycount == 0) {
/* LWIP_DEBUGF(HTTPD_DEBUG, (
"Sending headers.. (%d bytes)\r\n", strlen(st->hdrbuf))); */
wr_err = tcp_write(tpcb,
st->hdrbuf, strlen((char *) st->hdrbuf), 1);
retval = 1;
} else {
len = tcp_sndbuf(tpcb) - 1; // we can send this much data
if (len > 2048) {
len = 2048;
LWIP_DEBUGF(HTTPD_DEBUG, ("suspiciously big len: [%d]\r\n", len));
}
if (len > st->data_to_send) {
len = st->data_to_send;
}
wr_err = tcp_write(tpcb, st->sendbuf, len, 1);
if (wr_err == ERR_OK) {
st->data_to_send -= len;
st->sendbuf += len;
} else if (wr_err == ERR_MEM) {
LWIP_DEBUGF(HTTPD_DEBUG, ("tcp_write says ERR_MEM\r\n"));
} else {
LWIP_DEBUGF(HTTPD_DEBUG, ("tcp_write says fail!!\r\n"));
}
retval = 1;
}
if (st->data_to_send == 0) {
LWIP_DEBUGF(HTTPD_DEBUG, ("Closing connection...\r\n"));
st->state = ST_CLOSING;
httpd_close(tpcb, st);
//tcp_output(tpcb);
retval = 0;
}
st->bodycount ++;
//tprintf("Returing with [%d]\r\n", retval);
return retval;
}
void httpd_close(struct tcp_pcb *tpcb, struct httpd_state *st)
{
err_t err;
tcp_arg(tpcb, NULL);
tcp_sent(tpcb, NULL);
tcp_recv(tpcb, NULL);
tcp_err(tpcb, NULL);
tcp_poll(tpcb, NULL, 0);
if (st != NULL) {
mem_free(st);
}
err = tcp_close(tpcb);
if (err != ERR_OK) {
LWIP_DEBUGF(HTTPD_DEBUG, ("Error %d closing %p\n", err, (void*)tpcb));
}
}
/* vim: set sw=4 et: */
src/i2c.c 0 → 100644
View file @ 45999dcd
/*****************************************************************************
* i2c.c: I2C C file for NXP LPC11xx Family Microprocessors
*
* Copyright(C) 2008, NXP Semiconductor
* parts of this code are (C) 2010, MyVoice CAD/CAM Services
* All rights reserved.
*
* History
* 2009.12.07 ver 1.00 Preliminary version, first Release
* 2010.07.19 ver 1.10 Rob Jansen - MyVoice CAD/CAM Services:
* Major cleaning an a rewrite of some functions
* - adding ACK/NACK handling to the state machine
* - adding a return result to the I2CEngine()
* 2011.02.08 ver 1.200 J. Harwood - ported to LPC17xx
* 2011.03.07 ver 1.210 Larry Viesse - Corrected Buffer Sizes to accommodate writing 32 data bytes (a full page)
* 2012.03.05 ver 1.999 Upi Tamminen - adopted for my own projects
*
*****************************************************************************/
//#include <stdio.h>
#include "inc/LPC17xx.h"
// #include "type.h"
#include "i2c.h"
#include "tprintf.h"
volatile uint32_t I2CMasterState = I2CSTATE_IDLE;
volatile uint32_t I2CSlaveState = I2CSTATE_IDLE;
volatile uint8_t I2CMasterBuffer[Master_Buffer_BUFSIZE];
volatile uint8_t I2CSlaveBuffer[Slave_Buffer_BUFSIZE];
volatile uint32_t I2CReadLength;
volatile uint32_t I2CWriteLength;
volatile uint32_t RdIndex = 0;
volatile uint32_t WrIndex = 0;
/*****************************************************************************
** Function name: I2C_IRQHandler
**
** Descriptions: I2C interrupt handler, deal with master mode only.
**
** parameters: None
** Returned value: None
**
*****************************************************************************/
void I2C1_IRQHandler(void)
{
uint8_t StatValue;
/* this handler deals with master read and master write only */
StatValue = LPC_I2C1->I2STAT;
switch ( StatValue )
{
case 0x08:
/*
* A START condition has been transmitted.
* We now send the slave address and initialize
* the write buffer
* (we always start with a write after START+SLA)
*/
WrIndex = 0;
LPC_I2C1->I2DAT = I2CMasterBuffer[WrIndex++];
//LPC_I2C1->I2CONSET = I2CONSET_AA;
LPC_I2C1->I2CONCLR = (I2CONCLR_SIC | I2CONCLR_STAC);
I2CMasterState = I2CSTATE_PENDING;
break;
case 0x10:
/*
* A repeated START condition has been transmitted.
* Now a second, read, transaction follows so we
* initialize the read buffer.
*/
RdIndex = 0;
/* Send SLA with R bit set, */
LPC_I2C1->I2DAT = I2CMasterBuffer[WrIndex++];
//LPC_I2C1->I2CONSET = I2CONSET_AA;
LPC_I2C1->I2CONCLR = (I2CONCLR_SIC | I2CONCLR_STAC);
break;
case 0x18:
/*
* SLA+W has been transmitted; ACK has been received.
* We now start writing bytes.
*/
LPC_I2C1->I2DAT = I2CMasterBuffer[WrIndex++];
//LPC_I2C1->I2CONSET = I2CONSET_AA;
LPC_I2C1->I2CONCLR = I2CONCLR_SIC;
break;
case 0x20:
/*
* SLA+W has been transmitted; NOT ACK has been received.
* Send a stop condition to terminate the transaction
* and signal I2CEngine the transaction is aborted.
*/
LPC_I2C1->I2CONSET = I2CONSET_STO;
LPC_I2C1->I2CONCLR = I2CONCLR_SIC;
I2CMasterState = I2CSTATE_SLA_NACK;
break;
case 0x28:
/*
* Data in I2DAT has been transmitted; ACK has been received.
* Continue sending more bytes as long as there are bytes to send
* and after this check if a read transaction should follow.
*/
if ( WrIndex < I2CWriteLength )
{
/* Keep writing as long as bytes avail */
LPC_I2C1->I2DAT = I2CMasterBuffer[WrIndex++];
}
else
{
if ( I2CReadLength != 0 )
{
/* Send a Repeated START to initialize a read transaction */
/* (handled in state 0x10) */
LPC_I2C1->I2CONSET = I2CONSET_STA; /* Set Repeated-start flag */
}
else
{
I2CMasterState = I2CSTATE_ACK;
LPC_I2C1->I2CONSET = I2CONSET_STO; /* Set Stop flag */
}
}
LPC_I2C1->I2CONCLR = I2CONCLR_SIC;
break;
case 0x30:
/*
* Data byte in I2DAT has been transmitted; NOT ACK has been received
* Send a STOP condition to terminate the transaction and inform the
* I2CEngine that the transaction failed.
*/
LPC_I2C1->I2CONSET = I2CONSET_STO;
LPC_I2C1->I2CONCLR = I2CONCLR_SIC;
I2CMasterState = I2CSTATE_NACK;
break;
case 0x38:
/*
* Arbitration loss in SLA+R/W or Data bytes.
* This is a fatal condition, the transaction did not complete due
* to external reasons (e.g. hardware system failure).
* Inform the I2CEngine of this and cancel the transaction
* (this is automatically done by the I2C hardware)
*/
I2CMasterState = I2CSTATE_ARB_LOSS;
LPC_I2C1->I2CONCLR = I2CONCLR_SIC;
break;
case 0x40:
/*
* SLA+R has been transmitted; ACK has been received.
* Initialize a read.
* Since a NOT ACK is sent after reading the last byte,
* we need to prepare a NOT ACK in case we only read 1 byte.
*/
if ( I2CReadLength == 1 )
{
/* last (and only) byte: send a NACK after data is received */
LPC_I2C1->I2CONCLR = I2CONCLR_AAC;
}
else
{
/* more bytes to follow: send an ACK after data is received */
LPC_I2C1->I2CONSET = I2CONSET_AA;
}
LPC_I2C1->I2CONCLR = I2CONCLR_SIC;
break;
case 0x48:
/*
* SLA+R has been transmitted; NOT ACK has been received.
* Send a stop condition to terminate the transaction
* and signal I2CEngine the transaction is aborted.
*/
LPC_I2C1->I2CONSET = I2CONSET_STO;
LPC_I2C1->I2CONCLR = I2CONCLR_SIC;
I2CMasterState = I2CSTATE_SLA_NACK;
break;
case 0x50:
/*
* Data byte has been received; ACK has been returned.
* Read the byte and check for more bytes to read.
* Send a NOT ACK after the last byte is received
*/
I2CSlaveBuffer[RdIndex++] = LPC_I2C1->I2DAT;
if ( RdIndex < (I2CReadLength-1) )
{
/* lmore bytes to follow: send an ACK after data is received */
LPC_I2C1->I2CONSET = I2CONSET_AA;
}
else
{
/* last byte: send a NACK after data is received */
LPC_I2C1->I2CONCLR = I2CONCLR_AAC;
}
LPC_I2C1->I2CONCLR = I2CONCLR_SIC;
break;
case 0x58:
/*
* Data byte has been received; NOT ACK has been returned.
* This is the last byte to read.
* Generate a STOP condition and flag the I2CEngine that the
* transaction is finished.
*/
I2CSlaveBuffer[RdIndex++] = LPC_I2C1->I2DAT;
I2CMasterState = I2CSTATE_ACK;
LPC_I2C1->I2CONSET = I2CONSET_STO; /* Set Stop flag */
LPC_I2C1->I2CONCLR = I2CONCLR_SIC; /* Clear SI flag */
break;
default:
LPC_I2C1->I2CONCLR = I2CONCLR_SIC;
break;
}
return;
}
/*****************************************************************************
** Function name: I2CStart
**
** Descriptions: Create I2C start condition, a timeout
** value is set if the I2C never gets started,
** and timed out. It's a fatal error.
**
** parameters: None
** Returned value: true or false, return false if timed out
**
*****************************************************************************/
static uint32_t I2CStart( void )
{
uint32_t timeout = 0;
/*--- Issue a start condition ---*/
LPC_I2C1->I2CONSET = I2CONSET_STA; /* Set Start flag */
while((I2CMasterState != I2CSTATE_PENDING) && (timeout < MAX_TIMEOUT))
{
timeout++;
}
return (timeout < MAX_TIMEOUT);
}
/*****************************************************************************
** Function name: I2CStop
**
** Descriptions: Set the I2C stop condition
**
** parameters: None
** Returned value: true or never return
**
*****************************************************************************/
static uint32_t I2CStop( void )
{
uint32_t timeout = 0;
LPC_I2C1->I2CONSET = I2CONSET_STO; /* Set Stop flag */
LPC_I2C1->I2CONCLR = I2CONCLR_SIC; /* Clear SI flag */
/*--- Wait for STOP detected ---*/
while((LPC_I2C1->I2CONSET & I2CONSET_STO) && (timeout < MAX_TIMEOUT))
{
timeout++;
}
return (timeout >= MAX_TIMEOUT);
}
/*****************************************************************************
** Function name: I2CInit
**
** Descriptions: Initialize I2C controller
**
** parameters: I2c mode is either MASTER or SLAVE
** Returned value: true or false, return false if the I2C
** interrupt handler was not installed correctly
**
*****************************************************************************/
uint32_t I2CInit( uint32_t I2cMode )
{
/* 0.0 SDA1 */
LPC_PINCON->PINSEL0 |= (3 << 0);
/* 0.1 SCL1 */
LPC_PINCON->PINSEL0 |= (3 << 2);
/* 0.0 turn off pullup/pulldown */
LPC_PINCON->PINMODE1 &= ~(1 << 0);
LPC_PINCON->PINMODE1 |= (1 << 1);
/* 0.1 turn off pullup/pulldown */
LPC_PINCON->PINMODE0 &= ~(1 << 2);
LPC_PINCON->PINMODE0 |= (1 << 3);
/* 0.0 & 0.1 open drain */
LPC_PINCON->PINMODE_OD0 &= ~(3 << 0);
LPC_SC->PCLKSEL1 |= (0x3 << 6); // cclk/8
/*--- Clear flags ---*/
LPC_I2C1->I2CONCLR = I2CONCLR_AAC | I2CONCLR_SIC | I2CONCLR_STAC | I2CONCLR_I2ENC;
/*--- Reset registers ---*/
#if FAST_MODE_PLUS
LPC_I2C1->I2SCLL = I2SCLL_HS_SCLL;
LPC_I2C1->I2SCLH = I2SCLH_HS_SCLH;
#else
//LPC_I2C1->I2SCLL = 16; // i2c freq = (100,000,000/8)/ (32) = 390.63khz
//LPC_I2C1->I2SCLH = 16;
LPC_I2C1->I2SCLL = 900;
LPC_I2C1->I2SCLH = 900;
#endif
if ( I2cMode == I2CSLAVE )
{
LPC_I2C1->I2ADR0 = PCF8594_ADDR;
}
/* Enable the I2C Interrupt */
NVIC_EnableIRQ(I2C1_IRQn);
LPC_I2C1->I2CONSET = I2CONSET_I2EN;
return( 1 );
}
/*****************************************************************************
** Function name: I2CEngine
**
** Descriptions: The routine to complete a I2C transaction
** from start to stop. All the intervening
** steps are handled in the interrupt handler.
** Before this routine is called, the read
** length, write length and I2C master buffer
** need to be filled.
**
** parameters: None
** Returned value: Any of the I2CSTATE_... values. See i2c.h
**
*****************************************************************************/
uint32_t I2CEngine( void )
{
I2CMasterState = I2CSTATE_IDLE;
RdIndex = 0;
WrIndex = 0;
if ( I2CStart() == 0 )
{
I2CStop();
return ( 0 );
}
/* wait until the state is a terminal state */
while (I2CMasterState < 0x100);
return ( I2CMasterState );
}
void i2c_showbuffers(void)
{
uint32_t i;
tprintf("Slave: ");
for (i = 0; i < Slave_Buffer_BUFSIZE; i++) {
tprintf("%d ", I2CSlaveBuffer[i]);
}
tprintf(".\nMaster: ");
for (i = 0; i < Master_Buffer_BUFSIZE; i++) {
tprintf("%d ", I2CMasterBuffer[i]);
}
tprintf(".\n");
}
void i2c_clearbuffers(void)
{
uint8_t i;
for (i = 0; i < Master_Buffer_BUFSIZE; i++) {
I2CMasterBuffer[i] = 0;
}
for (i = 0; i < Slave_Buffer_BUFSIZE; i++) {
I2CSlaveBuffer[i] = 0;
}
}
/* vim: set et sw=4: */
src/led.c 0 → 100644
View file @ 45999dcd
/* Copyright (C) 2013 Upi Tamminen
* See the COPYRIGHT file for more information */
#include <stdint.h>
#include "inc/LPC17xx.h"
#include "config.h"
#include "hdr/hdr_sc.h"
inline void led_init(void)
{
/* LED2 is at 0.22 */
LPC_PINCON->PINSEL0 &= ~(3<<18);
LPC_GPIO0->FIODIR |= (1<<9);
}
inline void led_on(void)
{
LPC_GPIO0->FIOSET |= (1<<9);
}
inline void led_off(void)
{
LPC_GPIO0->FIOCLR |= (1<<9);
}
inline void led_toggle(void)
{
LPC_GPIO0->FIOPIN ^= (1<<9);
}
/* vim: set sw=4 et: */
src/main.c 0 → 100644
View file @ 45999dcd
/* Copyright (C) 2013 Upi Tamminen
* See the COPYRIGHT file for more information
*
* Based on the sample lpc1769 project by Freddie Chopin
* http://www.freddiechopin.info/
*/
#include <stdint.h>
#include <stdlib.h>
#include <string.h>
#include "inc/LPC17xx.h"
#include "config.h"
#include "hdr/hdr_sc.h"
#include "gpio.h"
#include "cpu.h"
#include "tprintf.h"
#include "spi.h"
#include "uart0.h"
#include "led.h"
#include "tvp7002.h"
#include "utils.h"
#include "cpld.h"
#include "lwip/mem.h"
#include "lwip/memp.h"
#include "lwip/pbuf.h"
#include "lwip/udp.h"
#include "lwip/tcp.h"
#include "lwip/tcp_impl.h"
#include "lwip/stats.h"
#include "netif/etharp.h"
#include "enc28j60.h"
#include "enc28j60if.h"
volatile uint32_t msTicks;
volatile uint32_t ledTicks;
volatile uint32_t arpTicks;
volatile uint32_t tcpFastTicks;
volatile uint32_t tcpSlowTicks;
volatile uint32_t statsTicks;
/* It's called "dmabuf", but we are not actually using dma at the moment */
uint8_t dmabuf[2048];
uint8_t enc_int;
void EINT3_IRQHandler(void)
{
if ((LPC_GPIOINT->IO0IntStatF & (1 << 27)) != 0) {
LPC_GPIOINT->IO0IntClr = (1 << 27);
enc_int = 1;
}
}
void SysTick_Handler(void)
{
msTicks++;
tcpFastTicks++;
tcpSlowTicks++;
arpTicks++;
ledTicks++;
statsTicks++;
}
void board_init(void)
{
/* Setup SysTick Timer for 1 msec interrupts */
if (SysTick_Config(FREQUENCY / 1000)) {
while (1); /* Capture error */
}
/* clkout of 10mhz on 1.27 */
LPC_PINCON->PINSEL3 &=~(3<<22);
LPC_PINCON->PINSEL3 |= (1<<22);
LPC_SC->CLKOUTCFG = (1<<8) | (11<<4); //enable and divide by 12
/* tvp7002_reset is at 0.10 */
LPC_PINCON->PINSEL0 &= ~(3<<20);
LPC_GPIO0->FIODIR |= (1<<10);
LPC_GPIO0->FIOSET |= (1<<10);
/* tvp7002_pwdn is at 0.11 */
LPC_PINCON->PINSEL0 &= ~(3<<22);
LPC_GPIO0->FIODIR |= (1<<11);
LPC_GPIO0->FIOSET |= (1<<11);
/* SAVE is at 0.16 */
LPC_PINCON->PINSEL1 &= (3 << 0);
LPC_GPIO0->FIODIR |= (1<<16);
LPC_GPIO0->FIOSET &= (1<<16);
/* XFR is at 0.15 */
LPC_PINCON->PINSEL0 &= (3 << 30);
LPC_GPIO0->FIODIR |= (1<<15);
LPC_GPIO0->FIOSET &= (1<<15);
/* OUTCLK is at 0.17 */
LPC_PINCON->PINSEL1 &= (3 << 2);
LPC_GPIO0->FIODIR |= (1<<17);
LPC_GPIO0->FIOSET &= (1<<17);
/* pixel data input from CPLD */
LPC_PINCON->PINSEL4 &= ~0x7fff; // P2.0->P2.7 GPIO
LPC_GPIO2->FIODIR &= ~0xff; // P2.0->P2.7 input
/* enc28j60 reset is at 0.7 */
LPC_PINCON->PINSEL0 &= ~(3<<14);
LPC_GPIO0->FIODIR |= (1<<7);
/* enc28j60 interrupt at 0.27 */
enc_int = 0;
LPC_PINCON->PINSEL1 &= (3<<22);
LPC_GPIO0->FIODIR &= ~(1<<27);
LPC_GPIOINT->IO0IntEnR &= (1 << 27); // rising edge no
LPC_GPIOINT->IO0IntEnF |= (1 << 27); // falling edge yes
NVIC_SetPriority(EINT3_IRQn, 0);
NVIC_EnableIRQ(EINT3_IRQn);
/* enc28j60 manual SSEL at 0.28 */
LPC_PINCON->PINSEL1 &= (3<<24);
LPC_GPIO0->FIODIR |= (1<<28);
LPC_GPIO0->FIOSET |= (1<<28);
spi_init();
led_init();
UART0_Init(115200);
/* I2C */
if (I2CInit((uint32_t) I2CMASTER) == 0) {
tprintf("Fatal error!\n");
while (1);
}
}
void tvp7002_start(void)
{
tprintf("Resetting TVP7002...");
LPC_GPIO0->FIOCLR |= (1<<11);
LPC_GPIO1->FIOCLR |= (1<<10);
delay_ms(50);
LPC_GPIO1->FIOSET |= (1<<10);
tprintf(" Done.\r\n");
delay_ms(100);
tprintf("Initializing TVP7002...");
tvp7002_init();
tprintf(" Done.\r\n");
}
int main(void)
{
arpTicks =
tcpFastTicks =
tcpSlowTicks =
ledTicks =
statsTicks = 0;
system_init();
pll0_start(CRYSTAL, FREQUENCY);
board_init();
tprintf("Reset!\r\n");
delay_ms(500);
tvp7002_start();
tprintf("Initializing ethernet...");
ethernet_init();
tprintf(" Done.\r\n");
while (1) {
/*
if (enc_int) {
enc_int = 0;
ethernet_action();
led_toggle();
}
*/
ethernet_action();
if (arpTicks >= ETHARP_TMR_INTERVAL) {
arpTicks = 0;
etharp_tmr();
}
if (tcpFastTicks >= TCP_FAST_INTERVAL) {
tcpFastTicks = 0;
tcp_fasttmr();
}
if (tcpSlowTicks >= TCP_SLOW_INTERVAL) {
tcpFastTicks = 0;
tcp_slowtmr();
}
if (ledTicks >= 1000) {
ledTicks = 0;
led_toggle();
}
if (statsTicks >= 5000) {
statsTicks = 0;
//stats_display();
enc_test();
}
}
}
/* vim: set sw=4 et: */
src/spi.c 0 → 100644
View file @ 45999dcd
/* Copyright (C) 2013 Upi Tamminen
* See the COPYRIGHT file for more information */
#include <stdint.h>
#include "inc/LPC17xx.h"
#include "config.h"
#include "hdr/hdr_sc.h"
void spi_init(void)
{
/* Enable AHB clock to the SSP0. */
LPC_SC->PCONP |= (0x1<<21);
/* Further divider is needed on SSP0 clock. Using default divided by 4 */
LPC_SC->PCLKSEL1 &= ~(0x3<<10);
LPC_SC->PCLKSEL1 |= (0x1<<10); // by 0
/* SCK0 1.20 */
LPC_PINCON->PINSEL3 |= (3<<8);
/* MISO0 1.23, MOSI0 1.24 */
LPC_PINCON->PINSEL3 |= ((3<<14) | (3<<16));
/* SSEL0 1.21 */
LPC_PINCON->PINSEL3 |= (3<<10);
/*
LPC_PINCON->PINMODE1 &= (3<<8); // pull-up 1.20
LPC_PINCON->PINMODE1 &= (3<<10); // pull-up 1.21
LPC_PINCON->PINMODE1 &= (3<<14); // pull-up 1.23
LPC_PINCON->PINMODE1 &= (3<<16); // pull-up 1.24
*/
LPC_GPIO1->FIODIR &= (1<<23);
/* Set DSS data to 8-bit,
Frame format SPI, CPOL = 0, CPHA = 0, and SCR is 15 */
LPC_SSP0->CR0 = 0x0207;
//LPC_SSP0->CR0 = 0x07; // SSP max speed, 8 bits
LPC_SSP0->CR1 = 0x02;
/* SSPCPSR clock prescale register,
master mode, minimum divisor is 0x02 */
//LPC_SSP0->CPSR = 0x12;
//LPC_SSP0->CPSR = 0x6; // 5.5mhz
LPC_SSP0->CPSR = 0x5; // 8.33mhz
}
uint8_t spi_write(uint8_t data)
{
LPC_SSP0->DR = data;
while ((LPC_SSP0->SR & 0x10));
return LPC_SSP0->DR;
}
uint8_t spi_read(uint8_t data)
{
spi_write(data);
return spi_write(0x00);
}
/* vim: set sw=4 et: */
src/tprintf.c 0 → 100644
View file @ 45999dcd
/*
* Tiny printf by oPossum
* http://www.43oh.com/forum/viewtopic.php?f=10&t=1732
* + Small changes by me
*/
#include <stdarg.h>
#include "uart0.h"
static const unsigned long dv[] = {
// 4294967296 // 32 bit unsigned max
1000000000, // +0
100000000, // +1
10000000, // +2
1000000, // +3
100000, // +4
// 65535 // 16 bit unsigned max
10000, // +5
1000, // +6
100, // +7
10, // +8
1, // +9
};
static void xtoa(unsigned long x, const unsigned long *dp)
{
char c;
unsigned long d;
if(x) {
while(x < *dp) ++dp;
do {
d = *dp++;
c = '0';
while(x >= d) ++c, x -= d;
UART0_Sendchar(c);
} while(!(d & 1));
} else
UART0_Sendchar('0');
}
static void puth(unsigned n)
{
static const char hex[16] = { '0','1','2','3','4','5','6','7','8','9','A','B','C','D','E','F'};
UART0_Sendchar(hex[n & 15]);
}
void tprintf(char *format, ...)
{
char c;
int i;
long n;
va_list a;
va_start(a, format);
while((c = *format++)) {
if(c == '%') {
switch(c = *format++) {
case 's': // String
UART0_PrintString(va_arg(a, char*));
break;
case 'c': // Char
UART0_Sendchar((char) va_arg(a, int));
break;
case 'i': // 16 bit Integer
case 'u': // 16 bit Unsigned
i = va_arg(a, int);
if(c == 'i' && i < 0) i = -i, UART0_Sendchar('-');
xtoa((unsigned)i, dv + 5);
break;
case 'l': // 32 bit Long
case 'n': // 32 bit uNsigned loNg
n = va_arg(a, long);
if(c == 'l' && n < 0) n = -n, UART0_Sendchar('-');
xtoa((unsigned long)n, dv);
break;
case 'x': // 16 bit heXadecimal
i = va_arg(a, int);
puth(i >> 12);
puth(i >> 8);
puth(i >> 4);
puth(i);
break;
case 0: return;
default: goto bad_fmt;
}
} else
bad_fmt: UART0_Sendchar(c);
}
va_end(a);
}
/* vim: set sw=4 et: */
src/tvp7002.c 0 → 100644
View file @ 45999dcd
/* Copyright (C) 2013 Upi Tamminen
* See the COPYRIGHT file for more information */
#include "inc/LPC17xx.h"
#include "tvp7002.h"
#include "i2c.h"
#include "tprintf.h"
#include "tvp7002_reg.h"
uint32_t tvp7002_set(uint8_t addr, uint8_t val)
{
i2c_clearbuffers();
I2CWriteLength = 3;
I2CReadLength = 0;
I2CMasterBuffer[0] = TVP7002_ADDR; /* EEPROM address */
I2CMasterBuffer[1] = addr; /* key */
I2CMasterBuffer[2] = val; /* value */
return I2CEngine();
}
uint8_t tvp7002_get(uint8_t addr)
{
i2c_clearbuffers();
I2CWriteLength = 2;
I2CReadLength = 1;
I2CMasterBuffer[0] = TVP7002_ADDR; /* EEPROM address */
I2CMasterBuffer[1] = (addr); /* key */
I2CMasterBuffer[2] = TVP7002_ADDR | RD_BIT;
while (I2CEngine() == I2CSTATE_SLA_NACK);
return I2CSlaveBuffer[0];
}
void tvp7002_info(void)
{
uint16_t cpln, lnpf, val;
//tprintf("Reading from TVP7002...\r\n");
val = tvp7002_get(0x00);
if (val != 0x02) {
tprintf("The data was not a proper revision number!\r\n");
return;
}
//tprintf("Input Mux Select 1: [0x%x]\r\n", tvp7002_get(0x19));
//tprintf("Input Mux Select 2: [0x%x]\r\n", tvp7002_get(0x1a));
//tprintf("Lines per frame: [0x%x][0x%x]\r\n",
// tvp7002_get(0x37), tvp7002_get(0x38));
lnpf = ((tvp7002_get(0x38) & 0xf) << 8) | tvp7002_get(0x37);
cpln = ((tvp7002_get(0x3a) & 0xf) << 8) | tvp7002_get(0x39);
tprintf("Lines per frame: %d\r\n", lnpf);
tprintf("Clocks per line: %d\r\n", cpln);
tprintf("Frame rate: ~%d\r\n", (6553600L / cpln / lnpf));
tprintf("Sync Control 1: [0x%x]\r\n", tvp7002_get(0x0e));
val = tvp7002_get(0x14);
if (tvp7002_get(0x14) != 0x95) {
tprintf("HSYNC detection status: [0x%x]\r\n", tvp7002_get(0x14));
tprintf(" HSYNC activity detected: %s\r\n",
(val & (1 << 7)) ? "yes" : "no");
tprintf(" Active HSYNC: %s\r\n",
(val & (1 << 6)) ? "selected SOG input" : "selected HSYNC input");
tprintf(" Input HSYNC Polarity Detect: %s\r\n",
(val & (1 << 5)) ? "Active-high" : "Active-low");
tprintf(" VSYNC activity detected: %s\r\n",
(val & (1 << 4)) ? "yes" : "no");
tprintf(" Input VSYNC Polarity Detect: %s\r\n",
(val & (1 << 3)) ? "Active-high" : "Active-low");
tprintf(" SOG activity detected: %s\r\n",
(val & (1 << 2)) ? "yes" : "no");
tprintf(" Input Coast Polarity: %s\r\n",
(val & (1 << 1)) ? "Active-high" : "Active-low");
}
}
void tvp7002_init(void)
{
/* some i2c settings according to
* TVP7002_THS8200_RGB_graphics_settings_081811.xls */
/* unique */
tvp7002_set(TVP7002_HPLL_FDBK_DIV_MSBS, 0x32);
tvp7002_set(TVP7002_HPLL_FDBK_DIV_LSBS, 0x00);
tvp7002_set(TVP7002_HPLL_CRTL, 0x20);
tvp7002_set(TVP7002_HSYNC_OUT_W, 0x60);
tvp7002_set(TVP7002_SYNC_CTL_1, 0x00);
tvp7002_set(TVP7002_ADC_SETUP, 0x50);
tvp7002_set(TVP7002_AVID_START_PIXEL_LSBS, 0x92);
tvp7002_set(TVP7002_AVID_START_PIXEL_MSBS, 0x00);
tvp7002_set(TVP7002_AVID_STOP_PIXEL_LSBS, 0x12);
tvp7002_set(TVP7002_AVID_STOP_PIXEL_MSBS, 0x03);
tvp7002_set(TVP7002_VBLK_F_0_START_L_OFF, 0x12);
tvp7002_set(TVP7002_VBLK_F_1_START_L_OFF, 0x12);
tvp7002_set(TVP7002_VBLK_F_0_DURATION, 0x2d);
tvp7002_set(TVP7002_VBLK_F_1_DURATION, 0x2d);
/* common */
tvp7002_set(0x04, 0x80);
tvp7002_set(0x05, 0x06);
tvp7002_set(0x06, 0x10);
tvp7002_set(0x08, 0x3c);
tvp7002_set(0x09, 0x3c);
tvp7002_set(0x0a, 0x3c);
tvp7002_set(0x0f, 0x2e);
tvp7002_set(0x10, 0x58);
tvp7002_set(0x11, 0x40);
tvp7002_set(0x12, 0x01);
tvp7002_set(0x13, 0x00);
tvp7002_set(0x15, 0x04);
tvp7002_set(0x17, 0x00);
tvp7002_set(0x18, 0x01);
tvp7002_set(0x19, 0xaa);
tvp7002_set(0x1a, 0xc2);
tvp7002_set(0x21, 0x0d);
tvp7002_set(0x22, 0x00);
tvp7002_set(0x26, 0x80); // 0x80 = enable, 0x00 = disable
tvp7002_set(0x28, 0x53);
tvp7002_set(0x2a, 0x07);
tvp7002_set(0x2b, 0x00); // Power Control
tvp7002_set(0x31, 0x18);
tvp7002_set(0x35, 0x00);
tvp7002_set(0x36, 0x00);
tvp7002_set(0x3d, 0x06);
/* 640x480 59.94hz recommended settings from datasheet */
tvp7002_set(TVP7002_HPLL_FDBK_DIV_MSBS, 0x32);
tvp7002_set(TVP7002_HPLL_FDBK_DIV_LSBS, 0x00);
tvp7002_set(TVP7002_HPLL_CRTL, 0x20);
tvp7002_set(TVP7002_HPLL_PHASE_SEL, 0x0);
/* my additions */
/* disable hsync/sog detect */
tvp7002_set(TVP7002_SYNC_CTL_1, 0x12);
tvp7002_set(0x36, 0x00);
tvp7002_set(TVP7002_IN_MUX_SEL_1, 0x00);
tvp7002_set(TVP7002_IN_MUX_SEL_2, 0xc2);
/* RGB 4:4:4 out */
tvp7002_set(TVP7002_OUT_FORMATTER, 0x04);
// 0x47 = 01000111
/* refclk at fdout */
tvp7002_set(TVP7002_MISC_CTL_2, 0x42);
/* enable automatic power management mode */
tvp7002_set(TVP7002_HPLL_AND_CLAMP_CTL, 0x2a);
/* disable blue & green for fun */
//tvp7002_set(TVP7002_PWR_CTL, 0x00);
// turn off colors
//tvp7002_set(TVP7002_PWR_CTL, 0x67);
tvp7002_set(TVP7002_PWR_CTL, 0x60);
}
#if 0
/* init according to tvp7002.c in linux */
void tvp7002_init(void)
{
/* default values */
/*
tvp7002_set(TVP7002_HPLL_FDBK_DIV_MSBS, 0x67);
tvp7002_set(TVP7002_HPLL_FDBK_DIV_LSBS, 0x20);
tvp7002_set(TVP7002_HPLL_CRTL, 0xa0);
tvp7002_set(TVP7002_HPLL_PHASE_SEL, 0x80);
tvp7002_set(TVP7002_CLAMP_START, 0x32);
tvp7002_set(TVP7002_CLAMP_W, 0x20);
tvp7002_set(TVP7002_HSYNC_OUT_W, 0x60);
tvp7002_set(TVP7002_B_FINE_GAIN, 0x00);
tvp7002_set(TVP7002_G_FINE_GAIN, 0x00);
tvp7002_set(TVP7002_R_FINE_GAIN, 0x00);
tvp7002_set(TVP7002_B_FINE_OFF_MSBS, 0x80);
tvp7002_set(TVP7002_G_FINE_OFF_MSBS, 0x80);
tvp7002_set(TVP7002_R_FINE_OFF_MSBS, 0x80);
tvp7002_set(TVP7002_SYNC_CTL_1, 0x20);
tvp7002_set(TVP7002_HPLL_AND_CLAMP_CTL, 0x2e);
tvp7002_set(TVP7002_SYNC_ON_G_THRS, 0x5d);
tvp7002_set(TVP7002_SYNC_SEPARATOR_THRS, 0x47);
tvp7002_set(TVP7002_HPLL_PRE_COAST, 0x00);
tvp7002_set(TVP7002_HPLL_POST_COAST, 0x00);
tvp7002_set(TVP7002_OUT_FORMATTER, 0x47);
tvp7002_set(TVP7002_MISC_CTL_1, 0x01);
tvp7002_set(TVP7002_MISC_CTL_2, 0x00);
tvp7002_set(TVP7002_MISC_CTL_3, 0x01);
tvp7002_set(TVP7002_IN_MUX_SEL_1, 0x00);
tvp7002_set(TVP7002_IN_MUX_SEL_2, 0x67);
tvp7002_set(TVP7002_B_AND_G_COARSE_GAIN, 0x77);
tvp7002_set(TVP7002_R_COARSE_GAIN, 0x07);
tvp7002_set(TVP7002_FINE_OFF_LSBS, 0x00);
tvp7002_set(TVP7002_B_COARSE_OFF, 0x10);
tvp7002_set(TVP7002_G_COARSE_OFF, 0x10);
tvp7002_set(TVP7002_R_COARSE_OFF, 0x10);
tvp7002_set(TVP7002_HSOUT_OUT_START, 0x08);
tvp7002_set(TVP7002_MISC_CTL_4, 0x00);
tvp7002_set(TVP7002_AUTO_LVL_CTL_ENABLE, 0x80);
tvp7002_set(TVP7002_AUTO_LVL_CTL_FILTER, 0x53);
tvp7002_set(0x29, 0x08);
tvp7002_set(TVP7002_FINE_CLAMP_CTL, 0x07);
tvp7002_set(TVP7002_PWR_CTL, 0x00);
tvp7002_set(TVP7002_ADC_SETUP, 0x50);
tvp7002_set(TVP7002_COARSE_CLAMP_CTL, 0x00);
tvp7002_set(TVP7002_SOG_CLAMP, 0x80);
tvp7002_set(TVP7002_RGB_COARSE_CLAMP_CTL, 0x00);
tvp7002_set(TVP7002_SOG_COARSE_CLAMP_CTL, 0x04);
tvp7002_set(TVP7002_ALC_PLACEMENT, 0x5a);
tvp7002_set(0x32, 0x18);
tvp7002_set(0x33, 0x60);
tvp7002_set(TVP7002_MVIS_STRIPPER_W, 0xff);
tvp7002_set(TVP7002_VSYNC_ALGN, 0x10);
tvp7002_set(TVP7002_SYNC_BYPASS, 0x00);
tvp7002_set(TVP7002_L_LENGTH_TOL, 0x03);
tvp7002_set(0x3e, 0x60);
tvp7002_set(TVP7002_VIDEO_BWTH_CTL, 0x01);
tvp7002_set(TVP7002_AVID_START_PIXEL_LSBS, 0x01);
tvp7002_set(TVP7002_AVID_START_PIXEL_MSBS, 0x2c);
tvp7002_set(TVP7002_AVID_STOP_PIXEL_LSBS, 0x06);
tvp7002_set(TVP7002_AVID_STOP_PIXEL_MSBS, 0x2c);
tvp7002_set(TVP7002_VBLK_F_0_START_L_OFF, 0x05);
tvp7002_set(TVP7002_VBLK_F_1_START_L_OFF, 0x00);
tvp7002_set(TVP7002_VBLK_F_0_DURATION, 0x1e);
tvp7002_set(TVP7002_VBLK_F_1_DURATION, 0x00);
tvp7002_set(TVP7002_FBIT_F_0_START_L_OFF, 0x00);
tvp7002_set(TVP7002_FBIT_F_1_START_L_OFF, 0x00);
tvp7002_set(TVP7002_YUV_Y_G_COEF_LSBS, 0xe3);
tvp7002_set(TVP7002_YUV_Y_G_COEF_MSBS, 0x16);
tvp7002_set(TVP7002_YUV_Y_B_COEF_LSBS, 0x4f);
tvp7002_set(TVP7002_YUV_Y_B_COEF_MSBS, 0x02);
tvp7002_set(TVP7002_YUV_Y_R_COEF_LSBS, 0xce);
tvp7002_set(TVP7002_YUV_Y_R_COEF_MSBS, 0x06);
tvp7002_set(TVP7002_YUV_U_G_COEF_LSBS, 0xab);
tvp7002_set(TVP7002_YUV_U_G_COEF_MSBS, 0xf3);
tvp7002_set(TVP7002_YUV_U_B_COEF_LSBS, 0x00);
tvp7002_set(TVP7002_YUV_U_B_COEF_MSBS, 0x10);
tvp7002_set(TVP7002_YUV_U_R_COEF_LSBS, 0x55);
tvp7002_set(TVP7002_YUV_U_R_COEF_MSBS, 0xfc);
tvp7002_set(TVP7002_YUV_V_G_COEF_LSBS, 0x78);
tvp7002_set(TVP7002_YUV_V_G_COEF_MSBS, 0xf1);
tvp7002_set(TVP7002_YUV_V_B_COEF_LSBS, 0x88);
tvp7002_set(TVP7002_YUV_V_B_COEF_MSBS, 0xfe);
tvp7002_set(TVP7002_YUV_V_R_COEF_LSBS, 0x00);
tvp7002_set(TVP7002_YUV_V_R_COEF_MSBS, 0x10);
*/
/* 640x480 59.94hz recommended settings from datasheet */
tvp7002_set(TVP7002_HPLL_FDBK_DIV_MSBS, 0x32);
tvp7002_set(TVP7002_HPLL_FDBK_DIV_LSBS, 0x00);
tvp7002_set(TVP7002_HPLL_CRTL, 0x20);
tvp7002_set(TVP7002_HPLL_PHASE_SEL, 0x0);
/* some other stuff, try without these? */
/*
tvp7002_set(TVP7002_AVID_START_PIXEL_LSBS, 0x91);
tvp7002_set(TVP7002_AVID_START_PIXEL_MSBS, 0x00);
tvp7002_set(TVP7002_AVID_STOP_PIXEL_LSBS, 0x0B);
tvp7002_set(TVP7002_AVID_STOP_PIXEL_MSBS, 0x00);
tvp7002_set(TVP7002_VBLK_F_0_START_L_OFF, 0x03);
tvp7002_set(TVP7002_VBLK_F_1_START_L_OFF, 0x01);
tvp7002_set(TVP7002_VBLK_F_0_DURATION, 0x13);
tvp7002_set(TVP7002_VBLK_F_1_DURATION, 0x13);
*/
/* additions */
/* disable hsync/sog detect */
tvp7002_set(TVP7002_SYNC_CTL_1, 0x12);
tvp7002_set(0x36, 0x00);
tvp7002_set(TVP7002_IN_MUX_SEL_1, 0x00);
tvp7002_set(TVP7002_IN_MUX_SEL_2, 0xc2);
/* RGB 4:4:4 out */
tvp7002_set(TVP7002_OUT_FORMATTER, 0x04);
// 0x47 = 01000111
/* refclk at fdout */
tvp7002_set(TVP7002_MISC_CTL_2, 0x42);
/* enable automatic power management mode */
tvp7002_set(TVP7002_HPLL_AND_CLAMP_CTL, 0x2a);
/* disable blue & green for fun */
//tvp7002_set(TVP7002_PWR_CTL, 0x06);
tvp7002_set(TVP7002_PWR_CTL, 0x60);
}
#endif
/* vim: set et sw=4: */
src/uart0.c 0 → 100644
View file @ 45999dcd
//*****************************************************************************
// +--+
// | ++----+
// +-++ |
// | |
// +-+--+ |
// | +--+--+
// +----+ Copyright (c) 2009 Code Red Technologies Ltd.
//
// UART example project for RDB1768 development board
//
// Software License Agreement
//
// The software is owned by Code Red Technologies and/or its suppliers, and is
// protected under applicable copyright laws. All rights are reserved. Any
// use in violation of the foregoing restrictions may subject the user to criminal
// sanctions under applicable laws, as well as to civil liability for the breach
// of the terms and conditions of this license.
//
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// USE OF THIS SOFTWARE FOR COMMERCIAL DEVELOPMENT AND/OR EDUCATION IS SUBJECT
// TO A CURRENT END USER LICENSE AGREEMENT (COMMERCIAL OR EDUCATIONAL) WITH
// CODE RED TECHNOLOGIES LTD.
//
//*****************************************************************************
#include <stdint.h>
#include "inc/LPC17xx.h"
#include "config.h"
#include "hdr/hdr_sc.h"
#include "uart0.h"
// PCUART0
#define PCUART0_POWERON (1 << 3)
#define PCLK_UART0 6
#define PCLK_UART0_MASK (3 << 6)
#define IER_RBR 0x01
#define IER_THRE 0x02
#define IER_RLS 0x04
#define IIR_PEND 0x01
#define IIR_RLS 0x03
#define IIR_RDA 0x02
#define IIR_CTI 0x06
#define IIR_THRE 0x01
#define LSR_RDR 0x01
#define LSR_OE 0x02
#define LSR_PE 0x04
#define LSR_FE 0x08
#define LSR_BI 0x10
#define LSR_THRE 0x20
#define LSR_TEMT 0x40
#define LSR_RXFE 0x80
// ***********************
// Function to set up UART
void UART0_Init(int baudrate)
{
int pclk;
unsigned long int Fdiv;
// PCLK_UART0 is being set to 1/4 of SystemCoreClock
pclk = FREQUENCY / 4;
// Turn on power to UART0
LPC_SC->PCONP |= PCUART0_POWERON;
// Turn on UART0 peripheral clock
LPC_SC->PCLKSEL0 &= ~(PCLK_UART0_MASK);
LPC_SC->PCLKSEL0 |= (0 << PCLK_UART0); // PCLK_periph = CCLK/4
// Set PINSEL0 so that P0.2 = TXD0, P0.3 = RXD0
LPC_PINCON->PINSEL0 &= ~0xf0;
LPC_PINCON->PINSEL0 |= ((1 << 4) | (1 << 6));
LPC_UART0->LCR = 0x83; // 8 bits, no Parity, 1 Stop bit, DLAB=1
Fdiv = ( pclk / 16 ) / baudrate; // Set baud rate
LPC_UART0->DLM = Fdiv / 256;
LPC_UART0->DLL = Fdiv % 256;
/* 0x07 == 2 stop bits */
LPC_UART0->LCR = 0x03; // 8 bits, no Parity, 1 Stop bit DLAB = 0
LPC_UART0->FCR = 0x07; // Enable and reset TX and RX FIFO
}
// ***********************
// Function to send character over UART
__INLINE void UART0_Sendchar(char c)
{
while( (LPC_UART0->LSR & LSR_THRE) == 0 ); // Block until tx empty
LPC_UART0->THR = c;
}
// ***********************
// Function to get character from UART
char UART0_Getchar(void)
{
char c;
while( (LPC_UART0->LSR & LSR_RDR) == 0 ); // Nothing received so just block
c = LPC_UART0->RBR; // Read Receiver buffer register
return c;
}
// ***********************
// Function to prints the string out over the UART
void UART0_PrintString(char *pcString)
{
int i = 0;
// loop through until reach string's zero terminator
while (pcString[i] != 0) {
UART0_Sendchar(pcString[i]); // print each character
i++;
}
}
/* vim: set et sw=4: */
src/utils.c 0 → 100644
View file @ 45999dcd
/* Copyright (C) 2013 Upi Tamminen
* See the COPYRIGHT file for more information */
#include <stdint.h>
#include <string.h>
#include "inc/LPC17xx.h"
#include "config.h"
#include "hdr/hdr_sc.h"
#include "tprintf.h"
extern volatile uint32_t msTicks;
__INLINE void delay_ms(uint32_t dlyTicks)
{
uint32_t curTicks;
curTicks = msTicks;
while ((msTicks - curTicks) < dlyTicks);
}
uint16_t hex2int(char *a, uint16_t len)
{
uint8_t i;
uint16_t val = 0;
for(i=0;i<len;i++)
if(a[i] <= 57)
val += (a[i]-48)*(1<<(4*(len-1-i)));
else
val += (a[i]-55)*(1<<(4*(len-1-i)));
return val;
}
void split_args(char *buf, char *p1, char *p2)
{
uint8_t n = 0, c, p1c = 0, p2c = 0;
for (c = 0; c < strlen(buf); c ++) {
if (buf[c] == ' ' && !n) {
n = 1;
continue;
}
if (n == 0) {
p1[p1c++] = buf[c];
} else {
p2[p2c++] = buf[c];
}
}
p1[p1c] = 0;
p2[p2c] = 0;
}
/* vim: set et sw=4: */
src/vectors.c 0 → 100644
View file @ 45999dcd
/** \file vectors.c
* \brief LPC175x / LPC176x vector table and __Default_Handler()
* \details LPC175x / LPC176x vector table and __Default_Handler()
* \author Freddie Chopin, http://www.freddiechopin.info/
* \date 2012-03-24
*/
/******************************************************************************
* chip: LPC175x / LPC176x
* compiler: arm-none-eabi-gcc (GNU Tools for ARM Embedded Processors) 4.6.2
* 20110921 (release) [ARM/embedded-4_6-branch revision 182083]
******************************************************************************/
/*------------------------------------------------------------------------*//**
* \brief Default interrupt handler.
* \details Default interrupt handler, used for interrupts that don't have their
* own handler defined.
*//*-------------------------------------------------------------------------*/
static void __Default_Handler(void) __attribute__ ((interrupt));
static void __Default_Handler(void)
{
while (1);
}
/*
+=============================================================================+
| assign all unhandled interrupts to the default handler
+=============================================================================+
*/
// Non Maskable Interrupt
void NMI_Handler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));
// All class of fault
void HardFault_Handler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));
// Cortex-M3 Memory Management Interrupt
void MemManage_Handler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));
// Cortex-M3 Bus Fault Interrupt
void BusFault_Handler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));
// Cortex-M3 Usage Fault Interrupt
void UsageFault_Handler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));
// Reserved 0x1C
void __Reserved_0x1C_Handler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));
// Reserved 0x20
void __Reserved_0x20_Handler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));
// Reserved 0x24
void __Reserved_0x24_Handler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));
// Reserved 0x28
void __Reserved_0x28_Handler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));
// Cortex-M3 SV Call Interrupt
void SVCall_Handler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));
// Cortex-M3 Debug Monitor Interrupt
void DebugMon_Handler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));
// Reserved 0x34
void __Reserved_0x34_Handler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));
// Cortex-M3 Pend SV Interrupt
void PendSV_Handler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));
// Cortex-M3 System Tick Interrupt
void SysTick_Handler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));
// Watchdog Timer Interrupt
void WDT_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));
// Timer0 Interrupt
void TIMER0_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));
// Timer1 Interrupt
void TIMER1_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));
// Timer2 Interrupt
void TIMER2_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));
// Timer3 Interrupt
void TIMER3_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));
// UART0 Interrupt
void UART0_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));
// UART1 Interrupt
void UART1_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));
// UART2 Interrupt
void UART2_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));
// UART3 Interrupt
void UART3_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));
// PWM1 Interrupt
void PWM1_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));
// I2C0 Interrupt
void I2C0_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));
// I2C1 Interrupt
void I2C1_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));
// I2C2 Interrupt
void I2C2_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));
// SPI Interrupt
void SPI_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));
// SSP0 Interrupt
void SSP0_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));
// SSP1 Interrupt
void SSP1_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));
// PLL0 Lock (Main PLL) Interrupt
void PLL0_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));
// Real Time Clock Interrupt
void RTC_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));
// External Interrupt 0 Interrupt
void EINT0_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));
// External Interrupt 1 Interrupt
void EINT1_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));
// External Interrupt 2 Interrupt
void EINT2_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));
// External Interrupt 3 Interrupt
void EINT3_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));
// A/D Converter Interrupt
void ADC_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));
// Brown-Out Detect Interrupt
void BOD_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));
// USB Interrupt
void USB_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));
// CAN Interrupt
void CAN_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));
// General Purpose DMA Interrupt
void DMA_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));
// I2S Interrupt
void I2S_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));
// Ethernet Interrupt
void ENET_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));
// Repetitive Interrupt Timer Interrupt
void RIT_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));
// Motor Control PWM Interrupt
void MCPWM_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));
// Quadrature Encoder Interface Interrupt
void QEI_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));
// PLL1 Lock (USB PLL) Interrupt
void PLL1_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));
// USB Activity interrupt
void USBActivity_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));
// CAN Activity interrupt
void CANActivity_IRQHandler(void) __attribute__ ((interrupt, weak, alias("__Default_Handler")));
/*
+=============================================================================+
| Vector table
+=============================================================================+
*/
extern const char __main_stack_end; // imported main stack end (from linker script)
void Reset_Handler(void); // import the address of Reset_Handler()
void (* const vectors[])(void) __attribute__ ((section(".vectors"))) = {
(void (*)(void))&__main_stack_end, // Main stack end address
Reset_Handler, // Reset
NMI_Handler, // Non Maskable Interrupt
HardFault_Handler, // All class of fault
MemManage_Handler, // Cortex-M3 Memory Management Interrupt
BusFault_Handler, // Cortex-M3 Bus Fault Interrupt
UsageFault_Handler, // Cortex-M3 Usage Fault Interrupt
__Reserved_0x1C_Handler, // Reserved 0x1C
__Reserved_0x20_Handler, // Reserved 0x20
__Reserved_0x24_Handler, // Reserved 0x24
__Reserved_0x28_Handler, // Reserved 0x28
SVCall_Handler, // Cortex-M3 SV Call Interrupt
DebugMon_Handler, // Cortex-M3 Debug Monitor Interrupt
__Reserved_0x34_Handler, // Reserved 0x34
PendSV_Handler, // Cortex-M3 Pend SV Interrupt
SysTick_Handler, // Cortex-M3 System Tick Interrupt
WDT_IRQHandler, // Watchdog Timer Interrupt
TIMER0_IRQHandler, // Timer0 Interrupt
TIMER1_IRQHandler, // Timer1 Interrupt
TIMER2_IRQHandler, // Timer2 Interrupt
TIMER3_IRQHandler, // Timer3 Interrupt
UART0_IRQHandler, // UART0 Interrupt
UART1_IRQHandler, // UART1 Interrupt
UART2_IRQHandler, // UART2 Interrupt
UART3_IRQHandler, // UART3 Interrupt
PWM1_IRQHandler, // PWM1 Interrupt
I2C0_IRQHandler, // I2C0 Interrupt
I2C1_IRQHandler, // I2C1 Interrupt
I2C2_IRQHandler, // I2C2 Interrupt
SPI_IRQHandler, // SPI Interrupt
SSP0_IRQHandler, // SSP0 Interrupt
SSP1_IRQHandler, // SSP1 Interrupt
PLL0_IRQHandler, // PLL0 Lock (Main PLL) Interrupt
RTC_IRQHandler, // Real Time Clock Interrupt
EINT0_IRQHandler, // External Interrupt 0 Interrupt
EINT1_IRQHandler, // External Interrupt 1 Interrupt
EINT2_IRQHandler, // External Interrupt 2 Interrupt
EINT3_IRQHandler, // External Interrupt 3 Interrupt
ADC_IRQHandler, // A/D Converter Interrupt
BOD_IRQHandler, // Brown-Out Detect Interrupt
USB_IRQHandler, // USB Interrupt
CAN_IRQHandler, // CAN Interrupt
DMA_IRQHandler, // General Purpose DMA Interrupt
I2S_IRQHandler, // I2S Interrupt
ENET_IRQHandler, // Ethernet Interrupt
RIT_IRQHandler, // Repetitive Interrupt Timer Interrupt
MCPWM_IRQHandler, // Motor Control PWM Interrupt
QEI_IRQHandler, // Quadrature Encoder Interface Interrupt
PLL1_IRQHandler, // PLL1 Lock (USB PLL) Interrupt
USBActivity_IRQHandler, // USB Activity interrupt
CANActivity_IRQHandler, // CAN Activity interrupt
};
/******************************************************************************
* END OF FILE
******************************************************************************/
startup.S 0 → 100644
View file @ 45999dcd
/******************************************************************************
* author: Freddie Chopin, http://www.freddiechopin.info/
* file: startup.S
* last change: 2012-03-18
*
* chip: ARMv7-M(E) (Cortex-M3 / Cortex-M4)
* compiler: arm-none-eabi-gcc (GNU Tools for ARM Embedded Processors) 4.6.2
* 20110921 (release) [ARM/embedded-4_6-branch revision 182083]
*
* description:
* ARMv7-M(E) (Cortex-M3 / Cortex-M4) assembly startup code
******************************************************************************/
/*
+=============================================================================+
| includes
+=============================================================================+
*/
#include "hdr/hdr_special_registers.h"
/*
+=============================================================================+
| ARMv7-M(E) (Cortex-M3 / Cortex-M4) startup code
+=============================================================================+
*/
.text
.balign 2
.syntax unified
.thumb
.thumb_func
.global Reset_Handler
Reset_Handler:
/*
+-----------------------------------------------------------------------------+
| Initialize the process stack pointer
+-----------------------------------------------------------------------------+
*/
ldr r0, =__process_stack_end
msr PSP, r0
/*
+-----------------------------------------------------------------------------+
| Thread mode uses process stack (PSP) and is privileged
+-----------------------------------------------------------------------------+
*/
movs r0, #CONTROL_ALTERNATE_STACK
msr CONTROL, r0
isb
/*
+-----------------------------------------------------------------------------+
| Branch to low_level_init_0() function (.data and .bss are not initialized!)
+-----------------------------------------------------------------------------+
*/
ldr r0, =low_level_init_0
blx r0
/*
+-----------------------------------------------------------------------------+
| Initialize .data section
+-----------------------------------------------------------------------------+
*/
ldr r1, =__data_init_start
ldr r2, =__data_start
ldr r3, =__data_end
1: cmp r2, r3
ittt lo
ldrlo r0, [r1], #4
strlo r0, [r2], #4
blo 1b
/*
+-----------------------------------------------------------------------------+
| Zero-init .bss section
+-----------------------------------------------------------------------------+
*/
movs r0, #0
ldr r1, =__bss_start
ldr r2, =__bss_end
1: cmp r1, r2
itt lo
strlo r0, [r1], #4
blo 1b
/*
+-----------------------------------------------------------------------------+
| Call C++ constructors for global and static objects
+-----------------------------------------------------------------------------+
*/
#ifdef __USES_CXX
ldr r0, =__libc_init_array
blx r0
#endif
/*
+-----------------------------------------------------------------------------+
| Branch to low_level_init_1() function
+-----------------------------------------------------------------------------+
*/
ldr r0, =low_level_init_1
blx r0
/*
+-----------------------------------------------------------------------------+
| Branch to main() with link
+-----------------------------------------------------------------------------+
*/
ldr r0, =main
blx r0
/*
+-----------------------------------------------------------------------------+
| Call C++ destructors for global and static objects
+-----------------------------------------------------------------------------+
*/
#ifdef __USES_CXX
ldr r0, =__libc_fini_array
blx r0
#endif
/*
+-----------------------------------------------------------------------------+
| On return - loop till the end of the world
+-----------------------------------------------------------------------------+
*/
b .
/*
+=============================================================================+
| __default_low_level_init() - replacement for undefined low_level_init_0()
| and/or low_level_init_1(). This function just returns.
+=============================================================================+
*/
.text
.balign 2
.syntax unified
.thumb
.thumb_func
.global __default_low_level_init
__default_low_level_init:
bx lr
/*
+=============================================================================+
| assign undefined low_level_init_0() and/or low_level_init_1() to
| __default_low_level_init()
+=============================================================================+
*/
.weak low_level_init_0
.global low_level_init_0
.set low_level_init_0, __default_low_level_init
.weak low_level_init_1
.global low_level_init_1
.set low_level_init_1, __default_low_level_init
/******************************************************************************
* END OF FILE
******************************************************************************/
verilog/blinker.v 0 → 100644
View file @ 45999dcd
/* Copyright (C) 2013 Upi Tamminen
* See the COPYRIGHT file for more information */
module blinker(clk, LED);
input clk;
output LED;
reg [32:0] cnt;
always @(posedge clk) cnt <= cnt + 1;
assign LED = cnt[23];
endmodule
/* vim: set sw=4 et: */
verilog/cpldtest1.qpf 0 → 100644
View file @ 45999dcd
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2011 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 32-bit
# Version 11.1 Build 259 01/25/2012 Service Pack 2.11 SJ Web Edition
# Date created = 12:28:47 January 21, 2013
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "11.1"
DATE = "12:28:47 January 21, 2013"
# Revisions
PROJECT_REVISION = "grabor"
verilog/cpldtest1.qsf 0 → 100644
View file @ 45999dcd
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2011 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 32-bit
# Version 11.1 Build 259 01/25/2012 Service Pack 2.11 SJ Web Edition
# Date created = 12:28:47 January 21, 2013
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# grabor_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "MAX II"
set_global_assignment -name DEVICE EPM240T100C5
set_global_assignment -name TOP_LEVEL_ENTITY grabor
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "11.1 SP2.11"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:28:47 JANUARY 21, 2013"
set_global_assignment -name LAST_QUARTUS_VERSION "11.1 SP2.11"
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
set_global_assignment -name POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR 3.3V
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_location_assignment PIN_73 -to LED
set_location_assignment PIN_64 -to clk
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
set_location_assignment PIN_55 -to PIXEL[7]
set_location_assignment PIN_54 -to PIXEL[6]
set_location_assignment PIN_53 -to PIXEL[5]
set_location_assignment PIN_52 -to PIXEL[4]
set_location_assignment PIN_51 -to PIXEL[3]
set_location_assignment PIN_50 -to PIXEL[2]
set_location_assignment PIN_49 -to PIXEL[1]
set_location_assignment PIN_48 -to PIXEL[0]
set_location_assignment PIN_66 -to HSYNC
set_location_assignment PIN_67 -to VSYNC
set_location_assignment PIN_84 -to SRAM_IO[5]
set_location_assignment PIN_85 -to SRAM_IO[4]
set_location_assignment PIN_86 -to SRAM_ADDR[14]
set_location_assignment PIN_87 -to SRAM_ADDR[13]
set_location_assignment PIN_88 -to SRAM_ADDR[12]
set_location_assignment PIN_89 -to SRAM_ADDR[11]
set_location_assignment PIN_90 -to SRAM_ADDR[10]
set_location_assignment PIN_91 -to SRAM_IO[6]
set_location_assignment PIN_92 -to SRAM_IO[7]
set_location_assignment PIN_95 -to SRAM_OE
set_location_assignment PIN_96 -to SRAM_ADDR[15]
set_location_assignment PIN_97 -to SRAM_ADDR[16]
set_location_assignment PIN_98 -to SRAM_ADDR[17]
set_location_assignment PIN_99 -to SRAM_ADDR[18]
set_location_assignment PIN_100 -to SRAM_ADDR[0]
set_location_assignment PIN_1 -to SRAM_ADDR[1]
set_location_assignment PIN_4 -to SRAM_ADDR[4]
set_location_assignment PIN_3 -to SRAM_ADDR[3]
set_location_assignment PIN_2 -to SRAM_ADDR[2]
set_location_assignment PIN_5 -to SRAM_CE
set_location_assignment PIN_15 -to SRAM_IO[3]
set_location_assignment PIN_8 -to SRAM_IO[2]
set_location_assignment PIN_7 -to SRAM_IO[1]
set_location_assignment PIN_6 -to SRAM_IO[0]
set_location_assignment PIN_16 -to SRAM_WE
set_location_assignment PIN_17 -to SRAM_ADDR[9]
set_location_assignment PIN_18 -to SRAM_ADDR[8]
set_location_assignment PIN_19 -to SRAM_ADDR[7]
set_location_assignment PIN_20 -to SRAM_ADDR[6]
set_location_assignment PIN_21 -to SRAM_ADDR[5]
set_location_assignment PIN_37 -to PIXELOUT[7]
set_location_assignment PIN_36 -to PIXELOUT[6]
set_location_assignment PIN_35 -to PIXELOUT[5]
set_location_assignment PIN_34 -to PIXELOUT[4]
set_location_assignment PIN_33 -to PIXELOUT[3]
set_location_assignment PIN_28 -to PIXELOUT[2]
set_location_assignment PIN_27 -to PIXELOUT[1]
set_location_assignment PIN_26 -to PIXELOUT[0]
set_location_assignment PIN_40 -to SAVE
set_location_assignment PIN_41 -to XFR
set_location_assignment PIN_42 -to OUTCLK
set_global_assignment -name CDF_FILE Chain1.cdf
verilog/cpldtest1.v 0 → 100644
View file @ 45999dcd
/* Copyright (C) 2013 Upi Tamminen
* See the COPYRIGHT file for more information */
module grabor(clk,
SRAM_ADDR, SRAM_IO, SRAM_OE, SRAM_CE, SRAM_WE,
SAVE, XFR, OUTCLK,
HSYNC, VSYNC, PIXEL,
PIXELOUT, LED);
input clk;
output LED;
input HSYNC;
input VSYNC;
input [7:0] PIXEL;
output reg [7:0] PIXELOUT; // DMA output to MCU
input SAVE;
input XFR;
output reg OUTCLK;
/* SRAM definitions */
output SRAM_OE;
output SRAM_CE;
output SRAM_WE;
inout SRAM_IO;
output SRAM_ADDR;
reg [18:0] SRAM_ADDR;
reg [7:0] SRAM_IO;
/* main blink turn on */
blinker Blinker(clk, LED);
/* SRAM controller */
reg [7:0] sram_q;
reg [18:0] sram_address;
reg [7:0] sram_d;
reg sram_wren;
sramctrl SRAMCtrl(clk, sram_wren, sram_d, sram_q, sram_address,
SRAM_WE, SRAM_CE, SRAM_OE, SRAM_IO, SRAM_ADDR);
/* fun */
reg [15:0] active_line;
reg [15:0] active_column;
reg [15:0] num_columns; // keep the total number of columns here
reg [15:0] num_rows; // keep the total number of rows here
reg can_save;
reg saving;
reg save_done;
reg [2:0] VSYNCr;
always @(posedge clk) VSYNCr <= {VSYNCr[1:0], VSYNC};
wire VSYNC_risingedge = (VSYNCr[2:1] == 2'b01);
wire VSYNC_fallingedge = (VSYNCr[2:1] == 2'b10);
wire VSYNC_active = ~VSYNCr[1];
reg [2:0] HSYNCr;
always @(posedge clk) HSYNCr <= {HSYNCr[1:0], HSYNC};
wire HSYNC_risingedge = (HSYNCr[2:1] == 2'b01);
wire HSYNC_fallingedge = (HSYNCr[2:1] == 2'b10);
wire HSYNC_active = ~HSYNCr[1];
/* save pin goes high = save */
reg [2:0] SAVEr;
always @(posedge clk) SAVEr <= {SAVEr[1:0], SAVE};
wire SAVE_risingedge = (SAVEr[2:1] == 2'b01);
/* xfr pin goes high = start clocking out data */
reg [2:0] XFRr;
always @(posedge clk) XFRr <= {XFRr[1:0], XFR};
wire XFR_risingedge = (XFRr[2:1] == 2'b01);
reg [13:0] pulse; /* temp test for pulses */
reg pulseflip;
reg [4:0] pulsediv;
always @(posedge clk) begin
/* DMA transfer to MCU */
pulsediv <= pulsediv + 1;
if (pulsediv == 2'b00000) begin
if (pulseflip) begin
if (pulse > 0 && pulse <= 2048) begin
PIXELOUT <= sram_q;
//PIXELOUT <= 8'b11111111;
OUTCLK <= 1'b1;
pulse <= pulse + 1;
sram_address <= sram_address + 1;
end else begin
OUTCLK <= 1'b0;
end
pulseflip = 0;
end else begin
OUTCLK <= 1'b0;
pulseflip = 1;
end
end
if (~HSYNC_active) begin
active_column = active_column + 1;
if (saving) begin
sram_address <= sram_address + 1;
sram_d <= PIXEL;
//sram_d <= 8'b00000010;
//sram_d = color_toggle == 1 ? 8'b11100000 : 8'b00011100;
sram_wren <= 1;
end
end
/* line begins */
if (HSYNC_risingedge) begin
active_line <= active_line + 1;
active_column <= 0;
/* line ends */
end else if (HSYNC_fallingedge) begin
num_columns <= active_column;
end
/* frame begins */
if (VSYNC_risingedge) begin
active_line <= 0;
if (can_save && !saving) begin
can_save <= 0;
saving <= 1;
sram_address <= 0;
sram_wren <= 0;
end
/* frame ends */
end else if (VSYNC_fallingedge) begin
num_rows <= active_line;
if (saving) begin
save_done <= 1;
sram_address <= 0;
saving <= 0;
sram_wren <= 0;
end
end
if (SAVE_risingedge) begin
saving <= 0;
can_save <= 1;
end
if (XFR_risingedge) begin
pulse <= 1'b1;
end
end
endmodule
/* vim: set sw=4 et: */
verilog/grabor.qpf 0 → 100644
View file @ 45999dcd
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2011 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 32-bit
# Version 11.1 Build 259 01/25/2012 Service Pack 2.11 SJ Web Edition
# Date created = 12:28:47 January 21, 2013
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "11.1"
DATE = "12:28:47 January 21, 2013"
# Revisions
PROJECT_REVISION = "grabor"
verilog/grabor.qsf 0 → 100644
View file @ 45999dcd
# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2011 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 32-bit
# Version 11.1 Build 259 01/25/2012 Service Pack 2.11 SJ Web Edition
# Date created = 12:28:47 January 21, 2013
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# grabor_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "MAX II"
set_global_assignment -name DEVICE EPM240T100C5
set_global_assignment -name TOP_LEVEL_ENTITY grabor
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "11.1 SP2.11"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "12:28:47 JANUARY 21, 2013"
set_global_assignment -name LAST_QUARTUS_VERSION "11.1 SP2.11"
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR "-1"
set_global_assignment -name POWER_EXT_SUPPLY_VOLTAGE_TO_REGULATOR 3.3V
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_location_assignment PIN_73 -to LED
set_location_assignment PIN_64 -to clk
set_global_assignment -name USE_CONFIGURATION_DEVICE ON
set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
set_location_assignment PIN_55 -to PIXEL[7]
set_location_assignment PIN_54 -to PIXEL[6]
set_location_assignment PIN_53 -to PIXEL[5]
set_location_assignment PIN_52 -to PIXEL[4]
set_location_assignment PIN_51 -to PIXEL[3]
set_location_assignment PIN_50 -to PIXEL[2]
set_location_assignment PIN_49 -to PIXEL[1]
set_location_assignment PIN_48 -to PIXEL[0]
set_location_assignment PIN_66 -to HSYNC
set_location_assignment PIN_67 -to VSYNC
set_location_assignment PIN_84 -to SRAM_IO[5]
set_location_assignment PIN_85 -to SRAM_IO[4]
set_location_assignment PIN_86 -to SRAM_ADDR[14]
set_location_assignment PIN_87 -to SRAM_ADDR[13]
set_location_assignment PIN_88 -to SRAM_ADDR[12]
set_location_assignment PIN_89 -to SRAM_ADDR[11]
set_location_assignment PIN_90 -to SRAM_ADDR[10]
set_location_assignment PIN_91 -to SRAM_IO[6]
set_location_assignment PIN_92 -to SRAM_IO[7]
set_location_assignment PIN_95 -to SRAM_OE
set_location_assignment PIN_96 -to SRAM_ADDR[15]
set_location_assignment PIN_97 -to SRAM_ADDR[16]
set_location_assignment PIN_98 -to SRAM_ADDR[17]
set_location_assignment PIN_99 -to SRAM_ADDR[18]
set_location_assignment PIN_100 -to SRAM_ADDR[0]
set_location_assignment PIN_1 -to SRAM_ADDR[1]
set_location_assignment PIN_4 -to SRAM_ADDR[4]
set_location_assignment PIN_3 -to SRAM_ADDR[3]
set_location_assignment PIN_2 -to SRAM_ADDR[2]
set_location_assignment PIN_5 -to SRAM_CE
set_location_assignment PIN_15 -to SRAM_IO[3]
set_location_assignment PIN_8 -to SRAM_IO[2]
set_location_assignment PIN_7 -to SRAM_IO[1]
set_location_assignment PIN_6 -to SRAM_IO[0]
set_location_assignment PIN_16 -to SRAM_WE
set_location_assignment PIN_17 -to SRAM_ADDR[9]
set_location_assignment PIN_18 -to SRAM_ADDR[8]
set_location_assignment PIN_19 -to SRAM_ADDR[7]
set_location_assignment PIN_20 -to SRAM_ADDR[6]
set_location_assignment PIN_21 -to SRAM_ADDR[5]
set_location_assignment PIN_37 -to PIXELOUT[7]
set_location_assignment PIN_36 -to PIXELOUT[6]
set_location_assignment PIN_35 -to PIXELOUT[5]
set_location_assignment PIN_34 -to PIXELOUT[4]
set_location_assignment PIN_33 -to PIXELOUT[3]
set_location_assignment PIN_28 -to PIXELOUT[2]
set_location_assignment PIN_27 -to PIXELOUT[1]
set_location_assignment PIN_26 -to PIXELOUT[0]
set_location_assignment PIN_40 -to SAVE
set_location_assignment PIN_41 -to XFR
set_location_assignment PIN_42 -to OUTCLK
set_global_assignment -name CDF_FILE Chain1.cdf
verilog/grabor.v 0 → 100644
View file @ 45999dcd
/* Copyright (C) 2013 Upi Tamminen
* See the COPYRIGHT file for more information */
module grabor(clk,
SRAM_ADDR, SRAM_IO, SRAM_OE, SRAM_CE, SRAM_WE,
SAVE, XFR, OUTCLK,
HSYNC, VSYNC, PIXEL,
PIXELOUT, LED);
input clk;
output LED;
input HSYNC;
input VSYNC;
input [7:0] PIXEL;
output reg [7:0] PIXELOUT; // DMA output to MCU
input SAVE;
input XFR;
output reg OUTCLK;
/* SRAM definitions */
output SRAM_OE;
output SRAM_CE;
output SRAM_WE;
inout SRAM_IO;
output SRAM_ADDR;
reg [18:0] SRAM_ADDR;
reg [7:0] SRAM_IO;
/* main blink turn on */
blinker Blinker(clk, LED);
/* SRAM controller */
reg [7:0] sram_q;
reg [18:0] sram_address;
reg [7:0] sram_d;
reg sram_wren;
sramctrl SRAMCtrl(clk, sram_wren, sram_d, sram_q, sram_address,
SRAM_WE, SRAM_CE, SRAM_OE, SRAM_IO, SRAM_ADDR);
/* fun */
reg [15:0] active_line;
reg [15:0] active_column;
reg [15:0] num_columns; // keep the total number of columns here
reg [15:0] num_rows; // keep the total number of rows here
reg can_save;
reg saving;
reg save_done;
reg [2:0] VSYNCr;
always @(posedge clk) VSYNCr <= {VSYNCr[1:0], VSYNC};
wire VSYNC_risingedge = (VSYNCr[2:1] == 2'b01);
wire VSYNC_fallingedge = (VSYNCr[2:1] == 2'b10);
wire VSYNC_active = ~VSYNCr[1];
reg [2:0] HSYNCr;
always @(posedge clk) HSYNCr <= {HSYNCr[1:0], HSYNC};
wire HSYNC_risingedge = (HSYNCr[2:1] == 2'b01);
wire HSYNC_fallingedge = (HSYNCr[2:1] == 2'b10);
wire HSYNC_active = ~HSYNCr[1];
/* save pin goes high = save */
reg [2:0] SAVEr;
always @(posedge clk) SAVEr <= {SAVEr[1:0], SAVE};
wire SAVE_risingedge = (SAVEr[2:1] == 2'b01);
/* xfr pin goes high = start clocking out data */
reg [2:0] XFRr;
always @(posedge clk) XFRr <= {XFRr[1:0], XFR};
wire XFR_risingedge = (XFRr[2:1] == 2'b01);
reg [13:0] pulse; /* temp test for pulses */
reg pulseflip;
reg [4:0] pulsediv;
always @(posedge clk) begin
/* DMA transfer to MCU */
pulsediv <= pulsediv + 1;
if (pulsediv == 2'b00000) begin
if (pulseflip) begin
if (pulse > 0 && pulse <= 2048) begin
PIXELOUT <= sram_q;
//PIXELOUT <= 8'b11111111;
OUTCLK <= 1'b1;
pulse <= pulse + 1;
sram_address <= sram_address + 1;
end else begin
OUTCLK <= 1'b0;
end
pulseflip = 0;
end else begin
OUTCLK <= 1'b0;
pulseflip = 1;
end
end
if (~HSYNC_active) begin
active_column = active_column + 1;
if (saving) begin
sram_address <= sram_address + 1;
sram_d <= PIXEL;
//sram_d <= 8'b00000010;
//sram_d = color_toggle == 1 ? 8'b11100000 : 8'b00011100;
sram_wren <= 1;
end
end
/* line begins */
if (HSYNC_risingedge) begin
active_line <= active_line + 1;
active_column <= 0;
/* line ends */
end else if (HSYNC_fallingedge) begin
num_columns <= active_column;
end
/* frame begins */
if (VSYNC_risingedge) begin
active_line <= 0;
if (can_save && !saving) begin
can_save <= 0;
saving <= 1;
sram_address <= 0;
sram_wren <= 0;
end
/* frame ends */
end else if (VSYNC_fallingedge) begin
num_rows <= active_line;
if (saving) begin
save_done <= 1;
sram_address <= 0;
saving <= 0;
sram_wren <= 0;
end
end
if (SAVE_risingedge) begin
saving <= 0;
can_save <= 1;
end
if (XFR_risingedge) begin
pulse <= 1'b1;
end
end
endmodule
/* vim: set sw=4 et: */
verilog/spihandler.v 0 → 100644
View file @ 45999dcd
/* Based on the fpga4fun SPI tutorial */
/*
Since the SPI bus is typically much slower than the FPGA operating clock
speed, we choose to over-sample the SPI bus using the FPGA clock. That makes
the slave code slightly more complicated, but has the advantage of having the
SPI logic run in the FPGA clock domain, which will make things easier
afterwards.
*/
/* 16bit spi here */
module spihandler(clk, SCK, MOSI, MISO, SSEL,
sendme, byte_received, byte_data_received);
input clk;
input SCK, SSEL, MOSI;
output MISO;
input [15:0] sendme;
output reg byte_received;
output reg [15:0] byte_data_received;
//output byte_received; // high when a byte has been received
//output [15:0] byte_data_received;
// sync SCK to the FPGA clock using a 3-bits shift register
reg [2:0] SCKr;
always @(posedge clk) SCKr <= {SCKr[1:0], SCK};
// now we can detect SCK rising and falling edges
wire SCK_risingedge = (SCKr[2:1] == 2'b01);
wire SCK_fallingedge = (SCKr[2:1] == 2'b10);
// same thing for SSEL
reg [2:0] SSELr;
always @(posedge clk) SSELr <= {SSELr[1:0], SSEL};
wire SSEL_active = ~SSELr[1]; // SSEL is active low
// message starts at falling edge and stops at rising edge
wire SSEL_startmessage = (SSELr[2:1] == 2'b10);
wire SSEL_endmessage = (SSELr[2:1] == 2'b01);
// and for MOSI
reg [1:0] MOSIr; always @(posedge clk) MOSIr <= {MOSIr[0], MOSI};
wire MOSI_data = MOSIr[1];
/* Now receiving data from the SPI bus is easy. */
reg [4:0] bitcnt; // 4 bits to count 16 bits
//reg byte_received; // high when a byte has been received
//reg [15:0] byte_data_received;
always @(posedge clk)
begin
if (~SSEL_active)
bitcnt <= 4'b0000;
else
if (SCK_risingedge)
begin
bitcnt <= bitcnt + 4'b0001;
// implement a shift-left register (since we receive the data MSB first)
byte_data_received <= {byte_data_received[14:0], MOSI_data};
end
end
always @(posedge clk)
begin
byte_received <= SSEL_active && SCK_risingedge && (bitcnt == 4'b1111);
end
/* Finally the transmission part. */
reg [15:0] byte_data_sent;
//reg [15:0] cnt;
//always @(posedge clk) cnt <= 43690; /* test data to be sent out */
//always @(posedge clk) if (SSEL_startmessage) cnt<=cnt+8'h1; // count the messages
always @(posedge clk)
if (SSEL_active)
begin
if (SSEL_startmessage)
byte_data_sent <= sendme;
else
if (SCK_fallingedge)
begin
if (bitcnt == 4'b0000)
byte_data_sent <= 8'h0000; // after that, we send 0s
else
byte_data_sent <= {byte_data_sent[14:0], 1'b0};
end
end
assign MISO = byte_data_sent[15]; // send MSB first
// we assume that there is only one slave on the SPI bus
// so we don't bother with a tri-state buffer for MISO
// otherwise we would need to tri-state MISO when SSEL is inactive
endmodule
/* vim: set sw=4 et: */
verilog/sramctrl.v 0 → 100644
View file @ 45999dcd
/*
* Based on:
* http://greenbird.tweakblogs.net/blog/3459/sram-controller.html
*/
module sramctrl(clk,
wren, d, q, address,
WE, CE, OE, IO, A);
input clk;
input wren;
input [7:0] d;
input [18:0] address;
output reg [7:0] q;
output reg WE;
output reg CE;
output reg OE;
inout [7:0] IO;
output reg [18:0] A;
reg io_oe;
reg [7:0] buffer_d;
assign IO = io_oe ? buffer_d : 8'bZ;
always @(posedge clk) begin
if (wren) begin
// write
A <= address;
OE <= 1;
CE <= 0;
WE <= 0;
io_oe <= 1;
end
else
begin
// read
A <= address;
CE <= 0;
OE <= 0;
WE <= 1;
io_oe <= 0;
end
buffer_d <= d;
end
always @(negedge clk) begin
if (wren == 0) begin
// read
q <= IO;
end
end
endmodule
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment