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rasky
grabor
Commits
30e75da9
Commit
30e75da9
authored
Apr 23, 2013
by
Upi Tamminen
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Inject frame width/height to the image data
parent
d81e8400
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1
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16 additions
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6 deletions
+16
-6
grabor.v
verilog/grabor.v
+16
-6
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verilog/grabor.v
View file @
30e75da9
...
@@ -96,21 +96,31 @@ always @(posedge clk) begin
...
@@ -96,21 +96,31 @@ always @(posedge clk) begin
end
else
begin
end
else
begin
OUTCLK
<=
1'b0
;
OUTCLK
<=
1'b0
;
end
end
pulseflip
=
0
;
pulseflip
<
=
0
;
end
else
begin
end
else
begin
OUTCLK
<=
1'b0
;
OUTCLK
<=
1'b0
;
pulseflip
=
1
;
pulseflip
<
=
1
;
end
end
end
end
if
(
~
HSYNC_active
)
begin
if
(
~
HSYNC_active
)
begin
active_column
=
active_column
+
1
;
active_column
<
=
active_column
+
1
;
if
(
saving
)
begin
if
(
saving
)
begin
sram_address
<=
sram_address
+
1
;
if
(
sram_address
==
0
)
begin
sram_d
<=
num_columns
[
7
:
0
]
;
end
else
if
(
sram_address
==
1
)
begin
sram_d
<=
num_columns
[
15
:
8
]
;
end
else
if
(
sram_address
==
2
)
begin
sram_d
<=
num_rows
[
7
:
0
]
;
end
else
if
(
sram_address
==
3
)
begin
sram_d
<=
num_rows
[
15
:
8
]
;
end
else
begin
sram_d
<=
PIXEL
;
sram_d
<=
PIXEL
;
end
//sram_d <= 8'b00000010;
//sram_d <= 8'b00000010;
//sram_d = color_toggle == 1 ? 8'b11100000 : 8'b00011100;
//sram_d = color_toggle == 1 ? 8'b11100000 : 8'b00011100;
sram_wren
<=
1
;
sram_wren
<=
1
;
sram_address
<=
sram_address
+
1
;
end
end
end
end
...
@@ -120,7 +130,7 @@ always @(posedge clk) begin
...
@@ -120,7 +130,7 @@ always @(posedge clk) begin
active_column
<=
0
;
active_column
<=
0
;
/* line ends */
/* line ends */
end
else
if
(
HSYNC_fallingedge
)
begin
end
else
if
(
HSYNC_fallingedge
)
begin
num_columns
<=
active_column
;
num_columns
<=
active_column
+
1
;
end
end
/* frame begins */
/* frame begins */
...
...
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